Index: .reviewboardrc =================================================================== --- /YC1121E/SoftCode/MCU/.reviewboardrc (nonexistent) +++ /YC1121E/SoftCode/MCU/.reviewboardrc (working copy) @@ -0,0 +1 @@ +REVIEWBOARD_URL = "http://47.102.118.39/reviews" REPOSITORY = "prj_share" REPOSITORY_TYPE = "svn" \ No newline at end of file Index: createRc.exe =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Property changes on: createRc.exe ___________________________________________________________________ Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: tag/Soft/Librarier/bt_rom/program/a2dp.prog =================================================================== --- /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/a2dp.prog (nonexistent) +++ /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/a2dp.prog (working copy) @@ -0,0 +1,1152 @@ +ifdef COMPILE_A2DP +//avdtp +l2cap_call_proc_avdtp: + bpatch patch15_6,mem_patch15 + call l2cap_malloc_is_fifo_full + nrtn blank + fetch 2,mem_l2cap_payload_ptr + copy pdata,contr + ifetch 1,contr + and pdata,0xf0,temp + rshift4 temp,temp + storet 1,mem_transaction_label + and pdata,0x3,rega + and pdata,0xc,pdata + bne AVDTP_PACKET_TYPE_SINGLE,avd_signal_prase_uncomplete + copy rega,pdata + beq AVDTP_MESSAGE_TYPE_CMD,avd_signal_parse_cmd + beq AVDTP_MESSGAE_TYPE_GENERAL_REJECT,avd_signal_parse_general_reject + beq AVDTP_MESSGAE_TYPE_RSP_ACCEPT,avd_signal_parse_rsp_accept + beq AVDTP_MESSGAE_TYPE_RSP_REJECT,avd_signal_parse_rsp_reject + branch assert + + +l2cap_call_proc_avdtp_media_start_sbc: + bpatch patch15_7,mem_patch15 + // set flag + arg LOG_POINT_1602,rega + fetcht 2,mem_tws_state + call debug_log_print + +// call audio_clear_dac_buf + call sbc_dac_address_init + call audio_filter_init + call sbc_init + call eq_init + call sbc_update_stream_out + + jam AUDIO_STATE_IDLE,mem_audio_state + jam AVD_AUDIO_ALLOW,mem_audio_allow + + jam FIRST_BUFFER_CACHE_ENABLE,mem_first_buffer_cache + + // add drop state machine var init + jam TWS_DROP_OR_ADD_PROCESS_STATE_NONE,mem_drop_or_add_process_state + jam 0,mem_drop_or_add_min_receive_packet_size + jam 0,mem_tws_wait_sync_ok + + fetch 1,core_dac_ctrl + bbit0 DAC_ENABLE,audio_dac_init_media + + rtn + + +l2cap_call_proc_avdtp_media_wait: + call sbc_hw_check_busy + nrtn zero + jam AUDIO_STATE_IDLE,mem_audio_state + branch l2cap_rx_reset_state + +l2cap_call_proc_avdtp_media: + bpatch patch16_0,mem_patch16 + fetch 1,mem_vp_enable + bbit1 VP_MODE_BIT,l2cap_call_proc_avdtp_media_titshi + bne VP_STATE_DISENABLE,l2cap_rx_reset_state +l2cap_call_proc_avdtp_media_titshi: + bmark1 mark_sco_flag,l2cap_rx_reset_state + jam L2CAP_RX_CLEAR,mem_l2cap_rx_done + fetch 1,mem_audio_allow + beq AVD_AUDIO_ALLOW,l2cap_call_proc_avdtp_media_allow + fetch 1,mem_a2dp_state + beq A2DP_STATE_START,l2cap_call_proc_avdtp_media_start_sbc + branch l2cap_rx_reset_state + + +l2cap_call_proc_avdtp_media_allow: + bpatch patch16_1,mem_patch16 + // Step 1: check sbc idle or not + fetch 1,mem_audio_state + beq AUDIO_STATE_WAIT_SBC,l2cap_call_proc_avdtp_media_allow_sbc_in_work + beq AUDIO_STATE_WAIT_SOFT_DMA,l2cap_call_proc_avdtp_media_allow_soft_dma_in_work +l2cap_call_proc_avdtp_media_allow_sbc_idle: + // Step 2.1: parse packet header + call l2cap_call_proc_avdtp_media_parse_header + + // Step 2.2: check buffer full or not + call a2dp_media_buffer_add_drop_packet_judge + + // Step 2.3: check to drop one packet + call a2dp_media_buffer_drop_packet_process + + // Step 2.4: check need free packet + fetch 1,mem_l2cap_rx_done + rtneq L2CAP_RX_DONE + + // Step 2.5: cache enough packet for first play work + call a2dp_media_first_buffer_cache_work + rtn user + + // Step 2.7: judge reserve dac buffer size + call audio_dac_judge_reserve_buffer_enough + nrtn user + + // Step 2.8: set farrow filter delta uk + call audio_dac_set_farrow_filter + + // Step 2.9: let media packet into sbc buffer + branch l2cap_call_proc_avdtp_media_data + + +l2cap_call_proc_avdtp_media_allow_sbc_prepare_dma_work: + jam AUDIO_STATE_WAIT_SOFT_DMA,mem_audio_state + + // Step 3.1: init dma table + call soft_dma_table_init + + // init local var + setarg 0 + store 2,mem_temp_sbc_soft_dma_start_addr + store 2,mem_temp_dac_soft_dma_start_addr + store 2,mem_temp_soft_dma_work_length + jam 0,mem_temp_soft_dma_work_table_index_value + + // Step 3.2: get sbc decode buffer size + call audio_dac_get_sbc_decode_buffer_size_in_different_buffer + store 2,mem_temp_sbc_decode_buffer_size + + // Step 3.3: update tws slave loss sync farrow filter work cnt + call a2dp_update_farrow_filter_work_sample + + // Step 3.4: media buffer add process + call a2dp_media_buffer_add_packet_process + + + // For tws start sync, we need let slave to sync master fast, so we use drop/add packet to deal it + // to change mem_temp_sbc_decode_buffer_size to reach the focus + call a2dp_soft_dma_tws_add_or_drop_bytes + + // to make two soft dma work process + call audio_dac_hw_get_write_ptr_right_reserve_buffer + store 2,mem_temp + + branch a2dp_soft_dma_work_process_1,blank + + // check buffer size ok or not +a2dp_soft_dma_work_process: + call a2dp_soft_dma_work_process_allow_work_size + storet 2,mem_temp_soft_dma_work_length + + setarg 0 + store 2,mem_temp_sbc_soft_dma_start_addr + + fetch 2,core_dac_wptr + store 2,mem_temp_dac_soft_dma_start_addr + + arg 0,rega + jam 1,mem_temp_soft_dma_work_table_index_value + + call a2dp_soft_dma_work_unit_set + + // increase sbc start addr + fetch 2,mem_temp_sbc_soft_dma_start_addr + fetcht 2,mem_temp_soft_dma_work_length + iadd temp,pdata + store 2,mem_temp_sbc_soft_dma_start_addr + + // store the dac write ptr + fetch 2,core_dac_wptr + fetcht 2,mem_temp_soft_dma_work_length + iadd temp,pdata + store 2,mem_temp_dac_soft_dma_work_wptr + + // need check reach end? + call a2dp_soft_dma_update_dac_wptr_loopback + + // check need prepare second process + fetcht 2,mem_temp_soft_dma_work_length + fetch 2,mem_temp_sbc_decode_buffer_size + isub temp,temp + branch a2dp_soft_dma_work_process_end,zero +a2dp_soft_dma_work_process_1: + fetcht 2,mem_temp_soft_dma_work_length + fetch 2,mem_temp_sbc_decode_buffer_size + isub temp,temp + storet 2,mem_temp_soft_dma_work_length + + //setarg 0 + //store 2,mem_temp_sbc_soft_dma_start_addr + + fetch 2,core_dac_saddr + store 2,mem_temp_dac_soft_dma_start_addr + + arg 1,rega + fetch 1,mem_temp_soft_dma_work_table_index_value + set1 1,pdata + store 1,mem_temp_soft_dma_work_table_index_value + + call a2dp_soft_dma_work_unit_set + + // store the dac write ptr + fetch 2,core_dac_saddr + fetcht 2,mem_temp_soft_dma_work_length + iadd temp,pdata + store 2,mem_temp_dac_soft_dma_work_wptr + +a2dp_soft_dma_work_process_end: + fetcht 1,mem_temp_soft_dma_work_table_index_value + call soft_dma_add_task + rtn + + +a2dp_soft_dma_tws_add_or_drop_bytes: + bpatch patch16_2,mem_patch16 + fetch 2,mem_a2dp_adjust_delta_bytes + rtn blank + + fetch 1,mem_a2dp_adjust_delta_bytes_sign_bit + branch a2dp_soft_dma_tws_drop_bytes,blank +a2dp_soft_dma_tws_add_bytes: + // the add bytes should not big to sbc buffer size + fetch 2,mem_a2dp_adjust_delta_bytes + fetcht 2,mem_temp_sbc_decode_buffer_size + iadd temp,temp + // to check length + fetch 2,core_sbc_dlen + isub temp,null + branch a2dp_soft_dma_tws_add_bytes_end_big,positive + fetch 2,core_sbc_dlen +a2dp_soft_dma_tws_add_bytes_end: + fetcht 2,mem_temp_sbc_decode_buffer_size + isub temp,temp // get delta + // update buffer size + store 2,mem_temp_sbc_decode_buffer_size + // update adjust bytes + fetch 2,mem_a2dp_adjust_delta_bytes + isub temp,pdata + store 2,mem_a2dp_adjust_delta_bytes + rtn + +a2dp_soft_dma_tws_add_bytes_end_big: + // update buffer size + storet 2,mem_temp_sbc_decode_buffer_size + // update adjust bytes + setarg 0 + store 2,mem_a2dp_adjust_delta_bytes + rtn + +a2dp_soft_dma_tws_drop_bytes: + // the drop bytes should not big to half sbc buffer size + fetch 2,mem_temp_sbc_decode_buffer_size + rshift pdata,pdata + fetcht 2,mem_a2dp_adjust_delta_bytes + isub temp,null + branch a2dp_soft_dma_tws_drop_bytes_end_big,positive + copy pdata,temp // limit buffer size +a2dp_soft_dma_tws_drop_bytes_end: + storet 2,mem_temp_sbc_decode_buffer_size + fetch 2,mem_a2dp_adjust_delta_bytes + isub temp,pdata + store 2,mem_a2dp_adjust_delta_bytes + rtn + +a2dp_soft_dma_tws_drop_bytes_end_big: + fetch 2,mem_temp_sbc_decode_buffer_size + fetcht 2,mem_a2dp_adjust_delta_bytes + isub temp,pdata + store 2,mem_temp_sbc_decode_buffer_size + setarg 0 + store 2,mem_a2dp_adjust_delta_bytes + rtn + + + + +// input: mem_temp: dac reserve buffer size; mem_temp_sbc_decode_buffer_size: sbc need size +// output: temp +a2dp_soft_dma_work_process_allow_work_size: + fetch 2,mem_temp + fetcht 2,mem_temp_sbc_decode_buffer_size + isub temp,pdata + rtn positive + fetcht 2,mem_temp + rtn + + +// input: rega(table index) +a2dp_soft_dma_work_unit_set: + fetcht 2,mem_temp_sbc_soft_dma_start_addr + call a2dp_sbc_get_full_dst_addr_with_offset + store 4,mem_soft_dma_src_addr + + fetcht 2,mem_temp_dac_soft_dma_start_addr + call a2dp_dac_get_full_dst_addr_with_offset + store 4,mem_soft_dma_dst_addr + + fetcht 2,mem_temp_soft_dma_work_length + + // input: mem_soft_dma_src_addr, mem_soft_dma_dst_addr, temp(length), rega(table index) + branch soft_dma_table_unit_set + + +a2dp_soft_dma_update_dac_wptr_loopback: + fetch 2,core_dac_saddr + fetcht 2,core_dac_len + iadd temp,pdata + pincrease 1 + fetcht 2,mem_temp_dac_soft_dma_work_wptr + isub temp,null + nrtn zero + fetch 2,core_dac_saddr + store 2,mem_temp_dac_soft_dma_work_wptr + rtn + +// input: temp +// output: pdata +a2dp_sbc_get_full_dst_addr_with_offset: + fetch 2,core_sbc_daddr + iadd temp,temp // start addr + + fetch 1,mem_param_a2dp_sbc_buffer_addr_mram_flag + branch get_full_sram_addr,blank + branch get_full_mram_addr + + +// input: temp +// output: pdata +a2dp_dac_get_full_dst_addr_with_offset: + fetch 1,mem_dac_mram_flag + branch get_full_sram_addr,blank + branch get_full_mram_addr + + + +l2cap_call_proc_avdtp_media_allow_soft_dma_in_work: + // Step 4.1: check soft dma work ready or not + // If soft dma work busy, do nothing + call soft_dma_check_work_ready + nrtn blank + + jam AUDIO_STATE_IDLE,mem_audio_state + + // Step 3.5: check dac buffer empty + call l2cap_call_proc_avdtp_media_with_dac_empty_detect + + // Step 3.6: get sbc decode buffer size + call a2dp_soft_dma_update_dac_wptr + + // Step 3.7: adjust vol + call a2dp_soft_dma_update_vol + + // Step 3.8: free packet + branch l2cap_call_proc_avdtp_media_free_packet + + +a2dp_soft_dma_update_vol: + fetch 1,mem_slave_force_mute_a2dp_voice + nbranch a2dp_soft_dma_mute_vol,blank + branch audio_dac_vol_adjust + +a2dp_soft_dma_mute_vol: + // Check in fast sync + fetch 1,mem_media_in_fast_mode + nbranch audio_dac_mute_vol,blank + + fetch 1,mem_slave_force_mute_a2dp_voice_cnt + branch audio_dac_vol_adjust,blank + increase -1,pdata + store 1,mem_slave_force_mute_a2dp_voice_cnt + + branch audio_dac_mute_vol + + +a2dp_soft_dma_update_dac_wptr: + fetch 2,mem_temp_dac_soft_dma_work_wptr + store 2,core_dac_wptr + rtn + + +l2cap_call_proc_avdtp_media_allow_sbc_in_work: + // Step 3.1: check sbc work ready or not + // If sbc work busy, do nothing + call sbc_hw_check_busy + nrtn zero + + // Step 3.2: check need or not to process soft dma process + fetch 1,mem_param_a2dp_dac_sbc_same_buffer_flag + branch l2cap_call_proc_avdtp_media_allow_sbc_prepare_dma_work,blank + + jam AUDIO_STATE_IDLE,mem_audio_state + + // Step 3.2: get sbc decode buffer size + call audio_dac_get_sbc_decode_buffer_size + store 2,mem_temp_sbc_decode_buffer_size + + // Step 3.3: update tws slave loss sync farrow filter work cnt + call a2dp_update_farrow_filter_work_sample + + // Step 3.4: media buffer add process + call a2dp_media_buffer_add_packet_process + + // Step 3.5: check dac buffer empty + call l2cap_call_proc_avdtp_media_with_dac_empty_detect + + // Step 3.6: get sbc decode buffer size + call sbc_update_dac_wptr + + // Step 3.7: adjust vol + call audio_dac_vol_adjust + + // Step 3.8: free packet + branch l2cap_call_proc_avdtp_media_free_packet + + +audio_dac_set_farrow_filter: + bpatch patch16_3,mem_patch16 + // clear first + setarg 0 + store 4,mem_farrow_filter_delta_uk + // Step1: set delta uk by tws loss + call audio_dac_set_farrow_filter_process + fetch 4,mem_farrow_filter_delta_uk + nbranch audio_dac_set_farrow_filter_end,blank + +audio_dac_set_farrow_filter_end: + branch audio_farrow_filter_set_delta_uk + + +audio_dac_set_farrow_filter_process: + fetch 4,mem_a2dp_adjust_total_work_sample + rtn blank + + fetch 4,mem_a2dp_adjust_delta_uk + store 4,mem_farrow_filter_delta_uk + + fetch 1,mem_a2dp_adjust_delta_uk_sign_bit + store 1,mem_farrow_filter_delta_uk_sign_bit + rtn + +a2dp_update_farrow_filter_work_sample: + fetch 4,mem_a2dp_adjust_total_work_sample + rtn blank + + fetcht 2,mem_temp_sbc_decode_buffer_size + // becouse is one channel dac out, one samle is 2bytes + rshift temp,temp + isub temp,pdata + nbranch tws_clear_farrow_filter_work_sample,positive + store 4,mem_a2dp_adjust_total_work_sample + rtn + +tws_clear_farrow_filter_work_sample: + setarg 0 + store 4,mem_a2dp_adjust_total_work_sample + store 4,mem_a2dp_adjust_delta_uk + rtn + + + +l2cap_call_proc_avdtp_media_with_dac_empty_detect: + call audio_dac_hw_check_empty + nrtn zero + // set flag + arg LOG_POINT_1630,rega + fetcht 1,mem_media_cur_len + call debug_log_print + + rtn + + +l2cap_call_proc_avdtp_media_free_packet: + call l2cap_rx_reset_state + rtn + +l2cap_call_proc_avdtp_media_parse_header: + arg mem_media_block,rega + call queue_get_read_ptr + + increase 4,pdata + store 2,mem_temp + ifetch 2,contr + store 2,mem_l2cap_rx_pkt_length + + // Get Seq Num + fetch 2,mem_temp + add pdata,2,contr + ifetch 2,contr + byteswap pdata,pdata + store 2,mem_a2dp_seq_num + + call a2dp_check_rcv_seq_error + rtn + +a2dp_check_rcv_seq_error: + fetch 1,mem_first_buffer_cache + beq FIRST_BUFFER_CACHE_ENABLE,a2dp_check_rcv_seq_error_end + + fetch 2,mem_a2dp_seq_num + fetcht 2,mem_last_a2dp_seq_num + isub temp,pdata + beq 1,a2dp_check_rcv_seq_error_end + beq 0,a2dp_check_rcv_seq_error_end + + // set flag + arg LOG_POINT_8000,rega + fetcht 2,mem_a2dp_seq_num + call debug_log_print +a2dp_check_rcv_seq_error_end: + fetch 2,mem_a2dp_seq_num + store 2,mem_last_a2dp_seq_num + rtn + +a2dp_update_min_receive_packet_size: + fetch 2,mem_drop_or_add_min_receive_packet_size + fetcht 2,mem_l2cap_rx_pkt_length + isub temp,null + rtn positive + + storet 2,mem_drop_or_add_min_receive_packet_size + rtn + + +l2cap_call_proc_avdtp_media_data: + bpatch patch16_4,mem_patch16 + // for tws must update sbc stream output format + call sbc_update_stream_out + + // set flag + arg LOG_POINT_1600,rega + fetcht 2,mem_a2dp_seq_num + call debug_log_print + // set flag + arg LOG_POINT_1601,rega + fetcht 2,mem_l2cap_rx_pkt_length + call debug_log_print + // set flag + arg LOG_POINT_1604,rega + fetcht 2,mem_media_cur_len + call debug_log_print + + arg mem_media_block,rega + call queue_get_read_ptr + + // point to data + add pdata,16,contr + + arg 12,rega +avd_media_get_offset_loop: + ifetch 1,contr + increase 1,rega + beq 0,avd_media_get_offset_loop + + ifetch 1,contr + bne 0x9c,assert + + //call sbc_block_disable + + // mem_temp store the point to data + fetch 2,mem_temp + iadd rega,pdata + store 2,core_sbc_saddr + + setarg 0x400 + store 2,core_sbc_slen + + // if not disable sbc block, must clear before core_sbc_swp + call a2dp_sbc_clear_ptr_work + + fetch 2,mem_l2cap_rx_pkt_length + isub rega,pdata + store 2,core_sbc_swp + + //call sbc_block_enable + + jam AUDIO_STATE_WAIT_SBC,mem_audio_state + arg 0,temp + branch sbc_hw_check_error + +a2dp_sbc_clear_ptr_work: + // if not same buffer, need clear sbc dst addr ptr + fetch 1,mem_param_a2dp_dac_sbc_same_buffer_flag + branch sbc_src_dst_addr_ptr_clr,blank + branch sbc_src_addr_ptr_clr + +// Use user flag to judge need wait or not +a2dp_media_first_buffer_cache_work: + bpatch patch16_5,mem_patch16 + disable user + fetch 1,mem_first_buffer_cache + rtnne FIRST_BUFFER_CACHE_ENABLE + + // set flag + arg LOG_POINT_1620,rega + fetcht 1,mem_media_cur_len + call debug_log_print + + enable user + // Get current cache packet cnt + fetch 1,mem_media_cur_len + // Max payload + fetcht 1,mem_l2cap_rx_malloc_num + //increase -1,temp + isub temp,null + nrtn positive + // cache success + jam 0,mem_first_buffer_cache + // init all param + branch disable_user + +a2dp_media_buffer_drop_packet_process: + call a2dp_update_min_receive_packet_size + fetch 1,mem_drop_or_add_process_state + rtnne TWS_DROP_OR_ADD_PROCESS_STATE_WAIT_DROP + fetch 2,mem_drop_or_add_min_receive_packet_size + fetcht 2,mem_l2cap_rx_pkt_length + isub temp,null + nrtn zero + + // set flag + arg LOG_POINT_1612,rega + fetcht 1,mem_media_cur_len + call debug_log_print + + // set flag + arg LOG_POINT_1613,rega + fetcht 2,mem_l2cap_rx_pkt_length + call debug_log_print + + jam TWS_DROP_OR_ADD_PROCESS_STATE_NONE,mem_drop_or_add_process_state + branch l2cap_call_proc_avdtp_media_free_packet + +a2dp_media_buffer_add_packet_process: + fetch 1,mem_drop_or_add_process_state + rtnne TWS_DROP_OR_ADD_PROCESS_STATE_WAIT_ADD + fetch 2,mem_a2dp_adjust_total_work_sample + nrtn blank + + // set flag + arg LOG_POINT_161A,rega + fetcht 1,mem_media_cur_len + call debug_log_print + + jam TWS_DROP_OR_ADD_PROCESS_STATE_NONE,mem_drop_or_add_process_state + rtn + +a2dp_media_buffer_add_drop_packet_judge: + fetch 1,mem_first_buffer_cache + beq FIRST_BUFFER_CACHE_ENABLE,a2dp_media_buffer_add_drop_packet_judge_end + call tws_check_master_slave_wait_sync_ok + branch a2dp_media_buffer_add_drop_packet_judge_end,user + + call a2dp_media_buffer_add_packet_judge + rtn user + call a2dp_media_buffer_drop_packet_judge + rtn user +a2dp_media_buffer_add_drop_packet_judge_end: + jam 0,mem_a2dp_buffer_judge_add + jam 0,mem_a2dp_buffer_judge_drop + rtn + +// rtn user: enable means tws in sync process, disable is not in +tws_check_master_slave_wait_sync_ok: + disable user + call tws_check_master_slave_connected + nrtn user + fetch 1,mem_tws_wait_sync_ok + nbranch enable_user,blank + branch disable_user + +a2dp_media_buffer_drop_packet_judge: + disable user + fetch 1,mem_param_a2dp_buffer_judge_drop_limit + rtn blank + fetch 1,mem_drop_or_add_process_state + rtnne TWS_DROP_OR_ADD_PROCESS_STATE_NONE + fetch 1,mem_media_in_fast_mode + nrtn blank + // Get current cache packet cnt + fetch 1,mem_media_cur_len + // Max payload + fetcht 1,mem_l2cap_rx_malloc_num + increase -1,temp + isub temp,null + nrtn positive + jam 0,mem_a2dp_buffer_judge_add + enable user + // If packet is near full, judge full cnt + fetch 1,mem_a2dp_buffer_judge_drop + increase 1,pdata + store 1,mem_a2dp_buffer_judge_drop + fetcht 1,mem_param_a2dp_buffer_judge_drop_limit + isub temp,null + nrtn positive +a2dp_media_buffer_drop_packet: + jam 0,mem_a2dp_buffer_judge_drop + + // set flag + arg LOG_POINT_1610,rega + fetcht 1,mem_media_cur_len + call debug_log_print + + call tws_check_master_slave_connected + branch a2dp_media_buffer_drop_packet_tws,user + +a2dp_media_buffer_drop_packet_normal: + branch l2cap_call_proc_avdtp_media_free_packet + +a2dp_media_buffer_drop_packet_tws: + fetch 1,mem_tws_state + rtnne TWS_STATE_SLAVE_CONNECTED + jam TWS_DROP_OR_ADD_PROCESS_STATE_INPROCESS,mem_drop_or_add_process_state + + jam TWS_SYNC_EVT_DROP_ONE_PACKET,mem_fifo_temp + branch tws_push_cmd_fifo + +a2dp_media_buffer_drop_packet_action: + // set flag + arg LOG_POINT_1611,rega + fetcht 1,mem_media_cur_len + call debug_log_print + jam TWS_DROP_OR_ADD_PROCESS_STATE_WAIT_DROP,mem_drop_or_add_process_state + rtn + +a2dp_media_buffer_add_packet_judge: + disable user + fetch 1,mem_param_a2dp_buffer_judge_add_limit + rtn blank + fetch 1,mem_drop_or_add_process_state + rtnne TWS_DROP_OR_ADD_PROCESS_STATE_NONE + fetch 1,mem_media_in_fast_mode + nrtn blank + // Get current cache packet cnt + fetch 1,mem_media_cur_len + sub pdata,1,null + nrtn positive + jam 0,mem_a2dp_buffer_judge_drop + enable user + // If packet is near empty, judge empty cnt + fetch 1,mem_a2dp_buffer_judge_add + increase 1,pdata + store 1,mem_a2dp_buffer_judge_add + fetcht 1,mem_param_a2dp_buffer_judge_add_limit + isub temp,null + nrtn positive +a2dp_media_buffer_add_packet: + jam 0,mem_a2dp_buffer_judge_add + + // set flag + arg LOG_POINT_1618,rega + fetcht 1,mem_media_cur_len + call debug_log_print + + + call tws_check_master_slave_connected + branch a2dp_media_buffer_add_packet_tws,user + +a2dp_media_buffer_add_packet_normal: + branch a2dp_media_buffer_add_packet_action + +a2dp_media_buffer_add_packet_tws: + fetch 1,mem_tws_state + rtnne TWS_STATE_SLAVE_CONNECTED + jam TWS_DROP_OR_ADD_PROCESS_STATE_INPROCESS,mem_drop_or_add_process_state + + jam TWS_SYNC_EVT_ADD_ONE_PACKET,mem_fifo_temp + branch tws_push_cmd_fifo + +a2dp_media_buffer_add_packet_action: + // set flag + arg LOG_POINT_1619,rega + fetcht 1,mem_media_cur_len + call debug_log_print + + // 1s align to 48000 + setarg 0xbb80 + store 4,mem_a2dp_adjust_total_work_sample + + // 21480000 = 20ms + setarg 0xA3E120 + store 4,mem_a2dp_adjust_delta_uk + jam 1,mem_a2dp_adjust_delta_uk_sign_bit + + jam TWS_DROP_OR_ADD_PROCESS_STATE_WAIT_ADD,mem_drop_or_add_process_state + rtn + + +avd_signal_parse_cmd: + bpatch patch16_6,mem_patch16 + ifetch 1,contr + and pdata,0x3f,pdata + store 1,mem_avdtp_signal_cmd + beq AVDTP_IDENTIFIER_DISCOVER,avd_signal_parse_cmd_discover + beq AVDTP_IDENTIFIER_GET_CAPABILITIES,avd_signal_parse_cmd_get_cap + beq AVDTP_IDENTIFIER_SET_CONFIGURATION,avd_signal_parse_cmd_set_conf + beq AVDTP_IDENTIFIER_GET_CONFIGURATION,avd_signal_parse_cmd_get_conf + beq AVDTP_IDENTIFIER_RECONFIGURE,avd_signal_parse_cmd_reconfig + beq AVDTP_IDENTIFIER_OPEN,avd_signal_parse_cmd_open + beq AVDTP_IDENTIFIER_START,avd_signal_parse_cmd_start + beq AVDTP_IDENTIFIER_CLOSE,avd_signal_parse_cmd_close + beq AVDTP_IDENTIFIER_SUSPEND,avd_signal_parse_cmd_suspend + beq AVDTP_IDENTIFIER_ABORT,avd_signal_parse_cmd_abort + beq AVDTP_IDENTIFIER_SECURITY_CONTROL,avd_signal_parse_cmd_security_control + beq AVDTP_IDENTIFIER_GET_ALL_CAPABILITIES,avd_signal_parse_cmd_get_all_cap + beq AVDTP_IDENTIFIER_DELAYREPORT,avd_signal_parse_cmd_delayreport + branch assert +avd_signal_parse_cmd_discover: + arg 4,rega + call avd_malloc_rsp_accept + setarg AVDTP_SEP1 + lshift2 pdata,pdata + istore 1,contw + setarg AVDTP_SEP1_CONFIG + istore 1,contw + branch l2cap_rx_reset_state +avd_signal_parse_cmd_get_cap: + ifetch 1,contr + rshift2 pdata,pdata + bne AVDTP_SEP1,avd_signal_rsp_reject + arg 16,rega + call avd_malloc_rsp_accept + //cap 1 + setarg AVDTP_CATEGORY_MEDIA_TRANS + istore 1,contw + setarg 0 + istore 1,contw + //cap 2 + setarg AVDTP_CATEGORY_CONTECT_PROTECT + istore 1,contw + setarg 2 + istore 1,contw + setarg AVD_CPTYPE_SCMS_T + istore 2,contw + //cap3 + setarg AVDTP_CATEGORY_MEDIA_CODEC + istore 1,contw + setarg 0x06 + istore 1,contw + fetch 6,mem_get_media_type + istore 6,contw + branch l2cap_rx_reset_state +avd_signal_parse_cmd_set_conf: + copy contr,pdata + fetchr rega,2,mem_l2cap_rx_pkt_length + iadd rega,rega + increase -2,rega + copy pdata,contr + + ifetch 2,contr +avd_analy_conf_loop: + //check end + copy contr,pdata + isub rega,null + branch avd_analy_conf_rsp,positive + //analy conf + ifetch 1,contr + storer contr,2,mem_contr + + arg AVDTP_CATEGORY_MEDIA_CODEC,temp + isub temp,null + call avd_analy_conf_codec_cap,zero + + fetch 2,mem_contr + copy pdata,contr + ifetch 1,contr + iadd contr,contr + branch avd_analy_conf_loop +avd_analy_conf_rsp: + arg 2,rega + call avd_malloc_rsp_accept + branch l2cap_rx_reset_state + +avd_analy_conf_codec_cap: + increase 1,contr //length&media type + ifetch 6,contr + store 6,mem_conf_media_type + rtn + +avd_signal_parse_cmd_open: + jam 11,mem_hp_avctp_timer + call a2dp_send_evt_open + jam A2DP_STATE_OPEN,mem_a2dp_state + branch avd_signal_parse_cmd_common + +avd_signal_parse_cmd_start: + call a2dp_send_evt_start + jam A2DP_STATE_START,mem_a2dp_state + jam AUDIO_STATE_IDLE,mem_audio_state +avd_signal_parse_cmd_common: + arg 2,rega + call avd_malloc_rsp_accept + branch l2cap_rx_reset_state + +avd_signal_parse_cmd_suspend: + call a2dp_send_evt_suspend + jam A2DP_STATE_SUSPEND,mem_a2dp_state + call avd_signal_parse_cmd_common + fetch 1,mem_telephone_dialing_state + rtneq HFP_DIALING_STATE_START + rtnmark1 mark_sco_flag + branch avd_stop_sbc_dac + +avd_signal_parse_cmd_close: + call a2dp_send_evt_close + jam A2DP_STATE_CLOSE,mem_a2dp_state + call avd_signal_parse_cmd_common + +avd_stop_sbc_dac: + jam AVD_AUDIO_FORBID,mem_audio_allow + call sbc_stop + branch audio_dac_stop + +avd_signal_parse_cmd_get_all_cap: + ifetch 1,contr + rshift2 pdata,pdata + bne AVDTP_SEP1,avd_signal_rsp_reject + arg 16,rega + call avd_malloc_rsp_accept + //cap 1 + setarg AVDTP_CATEGORY_MEDIA_TRANS + istore 1,contw + setarg 0 + istore 1,contw + //cap 2 + setarg AVDTP_CATEGORY_CONTECT_PROTECT + istore 1,contw + setarg 2 + istore 1,contw + setarg AVD_CPTYPE_SCMS_T + istore 2,contw + //cap3 + setarg AVDTP_CATEGORY_MEDIA_CODEC + istore 1,contw + setarg 0x06 + istore 1,contw + fetch 6,mem_get_media_type + istore 6,contw + branch l2cap_rx_reset_state + +avd_signal_parse_cmd_get_conf: +avd_signal_parse_cmd_reconfig: +avd_signal_parse_cmd_abort: +avd_signal_parse_cmd_security_control: +avd_signal_parse_cmd_delayreport: + branch assert + +avd_signal_parse_general_reject: +avd_signal_parse_rsp_reject: + branch l2cap_rx_reset_state + +avd_signal_parse_rsp_accept: + ifetch 1,contr + and pdata,0x3f,pdata + store 1,mem_avdtp_signal_cmd + beq AVDTP_IDENTIFIER_DISCOVER,avd_signal_parse_rsp_accept_discover + beq AVDTP_IDENTIFIER_GET_CAPABILITIES,avd_signal_parse_rsp_accept_getcap + beq AVDTP_IDENTIFIER_SET_CONFIGURATION,avd_signal_parse_rsp_accept_setconf + beq AVDTP_IDENTIFIER_OPEN,avd_sginal_parse_rsp_accept_open + branch l2cap_rx_reset_state + +avd_signal_parse_rsp_accept_discover: + //fetchr rega,2,mem_l2cap_rx_pkt_length + //increase -2,rega + //set0 0,rega + ifetch 1,contr + rshift2 pdata,pdata + store 1,mem_audio_src_endpoint + ifetch 1,contr +//avd_signal_parse_rsp_accept_discover_loop: + //increase -2,rega + branch l2cap_rx_reset_state +avd_signal_src_inuse: + call upper_reset_sm + branch l2cap_rx_reset_state + +avd_signal_parse_rsp_accept_getcap2: + fetch 1,mem_audio_src_endpoint_state + set1 AVD_SRC_ENDPOINT_GETCAP,pdata + store 1,mem_audio_src_endpoint_state + branch l2cap_rx_reset_state + +avd_signal_parse_rsp_accept_getcap: + copy contr,pdata + fetchr rega,2,mem_l2cap_rx_pkt_length + iadd rega,rega + increase -2,rega + copy pdata,contr +avd_signal_parse_rsp_accept_getcap_loop: + copy contr,pdata + isub rega,null + branch avd_signal_parse_rsp_accept_getcap2,positive + ifetch 1,contr + storer contr,2,mem_contr + arg AVDTP_CATEGORY_MEDIA_CODEC,temp + isub temp,null + call avd_signal_parse_rsp_getcap,zero + fetch 2,mem_contr + copy pdata,contr + ifetch 1,contr + iadd contr,contr + branch avd_signal_parse_rsp_accept_getcap_loop + +avd_signal_parse_rsp_getcap: + ifetch 1,contr + ifetch 6,contr + store 6,mem_get_r_media_type + rtn + +avd_signal_parse_rsp_accept_setconf: + fetch 1,mem_audio_src_endpoint_state + set1 AVD_SRC_ENDPOINT_SETCONF,pdata + store 1,mem_audio_src_endpoint_state + branch l2cap_rx_reset_state + +avd_sginal_parse_rsp_accept_open: + fetch 1,mem_audio_src_endpoint_state + set1 AVD_SRC_ENDPOINT_OPEN,pdata + store 1,mem_audio_src_endpoint_state + branch l2cap_rx_reset_state + +avd_signal_prase_uncomplete: + branch avd_signal_prase_uncomplete + +avd_signal_rsp_reject: + bpatch patch16_7,mem_patch16 + arg 2,rega + call l2cap_malloc_server_channel + setarg AVDTP_MESSGAE_TYPE_RSP_REJECT + branch avd_org_res + +avd_malloc_rsp_accept: + bpatch patch17_0,mem_patch17 + call l2cap_malloc_server_channel + setarg AVDTP_MESSGAE_TYPE_RSP_ACCEPT +avd_org_res: + fetcht 1,mem_transaction_label + lshift4 temp,temp + ior temp,pdata + istore 1,contw + fetch 1,mem_avdtp_signal_cmd + istore 1,contw + rtn + +avd_malloc_cmd: + fetch 1,mem_transaction_label + increase 1,pdata + store 1,mem_transaction_label + fetchr regd,2,mem_avdtpsignal_l2capch_ptr + call l2cap_malloc_server_channel + setarg AVDTP_MESSAGE_TYPE_CMD + branch avd_org_res + +avd_signal_send_discover: + jam AVDTP_IDENTIFIER_DISCOVER,mem_avdtp_signal_cmd + arg 2,rega + branch avd_malloc_cmd + +avd_signal_send_getcap: + jam AVDTP_IDENTIFIER_GET_CAPABILITIES,mem_avdtp_signal_cmd + arg 3,rega + call avd_malloc_cmd + fetch 1,mem_audio_src_endpoint + lshift2 pdata,pdata + istore 1,contw + rtn + +avd_signal_send_setconf: + jam AVDTP_IDENTIFIER_SET_CONFIGURATION,mem_avdtp_signal_cmd + arg 14,rega + call avd_malloc_cmd + fetch 1,mem_audio_src_endpoint + lshift2 pdata,pdata + istore 1,contw + arg 4,pdata //int seid = 1 + istore 1,contw + setarg 0x070001 + istore 3,contw + setarg 0x000006 + istore 3,contw + fetch 1,mem_get_r_samplefreq_channelmode + bbit1 5,avd_signal_send_setconf_44_1k + bbit1 4,avd_signal_send_setconf_48k +avd_signal_send_setconf_44_1k: + setarg 0x1521 + istore 2,contw + fetch 2,mem_get_min_bitpool + istore 2,contw + jam AVDTP_SAMPLE_FREQ_44K1,mem_conf_samplefreq_channelmode + rtn + +avd_signal_send_setconf_48k: + setarg 0x1511 + istore 2,contw + fetch 2,mem_get_min_bitpool + istore 2,contw + jam AVDTP_SAMPLE_FREQ_48K,mem_conf_samplefreq_channelmode + rtn + + +avd_signal_send_open: + jam AVDTP_IDENTIFIER_OPEN,mem_avdtp_signal_cmd + arg 3,rega + call avd_malloc_cmd + fetch 1,mem_audio_src_endpoint + lshift2 pdata,pdata + istore 1,contw + rtn + +a2dp_send_evt_open: + jam A2DP_STATE_OPEN,mem_fifo_temp + branch ipc_tx_a2dp_event +a2dp_send_evt_start: + jam A2DP_STATE_START,mem_fifo_temp + branch ipc_tx_a2dp_event +a2dp_send_evt_close: + jam A2DP_STATE_CLOSE,mem_fifo_temp + branch ipc_tx_a2dp_event +a2dp_send_evt_suspend: + jam A2DP_STATE_SUSPEND,mem_fifo_temp + branch ipc_tx_a2dp_event + + + + +a2dp_check_need_cal_media_frame_info: + // set flag + arg LOG_POINT_1603,rega + fetcht 2,mem_a2dp_seq_num + call debug_log_print + + // Only work for tws connected + call tws_check_master_slave_connected + nrtn user + + // Check seq is right or not + call a2dp_check_need_cal_media_frame_info_seq_check + nrtn blank + + fetch 2,mem_a2dp_seq_num + store 2,mem_process_a2dp_seq_num + + branch tws_save_media_process_info + + +a2dp_check_need_cal_media_frame_info_seq_check: + fetch 1,mem_media_in_fast_mode + arg 0x7f,temp + branch a2dp_check_need_cal_media_frame_info_seq_check_0,blank + arg 0x07,temp +a2dp_check_need_cal_media_frame_info_seq_check_0: + fetch 2,mem_a2dp_seq_num + iand temp,pdata + rtn + +endif Index: tag/Soft/Librarier/bt_rom/program/app.prog =================================================================== --- /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/app.prog (nonexistent) +++ /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/app.prog (working copy) @@ -0,0 +1,523 @@ + +app_init: + bpatch patch17_1,mem_patch17 + fetch 1,mem_device_option + branch app_init,blank /* wait ram to be initialized */ + beq dvc_op_hci,hci_init + beq dvc_op_test,test_init + beq dvc_op_headset,headset_init + rtn + +app_lpm_init: + jam 0,mem_tester_emulate + jam 0,mem_debug_config + jam 0, mem_lch_code + setarg 0 + store 5,mem_sp_state_start + rtn + + +app_process_idle: + call ui_dispatch + call check_51cmd + call app_process_bb_event + call ipc_rx_process + call ipc_check_m0_state + fetch 2,mem_cb_idle_process + branch callback_func + +app_process_bt: + fetch 2,mem_cb_bt_process + branch callback_func + +app_process_ble: + fetch 2,mem_cb_le_process + branch callback_func + +app_process_bb_event: + bpatch patch17_2,mem_patch17 + //return if c51 need to process bb event + arg mem_ipc_fifo_bt2c51,rega + call fifo_out + rtn blank + //reaching here mains c51 cannot get bb event. + copy pdata,regc + call app_event_normal_process + branch app_process_bb_event_priority + +app_discard_event: + arg 0,regc + rtn + +//************************************************// +//*APP BB EVENT NORMAL PROCESS**// +//************************************************// +app_event_normal_process: + beq BT_EVT_BB_CONNECTED,app_evt_bt_conn + beq BT_EVT_BUTTON_LONG_PRESSED,app_evt_button_long_pressed + beq BT_EVT_SETUP_COMPLETE,app_evt_setup_complete + beq BT_EVT_HID_HANDSHAKE,app_evt_hid_handshake + beq BT_EVT_HID_CONNECTED,app_bb_event_hid_connected + beq BT_EVT_RECONN_FAILED,app_bb_event_reconn_failed + beq BT_EVT_BB_DISCONNECTED,app_bb_event_bb_disconn + beq BT_EVT_RECONN_PAGE_TIMEOUT,app_bb_event_reconn_failed + beq BT_EVT_LE_CONNECTED,app_le_event_bb_connected + beq BT_EVT_LE_DISCONNECTED,app_le_event_bb_disconn + beq BT_EVT_RECONN_STARTED,app_event_reconn_start + beq BT_EVT_ENTER_SNIFF,app_event_enter_sniff + beq BT_EVT_EXIT_SNIFF,app_event_exit_sniff + + beq BT_EVT_LINKKEY_GENERATE,app_event_linkkey_generate + beq BT_EVT_SWITCH_FAIL_MASTER,app_event_switch_fail_master + beq BT_EVT_SWITCH_SUCCESS_MASTER,app_event_switch_success + beq BT_EVT_START_PAGE,app_event_start_page + rtn + +app_evt_bt_conn: + fetch 2,mem_ui_state_map + set1 UI_STATE_BT_CONNECTED,pdata + store 2,mem_ui_state_map + fetch APP_DISC_RSN_SIZE,mem_app_disconn_reason_flag + set0 APP_DISC_BY_BUTTON ,pdata + store APP_DISC_RSN_SIZE,mem_app_disconn_reason_flag + branch app_bt_stop_discovery + +app_event_switch_success: + jam 0,mem_switch_fail_master_count + rtn + +app_event_switch_fail_master: + fetch 1,mem_switch_fail_master_count + increase 1,pdata + store 1,mem_switch_fail_master_count + sub pdata,1,null + branch app_bt_role_switch,positive + jam 0,mem_switch_fail_master_count + fetch APP_DISC_RSN_SIZE,mem_app_disconn_reason_flag + set1 APP_DISC_SWITCH_FAIL,pdata + store APP_DISC_RSN_SIZE,mem_app_disconn_reason_flag + branch app_bt_disconnect + +app_event_start_page: + fetch APP_DISC_RSN_SIZE,mem_app_disconn_reason_flag + set1 APP_DISC_AFTER_PAGE ,pdata + store APP_DISC_RSN_SIZE,mem_app_disconn_reason_flag + rtn + +app_process_bb_event_priority: + fetch 2,mem_cb_bb_event_process + branch callback_func + +app_check_wake_lock: + fetch 2,mem_cb_check_wakelock + branch callback_func + +app_will_enter_lpm: + fetch 2,mem_cb_before_lpm + branch callback_func + +app_check_keyscan: + fetch 1,core_lpm_ldocnt + rtnbit0 gpio_latch + rtnbit1 cold_wake + fetch 1,core_lpm_ldotrim + rtnbit0 reload_code + fetch 2,mem_cb_keyscan + rtn blank + branch callback_func + +app_event_linkkey_generate: + fetch APP_DISC_RSN_SIZE,mem_app_disconn_reason_flag + set1 APP_DISC_AFTER_PAIRING ,pdata + store APP_DISC_RSN_SIZE,mem_app_disconn_reason_flag + rtn +// branch app_bt_store_reconn_info + +app_event_reconn_start: + fetch 2,mem_ui_state_map + set1 UI_STATE_BT_RECONNECT,pdata + store 2,mem_ui_state_map + fetch APP_DISC_RSN_SIZE,mem_app_disconn_reason_flag + set1 APP_DISC_AFTER_RECONN,pdata + store APP_DISC_RSN_SIZE,mem_app_disconn_reason_flag + rtn + +app_evt_setup_complete: + fetch 2,mem_ui_state_map + set1 UI_STATE_BT_SETUP_COMPLETE,pdata + store 2,mem_ui_state_map + fetch APP_DISC_RSN_SIZE,mem_app_disconn_reason_flag + set1 APP_DISC_AFTER_SETUP_DONE,pdata + store APP_DISC_RSN_SIZE,mem_app_disconn_reason_flag + rtn + +app_evt_hid_handshake: + fetch 2,mem_ui_state_map + set1 UI_STATE_BT_HID_HANDSHAKE,pdata + store 2,mem_ui_state_map + rtn + +app_event_enter_sniff: + fetch 2,mem_ui_state_map + set1 UI_STATE_BT_SNIFF,pdata + store 2,mem_ui_state_map + fetch APP_DISC_RSN_SIZE,mem_app_disconn_reason_flag + set1 APP_DISC_AFTER_SNIFF,pdata + store APP_DISC_RSN_SIZE,mem_app_disconn_reason_flag + rtn + +app_event_exit_sniff: + fetch 2,mem_ui_state_map + set0 UI_STATE_BT_SNIFF,pdata + store 2,mem_ui_state_map + rtn + +app_le_event_bb_connected: + fetch 2,mem_ui_state_map + set1 UI_STATE_BLE_CONNECTED,pdata + store 2,mem_ui_state_map + rtn + +app_le_event_bb_disconn: + fetch 2,mem_ui_state_map + set0 UI_STATE_BLE_CONNECTED,pdata + store 2,mem_ui_state_map + branch app_lpm_mult_disable + +app_bb_event_hid_connected: + fetch 2,mem_ui_state_map + set1 UI_STATE_BT_HID_CONN,pdata + store 2,mem_ui_state_map + rtn + +app_evt_button_long_pressed: + fetch APP_DISC_RSN_SIZE,mem_app_disconn_reason_flag + set1 APP_DISC_BY_BUTTON,pdata + store APP_DISC_RSN_SIZE,mem_app_disconn_reason_flag + rtn + + + +app_evt_timer: + store 1,mem_app_evt_timer_count + bpatch patch17_3,mem_patch17 + // For cm0 timer + call ipc_100ms_timer_work +app_evt_100ms_loop: + fetch 1,mem_app_evt_timer_count + rtn blank + increase -1,pdata + store 1,mem_app_evt_timer_count + + call tws_100ms_event_polling + + call app_debug_current_state + + + fetch 2,mem_cb_event_timer + call callback_func + branch app_evt_100ms_loop + +app_debug_current_state: + arg mem_app_debug_info_timer,regc + call timer_single_step + nrtn user + + arg LOG_POINT_1400,rega + fetcht 1,mem_tws_state + call debug_log_print + + arg LOG_POINT_1402,rega + fetcht 1,mem_scan_mode + call debug_log_print + + arg LOG_POINT_1403,rega + fetcht 1,mem_le_adv_enable + call debug_log_print + + arg LOG_POINT_1404,rega + fetcht 1,mem_le_scan_enable + call debug_log_print + + arg LOG_POINT_1405,rega + fetcht 2,mem_ui_state_map + call debug_log_print + + fetch 1,mem_param_app_debug_info_timeout + store 1,mem_app_debug_info_timer + rtn + +app_bb_event_reconn_failed: + call app_disconn_reason_flag_clear + fetch 2,mem_ui_state_map + set0 UI_STATE_BT_RECONNECT,pdata + store 2,mem_ui_state_map + fetch APP_DISC_RSN_SIZE,mem_app_disconn_reason_flag + set0 APP_DISC_AFTER_PAGE ,pdata + store APP_DISC_RSN_SIZE,mem_app_disconn_reason_flag + rtn + +app_bb_event_bb_disconn: + fetch 2,mem_ui_state_map + bbit1 UI_STATE_BT_RECONNECT,app_bb_event_bb_reconn_disconn + isolate0 UI_STATE_BT_SETUP_COMPLETE,pdata + call app_discard_event,true +app_bb_event_bb_reconn_disconn: + fetch 2,mem_ui_state_map + set0 UI_STATE_BT_CONNECTED,pdata + set0 UI_STATE_BT_SETUP_COMPLETE,pdata + set0 UI_STATE_BT_HID_CONN,pdata + set0 UI_STATE_BT_HID_HANDSHAKE,pdata + set0 UI_STATE_BT_SPP_CONN,pdata + set0 UI_STATE_BT_RECONNECT,pdata + store 2,mem_ui_state_map + branch app_lpm_mult_disable + +app_bb_hibernate: + call app_disconn_reason_clear + branch app_enter_hibernate + + +app_disconn_reason_clear: + setarg 0 + store APP_DISC_RSN_SIZE,mem_app_disconn_reason + rtn +app_disconn_reason_flag_clear: + setarg 0 + store APP_DISC_RSN_SIZE,mem_app_disconn_reason_flag + rtn + + +app_disconn_reason_collect_bt: + fetch APP_DISC_RSN_SIZE,mem_app_disconn_reason_flag + store APP_DISC_RSN_SIZE,mem_app_disconn_reason + setarg 0 + store APP_DISC_RSN_SIZE,mem_app_disconn_reason_flag + rtn + +app_disconn_reason_collect_ble: + fetch APP_DISC_RSN_SIZE,mem_app_disconn_reason_flag + set1 APP_DISC_BLE,pdata + store APP_DISC_RSN_SIZE,mem_app_disconn_reason + setarg 0 + store APP_DISC_RSN_SIZE,mem_app_disconn_reason_flag + rtn + + +//************************************************// +//********APP SHARED FUNCSIONS*******// +//************************************************// +app_le_check_reconn_target: + fetch 1,mem_ltk_exists + branch app_le_check_reconn_target_none,blank + branch app_ble_start_direct_adv +app_le_check_reconn_target_none: + branch app_ble_start_adv + +app_check_plap: + bpatch patch17_4,mem_patch17 + arg mem_check_plap_temp,regb + arg app_check_one_plap,regc + branch context_search + +app_check_one_plap: + arg 0,temp + bbit0 state_inconn,app_check_one_plap_next + add rega,coffset_plap,contr + ifetcht 6,contr +app_check_one_plap_next: + copy temp,pdata + ncall app_check_one_plap_device_exist,blank + istoret 6,regb + increase 6,regb + branch context_search_next +app_check_one_plap_device_exist: + fetch 1,mem_device_nums + increase 1,pdata + store 1,mem_device_nums + rtn + +app_check_conn_device_nums_addr: + jam 0,mem_device_nums + branch app_check_plap + +app_check_sniff: + fetch 1,mem_ui_state_map + isolate1 UI_STATE_BT_SNIFF,pdata + rtn + +//*****************************************// +//*****************API********************// +//*****************************************// +app_get_lpm_wake_lock: + arg wake_lock_app,queue + branch lpm_get_wake_lock + +app_put_lpm_wake_lock: + arg wake_lock_app,queue + branch lpm_put_wake_lock + + +app_l2cap_flow_control_enable: + jam L2CAP_FLOW_CTRL_ENABLE,mem_l2cap_flow_ctrl_flag + rtn + +app_l2cap_flow_control_disable: + jam L2CAP_FLOW_CTRL_DISABLE,mem_l2cap_flow_ctrl_flag + rtn + +app_bt_set_pincode: + jam BT_CMD_SET_PIN_CODE,mem_fifo_temp + branch ui_ipc_send_cmd + +app_bt_role_switch: + jam BT_CMD_ROLE_SWITCH,mem_fifo_temp + branch ui_ipc_send_cmd + +app_bt_start_reconnect: + fetch 1,mem_app_connection_options + store 1,mem_connection_options + jam 1,mem_link_key_exists + jam BT_CMD_RECONNECT,mem_fifo_temp + branch ui_ipc_send_cmd + +app_bt_start_reconnect_and_discover: + call app_bt_start_reconnect + branch app_bt_start_discovery + +app_bt_reconnect_cancel: + jam BT_CMD_BB_RECONN_CANCEL,mem_fifo_temp + branch ui_ipc_send_cmd + +app_bt_disconnect: + jam BT_CMD_DISCONNECT,mem_fifo_temp + branch ui_ipc_send_cmd + + +app_bt_start_discovery: + bpatch patch17_5,mem_patch17 + fetch 2,mem_discovery_timeout + store 2,mem_discovery_timer_count + jam BT_CMD_START_DISCOVERY,mem_fifo_temp + branch ui_ipc_send_cmd + +app_bt_stop_discovery: + setarg 0 + store 2,mem_discovery_timer_count + jam BT_CMD_STOP_DISCOVERY,mem_fifo_temp + branch ui_ipc_send_cmd + +app_ble_start_direct_adv: + jam BT_CMD_START_DIRECT_ADV,mem_fifo_temp + branch ui_ipc_send_cmd + +app_ble_stop_direct_adv: + jam BT_CMD_STOP_DIRECT_ADV,mem_fifo_temp + branch ui_ipc_send_cmd + +app_ble_stop_adv: + jam BT_CMD_STOP_ADV,mem_fifo_temp + branch ui_ipc_send_cmd + +app_ble_start_adv: + jam BT_CMD_START_ADV,mem_fifo_temp + branch ui_ipc_send_cmd + +app_ble_start_scan: + jam BT_CMD_LE_START_SCAN,mem_fifo_temp + branch ui_ipc_send_cmd + +app_ble_stop_scan: + jam BT_CMD_LE_STOP_SCAN,mem_fifo_temp + branch ui_ipc_send_cmd + +app_ble_start_conn: + jam BT_CMD_LE_START_CONN,mem_fifo_temp + branch ui_ipc_send_cmd + +app_ble_disconnect: + jam BT_CMD_LE_DISCONNECT,mem_fifo_temp + branch ui_ipc_send_cmd + + +app_enter_hibernate: + jam BT_CMD_ENTER_HIBERNATE,mem_fifo_temp + branch ui_ipc_send_cmd + +app_bt_sniff_exit: + jam BT_CMD_EXIT_SNIFF,mem_fifo_temp + branch ui_ipc_send_cmd + +app_bt_enter_sniff: + jam BT_CMD_ENTER_SNIFF,mem_fifo_temp + branch ui_ipc_send_cmd + +app_ble_store_reconn_info: + jam BT_CMD_STORE_RECONN_INFO_LE,mem_fifo_temp + branch ui_ipc_send_cmd + +app_bt_store_reconn_info: + jam BT_CMD_STORE_RECONN_INFO_BT,mem_fifo_temp + branch ui_ipc_send_cmd + +app_lpm_mult_enable: + set1 mark_lpm_mult_enable,mark + rtn + +app_lpm_mult_disable: + set0 mark_lpm_mult_enable,mark + rtn + +app_bt_esco_req: + jam BT_CMD_EST_ESCO_REQ,mem_fifo_temp + branch ui_ipc_send_cmd + +app_bt_rmv_esco_req: + jam BT_CMD_RMV_ESCO_REQ,mem_fifo_temp + branch ui_ipc_send_cmd + +app_bt_sco_req: + jam BT_CMD_EST_SCO_REQ,mem_fifo_temp + branch ui_ipc_send_cmd + +app_bt_rmv_sco_req: + jam BT_CMD_RMV_SCO_REQ,mem_fifo_temp + branch ui_ipc_send_cmd + +app_bt_play_pause: + jam BT_CMD_PLAY_PAUSE ,mem_fifo_temp + branch ui_ipc_send_cmd + +app_bt_backward: + jam BT_CMD_BACKWARD ,mem_fifo_temp + branch ui_ipc_send_cmd + +app_bt_forward: + jam BT_CMD_FORWARD ,mem_fifo_temp + branch ui_ipc_send_cmd + +app_bt_vol_up: + jam BT_CMD_VOL_UP,mem_fifo_temp + branch ui_ipc_send_cmd + +app_bt_vol_down: + jam BT_CMD_VOL_DOWN,mem_fifo_temp + branch ui_ipc_send_cmd + +app_bt_accept_call: + jam BT_CMD_ACCEPT_CALL,mem_fifo_temp + branch ui_ipc_send_cmd + +app_bt_hang_up: + jam BT_CMD_HANG_UP,mem_fifo_temp + branch ui_ipc_send_cmd + +app_bt_redial: + jam BT_CMD_REDIAL,mem_fifo_temp + branch ui_ipc_send_cmd + +app_bt_recognition: + jam BT_CMD_RECOGNITION,mem_fifo_temp + branch ui_ipc_send_cmd + + Index: tag/Soft/Librarier/bt_rom/program/audio.prog =================================================================== --- /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/audio.prog (nonexistent) +++ /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/audio.prog (working copy) @@ -0,0 +1,2261 @@ + + +/////////////////////////////////////// AUDIO DAC ////////////////////////////// + +audio_dac_init_mono: + jam 1,mem_mono_flag + jam DIN_SEL_L_LEFT_CHANNEL,mem_l_din_sel + jam DIN_SEL_R_LEFT_CHANNEL,mem_r_din_sel + branch audio_dac_init + +audio_dac_init_stero: + jam 0,mem_mono_flag + jam DIN_SEL_L_LEFT_CHANNEL,mem_l_din_sel + jam DIN_SEL_R_RIGHT_CHANNEL,mem_r_din_sel + branch audio_dac_init + + +audio_dac_init_tws_left_mono: + jam 1,mem_mono_flag + jam DIN_SEL_L_LEFT_CHANNEL,mem_l_din_sel + jam DIN_SEL_R_CLOSE,mem_r_din_sel + branch audio_dac_init + +audio_dac_init_tws_left_stero: + jam 1,mem_mono_flag // In tws only have one channel audio media + jam DIN_SEL_L_LEFT_CHANNEL,mem_l_din_sel + jam DIN_SEL_R_CLOSE,mem_r_din_sel + branch audio_dac_init + +audio_dac_init_tws_right_mono: + jam 1,mem_mono_flag + jam DIN_SEL_R_CLOSE,mem_l_din_sel + jam DIN_SEL_R_LEFT_CHANNEL,mem_r_din_sel + branch audio_dac_init + +audio_dac_init_tws_right_stero: + jam 1,mem_mono_flag // In tws only have one channel audio media + jam DIN_SEL_R_CLOSE,mem_l_din_sel + jam DIN_SEL_R_LEFT_CHANNEL,mem_r_din_sel + branch audio_dac_init + +audio_dac_init_media: + bpatch patch17_6,mem_patch17 + fetch 1,mem_audio_output_setting + beq AUDIO_OUTPUT_TWS_SINGLE_EAR_LEFT,audio_dac_init_tws_left_stero + beq AUDIO_OUTPUT_TWS_SINGLE_EAR_RIGHT,audio_dac_init_tws_right_stero + branch audio_dac_init_stero + +audio_dac_init_vp_call: + bpatch patch17_7,mem_patch17 + fetch 1,mem_audio_output_setting + beq AUDIO_OUTPUT_TWS_SINGLE_EAR_LEFT,audio_dac_init_tws_left_mono + beq AUDIO_OUTPUT_TWS_SINGLE_EAR_RIGHT,audio_dac_init_tws_right_mono + branch audio_dac_init_mono + +audio_dac_init: + bpatch patch18_0,mem_patch18 + fetch 2 ,core_clkoff + set0 CLOCK_OFF_AUDIO_DAC,pdata + store 2,core_clkoff + fetch 2,core_dac_sel2 + set0 DAC_ANA_CLK_EN,pdata + store 2,core_dac_sel2 + call audio_dac_set_l + call audio_dac_set_r + call audio_dac_mono_stero + call audio_dac_filter + call audio_dac_sdm + + call audio_dac_set_sample_rate + + call audio_dac_vol_adjust + fetch 1,mem_dac_mram_flag + call audio_dac_mram_sel + + fetch 1,core_dac_ctrl + set0 DAC_CONTINUOUS_MODE,pdata + set0 DAC_MUTU,pdata + store 1,core_dac_ctrl + + fetch 2,mem_dac_start_addr + store 2,core_dac_saddr + store 2,core_dac_wptr + store 2,core_dac_rptr + fetch 2,mem_dac_buf_size + increase -1,pdata + store 2,core_dac_len + +audio_dac_start: + fetch 1,core_dac_ctrl + set1 DAC_ENABLE,pdata + store 1,core_dac_ctrl + rtn + +audio_dac_mono_stero: + fetch 1,mem_mono_flag + branch audio_dac_stero,blank +audio_dac_mono: + fetch 1,core_dac_sel + set1 0,pdata + store 1,core_dac_sel + rtn + +audio_dac_stero: + fetch 1,core_dac_sel + set0 0,pdata + store 1,core_dac_sel + rtn + +audio_dac_set_sample_rate: + bpatch patch18_1,mem_patch18 + fetch 2,core_dac_sel2 + set0 DAC_ANA_CLK_EN,pdata + store 2,core_dac_sel2 + fetch 1,core_dac_ctrl + set0 DAC_INIT_FILTER,pdata + set0 DAC_SDM,pdata + store 1,core_dac_ctrl + + call audio_dlychain_dac_init + + call audio_dac_clk_check + fetch 1,core_dac_sel + and pdata,0xf3,pdata + ior temp,pdata + store 1,core_dac_sel + nop 200 + call audio_dac_coef_init + + call audio_dac_filter + call audio_dac_sdm + nop 1000 + branch audio_dac_ana_clk_en + + +//return temp +audio_dac_clk_check: + bpatch patch18_2,mem_patch18 + fetch 1,mem_dac_clk + beq 8,audio_dac_samplefreq_sel_8k + beq 16,audio_dac_samplefreq_sel_16k + beq 48,audio_dac_samplefreq_sel_48k +// beq 44,audio_dac_samplefreq_sel_44k +audio_dac_samplefreq_sel_44k: + call audio_load_dac_44k_coef + arg 0,temp +audio_dac_analog_sel_44k: + fetch 1,rf_rx_ib_lna + set0 0,pdata + store 1,rf_rx_ib_lna + rtn + +audio_dac_samplefreq_sel_48k: + call audio_load_dac_48k_coef + arg 0,temp + branch audio_dac_analog_sel_48k + +audio_dac_analog_sel_48k: + fetch 1,rf_rx_ib_lna + set1 0,pdata + store 1,rf_rx_ib_lna + rtn + +audio_dac_samplefreq_sel_8k: + call audio_load_dac_8k_coef + arg 8,temp + branch audio_dac_analog_sel_48k + +audio_dac_samplefreq_sel_16k: + call audio_load_dac_16k_coef + arg 4,temp + branch audio_dac_analog_sel_48k + + +audio_dlychain_dac_init: + setarg 0 + store 3,core_coef_wdata + fetch 1,core_coef_ctrl + set0 0,pdata + store 1,core_coef_ctrl + set1 0,pdata + store 1,core_coef_ctrl + arg 32,loopcnt +audio_dlychain_dac_init_loop: + set1 1,pdata + store 1,core_coef_ctrl + nop 60 //5us + set0 1,pdata + store 1,core_coef_ctrl + nop 60 + loop audio_dlychain_dac_init_loop + + set0 0,pdata + store 1,core_coef_ctrl + rtn + +audio_dac_coef_init: + fetch 1,core_coef_ctrl + set0 2,pdata + store 1,core_coef_ctrl + set1 2,pdata + store 1,core_coef_ctrl + arg 64 ,loopcnt + arg mem_coef_table_temp,contr + call audio_coef_init_loop + set0 2,pdata + store 1,core_coef_ctrl + rtn + +audio_coef_init_loop: + ifetcht 3,contr + rshift4 temp,temp + storet 3,core_coef_wdata + set1 3,pdata + store 1,core_coef_ctrl + nop 60 + set0 3,pdata + store 1,core_coef_ctrl + nop 60 + loop audio_coef_init_loop + rtn + + +audio_get_coef_start_addr: + fetch 3,mem_coef_base_addr + fetcht 3,mem_storage_start_addr + iadd temp,pdata + rtn + +audio_load_dac_48k_coef: + call audio_get_coef_start_addr + arg COEF_DAC_TABLE_48K_OFFSET,temp +audio_load_dac_coef_common: + iadd temp,pdata + store 3,mem_flash_address + arg COEF_DAC_TABLE_LENGTH,pdata +audio_load_coef_common: + store 2,mem_flash_trans_length + arg mem_coef_table_temp,pdata + store 2,mem_flash_data_address + branch qspi_read + +audio_load_dac_44k_coef: + call audio_get_coef_start_addr + arg COEF_DAC_TABLE_44K_OFFSET,temp + branch audio_load_dac_coef_common + +audio_load_dac_8k_coef: +audio_load_dac_16k_coef: + call audio_get_coef_start_addr + arg COEF_DAC_TABLE_8K_OFFSET,temp + branch audio_load_dac_coef_common + + +audio_dac_set_l: + fetch 1,mem_l_din_sel + beq DIN_SEL_L_CLOSE,audio_dac_close_l + fetch 1,core_dac_sel2 + set1 core_dac_sel2_clk_en_l,pdata //enable clk + and pdata,0xfc,pdata + fetcht 1,mem_l_din_sel + ior temp,pdata + store 1,core_dac_sel2 + rtn + +audio_dac_close_l: + fetch 1,core_dac_sel2 + set0 core_dac_sel2_clk_en_l,pdata //disable clk + store 1,core_dac_sel2 + rtn + +audio_dac_set_r: + fetch 1,mem_r_din_sel + beq DIN_SEL_R_CLOSE,audio_dac_close_r + fetch 1,core_dac_sel2 + set1 core_dac_sel2_clk_en_r,pdata //enable clk + and pdata,0xcf,pdata + fetcht 1,mem_r_din_sel + ior temp,pdata + store 1,core_dac_sel2 + rtn + +audio_dac_close_r: + fetch 1,core_dac_sel2 + set0 core_dac_sel2_clk_en_r,pdata //disable clk + store 1,core_dac_sel2 + rtn + +audio_dac_ana_clk_en: + fetch 2,core_dac_sel2 + set1 DAC_ANA_CLK_EN,pdata + store 2,core_dac_sel2 + rtn + +audio_dac_filter: + fetch 1,core_dac_ctrl + set1 DAC_INIT_FILTER,pdata + store 1,core_dac_ctrl + rtn + +audio_dac_sdm: + fetch 1,core_dac_ctrl + set1 DAC_SDM,pdata + store 1,core_dac_ctrl + rtn + +audio_dac_mram: + jam 1,mem_dac_mram_flag + rtn + +audio_dac_sched_ram: + jam 0,mem_dac_mram_flag + rtn + +//input pdata, 1: mram; 0 :not mram +audio_dac_mram_sel: + fetcht 1,core_dac_ctrl + nsetflag blank,DAC_MRAM_SEL,temp + storet 1,core_dac_ctrl + rtn + + +audio_dac_stop: + bpatch patch18_3,mem_patch18 + fetch 1,core_dac_ctrl + set0 DAC_ENABLE,pdata + store 1,core_dac_ctrl + jam 0,mem_dac_clk + nop 6000 //500us + setarg 0 + store 1,core_dac_lvol + store 1,core_dac_rvol + call eq_disable +audio_dac_clk_off: + fetch 2 ,core_clkoff + set1 CLOCK_OFF_AUDIO_DAC,pdata + set1 CLOCK_OFF_VOICE_FILTER,pdata + branch store_clkoff + +audio_dac_vol_adjust: + bpatch patch18_4,mem_patch18 + fetch 1,mem_hf_vlm_speaker + mul32 pdata,15,pdata + rshift2 pdata,pdata + fetcht 1,core_dac_lvol + isub temp,null + rtn zero +audio_dac_vol_adjust_end: + store 1,core_dac_lvol + store 1,core_dac_rvol + rtn + +audio_dac_mute_vol: + // set flag + arg LOG_POINT_1640,rega + fetcht 1,mem_tws_state + call debug_log_print + + setarg 0 + branch audio_dac_vol_adjust_end + +// out: pdata: use buffer size +audio_dac_hw_get_use_count: + bpatch patch18_5,mem_patch18 + fetch 2,core_dac_wptr + fetcht 2,core_dac_rptr + isub temp,pdata + rtn positive + fetch 2,core_dac_rptr + fetcht 2,core_dac_wptr + isub temp,temp + fetch 2,core_dac_len + isub temp,pdata + rtn + +// out: pdata: reserve buffer size +audio_dac_hw_get_reserve_count: + call audio_dac_hw_get_use_count + copy pdata,temp + fetch 2,core_dac_len + isub temp,pdata + rtn + +audio_dac_hw_check_empty: + fetch 2,core_dac_wptr + fetcht 2,core_dac_rptr + isub temp,null + rtn + +audio_dac_hw_get_write_ptr_right_reserve_buffer: + fetch 2,core_dac_wptr + fetcht 2,core_dac_saddr + isub temp,pdata + + copy pdata,temp + fetch 2,core_dac_len + isub temp,pdata + // dac length loss one byte + // asic use <=, not < + pincrease 1 + rtn + +// in: temp: origin size +// out: temp: decode size +audio_dac_get_sbc_decode_buffer_size_by_cal: + bpatch patch18_6,mem_patch18 + fetch 1,mem_audio_output_setting + // bitpoot in 35 will increase 8 mult, single channel is 4 mult + lshift2 temp,temp + nbranch audio_dac_get_sbc_decode_buffer_size_by_cal_0,blank + lshift temp,temp +audio_dac_get_sbc_decode_buffer_size_by_cal_0: + rtn + +// out: pdata: decode real size +audio_dac_get_sbc_decode_buffer_size: + // get current sbc write ptr + fetch 2,core_sbc_dwp + fetcht 2,core_sbc_daddr + iadd temp,rega + + copy rega,pdata + fetcht 2,core_dac_wptr + isub temp,pdata + rtn positive + + fetch 2,core_dac_wptr + copy rega,temp + isub temp,temp + fetch 2,core_dac_len + isub temp,pdata + rtn + +// out: pdata: decode real size +audio_dac_get_sbc_decode_buffer_size_in_different_buffer: + // get current sbc write ptr + fetch 2,core_sbc_dwp + rtn + + +audio_dac_judge_reserve_buffer_enough: + enable user + fetcht 2,mem_l2cap_rx_pkt_length + call audio_dac_get_sbc_decode_buffer_size_by_cal + copy temp,rega + + call audio_dac_hw_get_reserve_count + + isub rega,null + rtn positive + + branch disable_user + +/////////////////////////////////////// AUDIO DAC END ////////////////////////////// + +/////////////////////////////////////// RAMP ////////////////////////////// +//input pdata :dest ; temp:step +ramp_left_down: + store 2,core_left_down_dest + fetch 1,core_left_step + ior temp,pdata + store 1,core_left_step + fetch 1,core_ramp_ctrl + set1 RAMP_CTRL_LEFF_DOWN_EN,pdata + branch ramp_store_ramp_ctrl + +//input pdata :dest ; temp:step +ramp_left_up: + store 1,core_left_up_dest + fetch 1,core_left_step + lshift4 temp,temp + ior temp,pdata + store 1,core_left_step + fetch 1,core_ramp_ctrl + set1 RAMP_CTRL_LEFT_UP_EN,pdata + branch ramp_store_ramp_ctrl + +//input pdata :dest ; temp:step +ramp_right_down: + store 2,core_right_down_dest + fetch 1,core_right_step + ior temp,pdata + store 1,core_right_step + fetch 1,core_ramp_ctrl + set1 RAMP_CTRL_RIGHT_DOWN_EN,pdata + branch ramp_store_ramp_ctrl + +//input pdata :dest ; temp:step +ramp_right_up: + store 1,core_right_up_dest + fetch 1,core_right_step + lshift4 temp,temp + ior temp,pdata + store 1,core_right_step + fetch 1,core_ramp_ctrl + set1 RAMP_CTRL_RIGHT_UP_EN,pdata + branch ramp_store_ramp_ctrl +/* +//input queue:4 down; 5 up +//output ture:finish +ramp_check_finish: + fetch 1,core_dac_status + qisolate1 pdata + rtn +*/ + +//input queue: 4 :down ; 5 up +ramp_finish_clr: + fetch 1,core_ramp_ctrl + qset1 pdata +ramp_store_ramp_ctrl: + store 1,core_ramp_ctrl + rtn + +ramp_finish_clr_down: + arg 4,queue + branch ramp_finish_clr + +ramp_finish_clr_up: + arg 5,queue + branch ramp_finish_clr + +/////////////////////////////////////// RAMP END ////////////////////////////// + +/////////////////////////////////////// FILTER ////////////////////////////// + +audio_filter_init: + bpatch patch18_7,mem_patch18 + call audio_farrow_filter_clear + call audio_filter_var_init + call audio_soft_dma_var_init + fetch 1,mem_conf_samplefreq_channelmode +// bbit1 AVDTP_44K_BIT,audio_44k_no_filter +// bbit1 AVDTP_48K_BIT,audio_48k_no_filter + bbit1 AVDTP_44K_BIT,audio_filter_44kto48k + bbit1 AVDTP_48K_BIT,audio_filter_48kto48k + rtn + +audio_filter_var_init: + jam 0,mem_farrow_filter_delta_uk_sign_bit + jam 0,mem_a2dp_adjust_delta_uk_sign_bit + setarg 0 + store 4,mem_a2dp_adjust_delta_uk + store 4,mem_farrow_filter_delta_uk + store 4,mem_a2dp_adjust_total_work_sample + rtn + +audio_soft_dma_var_init: + jam 0,mem_a2dp_adjust_delta_bytes_sign_bit + setarg 0 + store 2,mem_a2dp_adjust_delta_bytes + rtn + +audio_44k_no_filter: + jam 44,mem_dac_clk + call audio_disable_farrow_filter +audio_disable_44kto48k: + fetch 1,core_tone_ctrl + set0 6,pdata + store 1,core_tone_ctrl + rtn + +audio_filter_44kto48k: + arg CLOCK_OFF_VOICE_FILTER,queue + call clk_on + jam 48,mem_dac_clk + call audio_disable_farrow_filter +audio_enable_44kto48k: + fetch 1,core_tone_ctrl + set1 6,pdata + store 1,core_tone_ctrl + rtn + +audio_48k_no_filter: + jam 48,mem_dac_clk + call audio_disable_farrow_filter + branch audio_disable_44kto48k + +audio_filter_48kto48k: + arg CLOCK_OFF_VOICE_FILTER,queue + call clk_on + jam 48,mem_dac_clk + call audio_enable_44kto48k +audio_enable_farrow_filter: + fetch 1,core_sbc_ctrl + set1 4,pdata + store 1,core_sbc_ctrl + rtn + +audio_disable_farrow_filter: + fetch 1,core_sbc_ctrl + set0 4,pdata + store 1,core_sbc_ctrl + rtn + + +audio_farrow_filter_clear: + jam 0x80,core_sbc_clr + nop 1 + jam 0,core_sbc_clr + rtn + + +audio_farrow_filter_set_delta_uk: + fetcht 4,mem_farrow_filter_delta_uk + fetch 1,mem_farrow_filter_delta_uk_sign_bit + branch audio_farrow_filter_set_delta_uk_0,blank + mul32 temp,-1,temp +audio_farrow_filter_set_delta_uk_0: + storet 1,core_ff_dither0 + rshift8 temp,temp + storet 1,core_ff_dither1 + rshift8 temp,temp + storet 1,core_ff_dither2 + rshift8 temp,temp + lshift4 temp,temp + and_into 0x30,temp + + fetch 1,core_tone_ctrl + // clear origin bits + and_into 0xcf,pdata + ior temp,pdata + store 1,core_tone_ctrl + + rtn +/////////////////////////////////////// FILTER END ////////////////////////////// + +/////////////////////////////////////// SBC ////////////////////////////// + +sbc_dac_address_init: + fetch 2,mem_param_a2dp_dac_buffer_start_addr + store 2,mem_dac_start_addr + fetch 2,mem_param_a2dp_dac_buffer_size + store 2,mem_dac_buf_size + fetch 2,mem_param_a2dp_dac_buffer_addr_mram_flag + branch audio_dac_sched_ram,blank + branch audio_dac_mram + +sbc_clear: + bpatch patch19_0,mem_patch19 + call sbc_clk_on + jam 1,core_sbc_ctrl2 + jam 0xf9,core_sbc_clr + nop 1 + jam 0,core_sbc_clr + branch sbc_busy_wait + +sbc_init: + bpatch patch19_1,mem_patch19 + call sbc_clear + jam 0,core_sbc_cache_cfg2 + setarg 0 + store 2,core_sbc_saddr + setarg 0 + store 2,core_sbc_swp + setarg MEDIA_SBC_SRC_BUFFER_SIZE + store 2,core_sbc_slen + fetch 2,mem_param_a2dp_sbc_buffer_start_addr + store 2,core_sbc_daddr + fetch 2,mem_param_a2dp_sbc_buffer_size + store 2,core_sbc_dlen + call sbc_dst_mram_sel + jam 0x06,core_sbc_clr + nop 1 + jam 0,core_sbc_clr + arg 0,temp + branch sbc_hw_check_error + +sbc_update_stream_out: + bpatch patch19_2,mem_patch19 + fetch 1,mem_audio_output_setting + beq AUDIO_OUTPUT_FULLMODE,sbc_set_full_out + fetch 1,mem_tws_state + beq TWS_STATE_SLAVE_LISTEN,sbc_update_stream_out_tws + beq TWS_STATE_SLAVE_CONNECTED,sbc_update_stream_out_tws + beq TWS_STATE_MASTER_LISTEN,sbc_update_stream_out_tws + beq TWS_STATE_MASTER_CONNECTED,sbc_update_stream_out_tws + branch sbc_set_left_right_mix_out + +sbc_update_stream_out_tws: + bpatch patch19_3,mem_patch19 + fetch 1,mem_hsp_role + beq HSP_ROLE_L,sbc_set_single_left_out + branch sbc_set_single_right_out + +sbc_set_single_left_out: + fetch 1,core_sbc_cache_cfg2 + set0 sbc_ctrl_channel_0_disable,pdata + set1 sbc_ctrl_channel_1_disable,pdata + set0 sbc_ctrl_channel_01_mux,pdata + store 1,core_sbc_cache_cfg2 + rtn + +sbc_set_single_right_out: + fetch 1,core_sbc_cache_cfg2 + set1 sbc_ctrl_channel_0_disable,pdata + set0 sbc_ctrl_channel_1_disable,pdata + set0 sbc_ctrl_channel_01_mux,pdata + store 1,core_sbc_cache_cfg2 + rtn + +sbc_set_left_right_mix_out: + fetch 1,core_sbc_cache_cfg2 + set0 sbc_ctrl_channel_0_disable,pdata + set1 sbc_ctrl_channel_1_disable,pdata + set1 sbc_ctrl_channel_01_mux,pdata + store 1,core_sbc_cache_cfg2 + rtn + +sbc_set_full_out: + fetch 1,core_sbc_cache_cfg2 + set0 sbc_ctrl_channel_0_disable,pdata + set0 sbc_ctrl_channel_1_disable,pdata + set0 sbc_ctrl_channel_01_mux,pdata + store 1,core_sbc_cache_cfg2 + rtn + + +sbc_clk_on: + arg CLOCK_OFF_SBC,queue + branch clk_on + +//input temp:0:sbc ; 1:msbc +sbc_hw_check_error: + bpatch patch19_4,mem_patch19 + fetch 1,core_sbc_status + and pdata,0xc0,pdata + rtneq 0 + fetch 1,mem_sbc_error + increase 1,pdata + store 1,mem_sbc_error + copy temp,pdata + beq 0,sbc_init + call sbc_clear + branch mSBC_decode_init + +sbc_src_addr_ptr_clr: + jam 0x02,core_sbc_clr + nop 1 + jam 0,core_sbc_clr + rtn + +sbc_src_dst_addr_ptr_clr: + jam 0x06,core_sbc_clr + nop 1 + jam 0,core_sbc_clr + rtn + +sbc_update_dac_wptr: + bpatch patch19_5,mem_patch19 + fetch 2,core_sbc_dwp +// copy pdata,rega +// and pdata,0x3,pdata +// bne 0,assert +// copy rega,pdata + fetcht 2,core_sbc_daddr + iadd temp,pdata + store 2,core_dac_wptr + rtn + +sbc_hw_check_busy: + fetch 2,core_sbc_swp + fetcht 2,core_sbc_srp + isub temp,null + rtn + +//input temp +sbc_dst_mram_sel: + fetcht 1,core_sbc_ctrl2 + fetch 1,mem_param_a2dp_sbc_buffer_addr_mram_flag + nsetflag blank,3,temp + storet 1,core_sbc_ctrl2 + rtn + + +sbc_block_enable: + fetch 1,core_sbc_ctrl2 + set1 0,pdata + store 1,core_sbc_ctrl2 + rtn + +sbc_block_disable: + fetch 1,core_sbc_ctrl2 + set0 0,pdata + store 1,core_sbc_ctrl2 + rtn + +sbc_clear_dac_buf: + fetch 1,mem_dac_mram_flag + nrtn blank + fetch 2,mem_param_a2dp_dac_buffer_size + copy pdata,loopcnt + fetch 2,mem_param_a2dp_dac_buffer_start_addr + copy pdata,contw + branch clear_mem_fast + +sbc_stop: + bpatch patch19_6,mem_patch19 + jam 0,core_sbc_ctrl2 + setarg 0 + store 2,core_sbc_swp + jam 0xff,core_sbc_clr + nop 1 + jam 0,core_sbc_clr + call sbc_busy_wait + fetch 1,core_sbc_ctrl + and pdata,0x80,pdata + store 1,core_sbc_ctrl + fetch 1,core_tone_ctrl + and pdata,0x8f,pdata + store 1,core_tone_ctrl +sbc_clk_off: + arg CLOCK_OFF_SBC,queue + branch clk_off + +sbc_busy_wait: + fetch 1,core_misc_status + bbit1 4,sbc_busy_wait + rtn + + +/////////////////////////////////////// SBC END ////////////////////////////// + +/////////////////////////////////////// EQ ////////////////////////////// + +eq_init: + bpatch patch19_7,mem_patch19 + fetch 1,mem_eq_flag + rtn blank + call audio_get_coef_start_addr + arg COEF_EQ_TABLE_OFFSET,temp + iadd temp,pdata + store 3,mem_flash_address + arg COEF_EQ_TABLE_LENGTH,pdata + call audio_load_coef_common + fetch 2,core_clkoff + set0 CLOCK_OFF_VOICE_FILTER,pdata + store 2,core_clkoff + jam 0x10,core_coef_ctrl + arg 51,loopcnt + arg mem_coef_table_temp,contr +eq_coef_init_loop: + ifetcht 3,contr + storet 3,core_coef_wdata + jam 0x30,core_coef_ctrl + jam 0x10,core_coef_ctrl + loop eq_coef_init_loop + arg 66,loopcnt + arg 0,temp +eq_coef_set0_loop: + storet 3,core_coef_wdata + jam 0x30,core_coef_ctrl + jam 0x10,core_coef_ctrl + loop eq_coef_set0_loop + jam 0,core_coef_ctrl + +eq_enable: + fetch 1,core_sbc_ctrl + set1 6,pdata + store 1,core_sbc_ctrl + rtn + +eq_disable: + fetch 1,core_sbc_ctrl + set0 6,pdata + store 1,core_sbc_ctrl + rtn + +/////////////////////////////////////// EQ END ////////////////////////////// + + +/////////////////////////////////////// VOICE DAC ////////////////////////////// + +msbc_dac_init: + jam 16,mem_dac_clk + call msbc_dac_address_init + call audio_dac_init_vp_call + branch voice_dac_update_vol + + +msbc_dac_address_init: + fetch 2,mem_msbc_pcm_out_saddr + store 2,mem_dac_start_addr + setarg MSBC_PCM_MAX_PACKET_LEN + store 2,mem_dac_buf_size + branch audio_dac_sched_ram + +cvsd_dac_address_init_8k: + fetch 2,core_pcmout_8k_saddr + store 2,mem_dac_start_addr + fetch 2,core_cvsd_buf_len + increase 1,pdata + lshift pdata,pdata + store 2,mem_dac_buf_size + fetch 1,core_cvsd_ctrl1 + bbit1 DECODE_8KPCM_OUT_MRAM_SEL,audio_dac_mram + branch audio_dac_sched_ram + +cvsd_dac_address_init_48k: + fetch 2,core_pcmout_48k_saddr + store 2,mem_dac_start_addr + fetch 2,core_cvsd_buf_len + increase 1,pdata + mul32 pdata,12,pdata + store 2,mem_dac_buf_size + fetch 1,core_cvsd_ctrl + bbit1 CVSD_SELECT_MRAM,audio_dac_mram + branch audio_dac_sched_ram + +cvsd_dac_init_8k: + bpatch patch1a_0,mem_patch1a + jam 8,mem_dac_clk + call cvsd_dac_address_init_8k + branch audio_dac_init_vp_call + +cvsd_dac_init_48k: + jam 48,mem_dac_clk + call cvsd_dac_address_init_48k + branch audio_dac_init_vp_call + +cvsd_dac_init_wait: + fetch 2,core_8k_pcmout_ptr + fetcht 2,core_pcmout_8k_saddr + isub temp,pdata + arg CVSD_IN_MAX_LEN,temp +//arg 60,temp + isub temp,null + nrtn positive + branch cvsd_dac_init_48k + +voice_dac_update_vol: + call HFP_get_vol + storet 1,core_dac_lvol + storet 1,core_dac_rvol + rtn + +/////////////////////////////////////// VOICE DAC END ////////////////////////////// + +/////////////////////////////////////// ADC ////////////////////////////// +audio_adc_filter: + call audio_get_coef_start_addr + arg COEF_ADC_TABLE_OFFSET,temp + iadd temp,pdata + store 3,mem_flash_address + arg COEF_ADC_TABLE_LENGTH,pdata + call audio_load_coef_common + jam 0x10,core_coef_ctrl + arg 112,loopcnt + arg mem_coef_table_temp,contr +audio_adc_coef_init_loop: + ifetcht 3,contr + storet 3,core_coef_wdata + jam 0x30,core_coef_ctrl + jam 0x10,core_coef_ctrl + loop audio_adc_coef_init_loop + arg 224,loopcnt + arg 0,temp +audio_adc_coef_set0_loop: + storet 3,core_coef_wdata + jam 0x30,core_coef_ctrl + jam 0x10,core_coef_ctrl + loop audio_adc_coef_set0_loop + jam 0,core_coef_ctrl + rtn + + +aduio_adc_cvsd_init: + // Step1: pcm in and adc init + // adc buffer align to pcm in buffer + fetch 2,mem_param_pcm_in_buffer_addr + store 2,mem_adc_start_addr + setarg CVSD_IN_MAX_LEN + lshift pdata,pdata + store 2,mem_adc_buf_size + // mram setting + fetch 1,mem_param_pcm_in_buffer_addr_mram_flag + call cvsd_8kpcm_in_mram_sel + // mram setting + fetch 1,mem_param_pcm_in_buffer_addr_mram_flag + store 1,mem_adc_mram_flag + // init adc filter and adc buffer size + call audio_adc_init + + + // Step2: cvsd out setting + fetch 2,mem_param_cvsd_out_buffer_addr + store 2,core_cvsdout_saddr + store 2,mem_cvsd_out_addr_ptr + arg CVSD_IN_MAX_LEN,loopcnt + iadd loopcnt,pdata + store 2,mem_cvsd_out_addr_end + // mram setting + fetch 1,mem_param_cvsd_out_buffer_addr_mram_flag + call cvsd_out_mram_sel + +// arg CVSD_OUT_BUFFER_ADDR,contw +// call set_0x55_fast + setarg CVSD_IN_MAX_LEN + increase -1,pdata + store 2,core_cvsd_buf_len + + // Step3: enable adc work + branch audio_adc_start_8k + +aduio_adc_msbc_init: + setarg MSBC_PCM_IN_BUFFER_ADDR + store 2,mem_adc_start_addr + setarg MSBC_PCM_MAX_PACKET_LEN + store 2,mem_adc_buf_size + call audio_adc_init + branch audio_adc_start_16k + +// need set mem_adc_start_addr and mem_adc_buf_size +audio_adc_init: + bpatch patch1a_1,mem_patch1a + // Step1: adc filter setting + call audio_adc_filter + + fetch 2,mem_adc_start_addr + store 2,core_adcd_saddr + store 2,core_pcmin_saddr +// setarg CVSD_IN_MAX_LEN +// lshift pdata,loopcnt +// arg PCM_IN_BUFFER_ADDR,contw +// call clear_mem_fast + + fetch 2,core_adcd_saddr + fetchr loopcnt,2,mem_adc_buf_size + increase -1,loopcnt + iadd loopcnt,pdata + store 2,core_adcd_eaddr + store 2,mem_pcm_in_addr_end + +// jam 0x08,core_adcd_dcoff +// setarg 0 +// store 2,core_adcd_delay + jam 0x28,core_adc_filter_ctrl + fetch 1,core_tone_ctrl + and pdata,0xf0,pdata + or pdata,0xe,pdata + store 1,core_tone_ctrl +// branch audio_adc_stop + rtn + +audio_adc_start_8k: + jam 0x80,core_adcd_delay + jam 0,core_adcd_ctrl + fetch 1,mem_adc_mram_flag + call audio_adc_mram_sel +audio_adc_dma_enable: + fetch 1,core_adcd_ctrl + set1 7,pdata + store 1,core_adcd_ctrl + rtn + +audio_adc_start_16k: + jam 0x80,core_adcd_delay + jam 0x10,core_adcd_ctrl + fetch 1,mem_adc_mram_flag + call audio_adc_mram_sel + branch audio_adc_dma_enable + +audio_adc_stop: + fetch 1,core_tone_ctrl + and pdata,0xf0,pdata + store 1,core_tone_ctrl + jam 0,mem_cvsd_start_send + jam 0,mem_msbc_adc_start_send + jam 0x00,core_adcd_delay + jam 0x00,core_adcd_ctrl + rtn + +//input pdata, 1: mram; 0 :not mram +audio_adc_mram_sel: + fetcht 1,core_adcd_ctrl + nsetflag blank,6,temp + storet 1,core_adcd_ctrl + rtn + +/////////////////////////////////////// ADC END ////////////////////////////// + + +/////////////////////////////////////// CVSD ////////////////////////////// + + +cvsd_init: + bpatch patch1a_2,mem_patch1a + call cvsd_init_process + fetch 1,mem_param_sco_use_cm0 + nbranch cvsd_dac_init_48k,blank + branch cvsd_start_with_init_data + +cvsd_init_process: + // Enable clock + call cvsd_clk_enable + + // Init cvsd out, pcm in buffer, and init adc + call aduio_adc_cvsd_init + + //cvsd filter enable, it will reuse sbc resource. 1: for cvsd; 0: for sbc/msbc + fetch 1,core_sbc_cache_cfg2 + set1 7,pdata + store 1,core_sbc_cache_cfg2 + + // Init cvsd in buffer addr + fetch 2,mem_param_cvsd_in_buffer_addr + store 2,core_cvsdin_saddr + store 2,mem_cvsd_in_addr_ptr + + arg CVSD_IN_MAX_LEN,loopcnt + iadd loopcnt,pdata + store 2,mem_cvsd_in_addr_end + // mram setting + fetch 1,mem_param_cvsd_in_buffer_addr_mram_flag + call cvsd_in_mram_sel + +// arg CVSD_IN_BUFFER_ADDR,contw +// call set_0x55_fast + +/* setarg PCM_IN_BUFFER_ADDR + store 2,core_pcmin_saddr +// setarg CVSD_IN_MAX_LEN +// lshift pdata,loopcnt +// arg PCM_IN_BUFFER_ADDR,contw +// call clear_mem_fast + + setarg CVSD_OUT_BUFFER_ADDR + store 2,core_cvsdout_saddr + store 2,mem_cvsd_out_addr_ptr +// store 2,mem_cvsd_out_addr_start + arg CVSD_IN_MAX_LEN,loopcnt + iadd loopcnt,pdata + store 2,mem_cvsd_out_addr_end +// arg CVSD_OUT_BUFFER_ADDR,contw +// call set_0x55_fast +*/ + // In cvsd, it have 8K and 48K out + fetch 2,mem_param_pcm_8k_out_buffer_addr + store 2,core_pcmout_8k_saddr + // mram setting + fetch 1,mem_param_pcm_8k_out_buffer_addr_mram_flag + call cvsd_8kpcm_out_mram_sel + + fetch 2,mem_param_pcm_48k_out_buffer_addr + store 2,core_pcmout_48k_saddr + // mram setting + fetch 1,mem_param_pcm_48k_out_buffer_addr_mram_flag + call cvsd_48kpcm_out_mram_sel +// setarg CVSD_IN_MAX_LEN +// lshift pdata,loopcnt +// arg PCM_OUT_BUFFER_ADDR,contw +// call clear_mem_fast + + //initial the cvsd buffer len, for out buffer + setarg CVSD_IN_MAX_LEN + increase -1,pdata + store 2,core_cvsd_buf_len + + // clear and init cvsd filter + call cvsd_coef_init + + // cvsd encode and decode will work with the length + fetch 2,mem_sco_rx_packet_len + store 2,core_cvsd_grp_len + + call cvsd_start + rtn + +cvsd_start_with_init_data: + // Init base packet into buffer + call cvsd_push_0x55_to_cvsd_fifo + branch cvsd_enable_group + +cvsd_coef_init: + // clear and init cvsd filter + fetch 1,core_cvsd_ctrl + set1 CVSD_FILTER_DELAY_CHAIN_CLEAN_ENABLE,pdata + store 1,core_cvsd_ctrl + call audio_cvsd_coef_init + call cvsd_wait_cvsd_filter_clr_done + rtn + +cvsd_clk_enable: + fetch 2,core_clkoff + set0 CLOCK_OFF_VOICE_FILTER,pdata + set0 CLOCK_OFF_SBC,pdata + set0 CLOCK_OFF_MRAM,pdata + store 2,core_clkoff + rtn + +cvsd_start: + bpatch patch1a_3,mem_patch1a + fetch 1,core_cvsd_ctrl + set1 CVSD_DECODE_8K_MODE_ENABLE,pdata + set1 CVSD_DECODE_48K_MODE_ENABLE,pdata + set1 CVSD_64TO48K_ENABLE,pdata + set1 CVSD_DMA_ENABLE,pdata +cvsd_write_ctrl: + store 1,core_cvsd_ctrl + rtn + +cvsd_enable_group: + fetch 1,core_cvsd_ctrl + set1 CVSD_GROUP_ENABLE,pdata +// set1 CVSD_DMA_ENABLE,pdata + branch cvsd_write_ctrl + +cvsd_disable_group: + fetch 1,core_cvsd_ctrl + set0 CVSD_GROUP_ENABLE,pdata +// set0 CVSD_DMA_ENABLE,pdata + branch cvsd_write_ctrl + +cvsd_wait_cvsd_filter_clr_done: + fetch 1,core_perf_status + bbit0 7,cvsd_wait_cvsd_filter_clr_done + rtn + +audio_cvsd_coef_init: + call audio_get_coef_start_addr + arg COEF_VOICE_TABLE_OFFSET,temp + iadd temp,pdata + store 3,mem_flash_address + arg COEF_VOICE_TABLE_LENGTH,pdata + call audio_load_coef_common + jam 0x40,core_coef_ctrl + arg 41 ,loopcnt + arg mem_coef_table_temp,contr +audio_cvsd_coef_init_loop: + ifetcht 2,contr + storet 3,core_coef_wdata + jam 0x40,core_coef_ctrl + jam 0xc0,core_coef_ctrl + loop audio_cvsd_coef_init_loop + jam 0,core_coef_ctrl + rtn + + +cvsd_stop: + jam 0,core_cvsd_ctrl + rtn + + +cvsd_push_0x55_to_cvsd_fifo: + setarg CVSD_IN_MAX_LEN + call cvsd_push_cvsd_in_fifo_ptr + arg CVSD_IN_MAX_LEN,loopcnt + branch set_0x55_fast + + +//input: pdata --- length of packet +//output: contw +cvsd_push_cvsd_in_fifo_ptr: + fetchr rega,2,core_cvsdin_saddr + iadd rega,pdata + fetcht 2,mem_cvsd_in_addr_end + isub temp,null + nbranch cvsd_push_cvsd_in_fifo_end, positive + fetch 2, mem_cvsd_in_addr_ptr +cvsd_push_cvsd_in_fifo_end: + store 2,core_cvsdin_saddr + // Check mRAM flag + fetch 1,core_cvsd_ctrl1 + bbit0 DECODE_CVSD_IN_MRAM_SEL,cvsd_push_cvsd_in_fifo_end_0 + set1 16,rega +cvsd_push_cvsd_in_fifo_end_0: + copy rega,contw + rtn + +//output: contr +cvsd_pop_cvsd_out_fifo_ptr: + bpatch patch1a_4,mem_patch1a + fetch 2,mem_sco_tx_packet_len + fetchr rega,2,mem_cvsd_out_addr_ptr + iadd rega,pdata +// copy rega,pdata + fetcht 2,mem_cvsd_out_addr_end + isub temp,null + nbranch cvsd_push_cvsd_out_fifo_end, positive + fetch 2,core_cvsdout_saddr +cvsd_push_cvsd_out_fifo_end: + store 2,mem_cvsd_out_addr_ptr + // Check mRAM flag + fetch 1,core_cvsd_ctrl1 + bbit0 ENCODE_CVSD_OUT_MRAM_SEL,cvsd_push_cvsd_out_fifo_end_0 + set1 16,rega +cvsd_push_cvsd_out_fifo_end_0: + copy rega,contr + rtn + +cvsd_check_decoded_data: + bpatch patch1a_5,mem_patch1a + rtnmark0 mark_sco_flag +// cvsd_check_decoded_data: + fetch 1,mem_codec_type + rtnne CODEC_TYPE_CVSD + fetch 1,mem_vp_enable + bbit1 VP_MODE_BIT,cvsd_check_decoded_data_tishi + rtnne VP_STATE_DISENABLE +cvsd_check_decoded_data_tishi: + fetch 1, core_cvsd_ctrl + rtnbit0 CVSD_GROUP_ENABLE + // wait cvsd work success + fetch 1,core_perf_status + rtnbit0 2 + // check dac ready or not + fetch 1,core_dac_ctrl + bbit0 DAC_ENABLE,push_cvsd_data_dac_not_start +push_cvsd_data_dac_start: + bpatch patch1a_6,mem_patch1a + fetch 2,core_48k_pcmout_ptr +// set0 16,pdata + fetcht 2,core_dac_wptr + isub temp,null + branch push_cvsd_data_to_dec,zero + store 2,core_dac_wptr + call voice_dac_update_vol + call cvsd_disable_group +push_cvsd_data_to_dec: + fetch 2,mem_sco_rx_packet_len + call cvsd_push_cvsd_in_fifo_ptr + fetchr loopcnt,2,mem_sco_rx_packet_len + fetch 1,mem_sco_flag + bbit0 sco_rcv_flag,push_0x55_to_dec + arg mem_sco_indata,contr + call memcpy_fast + branch cvsd_enable_group + + +push_0x55_to_dec: + call set_0x55_fast + branch cvsd_enable_group + + +push_cvsd_data_dac_not_start: + call cvsd_dac_init_wait + fetch 1,core_dac_ctrl + bbit1 DAC_ENABLE,push_cvsd_data_dac_start + call cvsd_disable_group + + branch push_cvsd_data_to_dec + +cvsd_check_decoded_data_cm0: + rtn + +pop_cvsd_data_pcm_ahead: + sub pdata,0,pdata + branch pop_cvsd_data_check_ahead + +pop_cvsd_data_send: + bpatch patch1a_7,mem_patch1a + rtnmark0 mark_sco_flag + fetch 1,mem_codec_type + rtnne CODEC_TYPE_CVSD +// fetch 1,core_adcd_ctrl +// bbit0 7,pop_cvsd_data_send_start + fetch 1,mem_cvsd_start_send + nbranch pop_cvsd_data_send_start,blank + + fetch 2,core_adcd_addr + fetcht 2,core_pcmin_saddr + isub temp,pdata + nbranch pop_cvsd_data_pcm_ahead,positive +pop_cvsd_data_check_ahead: + arg CVSD_IN_MAX_LEN,temp + isub temp,null + nbranch pop_cvsd_0x55,positive + jam 1,mem_cvsd_start_send + +pop_cvsd_data_send_start: + bpatch patch1b_0,mem_patch1b + fetch 2,core_pcmin_saddr + fetcht 2,mem_sco_tx_packet_len + lshift temp,temp + iadd temp,pdata + fetcht 2,mem_pcm_in_addr_end + increase 1,temp + isub temp,null + nbranch cvsd_pop_cvsd_fifo_end,positive + fetch 2,core_adcd_saddr +cvsd_pop_cvsd_fifo_end: + store 2,core_pcmin_saddr + branch pop_cvsd_data + +pop_cvsd_0x55: + fetchr loopcnt,2,mem_sco_tx_packet_len + arg mem_sco_outdata,contw + branch set_0x55_fast + +pop_cvsd_data: + call cvsd_pop_cvsd_out_fifo_ptr + copy contr,rega + fetchr loopcnt,2,mem_sco_tx_packet_len + arg mem_sco_outdata,contw + copy rega,contr + branch memcpy_fast + + +pop_cvsd_data_send_cm0: + rtn + + + +//input pdata, 1: mram; 0 :not mram +cvsd_48kpcm_out_mram_sel: + fetcht 1,core_cvsd_ctrl + nsetflag blank,CVSD_SELECT_MRAM,temp //48k mram + storet 1,core_cvsd_ctrl + rtn + +//input pdata, 1: mram; 0 :not mram +cvsd_8kpcm_in_mram_sel: + fetcht 1,core_cvsd_ctrl1 + nsetflag blank,ENCODE_8KPCM_IN_MRAM_SEL,temp + storet 1,core_cvsd_ctrl1 + rtn + + +//input pdata, 1: mram; 0 :not mram +cvsd_8kpcm_out_mram_sel: + fetcht 1,core_cvsd_ctrl1 + nsetflag blank,DECODE_8KPCM_OUT_MRAM_SEL,temp + storet 1,core_cvsd_ctrl1 + rtn + +//input pdata, 1: mram; 0 :not mram +cvsd_in_mram_sel: + fetcht 1,core_cvsd_ctrl1 + nsetflag blank,DECODE_CVSD_IN_MRAM_SEL,temp + storet 1,core_cvsd_ctrl1 + rtn + +//input pdata, 1: mram; 0 :not mram +cvsd_out_mram_sel: + fetcht 1,core_cvsd_ctrl1 + nsetflag blank,ENCODE_CVSD_OUT_MRAM_SEL,temp + storet 1,core_cvsd_ctrl1 + rtn + +/////////////////////////////////////// CVSD END ////////////////////////////// + +/////////////////////////////////////// mSBC ////////////////////////////// + +mSBC_init: + bpatch patch1b_1,mem_patch1b + call sbc_clear + call mSBC_encode_init + call mSBC_decode_init + call aduio_adc_msbc_init + branch enable_xip + + +mSBC_stop: +// jam MSBC_SM_NULL,mem_msbc_sm + branch mSBC_enc_dec_stop + + +mSBC_encode_init: + fetch 2,mem_sco_rx_packet_len + increase -3,pdata + arg MSBC_PACKET_LEN,temp + isub temp,null + nbranch assert,zero + store 2,mem_msbc_packet_len + setarg MSBC_PCM_PACKET_LEN + store 2,mem_msbc_pcm_packet_len + + call sbc_clk_on + + setarg MSBC_PCM_IN_BUFFER_ADDR + store 2,mem_msbc_pcm_in_wptr + store 2,mem_msbc_pcm_in_rptr + setarg MSBC_OUT_BUFFER_ADDR + store 2,mem_msbc_out_wptr + store 2,mem_msbc_out_rptr + call mSBC_clear_outbuf + call mSBC_clear_txbuf + +mSBC_clear_buf: + arg MSBC_BUF_LENTH,loopcnt + arg MSBC_ENCODE_BUF_ADDRESS,contw + call clear_mem_fast + arg MSBC_BUF_LENTH,loopcnt + arg MSBC_DECODE_BUF_ADDRESS,contw + branch clear_mem_fast + +mSBC_clear_txbuf: + fetchr loopcnt,2,mem_sco_tx_packet_len + arg mem_sco_outdata ,contw + branch clear_mem_fast + +mSBC_clear_outbuf: + arg MSBC_PACKET_MAX_LEN,loopcnt + fetch 2,mem_msbc_out_wptr + copy pdata,contw + branch clear_mem_fast + + +//input pdata +//output pdata +msbc_pcm_in_len_update: + fetcht 2,mem_msbc_pcm_packet_len + iadd temp,pdata + arg MSBC_PCM_MAX_PACKET_LEN+MSBC_PCM_IN_BUFFER_ADDR,temp + isub temp,null + nrtn positive + setarg MSBC_PCM_IN_BUFFER_ADDR + rtn + +msbc_pcm_out_len_update: + fetcht 2,mem_msbc_pcm_packet_len + iadd temp,pdata + arg MSBC_PCM_MAX_PACKET_LEN+MSBC_PCM_OUT_BUFFER_ADDR,temp + isub temp,null + nrtn positive + setarg MSBC_PCM_OUT_BUFFER_ADDR + rtn + +msbc_in_len_update: + fetcht 2,mem_msbc_packet_len + iadd temp,pdata + arg MSBC_PACKET_MAX_LEN+MSBC_IN_BUFFER_ADDR,temp + isub temp,null + nrtn positive + setarg MSBC_IN_BUFFER_ADDR + rtn + +msbc_out_len_update: + fetcht 2,mem_msbc_packet_len + iadd temp,pdata + arg MSBC_PACKET_MAX_LEN+MSBC_OUT_BUFFER_ADDR,temp + isub temp,null + nrtn positive + setarg MSBC_OUT_BUFFER_ADDR + rtn + +mSBC_decode_init: + setarg MSBC_IN_BUFFER_ADDR + store 2,mem_msbc_in_wptr + store 2,mem_msbc_in_rptr + setarg MSBC_PCM_OUT_BUFFER_ADDR + store 2,mem_msbc_pcm_out_saddr + store 2,mem_msbc_pcm_out_wptr + store 2,mem_msbc_pcm_out_rptr + rtn + +mSBC_enc_dec_stop: + branch sbc_stop + +mSBC_pop_packet: + rtnmark0 mark_sco_flag + fetch 1,mem_codec_type + rtnne CODEC_TYPE_mSBC + +// fetch 1,core_adcd_ctrl +// bbit0 7,mSBC_pop_packet_0 + + fetch 2,mem_msbc_pcm_in_wptr + call msbc_pcm_in_len_update + store 2,mem_msbc_pcm_in_wptr + + + fetch 1,mem_msbc_adc_start_send + branch mSBC_adc_wait,blank + +mSBC_pop_packet_normal: + bpatch patch1b_2,mem_patch1b + arg MSBC_H2_SYNCWORD,temp + fetch 1,mem_sequence_number_tx + beq MSBC_SEQUENCE_NUMBER_0,mSBC_packet_sequence_number1 + beq MSBC_SEQUENCE_NUMBER_1,mSBC_packet_sequence_number2 + beq MSBC_SEQUENCE_NUMBER_2,mSBC_packet_sequence_number3 + beq MSBC_SEQUENCE_NUMBER_3,mSBC_packet_sequence_number0 + branch mSBC_packet_sequence_number0 + +mSBC_packet_sequence_number0: + setarg MSBC_SEQUENCE_NUMBER_0 + branch mSBC_packet_common +mSBC_packet_sequence_number1: + setarg MSBC_SEQUENCE_NUMBER_1 + branch mSBC_packet_common +mSBC_packet_sequence_number2: + setarg MSBC_SEQUENCE_NUMBER_2 + branch mSBC_packet_common +mSBC_packet_sequence_number3: + setarg MSBC_SEQUENCE_NUMBER_3 +mSBC_packet_common: + store 1,mem_sequence_number_tx + lshift8 pdata,pdata + ior temp,pdata + store 2,mem_sco_outdata + fetchr loopcnt, 2,mem_msbc_packet_len + fetch 2,mem_msbc_out_rptr + copy pdata,contr + call memcpy_fast + setarg 0 + istore 1,contw + fetch 2,mem_msbc_out_rptr + call msbc_out_len_update + store 2,mem_msbc_out_rptr + rtn + +mSBC_pop_packet_0: + fetchr loopcnt, 2,mem_sco_tx_packet_len + arg mem_sco_outdata,contw + branch clear_mem_fast + + +mSBC_pop_packet_cm0: + rtn + +mSBC_adc_wait: + fetch 2,mem_msbc_pcm_in_wptr + fetcht 2,mem_adc_start_addr + isub temp,pdata + fetcht 2,mem_adc_buf_size + rshift temp,temp + isub temp,null + nrtn positive + jam 1,mem_msbc_adc_start_send + branch mSBC_pop_packet_normal + + +mSBC_packet_process: + rtnmark0 mark_sco_flag + fetch 1,mem_codec_type + rtnne CODEC_TYPE_mSBC + fetch 1,mem_sco_flag + bbit0 sco_rcv_flag,mSBC_packet_process_miss + arg 0xfff,temp + fetch 2,mem_sco_indata + iand temp,pdata + arg MSBC_H2_SYNCWORD,temp + isub temp,null + nbranch mSBC_packet_process_error,zero + bpatch patch1b_3,mem_patch1b + fetch 1,mem_sco_indata+1 + and pdata,0xf0,pdata + beq MSBC_SEQUENCE_NUMBER_0,mSBC_packet_process2 + beq MSBC_SEQUENCE_NUMBER_1,mSBC_packet_process2 + beq MSBC_SEQUENCE_NUMBER_2,mSBC_packet_process2 + beq MSBC_SEQUENCE_NUMBER_3,mSBC_packet_process2 + branch mSBC_packet_process_error + +mSBC_packet_process2: + store 1,mem_sequence_number_rx + copy contr,temp + fetchr loopcnt, 2,mem_msbc_packet_len + fetch 2,mem_msbc_in_wptr + copy pdata,contw + copy temp,contr + call memcpy_fast + call mSBC_update_wptr + + fetch 1,core_dac_ctrl + bbit0 DAC_ENABLE,mSBC_wait_dac_start + call voice_dac_update_vol + arg 1,temp + branch sbc_hw_check_error + + +mSBC_packet_process_cm0: + rtn + +mSBC_update_wptr: + jam 1,mem_msbc_enc_dec_bt_lock + fetch 2,mem_msbc_in_wptr + call msbc_in_len_update + store 2,mem_msbc_in_wptr + jam 0,mem_msbc_enc_dec_bt_lock + rtn + +mSBC_wait_dac_start: + fetch 2,mem_msbc_pcm_out_wptr + fetcht 2,mem_msbc_pcm_out_saddr + isub temp,pdata + arg MSBC_PCM_MAX_PACKET_LEN,temp + rshift temp,temp + isub temp,null + branch msbc_dac_init,positive + rtn + +mSBC_packet_process_error: + fetch 2,mem_msbc_error + increase 1,pdata + store 2,mem_msbc_error + rtn + +mSBC_packet_process_miss: + fetch 2,mem_msbc_miss + increase 1,pdata + store 2,mem_msbc_miss + branch mSBC_update_wptr + + +ifdef MSBC_TEST + +mSBC_load_cache_wait: +// nop 100 + fetch 2,core_sbc_swp + fetcht 2,core_sbc_srp + isub temp,null + nbranch mSBC_load_cache_wait,zero +// nop 1000 + rtn + +mSBC_update_cache_wait: +// nop 100 + fetch 1,core_misc_status + bbit1 4,mSBC_update_cache_wait + rtn + +mSBC_encode_start_test: +// fetch 1,mem_msbc_sm +// rtnne MSBC_SM_NULL + + fetch 2,mem_msbc_pcm_in_rptr + store 2,core_sbc_saddr + fetch 2,mem_msbc_out_wptr + store 2,core_sbc_daddr + jam 0x80,core_sbc_ctrl2 + fetch 2,mem_msbc_pcm_packet_len + increase 1,pdata + store 2,core_sbc_slen + fetch 2,mem_msbc_packet_len + store 2,core_sbc_dlen + jam 0x06,core_sbc_clr + nop 1 + jam 0,core_sbc_clr + + jam 0x81,core_sbc_ctrl2 + + setarg MSBC_ENCODE_BUF_ADDRESS + store 2,core_sbc_cache_cfg0 + jam 0x02,core_sbc_cache_cfg2 + jam 0x00,core_sbc_cache_cfg2 + + call mSBC_update_cache_wait + fetch 2,mem_msbc_pcm_packet_len + store 2,core_sbc_swp + call mSBC_load_cache_wait + + setarg MSBC_ENCODE_BUF_ADDRESS + store 2,core_sbc_cache_cfg0 + jam 4,core_sbc_cache_cfg2 + jam 0,core_sbc_cache_cfg2 + + call mSBC_update_cache_wait + + call mSBC_enc_dec_stop + fetch 2,mem_msbc_out_wptr + call msbc_out_len_update + store 2,mem_msbc_out_wptr + fetch 2,mem_msbc_pcm_in_rptr + call msbc_pcm_in_len_update + store 2,mem_msbc_pcm_in_rptr + rtn + +mSBC_decode_start_test: //msbc to pcm +// fetch 1,mem_msbc_sm +// rtnne MSBC_SM_NULL + fetch 2,mem_msbc_in_rptr + store 2,core_sbc_saddr + fetch 2,mem_msbc_pcm_out_wptr + store 2,core_sbc_daddr + jam 0,core_sbc_ctrl2 + fetch 2,mem_msbc_packet_len + increase 1,pdata + store 2,core_sbc_slen + fetch 2,mem_msbc_pcm_packet_len + store 2,core_sbc_dlen + jam 0x06,core_sbc_clr + nop 1 + jam 0,core_sbc_clr + + fetch 1,core_sbc_ctrl + set1 5,pdata + store 1,core_sbc_ctrl + jam 0x01,core_sbc_ctrl2 + + setarg MSBC_DECODE_BUF_ADDRESS + store 2,core_sbc_cache_cfg0 + jam 2,core_sbc_cache_cfg2 + jam 0,core_sbc_cache_cfg2 + call mSBC_update_cache_wait + fetch 2,mem_msbc_packet_len + store 2,core_sbc_swp + + call mSBC_load_cache_wait + setarg MSBC_DECODE_BUF_ADDRESS + store 2,core_sbc_cache_cfg0 + jam 4,core_sbc_cache_cfg2 + jam 0,core_sbc_cache_cfg2 + call mSBC_update_cache_wait + + call mSBC_enc_dec_stop + + fetch 2,mem_msbc_pcm_out_wptr + call msbc_pcm_out_len_update + store 2,mem_msbc_pcm_out_wptr + + fetch 2,mem_msbc_in_rptr + call msbc_in_len_update + store 2,mem_msbc_in_rptr +//branch mSBC_set_sm_null + rtn +endif + +/////////////////////////////////////// mSBC END ////////////////////////////// + +/////////////////////////////////////// TISHI ////////////////////////////// +// input: temp voice addr +vp_play_by_cmd: + jam 1,mem_vp_play_by_cmd + fetch 1,mem_vp_play_addr_offset_temp + arg mem_vp_addr,temp + iadd temp,temp + call vp_play_check_language + jam 0,mem_vp_play_by_cmd + rtn + +vp_play_tishi_by_cmd: + jam 1,mem_vp_play_by_cmd + fetch 1,mem_vp_play_addr_offset_temp + arg mem_vp_addr,temp + iadd temp,temp + call tishi_play_check_language + jam 0,mem_vp_play_by_cmd + rtn + +vp_play_poweron: + arg mem_vp_addr+VP_POWERON_OFFSET,temp + branch vp_play_check_language + +vp_play_battery_near_empty: + call vp_play_check_48k + branch tishi_play_battery_near_empty ,user + arg mem_vp_addr+VP_BATTERY_NEAR_EMPTY_OFFSET,temp + branch vp_play_check_language + +vp_play_max_volume: + call vp_play_check_48k + branch tishi_play_max_volume,user + arg mem_vp_addr+VP_MAX_VOLUME_OFFSET,temp + branch vp_play_check_language + +vp_play_poweroff: + arg mem_vp_addr+VP_POWEROFF_OFFSET,temp + branch vp_play_check_language + +vp_play_connect: + arg mem_vp_addr+VP_CONNECTED_OFFSET,temp + branch vp_play_check_language + +vp_play_disconnect: + arg mem_vp_addr+VP_DISCONNECT_OFFSET,temp + branch vp_play_check_language + +vp_play_tws_connected: + arg mem_vp_addr+VP_TWS_CONNECTED_OFFSET,temp + branch vp_play_check_language + +vp_play_phone_number_timer: + bpatch patch1b_4,mem_patch1b + fetch 1,mem_telephone_dialing_state + rtnne HFP_DIALING_STATE_START + arg mem_telephone_dialing_timer,regc + call timer_single_step + nrtn user + jam 8,mem_telephone_dialing_timer +vp_play_number: + fetch 1,mem_phone_num_count + arg mem_phone_number,temp + iadd temp,temp + increase 1,pdata + store 1,mem_phone_num_count + ifetch 1,temp + mul32 pdata,3,pdata + arg mem_vp_addr+VP_PHONENUMBER_0_OFFSET,temp + iadd temp,temp + call vp_play_check_language + fetch 1,mem_phone_num_count + fetcht 1,mem_phone_num_len + isub temp,null + branch hfp_dialing_stop ,positive + rtn + +vp_play_check_48k: + bpatch patch1b_5,mem_patch1b + call disable_user + fetch 1, core_dac_ctrl + rtnbit0 DAC_ENABLE + fetch 1,mem_dac_clk + beq 48, enable_user + rtn + +vp_play_check_language: + fetch 1,mem_param_use_cm0_control_flag + branch vp_play_check_language_1,blank + fetch 1,mem_vp_play_by_cmd + rtn blank +vp_play_check_language_1: + fetch 1,mem_vp_language + beq VP_LANGUAGE_ENGLISH,vp_play_english + branch vp_play_voice_prompt + +vp_play_english: + bpatch patch1b_6,mem_patch1b + add temp,VP_ENGLISH_OFFSET,temp +//input temp:vp_address +vp_play_voice_prompt: + ifetch 3,temp + rtn blank + store 3,mem_vp_addr_temp + call vp_check_header + nrtn zero + fetch 3,mem_vp_addr_temp + increase 2,pdata + store 3,mem_vp_addr_temp + jam VP_MODE,mem_vp_enable + bmark1 mark_esco,vp_play_voice_prompt2 + fetch 2,mem_ui_state_map + bbit1 UI_STATE_BT_SNIFF, vp_state_sniff +vp_play_voice_prompt2: + bpatch patch1b_7,mem_patch1b + call HFP_voice_stop + call sbc_stop + jam AVD_AUDIO_FORBID,mem_audio_allow + + fetch 3,mem_vp_addr_temp + call vp_get_length +// fetch 1,mem_telephone_dialing_cnt +// sub pdata,1,null +// nbranch play_voice_prompt3,positive +// call p_HFP_voice_stop_noadc +//play_voice_prompt3: +// call vp_dac_enable + jam 0,mem_vp_mram_flag + jam 0,mem_vp_play_block_num + call vp_enable + call vp_dac_address_init + arg VP_DAC_BUFFER_SIZE_HALF,temp + call vp_get_data + jam 8,mem_dac_clk + call audio_dac_init_vp_call + branch vp_update_dac_wptr + +vp_check_header: + fetch 3,mem_vp_addr_temp + store 3,mem_flash_address + setarg mem_vp_length + store 2,mem_flash_data_address + setarg 2 + store 2,mem_flash_trans_length + call qspi_read + fetcht 2,mem_vp_length + setarg VP_CHECK_HEADER_DATA + isub temp,null + rtn + +vp_state_sniff: + fetch 1,mem_vp_enable + and pdata,0x80,pdata + or pdata,VP_STATE_WAIT_SNIFF,pdata + store 1,mem_vp_enable + branch app_bt_sniff_exit + +vp_enable: + call vp_get_wake_lock + fetch 1,mem_vp_enable + and pdata,0x80,pdata + or pdata,VP_STATE_ENABLE,pdata + store 1,mem_vp_enable + rtn + +vp_play_wait_sniff: + fetch 2,mem_ui_state_map + rtnbit1 UI_STATE_BT_SNIFF + fetch 1,mem_vp_enable + bbit1 VP_MODE_BIT ,tishi_play_voice_prompt2 + branch vp_play_voice_prompt2 + +vp_wait_end: + fetch 1,mem_vp_enable + rtneq VP_STATE_DISENABLE +// call p_kick_watchdog + nop 1000 + call vp_check_get_data + branch vp_wait_end + +vp_check_get_data: + bpatch patch1c_0,mem_patch1c + fetch 1,mem_vp_enable + rtneq VP_STATE_DISENABLE + and pdata,0x7f,pdata + beq VP_STATE_WAIT_SNIFF, vp_play_wait_sniff + fetch 1,mem_vp_enable + bbit1 VP_MODE_BIT,tishi_check_get_data + call vp_check_dac_wptr + nrtn user2 + fetch 1,mem_vp_play_block_num + setflip 0,pdata + store 1,mem_vp_play_block_num + fetcht 3,mem_vp_start_addr + fetch 3,mem_vp_end_addr + isub temp,pdata + branch vp_dac_disable,zero + arg VP_DAC_BUFFER_SIZE_HALF,temp + isub temp,null + nbranch vp_get_last_data,positive + call vp_get_data + branch vp_update_dac_wptr + +vp_get_last_data: + copy pdata,temp + call vp_get_data + branch vp_update_dac_wptr + +vp_check_dac_wptr: + disable user2 + fetch 2,core_dac_wptr + fetcht 2,core_dac_rptr + isub temp,pdata + branch enable_user2, zero + nbranch vp_check_dac_wptr_positive,positive +vp_check_dac_buff: + arg VP_DAC_REMAIND_SIZE,temp + isub temp,null + rtn positive + branch enable_user2 + +vp_check_dac_wptr_positive: + fetcht 2,core_dac_wptr + fetch 2,core_dac_rptr + isub temp,pdata + branch vp_check_dac_buff + +vp_dac_disable: + call vp_put_wake_lock + jam VP_STATE_DISENABLE ,mem_vp_enable + call audio_dac_stop + bmark1 mark_esco,HFP_voice_start + fetch 1,mem_a2dp_state + beq A2DP_STATE_START,vp_restart_a2dp + rtn + +vp_restart_a2dp: + rtn + +vp_get_length: + store 3,mem_flash_address + increase 3,pdata + store 3,mem_vp_start_addr + setarg mem_vp_length + store 2,mem_flash_data_address + setarg 3 + store 2,mem_flash_trans_length + call qspi_read + fetch 3,mem_vp_length + fetcht 3,mem_vp_start_addr + iadd temp,pdata + store 3,mem_vp_end_addr + rtn + +//input temp : get data length +vp_get_data: + storet 2,mem_flash_trans_length + bpatch patch1c_1,mem_patch1c + fetch 3,mem_vp_start_addr + store 3,mem_flash_address + iadd temp,pdata + store 3,mem_vp_start_addr + + fetch 1,mem_vp_play_block_num + branch vp_get_data_block0,blank +vp_get_data_block1: + fetch 2,mem_vp_dac_half + branch vp_get_data_set_block +vp_get_data_block0: + fetch 2,mem_vp_dac_addr +vp_get_data_set_block: + store 2,mem_flash_data_address + iadd temp,pdata + store 2,mem_flash_data_address_t +vp_check_mram: + fetch 1,mem_vp_mram_flag + branch qspi_read,blank + branch mqspi_read + +vp_update_dac_wptr: + fetch 2,mem_flash_data_address_t + arg VP_DAC_START_ADDR_END,temp + isub temp,null + call vp_update_dac_wptr_start,zero + store 2,core_dac_wptr + rtn + +vp_update_dac_wptr_start: + fetch 2,core_dac_saddr + rtn + +vp_dac_address_init: + setarg VP_DAC_START_ADDR + store 2,mem_dac_start_addr + store 2,mem_vp_dac_addr + setarg VP_DAC_START_ADDR_HALF + store 2,mem_vp_dac_half + setarg VP_DAC_BUFFER_SIZE + store 2,mem_dac_buf_size + branch audio_dac_sched_ram + +vp_get_wake_lock: + arg wake_lock_app,queue + branch lpm_get_wake_lock + +vp_put_wake_lock: + arg wake_lock_app,queue + branch lpm_put_wake_lock + +tishi_play_battery_near_empty: + arg mem_vp_addr+VP_BATTERY_NEAR_EMPTY_48K_OFFSET ,temp + branch tishi_play_check_language + +tishi_play_max_volume: + arg mem_vp_addr+VP_MAX_VOLUME_48K_OFFSET ,temp + branch tishi_play_check_language + +tishi_play_check_language: + bpatch patch1c_2,mem_patch1c + fetch 1,mem_param_use_cm0_control_flag + branch tishi_play_check_language_1,blank + fetch 1,mem_vp_play_by_cmd + rtn blank +tishi_play_check_language_1: + fetch 1,mem_vp_language + beq VP_LANGUAGE_ENGLISH,tishi_play_english + branch tishi_play_voice_prompt + +tishi_play_english: + add temp,3,temp +tishi_play_voice_prompt: + bpatch patch1c_3,mem_patch1c + ifetch 3,temp + rtn blank + store 3,mem_vp_addr_temp + call vp_check_header + nrtn zero + fetch 3,mem_vp_addr_temp + increase 2,pdata + store 3,mem_vp_addr_temp + bpatch patch1c_4,mem_patch1c + jam VP_MODE_TISHI,mem_vp_enable + bmark1 mark_esco,tishi_play_voice_prompt2 + fetch 2,mem_ui_state_map + bbit1 UI_STATE_BT_SNIFF, vp_state_sniff +tishi_play_voice_prompt2: + bpatch patch1c_5,mem_patch1c + fetch 1,core_dac_ctrl + rtnbit0 DAC_ENABLE + jam 1,mem_vp_mram_flag + fetch 3,mem_vp_addr_temp + call vp_get_length + jam 0,mem_vp_play_block_num + call vp_enable + call tishi_address_init + arg TISHI_BUFFER_SIZE_HALF,temp + call vp_get_data + call tisthi_enable + branch tishi_update_dac_wptr + + +tishi_address_init: + fetch 2,mem_param_tishi_start_addr + store 2,core_tishi_saddr + store 2,mem_vp_dac_addr + + arg TISHI_BUFFER_SIZE,temp + rshift temp,temp + iadd temp,pdata + store 2,mem_vp_dac_half + setarg TISHI_BUFFER_SIZE + increase -1,pdata + store 2,core_tishi_len + rtn + +tisthi_enable: + jam 0xe3, core_tishi_ctrl + branch vp_get_wake_lock + +tisthi_disable: + call vp_put_wake_lock + jam VP_STATE_DISENABLE ,mem_vp_enable + setarg 0 + store 2,core_tishi_saddr + store 2,core_tishi_len + jam 0, core_tishi_ctrl + rtn + +tishi_check_wptr: + disable user2 + fetch 2,core_tishi_wptr + fetcht 2,core_tishi_rptr + isub temp,pdata + branch enable_user2, zero + nbranch tishi_check_dac_wptr_positive,positive +tishi_check_dac_buff: + arg TISHI_REMAIND_SIZE,temp + isub temp,null + rtn positive + branch enable_user2 + +tishi_check_dac_wptr_positive: + fetcht 2,core_tishi_wptr + fetch 2,core_tishi_rptr + isub temp,pdata + branch tishi_check_dac_buff + +tishi_update_dac_wptr: + bpatch patch1c_6,mem_patch1c + fetcht 2,mem_param_tishi_start_addr + arg TISHI_BUFFER_SIZE,pdata + iadd temp,temp + fetch 2,mem_flash_data_address_t + isub temp,null + call tishi_update_dac_wptr_start,zero + store 2,core_tishi_wptr + rtn + +tishi_update_dac_wptr_start: + fetch 2,core_tishi_saddr + rtn + +tishi_check_get_data: + bpatch patch1c_7,mem_patch1c + call vp_play_check_48k + nbranch tisthi_disable,user + call tishi_check_wptr + nrtn user2 + fetch 1,mem_vp_play_block_num + setflip 0,pdata + store 1,mem_vp_play_block_num + fetcht 3,mem_vp_start_addr + fetch 3,mem_vp_end_addr + isub temp,pdata + branch tisthi_disable,zero + arg TISHI_BUFFER_SIZE_HALF,temp + isub temp,null + nbranch tishi_get_last_data,positive + call vp_get_data + branch tishi_update_dac_wptr + + +tishi_get_last_data: + copy pdata,temp + call vp_get_data + branch tishi_update_dac_wptr + + + +/////////////////////////////////////// TISHI END ////////////////////////////// + Index: tag/Soft/Librarier/bt_rom/program/avctp.prog =================================================================== --- /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/avctp.prog (nonexistent) +++ /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/avctp.prog (working copy) @@ -0,0 +1,393 @@ +//avctp +l2cap_call_proc_avctp: + fetch 2,mem_l2cap_payload_ptr + icopy contr + ifetch 1,contr + rshift4 pdata,rega + storer rega,1,mem_avctp_rx_label + and pdata,0x03,regb + ifetch 2,contr + arg ACTP_PROFILE_IDENTIFIER_AVRCP,temp + isub temp,null + nbranch l2cap_rx_reset_state,zero + bpatch patch1d_0,mem_patch1d + copy regb,pdata + beq AVCTP_TYPE_COMMAND,process_avctp_cmd + beq AVCTP_TYPE_RESPONSE,process_avctp_rsp + branch l2cap_rx_reset_state + +process_avctp_cmd: + ifetch 1,contr + increase 1,contr + icopy temp + beq AVRCP_CMD_TYPE_STATUS,process_avctp_cmd_status + beq AVRCP_CMD_TYPE_NOTIFY,process_avctp_notify + beq AVRCP_CMD_TYPE_CONTROL,process_avctp_control + branch l2cap_rx_reset_state + +process_avctp_rsp: + ifetch 1,contr + increase 1,contr + icopy temp + beq AVRCP_RES_CHANGED,process_avctp_change + branch l2cap_rx_reset_state + +process_avctp_change: + increase 9,contr + ifetch 1,contr + store 1,mem_avctp_play_state + branch l2cap_rx_reset_state + +process_avctp_notify: + bpatch patch1d_1,mem_patch1d + ifetch 1,contr + bne AVRCP_OPERA_CODE_VENDOR_DEPENDENT,l2cap_rx_reset_state + ifetcht 3,contr + setarg AVRCP_OP_COMPANYID_SIG + isub temp,null + nbranch l2cap_rx_reset_state,zero + ifetch 1,contr + beq AVRCP_PDU_RIGISTER_NOTIFY,process_avctp_notify_register_notification + branch l2cap_rx_reset_state + +process_avctp_notify_register_notification: + ifetch 3,contr + ifetch 1,contr + beq AVRCP_EVENT_VOLUME_CHANGED,process_avctp_notify_vol_changed + branch l2cap_rx_reset_state + +process_avctp_notify_vol_changed: + call avctp_send_notify_rsp + branch l2cap_rx_reset_state + +process_avctp_cmd_status: + bpatch patch1d_2,mem_patch1d + ifetch 1,contr + bne AVRCP_OPERA_CODE_VENDOR_DEPENDENT,l2cap_rx_reset_state + ifetcht 3,contr + setarg AVRCP_OP_COMPANYID_SIG + isub temp,null + nbranch l2cap_rx_reset_state,zero + ifetch 1,contr + beq AVRCP_PDU_GET_CAP,process_avctp_get_cap + branch l2cap_rx_reset_state + +process_avctp_get_cap: + call l2cap_rx_reset_state + branch avctp_send_get_cap_rsp + +process_avctp_control: + increase 4,contr + ifetch 1,contr + beq AVRCP_PDU_SET_ABSOLUTE_VOLUME,process_avctp_control_set_vol + branch l2cap_rx_reset_state + +process_avctp_control_set_vol: + bpatch patch1d_3,mem_patch1d + increase 3,contr + ifetch 1,contr + store 1,mem_avrcp_vol + beq 0x7f,process_avctp_control_set_vol_max + lshift2 pdata,pdata + div pdata,17 + call wait_div_end + quotient pdata + store 1,mem_hf_vlm_speaker + call l2cap_rx_reset_state +//0e 09 48 00 00 19 58 50 00 00 01 78 +process_avctp_control_set_vols_res: + arg 0xe,rega + jam AVCTP_TYPE_RESPONSE,mem_avctp_command_response + fetch 1,mem_avctp_rx_label + store 1,mem_avctp_tx_label + call avctp_malloc_tx_buff + setarg AVRCP_RES_ACCEPTED + call avctp_send_vd_common + setarg AVRCP_PDU_SET_ABSOLUTE_VOLUME + istore 1,contw + setarg AVRCP_OP_PACKET_TYPE_NON_FRA + istore 1,contw + setarg 1 //length + byteswap pdata,pdata + istore 2,contw + fetch 1,mem_avrcp_vol + istore 1,contw + rtn + +process_avctp_control_set_vol_max: + call HFP_adjust_max_volume + call l2cap_rx_reset_state + branch process_avctp_control_set_vols_res + +//input rega length; +//input mem_command_response:0 command ; 2 response +//input regd:ptr to l2cap context +//input mem_avctp_tx_label:label +avctp_malloc_tx_buff: + bpatch patch1d_4,mem_patch1d + call l2cap_malloc_server_channel + fetch 1,mem_avctp_tx_label + and pdata,0xf,pdata + lshift4 pdata,pdata + fetcht 1,mem_avctp_command_response + iadd temp,pdata + istore 1,contw + setarg ACTP_PROFILE_IDENTIFIER_AVRCP + istore 2,contw + rtn + +avctp_send_avr_vd_get_cap: + bpatch patch1d_5,mem_patch1d + fetch 2,mem_avr_l2capch_ptr + rtn blank + copy pdata,regd + add regd,offset_lc_state,contr + ifetch 1,contr + rtnne 0x3f + fetch 1,mem_avr_state + rtnbit1 AVCTP_GET_CAP_REQ +avctp_send_vd_get_cap: + fetch 1,mem_avr_state + set1 AVCTP_GET_CAP_REQ,pdata + store 1,mem_avr_state + jam AVCTP_TYPE_COMMAND,mem_avctp_command_response + arg 14,rega + jam 0,mem_avctp_tx_label + call avctp_malloc_tx_buff + setarg AVRCP_CMD_TYPE_STATUS + call avctp_send_vd_common + setarg AVRCP_PDU_GET_CAP + istore 1,contw + setarg AVRCP_OP_PACKET_TYPE_NON_FRA + istore 1,contw + setarg 1 + byteswap pdata,pdata + istore 2,contw + setarg AVRCP_OP_CAP_EVT_SUPPORT + istore 1,contw + rtn + +avctp_get_vol: + fetch 1,mem_hf_vlm_speaker + mul32 pdata,17,pdata + rshift2 pdata,pdata + rtn + +avctp_send_get_cap_rsp: +//10 0c 48 00 00 19 58 10 00 00 03 03 01 0d + arg 16,rega + jam AVCTP_TYPE_RESPONSE,mem_avctp_command_response + fetch 1,mem_avctp_rx_label + store 1,mem_avctp_tx_label + call avctp_malloc_tx_buff + setarg AVRCP_RES_STABLE + call avctp_send_vd_common + setarg AVRCP_PDU_GET_CAP + istore 1,contw + setarg AVRCP_OP_PACKET_TYPE_NON_FRA + istore 1,contw + setarg 3 //length + byteswap pdata,pdata + istore 2,contw + setarg AVRCP_OP_CAP_EVT_SUPPORT + istore 1,contw + setarg 1 + istore 1,contw + setarg AVRCP_EVENT_VOLUME_CHANGED + istore 1,contw + rtn + + +avctp_send_vd_playback_status_change: + fetch 2,mem_avr_l2capch_ptr + rtn blank + copy pdata,regd + arg 18,rega + jam AVCTP_TYPE_COMMAND,mem_avctp_command_response + call avctp_malloc_tx_buff + setarg AVRCP_CMD_TYPE_NOTIFY + call avctp_send_vd_common + setarg AVRCP_PDU_RIGISTER_NOTIFY + istore 1,contw + istore 1,contw + setarg AVRCP_OP_PACKET_TYPE_NON_FRA + setarg 5 + istore 2,contw + setarg AVRCP_OP_CAP_EVT_STATUS_CHNAGED + istore 1,contw + setarg 0 + istore 4,contw + rtn + +avctp_send_vol_changed: + fetch 1,mem_vlm_notify_enable + rtn blank + jam 0,mem_vlm_notify_enable +//0f 0D 48 00 00 19 58 31 00 00 02 0d 08 + arg 0xf,rega + jam AVCTP_TYPE_RESPONSE,mem_avctp_command_response + fetch 1,mem_vlm_notify_label + store 1,mem_avctp_tx_label + call avctp_malloc_tx_buff + setarg AVRCP_RES_CHANGED +avctp_send_vol_changed2: + call avctp_send_vd_common + setarg AVRCP_PDU_RIGISTER_NOTIFY + istore 1,contw + setarg AVRCP_OP_PACKET_TYPE_NON_FRA + istore 1,contw + setarg 2 //length + byteswap pdata,pdata + istore 2,contw + setarg AVRCP_EVENT_VOLUME_CHANGED + istore 1,contw + call avctp_get_vol + istore 1,contw + rtn + + +//0f 0F 48 00 00 19 58 31 00 00 02 0D 78 +avctp_send_notify_rsp: + call l2cap_rx_reset_state + jam 1,mem_vlm_notify_enable + fetch 1,mem_avctp_rx_label + store 1,mem_vlm_notify_label + store 1,mem_avctp_tx_label + arg 0xf,rega + jam AVCTP_TYPE_RESPONSE,mem_avctp_command_response + call avctp_malloc_tx_buff + setarg AVRCP_RES_INTERIM + branch avctp_send_vol_changed2 + +avctp_send_vd_common: + istore 1,contw + setarg AVRCP_SUBMIT_TYPE_PANEL + lshift3 pdata,pdata + xor pdata,AVRCP_SUBMIT_ID_0,pdata + istore 1,contw + setarg AVRCP_OPERA_CODE_VENDOR_DEPENDENT + istore 1,contw + setarg AVRCP_OP_COMPANYID_SIG + istore 3,contw + rtn + + +/////////////////////////////////////// PASS THROUGH ////////////////////// + +avctp_send_play_pause: + fetch 1,mem_a2dp_state + beq A2DP_STATE_OPEN,avctp_send_play + beq A2DP_STATE_START,avctp_send_pause + beq A2DP_STATE_SUSPEND,avctp_send_play + beq A2DP_STATE_PALY_RELEASE,avctp_send_pause + beq A2DP_STATE_PAUSE_RELEASE,avctp_send_play + rtn + +avctp_send_play: + call l2cap_malloc_is_fifo_nearly_full + nrtn blank + call avctp_play_press + branch avctp_play_release + +avctp_send_pause: + call l2cap_malloc_is_fifo_nearly_full + nrtn blank + call avctp_pause_press + branch avctp_pause_release + +avctp_send_backward: + call l2cap_malloc_is_fifo_nearly_full + nrtn blank + call avctp_backward_press + branch avctp_backward_release + +avctp_send_forward: + call l2cap_malloc_is_fifo_nearly_full + nrtn blank + call avctp_forward_press + branch avctp_forward_release + +avctp_play_press: + jam A2DP_STATE_PALY_PRESS ,mem_a2dp_state + arg PASSTHROUGH_ID_PLAY,rege + branch arctp_send_pass_through + +avctp_play_release: + jam A2DP_STATE_PALY_RELEASE ,mem_a2dp_state + arg PASSTHROUGH_ID_PLAY|AVRCP_STATE_FLAG_RELEASE,rege + branch arctp_send_pass_through + +avctp_pause_press: + jam A2DP_STATE_PAUSE_PRESS ,mem_a2dp_state + arg PASSTHROUGH_ID_PAUSE,rege + branch arctp_send_pass_through + +avctp_pause_release: + jam A2DP_STATE_PAUSE_RELEASE ,mem_a2dp_state + arg PASSTHROUGH_ID_PAUSE|AVRCP_STATE_FLAG_RELEASE,rege + branch arctp_send_pass_through + +avctp_backward_press: + arg PASSTHROUGH_ID_BACKWARD,rege + branch arctp_send_pass_through + +avctp_backward_release: + arg PASSTHROUGH_ID_BACKWARD|AVRCP_STATE_FLAG_RELEASE,rege + branch arctp_send_pass_through + +avctp_forward_press: + arg PASSTHROUGH_ID_FORWARD,rege + branch arctp_send_pass_through + +avctp_forward_release: + arg PASSTHROUGH_ID_FORWARD|AVRCP_STATE_FLAG_RELEASE,rege + branch arctp_send_pass_through + +//operands :rege +arctp_send_pass_through: + bpatch patch1d_6,mem_patch1d + fetch 2,mem_avr_l2capch_ptr + rtn blank + copy pdata,regd + fetch 1,mem_avctp_tx_label + increase 1,pdata + store 1,mem_avctp_tx_label + jam AVCTP_TYPE_COMMAND,mem_avctp_command_response + arg 8,rega + call avctp_malloc_tx_buff + setarg AVRCP_CMD_TYPE_CONTROL + istore 1,contw + setarg AVRCP_SUBMIT_TYPE_PANEL + lshift3 pdata,pdata + xor pdata,AVRCP_SUBMIT_ID_0,pdata + istore 1,contw + setarg AVRCP_OPERA_CODE_PASS_THROUGH + istore 1,contw + copy rege,pdata + istore 1,contw + setarg 0 + istore 1,contw + rtn +/////////////////////////////////////// PASS THROUGH END ////////////////////// + +/* +avctp_malloc_rsp_buff: + fetchr regd, 2,mem_avr_l2capch_ptr + //l2cap length + ifetchr rega,1,regc + storer regc,2,mem_temp1 + call l2cap_malloc_server_channel + fetch 1,mem_temp + and pdata,0xf,pdata + lshift4 pdata,pdata + increase 2,pdata + istore 1,contw + setarg ACTP_PROFILE_IDENTIFIER_AVRCP + istore 2,contw + fetch 2,mem_temp1 + icopy contr + ifetch 1,contr + add pdata,-3,loopcnt + branch memcpy +*/ + Index: tag/Soft/Librarier/bt_rom/program/bt.prog =================================================================== --- /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/bt.prog (nonexistent) +++ /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/bt.prog (working copy) @@ -0,0 +1,4857 @@ +define FPGA +define ROMCODE +//define RAM_VERSION +//define CLK6M +//define DEBUG_MALLOC +//define DEBUG_H4LOG_ENABLE +//define ACL_DEBUG + +define SIMPLE_PAIRING +define SECURE_CONNECTION + +define COMPILE_RFCOMM +//define COMPILE_SHUTTER +//define COMPILE_MOUSE +define COMPILE_MODULE +define COMPILE_AT +define COMPILE_PRCP +define COMPILE_USB +//define COMPILE_DONGLE +define COMPILE_LE +define COMPILE_A2DP +define COMPILE_HFP_HSP +//define COMPILE_SBC +//define COMPILE_24G +define COMPILE_HEADSET + +INCLUDE "bt_format" + +org 0x0000 // start from patch ram address start +ifdef ROMCODE +ifdef SIM +include sim.prog +else +include patch.prog +endif + +/******************************************/ +/*********** ROM Start ***************/ +/******************************************/ + +ifdef RAM_VERSION +org 0x4000 +else +org 0x2000 // start from rom address start +endif +start: + call lpmstate +endif + + +soft_reset: + bpatch patch00_0,mem_patch00 + clear_stack + call initialize_radio + call iicd_init_30clk + call init_param + call l2cap_init + call rfc_init + call init_lmp + call ui_init + call ipc_init + call app_init + bpatch patch00_1,mem_patch00 + call app_lpm_init,wake +ifdef SIMPLE_PAIRING + call sp_initialize +else + call ssp_disable +endif +ifdef SECURE_CONNECTION + call publickey_init +endif + call lpm_recover_clk,wake +ifdef SIMPLE_PAIRING +sp_cal_loop: + call sp_calc_sequence + fetch 1,mem_ssp_enable + beq 0,main_loop + fetch 1,mem_sp_local_key_invalid // simple pairing is not ready + branch sp_cal_loop,blank +endif +main_loop: + bpatch patch00_2,mem_patch00 +ifdef SIMPLE_PAIRING + call sp_calc_sequence +endif +ifdef SECURE_CONNECTION + call sp_calc_sequence_256 +endif +ifdef SIMPLE_PAIRING +ifdef SECURE_CONNECTION + call publickey_calc +endif +endif + call le_dispatch + bpatch patch00_3,mem_patch00 + call idle_dispatch + call app_process_idle + call inquiry_dispatch + call inquiry_scan_dispatch + call page_scan_dispatch + call connection_dispatch + call tws_pairing + call lpm_dispatch + branch main_loop + +connection_dispatch: + call connection_incontext + rtnmark0 mark_context + set0 mark_context,mark + call context_save + branch le_disable + +connection_incontext: + bpatch patch00_4,mem_patch00 + call context_search_insniff + nbranch connection_nosniff,zero + call context_load + add rega,coffset_mode,contr + ifetch 1,contr + bbit1 mode_le,le_conn_dispatch + bbit1 mode_master, master_dispatch + branch slave_dispatch +connection_nosniff: + call context_get_next + copy loopcnt,null + rtn zero + call context_load + fetch 1,mem_state + bbit1 state_inpage,master_page + fetch 1,mem_mode + bbit1 mode_master, master_dispatch + branch slave_dispatch + + + +/**************************************/ +/**************idle dispatch*********/ +/**************************************/ + +idle_dispatch: + fetch 1,mem_hci_cmd + rtn blank + beq hci_cmd_inquiry,idle_inquiry + beq hci_cmd_inquiry_cancel,idle_inquiry_cancel + beq hci_cmd_remote_name_req,idle_remote_name_req + beq hci_cmd_create_conn,idle_create_conn + beq hci_cmd_le_create_conn,idle_le_create_conn + call context_search_conn_handle + rtn zero + call context_search_plap + rtn zero +idle_exit: + jam 0,mem_hci_cmd + rtn + +idle_le_create_conn: + jam hci_cmd_le_create_conn,mem_cmd_le_create_conn + jam 0,mem_hci_cmd + rtn + +idle_inquiry: + set1 mark_inquiry_on,mark + set0 mark_inquiry_trainb,mark + jam param_ninquiry,mem_ninqy_index + jam 31,mem_nfreq_index_inq + branch idle_exit + +idle_inquiry_cancel: + set0 mark_inquiry_on,mark + force 0,stop_watch + branch idle_exit + +idle_remote_name_req: + call context_search_plap + rtn zero + force LMP_NAME_REQ,temp + jam 5,mem_nameres_cnt + branch idle_start_page + +idle_create_conn: + bpatch patch00_5,mem_patch00 + fetch 1,mem_device_option + beq dvc_op_hci,idle_create_conn_hci +idle_create_conn_device: + fetch 6,mem_hci_plap + branch idle_exit,blank + //jam HS_INIT_CALL,mem_hs_mode //init as master + jam BT_EVT_START_PAGE,mem_fifo_temp + call ui_ipc_send_event + jam CONN_SM_WAIT_FEATURES_RES,mem_reconn_lmp_sm + branch idle_create_conn_cont + +idle_create_conn_hci: + fetch 6,mem_hci_plap + branch idle_exit,blank + store 6,mem_plap +idle_create_conn_cont: + force LMP_VERSION_REQ,temp +idle_start_page: + bpatch patch00_6,mem_patch00 + fetch 1,mem_page_mode + branch idle_page_mode_r0,blank + lshift3 pdata,pdata + lshift4 pdata,pdata + increase -1,pdata +idle_page_mode_r0: + store 1,mem_npage + store 1,mem_npage_index + jam 31,mem_nfreq_index_page + set0 mark_page_trainb,mark + call context_new + nbranch idle_page_fail,zero + call get_free_amaddr + store 1,mem_amaddr + storet 1,mem_lmo_opcode2 + fetch 6,mem_hci_plap + store 6,mem_plap + bpatch patch00_7,mem_patch00 + force 0,pdata + compare LMP_NAME_REQ,temp,0xff + nsetflag true,state_init_seq,pdata + set1 state_inpage,pdata + store 1,mem_state + force 0,pdata + setflag true,smap_name_req,pdata + store 1,mem_state_map + setarg 0 + set1 mode_master,pdata + store 1,mem_mode + enable master + call context_save + disable master + force page_length_timer,queue + fetch 2,mem_page_to + call timer_init + branch idle_exit +idle_page_fail: + bpatch patch01_0,mem_patch01 + fetch 6,mem_hci_plap + store 6,mem_plap + compare LMP_NAME_REQ,temp,0xff + branch idle_name_fail,true + force HCI_ERROR_MEMORY_FULL,temp + branch idle_exit +idle_name_fail: + arg mem_tmp_buffer,contw + arg 8,loopcnt + call memset0 + force HCI_ERROR_MEMORY_FULL,queue + jam BT_EVT_RECONN_FAILED,mem_fifo_temp + call ui_ipc_send_event + branch idle_exit + + +/******************************************/ +/************** Inquiry *****************/ +/******************************************/ + +inquiry_dispatch: + rtnmark0 mark_inquiry_on + force inquiry_length_timer,queue + call timer_check + nsetflag blank,mark_inquiry_on,mark + nbranch inquiry_start,blank + rtn + + + +inquiry_start: + bpatch patch01_1,mem_patch01 + fetcht 2,mem_inq_window + force 4,queue + call sniff_check_window + rtn user + call afh_clear + force 0,freq_mode +inquiry_restart: + rtn timeout + set0 mark_fhs_already_good,mark + set0 mark_fhs_eir,mark +inquiry_rx_restart: + add clkn_bt,1,bt_clk + isolate1 mark_inquiry_trainb,mark + setflag true,2,freq_mode + compare 0x00,bt_clk,0x02 /* see if this is even slot */ + nbranch inquiry_receive,true + +inquiry_transmit: + bpatch patch01_2,mem_patch01 + fetch 1,mem_inquiry_transmit + increase 1,pdata + store 1,mem_inquiry_transmit + call fetch_giac + call tx_radio_freq + call fetch_diac + call start_transmitter /* get ready for that id packet */ + call start_tx_native + call send_access_word + call end_of_packet + call inquiry_check_train + branch inquiry_restart + +inquiry_check_train: + bpatch patch01_3,mem_patch01 + fetch 1,mem_nfreq_index_inq + increase -1,pdata + store 1,mem_nfreq_index_inq + rtn positive /* if it's time to incremnt N */ + jam 31,mem_nfreq_index_inq + fetch 1,mem_ninqy_index + increase -1,pdata + store 1,mem_ninqy_index + rtn positive /* if it's time to change train */ + setflip mark_inquiry_trainb,mark + jam param_ninquiry,mem_ninqy_index + rtn + +inquiry_receive: + bpatch patch01_4,mem_patch01 + call fetch_giac + call rx_radio_freq + call fetch_diac + call start_rx_native + call start_receiver /* get ready for that id packet */ + call wait_access_clkn_rt + branch inquiry_sync,sync /* try look for id packet again if not found */ + call inquiry_check_train + branch inquiry_rx_restart +inquiry_sync: + bpatch patch01_5,mem_patch01 + call save_rssi + call scan_mode_whiten + call receive_packet_whitened + set0 mark_rxbuf_inuse,mark + rtnmark0 mark_fhs_already_good +inquiry_receive_rtn: + bpatch patch01_6,mem_patch01 +inquiry_receive_eir_rtn: + fetch 1,mem_inquiry_rcv + increase 1,pdata + store 1,mem_inquiry_rcv + rtn +inquiry_receive_eir: + set0 mark_fhs_already_good,mark + call rf_setup_time_slave_slot_eir + call fetch_giac + call rx_radio_freq + call init_rx_packet_flags + call start_rx_native /* start listening at start_rx time */ + call start_receiver + call wait_access_clkn_rt + branch inquiry_receive_eir_packet,sync /* try look for id packet again if not found */ + rtn +inquiry_receive_eir_packet: + call scan_mode_whiten + call receive_packet_whitened + set0 mark_rxbuf_inuse,mark /*open recive pkt*/ + branch inquiry_receive_rtn,crc_failed + branch inquiry_receive_eir_rtn + +rf_setup_time_slave_slot_eir: + fetchr timeup,2,mem_param_rf_setup +rf_setup_time_eir: + until clkn_rt,meet + and clkn_bt,3,pdata + bne 1,rf_setup_time_eir + rtn + + +/******************************************/ +/************** Master Dispatch *************/ +/******************************************/ + + + +master_page: + bpatch patch01_7,mem_patch01 + enable master + enable clknt + fetch 2,mem_page_interval + branch master_page_no_interval,blank + force page_interval_timer,queue + call timer_check + nrtn blank +master_page_no_interval: + fetcht 2,mem_page_window + force 40,queue + call sniff_check_window + branch page_exit,user + force page_length_timer,queue + call timer_check + nbranch page_start,blank + fetch 1,mem_state_map + bbit1 smap_name_req,master_npage_timeout + force HCI_ERROR_PAGE_TIMEOUT,temp + branch master_page_timeout +master_npage_timeout: + arg mem_tmp_buffer,contw + arg 8,loopcnt + call memset0 + force HCI_ERROR_PAGE_TIMEOUT,queue +master_page_timeout: + bpatch patch02_0,mem_patch02 + jam 0,mem_state + call init_lmp_work + jam BT_EVT_RECONN_PAGE_TIMEOUT,mem_fifo_temp + call ui_ipc_send_event + branch page_exit + +page_start: + bpatch patch02_1,mem_patch02 + force 0,timeup + until clkn_rt,meet + fetch 1,mem_page_clk + increase -1,pdata + ixor clkn_bt,pdata + compare 0,pdata,3 + nbranch page_start,true + deposit am_addr + store 1,mem_fhs_am_addr + force 0,N_tx_slot + force 0,freq_mode + +page_restart: + bpatch patch02_2,mem_patch02 + branch page_exit,timeout + call fetch_page_bt_adr + fetchr timeup,2,mem_param_rf_setup + until clkn_rt,meet /* wait for the start_receiver time against native real clk */ +page_rx_restart: + bpatch patch02_3,mem_patch02 + fetch 4,mem_page_clk /* deposit clk_estimate */ + iforce bt_clk + increase 1,pdata + store 4,mem_page_clk + isolate1 mark_page_trainb,mark + setflag true,2,freq_mode + compare 0x00,bt_clk,0x02 /* see if this is even slot */ + nbranch page_receive,true + fetch 1, mem_page_transmit + increase 1,pdata + store 1, mem_page_transmit + call tx_radio_freq + call start_transmitter /* get ready for that id packet */ + call start_tx_native + call send_access_word + call end_of_packet + call page_check_train + branch page_restart +master_dispatch_exit: +page_exit: + bpatch patch02_4,mem_patch02 + disable master + fetch 2,mem_page_interval + rtn blank + force page_interval_timer,queue + branch timer_init + +page_check_train: + bpatch patch02_5,mem_patch02 + fetch 1,mem_nfreq_index_page + increase -1,pdata + store 1,mem_nfreq_index_page + rtn positive + jam 31,mem_nfreq_index_page + fetch 1,mem_npage_index + increase -1,pdata /* increment N */ + store 1,mem_npage_index + rtn positive /* if it's time to change train */ + setflip mark_page_trainb,mark /* change train */ + fetch 1,mem_npage + store 1,mem_npage_index + rtn + +page_receive: + bpatch patch02_6,mem_patch02 + call rx_radio_freq + call start_rx_native + call start_receiver /* get ready for that id packet */ + call wait_access_clkn_rt /* try id look for id packet again */ + branch page_sync,sync /* restart if didn't receive anything */ + call page_check_train + branch page_rx_restart +page_sync: + call end_of_packet + fetch 1, mem_page_rcv + increase 1,pdata + store 1, mem_page_rcv + force 0,stop_watch + fetch 4,mem_page_clk +page_send_fhs: + bpatch patch02_7,mem_patch02 + call rf_setup_time_master_slot + call fetch_page_bt_adr + increase 1,N_tx_slot +page_send_fhs_continue: + and_into 0x1fd,bt_clk + and_into 0x1fc,freq_mode /* master response = x00, even_train settin must remain the same */ + call tx_radio_freq + call start_transmitter /* get ready for that id packet */ + call start_tx_native + call send_access_word + deposit clkn_bt + store 4,mem_clkn_bt + force 0,am_addr + force type_fhs,type + call scan_mode_whiten + call transmit_packet_whitened +page_wait_fhs_reply: + bpatch patch03_0,mem_patch03 + call rf_setup_time_slave_slot + or_into 0x02,bt_clk + and_into 0x1fc,freq_mode /* master response sequence = x00, even train setting must be preserved */ + call rx_radio_freq + call start_rx_native + call start_receiver /* get ready for that id packet */ + call wait_access_clkn_rt /* look for that reply */ + call end_of_packet,sync /* id reply is enough */ + branch page_wait_fhs_reply_ok,sync /* no reply then send fhs again */ + fetch 1,mem_fhs_wait_counter + branch page_restart,blank + increase -1,pdata + store 1,mem_fhs_wait_counter + branch page_send_fhs + +page_wait_fhs_reply_ok: + bpatch patch03_1,mem_patch03 + fetch 1, mem_page_rcv_fhs + increase 1,pdata + store 1, mem_page_rcv_fhs + call prepare_newconn +master_newconn_loop: + call master_newconn_once + branch newconn_poll_responded,sync + call new_conn_timeout + nbranch master_newconn_loop,blank + branch page_restart + +newconn_poll_responded: + bpatch patch03_2,mem_patch03 + fetch 1,mem_state + set0 state_inpage,pdata + store 1,mem_state + call newconn_init + disable master + rtn + + +master_dispatch: + bpatch patch03_3,mem_patch03 + enable master + enable clknt + call role_switch_master + rtn user + call load_context_to_esco +// call pop_cvsd_data_send + call check_bt_disabled + call rf_setup_time_master_slot + add clkn_bt,1,bt_clk + call fetch_self_bt_adr + force 0x03,freq_mode + call scheduler_tx_l2cap_pkt + call prepare_tx + call tx_radio_freq + call start_transmitter + call start_tx_native + call send_access_word + call transmit_packet +master_loop: + bpatch patch03_4,mem_patch03 + call parse_lmp + call process_cmd + call master_conn_recv_packet + nbranch master_notmatch,match + call supervision_flush + call parse_l2cap + fetch 1,mem_master_rcvcnt + increase 1,pdata + store 1,mem_master_rcvcnt +master_notmatch: + bpatch patch03_5,mem_patch03 + call scheduler_process + call check_master_disconnect + nrtn master /* disconnected */ + call check_attempt + nbranch master_attempt,blank +master_exit: + disable master +// call push_cvsd_data_to_dec + branch load_context_to_acl + +master_attempt: + call prepare_tx + call master_conn_send_packet + branch master_loop + + +check_master_disconnect: + branch check_master_match,match + call supervision_update + branch master_disconnect,positive +check_master_match: + call check_disconnect_timeout + nbranch master_disconnect,user + fetch 1,mem_state_map + rtnbit0 smap_name_req + rtnbit1 smap_name_res + fetch 1,mem_op + rtnbit1 op_disconn + call conn_timer_expired + nrtn blank + fetch 1,mem_nameres_cnt + increase -1,pdata + store 1,mem_nameres_cnt + nrtn blank + branch lmp_disconnect + +master_disconnect: + bpatch patch03_6,mem_patch03 + call quit_connection + disable master + fetch 1,mem_state_map + bbit1 smap_name_req,master_name_disconnect + fetch 1,mem_state + bbit0 state_conn_comp,master_disconnect_quiet + fetcht 1,mem_conn_handle + rtn +master_disconnect_quiet: + rtn +master_name_disconnect: + force HCI_SUCCESS,queue +master_name_error: + force HCI_ERROR_PAGE_TIMEOUT,queue + arg mem_tmp_buffer,contw + arg 8,loopcnt + branch memset0 + + +check_disconnect_timeout: + bpatch patch03_7,mem_patch03 + enable user + fetch 1,mem_op + rtnbit0 op_disconn + call conn_timer_expired + nrtn blank + disable user + rtn + +conn_timer_expired: + fetch 1,mem_conn_timer + increase -1,pdata + store 1,mem_conn_timer + rtn + +linkkey_ready: + bpatch patch04_0,mem_patch04 + fetch 1,mem_state + bbit1 state_linkkey,linkkey_set + fetch 1,mem_device_option + beq dvc_op_hci,linkkey_send_hci + fetch 1,mem_pairing_auth + branch linkkey_set,blank + jam DEFALT_PAIRING_AUTH,mem_pairing_auth + jam BT_EVT_LINKKEY_GENERATE,mem_fifo_temp + call ui_ipc_send_event + branch linkkey_set +linkkey_send_hci: +linkkey_set: + bpatch patch04_1,mem_patch04 + call context_traverse_linkkey + fetch 1,mem_state + set1 state_linkkey,pdata + store 1,mem_state +linkkey_set_continue: + rtn + +generate_linkkey_continue: + jam PAIRING_AUTH,mem_pairing_auth +clear_linkstate: + fetch 1,mem_state + set0 state_linkkey,pdata + store 1,mem_state + rtn + + + /* rtn user if switch */ +role_switch_check: + bpatch patch04_2,mem_patch04 + disable user + fetch 2,mem_tsniff + arg 0xffff,temp + isub temp,null + nrtn zero + fetch 4,mem_sniff_anchor + branch role_switch_clkn,clknt + isub clke_bt,pdata + branch role_switch_clke +role_switch_clkn: + isub clkn_bt,pdata +role_switch_clke: + sub pdata,4,null + nrtn positive + force 0,pdata + store 2,mem_tsniff + branch enable_user + + + /* pdata: switch instant, set tsniff=0 for special sniff */ +role_switch_prepare: + copy pdata,temp + bpatch patch04_3,mem_patch04 + storet 4,mem_sniff_anchor +role_switch_prepare0: + jam SWITCH_FLAG_ACCEPT,mem_switch_flag + setarg 0xffff + store 2,mem_tsniff + jam 1,mem_sniff_attempt + rtn + + +role_switch_master: + bpatch patch04_4,mem_patch04 + call role_switch_check + nrtn user + disable user + jam param_newconnto,mem_newconnto_counter + set0 mark_fhs_already_good,mark +roles_waitfhs_loop: + call rf_setup_time_master_slot + call master_recv_packet + bmark1 mark_fhs_already_good,roles_replyto_fhs + call new_conn_timeout + nbranch roles_waitfhs_loop,blank +role_switch_fail_master: + bpatch patch04_5,mem_patch04 + disable user + deposit clkn_bt + store 4,mem_next_btclk + enable clknt + enable master + jam BT_EVT_SWITCH_FAIL_MASTER,mem_fifo_temp + branch ui_ipc_send_event + +roles_replyto_fhs: + bpatch patch04_6,mem_patch04 + call rf_setup_time_slave_slot + arg type_id,type + call master_send_packet + disable clknt + disable master + call apply_switch_clke + call prepare_newconn +roles_newconns_loop: + bpatch patch04_7,mem_patch04 + call slave_newconn_once + branch roles_newconns_responded,match + call new_conn_timeout + nbranch roles_newconns_loop,blank + branch role_switch_fail_master +roles_newconns_responded: + force 1,temp + fetch 1,mem_mode + set0 mode_master,pdata + store 1,mem_mode + call supervision_flush + call calc_clke_offset + enable user + jam BT_EVT_SWITCH_SUCCESS_MASTER,mem_fifo_temp + branch ui_ipc_send_event + + +context_load: + bpatch patch05_0,mem_patch05 + set1 mark_context,mark + storer rega,2,mem_context_ptr + force context_size,loopcnt + arg mem_le_state,contw + add rega,coffset_mode,contr + ifetch 1,contr + copy rega,contr + bbit1 mode_le,memcpy_fast + arg mem_state,contw + call memcpy_fast + disable attempt + fetch 1,mem_amaddr + iforce am_addr + jam 1,mem_current_sniff_attempt + branch context_load_master,master + jam 1,mem_current_sniff_attempt +context_load_master: + fetch 1,mem_state + rtnbit0 state_insniff + fetch 1,mem_esco_abnormal_attempt + branch context_load_normal,blank + jam 0,mem_esco_abnormal_attempt + jam 2,mem_current_sniff_attempt + branch context_load_end +context_load_normal: + fetch 1,mem_sniff_attempt + store 1,mem_current_sniff_attempt +context_load_end: + fetch 1,mem_sniff_timeout + store 1,mem_current_sniff_timeout + rtn + +context_save: + bpatch patch05_1,mem_patch05 + fetch 2,mem_context_ptr + iforce contw + force context_size,loopcnt + arg mem_le_state,contr + branch memcpy_fast,le + arg mem_state,contr + branch memcpy_fast + + + +context_get_next: + fetcht 1,mem_current_context + arg context_num,loopcnt +context_get_next_loop: + increase 1,temp + compare context_num,temp,0xff + nbranch context_get_next_cont,true + arg 0,temp +context_get_next_cont: + storet 1,mem_current_context + mul32 temp,context_size,pdata + arg mem_context,rega + iadd rega,rega + ifetch 1,rega + bbit0 state_insniff,context_get_next_nosniff + increase 1,contr + ifetch 2,contr + nbranch context_get_next_sniff,blank /* tsniff != 0, real sniff */ +context_get_next_nosniff: + rtnbit1 state_inconn + rtnbit1 state_inpage +context_get_next_sniff: + loop context_get_next_loop + rtn + +context_new: + bpatch patch05_2,mem_patch05 + arg context_search_empty,regc + call context_search + nrtn zero // all occupied + storer rega,2,mem_context_ptr + force 0,null + rtn + + //return zero if anyone's wack is 1. + //return nzero if all wack is 0 +context_check_all_wack: + call check_amaddr_is_esco + branch context_check_esco_wack,true + fetch 2,mem_context_ptr + add pdata,coffset_arq,contw + fetch 1,mem_cur_arq + istore 1,contw + arg context_check_a_wack,regc + branch context_search + +context_check_esco_wack: + fetch 1,mem_cur_arq + isolate1 wack,pdata + branch context_esco_wack,true + force 1,null + rtn +context_esco_wack: + force 0,null + rtn + + //rtn nzero if idle(no conn) +context_check_idle: + arg context_check_inconn,regc + branch context_search + +context_traverse_linkkey: + fetcht 2,mem_context_ptr + arg context_traverse_clearkey,regc + branch context_search + +context_traverse_max_slot: + fetcht 2,mem_context_ptr + arg context_traverse_mslot,regc + branch context_search + + /* return zero if conn handle is found */ +context_search_conn_handle: + fetcht 1,mem_hci_conn_handle +context_search_conn_handle2: + arg context_search_handle,regc + branch context_search + /* return zero if plap is found */ +context_search_plap: + bpatch patch05_3,mem_patch05 + fetcht 6,mem_hci_plap +context_search_plap2: + arg context_search_lap,regc + branch context_search + /* return zero if sniff anchor is meet and rega pointers to context */ +context_search_insniff: + arg context_search_sniff,regc + branch context_search + /* return zero if sniff window is in content with current transaction */ +context_search_sniff_window: + arg context_search_window,regc +context_search: + bpatch patch05_4,mem_patch05 + arg mem_context,rega + force context_num,loopcnt +context_search_loop: + ifetch 1,rega + copy regc,pc +context_search_next: + increase context_size,rega + loop context_search_loop + force 1,null + rtn + +context_search_empty: + bbit1 state_inconn,context_search_next +// bbit1 state_inpage,context_search_next + force 0,null + rtn + +context_search_lap: + bbit1 state_inpage,context_search_lap_cont + bbit0 state_inconn,context_search_next +context_search_lap_cont: + add rega,coffset_plap,contr + ifetch 6,contr + isub temp,null + rtn zero + branch context_search_next + +context_search_handle: + bbit0 state_inconn,context_search_next + add rega,coffset_conn_handle,contr + ifetch 1,contr + isub temp,null + rtn zero + branch context_search_next + +context_search_sniff: + bbit0 state_insniff,context_search_next +context_search_sniff_loop: + call context_get_anchor + call sign_pdata_temp + isub temp,pdata + increase 1,pdata + nbranch context_search_sniff_cont,positive + branch context_search_master,user2 + bmark0 mark_enter_sco_sniff,context_search_master + fetch 1,mem_esco_test + increase 1,pdata + store 1,mem_esco_test + jam 1,mem_esco_abnormal_attempt + branch context_search_meet + //bmark1 mark_enter_sco_sniff,context_search_meet +context_search_master: + iforce regb + add rega,coffset_tsniff,contr + ifetch 2,contr + branch context_search_meet,blank + call context_next_anchor + branch context_search_sniff_loop +context_search_sniff_cont: + bmark1 mark_sco_flag,context_search_sco_sniff + increase 5,pdata + branch context_search_sniff_check +context_search_sco_sniff: + increase 2,pdata + nbranch context_search_next,positive + set1 mark_enter_sco_sniff,mark +context_search_sniff_check: + nbranch context_search_next,positive +context_search_meet: + copy temp,bt_clk + call context_next_anchor + force 0,null + rtn + + +context_search_have_link: + disable user + arg mem_context,rega + force context_num,loopcnt +context_search_have_link_loop: + // get mem_state + ifetch 1,rega + nbranch enable_user,blank +context_search_have_link_next: + increase context_size,rega + loop context_search_have_link_loop + force 1,null + rtn + + + + // process 0-fffffff or fffffff-0 +sign_pdata_temp: + rshift16 pdata,timeup + rshift8 timeup,timeup + branch sign_pdata_temp_p0,zero + compare 0xf,timeup,0xf + nrtn true + rshift16 temp,timeup + rshift8 timeup,timeup + nrtn zero + set1 28,temp + rtn +sign_pdata_temp_p0: + rshift16 temp,timeup + rshift8 timeup,timeup + compare 0xf,timeup,0xf + nrtn true + set1 28,pdata + rtn + + +context_check_inconn: + bbit0 state_inconn,context_search_next + force 0,null // found + rtn + +context_check_a_wack: + bbit0 state_inconn,context_search_next + add rega,coffset_mode,contr + ifetch 1,contr + bbit1 mode_le,context_search_next + add rega,coffset_arq,contr + ifetch 1,contr + bbit0 wack,context_search_next + force 0,null // found + rtn + +context_get_anchor: + enable user2 + add rega,coffset_mode,contr + ifetcht 1,contr + deposit clkn_bt + isolate1 mode_master,temp + add rega,coffset_sniff_anchor,contr + ifetcht 4,contr + rtn true + add rega,coffset_clk_offset,contr + ifetch 6,contr + call calc_clke2 + deposit clke_bt + disable user2 + rtn + +context_next_anchor: + add rega,coffset_tsniff,contr + add rega,coffset_sniff_anchor,contw + ifetch 2,contr + iadd temp,timeup /* wrap to 28 bits */ + istorer timeup,4,contw + branch le_context_nexthop + + +context_search_window: + bbit0 state_insniff,context_search_next + call context_get_anchor + iadd stop_watch,pdata + iadd stop_watch,pdata + iadd queue,pdata + isub temp,null + nbranch context_search_next,positive + force 0,null + rtn + +context_traverse_mslot: + bbit0 state_inconn,context_search_next + deposit temp + isub rega,null + branch context_search_next,null + add rega,coffset_mode,contr + ifetch 1,contr + bbit1 mode_le,context_search_next + add rega,coffset_lmp_to_send,contw + ifetch 1,contw + nbranch context_search_next,blank + force LMP_MAX_SLOT,pdata + istore 1,contw + branch context_search_next + +context_traverse_clearkey: + bbit0 state_inconn,context_search_next + deposit temp + isub rega,null + branch context_search_next,null + add rega,coffset_mode,contr + ifetch 1,contr + bbit1 mode_le,context_search_next + ifetch 1,rega + set0 state_linkkey,pdata + istore 1,rega + branch context_search_next + + +master_conn_send_packet: + bpatch patch05_5,mem_patch05 + call rf_setup_time_master_slot +master_send_packet: + add clkn_bt,1,bt_clk /* master start to use native clock */ + call fetch_self_bt_adr + force 0x03,freq_mode /* we are in connection!! */ + call tx_radio_freq + call start_transmitter + call start_tx_native + call send_access_word + branch transmit_packet + +master_conn_recv_packet: + bpatch patch05_6,mem_patch05 + call rf_setup_time_slave_slot +master_recv_packet: + add clkn_bt,1,bt_clk /* master start to use native clock */ + call fetch_self_bt_adr + force 0x03,freq_mode /* we are in connection!! */ + call rx_radio_freq + call init_rx_packet_flags + call prep_crypt + call start_rx_native /* start listening at start_rx time */ + call start_receiver +master_rx_conn_finish_packet: + call wait_access_clkn_rt /* master use native clock */ + nrtn sync + call save_rssi + branch receive_packet + + + +master_newconn_once: + bpatch patch05_7,mem_patch05 + fetch 1,mem_fhs_am_addr + iforce am_addr //review + force type_poll,type + call master_conn_send_packet + branch master_conn_recv_packet + + + + + + +/******************************************/ +/************* Inquiry Scan ***************/ +/******************************************/ + +inquiry_scan_dispatch: + fetch 1,mem_scan_mode + rtnbit0 inq_scan_mode + force iscan_interval_timer,queue + call timer_check + nrtn blank + fetcht 2,mem_iscan_window + force 4,queue + call sniff_check_window + rtn user + call inquiry_scan_start + force iscan_interval_timer,queue + fetch 2,mem_iscan_interval + nbranch timer_init,sync + random pdata /* inquiry scan backoff */ + iand mask3ff,pdata + branch timer_init + + +inquiry_scan_start: + bpatch patch06_0,mem_patch06 + jam 0,mem_fhs_am_addr + disable clknt + disable attempt + call afh_clear + and clkn_bt,0x1fc,bt_clk /* freeze the clock, set bit[1] 0, this is version 1.1 */ + force 0x01,freq_mode /* slave in inquiry scan, kind of same as inquriy_response, this is version 1.1 */ + call fetch_giac + call rx_radio_freq + setflip mark_inquiry_state,mark + fetch 1,mem_inquiryscan_waitcnt + increase 1,pdata + store 1,mem_inquiryscan_waitcnt + call fetch_diac + call start_receiver /* get ready for that id packet */ + call wait_access_forever /* until there is timeout, or matched (true) */ + nrtn sync + bpatch patch06_1,mem_patch06 + force 0,stop_watch + call shutdown_radio /* must have heard */ + fetch 1,mem_inquiryscan_rcvcnt + increase 1,pdata + store 1,mem_inquiryscan_rcvcnt + call fetch_giac + call rf_setup_time_slave_slot + or_into 0x002,bt_clk /* put clk(1) to 1 */ + force 0x01,freq_mode /* slave in inquriy and page, response only */ + call tx_radio_freq + call fetch_diac + call start_transmitter /* get ready for that id packet */ + call start_tx_external + deposit clkn_bt + store 4,mem_clkn_bt + call send_access_word + force type_fhs,type + force 0,am_addr /* put 0 into am_addr field for fhs */ + call scan_mode_whiten + call transmit_packet_whitened + call send_eir + and_into 0x1fd,bt_clk /* put clk(1) back to 0 */ + increase 1,N_tx_slot + rtn + +send_eir: + bpatch patch06_2,mem_patch06 + fetch 1,mem_eir_enable + rtn blank + arg mem_eir,contw + fetch 1,mem_local_name_length + copy pdata,loopcnt + increase 1,pdata + istore 1,contw + copy contw,temp + increase 1,pdata + store 2,mem_tx_len + copy temp,contw + setarg 0x09 //type:name + istore 1,contw + arg mem_local_name,contr + call memcpy //name + + arg mem_all_uuid_128bits,regc + arg 4,loopcnt + call get_all_uuid + arg mem_all_uuid_16bits,regc + arg 1,loopcnt + call get_all_uuid + + force type_dm3,type /* DM3 */ + jam 2,mem_tx_lch + setarg mem_eir + store 2,mem_txptr + call rf_setup_time_slave_slot + call tx_radio_freq + call start_transmitter /* get ready for that id packet */ + call start_tx_external + call send_access_word + call scan_mode_whiten + call transmit_packet_whitened + rtn + + +get_all_uuid: + copy contw,temp + copy regc,contr + ifetch 1,contr + rtn blank +lshift_loop: + lshift pdata,pdata + loop lshift_loop + copy pdata,rega + increase 2,pdata + copy pdata,queue + fetch 2,mem_tx_len + iadd queue,pdata + store 2,mem_tx_len + copy temp,contw + add rega,1,pdata + istore 1,contw + copy regc,contr + ifetch 1,contr + ifetch 1,contr //fetch type + istore 1,contw + copy rega,loopcnt + branch memcpy //copy uuid + +/******************************************/ +/******** Slave dispatch ***********/ +/******************************************/ + +page_scan_dispatch: + fetch 1,mem_scan_mode + rtnbit0 page_scan_mode + force pscan_interval_timer,queue + call timer_check + nrtn blank + fetcht 2,mem_pscan_window + force 40,queue + call sniff_check_window + rtn user + force 0,am_addr + jam param_pagerespto,mem_fhs_wait_counter + set0 mark_fhs_already_good,mark + call page_scan_start + force pscan_interval_timer,queue + fetch 2,mem_pscan_interval + branch timer_init + + +page_scan_start: + bpatch patch06_3,mem_patch06 + disable clknt + call afh_clear + fetch 1,mem_pagescan_waitcnt + increase 1,pdata + store 1,mem_pagescan_waitcnt + force 0,N_tx_slot + call fetch_self_bt_adr + add clkn_bt,1,bt_clk /* freeze the clock on native clock until scan window is up */ + force 0x02, freq_mode /* slave in inquiry and page, not response */ + bpatch patch06_4,mem_patch06 + call rx_radio_freq + call start_receiver /* wait for that id packet from master */ + call wait_access_forever + nrtn sync /* pscan window timeout occured, back to dispatch */ + call shutdown_radio /* got the id packet */ + fetch 1,mem_pagescan_rcvcnt + increase 1,pdata + store 1,mem_pagescan_rcvcnt + force 0,stop_watch + call rf_setup_time_slave_slot + or_into 0x002,bt_clk /* put clk(1) to 1 */ + force 0x01,freq_mode /* slave in inquriy and page, response only */ + call tx_radio_freq + call start_transmitter + call start_tx_external + call send_access_word + call end_of_packet + force 0,am_addr + fetchr timeup,2,mem_param_rf_setup + until clke_rt,meet + or_into 0x03,clke_bt + and_into 0x1fd,bt_clk +page_scan_wait_fhs_restart: + bpatch patch06_5,mem_patch06 + increase 1,N_tx_slot + call rx_radio_freq + call start_receiver + call wait_access_mhalfbnd + nbranch page_scan_wait_fhs_again,sync /* go back if didn't find access code */ + call scan_mode_whiten + call receive_packet_whitened + bmark1 mark_fhs_already_good,page_scan_reply_to_fhs +page_scan_wait_fhs_again: + fetch 1,mem_fhs_wait_counter + rtn blank + increase -1,pdata + store 1,mem_fhs_wait_counter + call rf_setup_time_master_slot /* set up expiration time */ + branch page_scan_wait_fhs_restart + + +page_scan_reply_to_fhs: + bpatch patch06_6,mem_patch06 + set0 1,clke_bt + set1 0,clke_bt + fetch 1,mem_pagescan_rcvfhscnt + increase 1,pdata + store 1,mem_pagescan_rcvfhscnt + call rf_setup_time_slave_slot + or_into 0x02,bt_clk + call tx_radio_freq + call start_transmitter + call start_tx_external + call send_access_word + call end_of_packet +slave_apply_clke_bt: + compare 0x03,clke_bt,0x03 + branch slave_apply_clke_bt_now,true + until null,mhalfbnd + branch slave_apply_clke_bt +slave_apply_clke_bt_now: + fetch 4,mem_clke_bt + or_into 0x03,pdata + icopy clke_bt + +start_slave_connection: + bpatch patch06_7,mem_patch06 + fetch 6,extm_lap + store 6,mem_plap + call prepare_newconn +slave_newconn_loop: + call slave_newconn_once + branch sconn_successful,match /* we were talked to */ + call new_conn_timeout + nbranch slave_newconn_loop,blank + rtn + + +sconn_successful: + bpatch patch07_0,mem_patch07 + jam 0,mem_state + call newconn_init + call context_new + nrtn zero + jam 0,mem_mode + call calc_clke_offset + branch context_save + +slave_dispatch: + bpatch patch07_1,mem_patch07 + call calc_clke + call role_switch_slave + rtn user + call load_context_to_esco + call prepare_sco_packet +slave_loop: + bpatch patch07_2,mem_patch07 + call scheduler_process + call slave_conn_recv_packet /* go listen for a packet */ + nbranch slave_notmatch,match + call supervision_flush + call scheduler_tx_l2cap_pkt + call prepare_tx + call set_flow_flag + call slave_conn_send_packet + call parse_l2cap + call parse_lmp + call process_cmd + fetch 1,mem_slave_rcvcnt + increase 1,pdata + store 1,mem_slave_rcvcnt + call calc_clke_offset +slave_notmatch: + bpatch patch07_3,mem_patch07 + call lpm_set_mult + call supervision_update + branch slave_discon_supervision_timeout,positive + call check_disconnect_timeout + nbranch slave_disconnect,user + call media_queue + call check_attempt + nbranch slave_loop,blank + call process_sco_packet + call tws_check_end_hfp_start_sync + branch load_context_to_acl + +prepare_sco_packet: + bpatch patch07_4,mem_patch07 + rtnmark0 mark_sco_flag + fetch 1,mem_param_sco_use_cm0 + nbranch prepare_sco_packet_cm0,blank + call pop_cvsd_data_send + call mSBC_pop_packet + rtn + +prepare_sco_packet_cm0: + bmark1 mark_esco,prepare_esco_packet_cm0 + branch m0_sco_tx_data_pop +prepare_esco_packet_cm0: + fetch 1,mem_sco_flag + rtnbit0 sco_transaction_begin_flag + + branch m0_sco_tx_data_pop + + +process_sco_packet: + bpatch patch07_5,mem_patch07 + rtnmark0 mark_sco_flag + fetch 1,mem_param_sco_use_cm0 + nbranch process_sco_packet_cm0,blank + call cvsd_check_decoded_data + call mSBC_packet_process + rtn + +process_sco_packet_cm0: + bmark1 mark_esco,process_esco_packet_cm0 + fetch 1,mem_sco_flag + rtnbit0 sco_rcv_full_packet_flag + + call m0_sco_rx_data_push + fetch 1,mem_sco_flag + set0 sco_rcv_full_packet_flag,pdata + store 1,mem_sco_flag + rtn +process_esco_packet_cm0: + fetch 1,mem_sco_flag + rtnbit0 sco_transaction_begin_flag + set0 sco_transaction_begin_flag,pdata + store 1,mem_sco_flag + // set flag + arg LOG_POINT_3000,rega + fetcht 1,mem_sco_flag + call debug_log_print + + branch m0_sco_rx_data_push + +slave_discon_supervision_timeout: + set1 mark_supervision_disconn,mark + branch slave_disconnect + +set_flow_flag: + bmark0 mark_flow,clear_flow_flag + fetch 1,mem_cur_arq + set0 flowx,pdata + store 1,mem_cur_arq + rtn +clear_flow_flag: + fetch 1,mem_cur_arq + set1 flowx,pdata + store 1,mem_cur_arq + rtn + +slave_disconnect: + bpatch patch07_6,mem_patch07 + jam 0,mem_tester_emulate + jam 0,mem_debug_config + call quit_connection + set0 mark_testmode,mark + branch test_enable_white + + +role_switch_slave: + bpatch patch07_7,mem_patch07 + call role_switch_check + nrtn user + copy am_addr,temp + call get_free_amaddr + store 1,mem_fhs_am_addr + copy temp,am_addr + jam param_newconnto,mem_newconnto_counter +roles_sendfhs_loop: + bpatch patch08_0,mem_patch08 + call rf_setup_time_master_slot + force type_fhs,type + call slave_send_access + deposit clkn_bt + store 4,mem_clkn_bt + call transmit_packet + call rf_setup_time_slave_slot + enable user3 + call slave_receive_access + branch roles_got_fhs_reply,sync + call shutdown_radio + call new_conn_timeout + nbranch roles_sendfhs_loop,blank + rtnmark0 mark_accept_switch + jam LMP_SLOT_OFFSET,mem_lmo_opcode2 + set1 mark_switch_initiated,mark + rtn +roles_got_fhs_reply: + enable clknt + call prepare_newconn + call afh_clear +roles_newconn_loop: + bpatch patch08_1,mem_patch08 + call master_newconn_once + branch roles_newconn_responded,sync + call new_conn_timeout + nbranch roles_newconn_loop,blank + disable clknt + deposit clke_bt + store 4,mem_next_btclk + rtn +roles_newconn_responded: + enable master + bmark0 mark_accept_switch,roles_newconn_nolmp + set0 mark_accept_switch,mark + jam LMP_ACCEPTED,mem_lmo_opcode2 + jam LMP_HOST_CONNECTION_REQ,mem_lmi_opcode2 + call tid_set_reply +roles_newconn_nolmp: + deposit am_addr + store 1,mem_amaddr + force 0,pdata + store 6,mem_clk_offset + fetch 1,mem_mode + set1 mode_master,pdata + store 1,mem_mode + call supervision_flush + disable master + enable user + rtn + + + +init_rx_packet_flags: + bpatch patch08_2,mem_patch08 + disable match + set0 mark_loopback,mark + set0 mark_am_addr_broadcast,mark /* initialize slave flags */ + set0 mark_longpacket,mark + set0 mark_old_packet,mark +init_rx_packet_header_flags: + fetch 1,mem_cur_arq /* mem_cur_arq + am_addr */ + set0 arqnx,pdata + set1 flowx,pdata + store 1,mem_cur_arq + rtn + +prepare_newconn: + bpatch patch08_3,mem_patch08 + jam param_newconnto,mem_newconnto_counter + jam param_newconn_arq,mem_cur_arq + fetch 2,mem_rx_window_init + store 2,mem_rx_window + deposit clkn_bt + store 4,mem_next_btclk + rtn clknt + deposit clke_bt + store 4,mem_next_btclk + rtn + +newconn_init: + bpatch patch08_4,mem_patch08 + call init_lmp_reinit + call new_conn_handle + store 1,mem_conn_handle + setarg param_supervision_to + store 2,mem_supervision_to + fetch 1,mem_state + set1 state_inconn,pdata + store 1,mem_state + jam 0,mem_op + jam 0,mem_state_map + jam 0,mem_lpm_current_mult + set0 mark_supervision_disconn,mark + branch supervision_flush + + +clear_linkkey: + bpatch patch08_5,mem_patch08 + force 0,pdata + store 8,mem_link_key + istore 8,contw + call clear_linkstate + branch context_traverse_linkkey + +new_conn_timeout: + fetch 1,mem_newconnto_counter + increase -1,pdata + store 1,mem_newconnto_counter + rtn + +new_conn_handle: + fetch 1,mem_handle_num + increase 1,pdata + store 1,mem_handle_num + rtn + + +quit_connection: + bpatch patch08_6,mem_patch08 + fetch 1,mem_hci_cmd + beq hci_cmd_remote_name_req,quit_connection_name + fetch 1,mem_lmp_to_send + bne LMP_NAME_REQ,quit_connection_cont +quit_connection_name: + call cmd_check_plap + nbranch quit_connection_cont,zero + call master_name_error + jam 0,mem_hci_cmd +quit_connection_cont: + bpatch patch08_7,mem_patch08 + call app_disconn_reason_collect_bt + call process_cmd /* clear pending command */ + //call sniff_exit + call lmp_exit_acl_sniff + call lmp_exit_sco_sniff + jam BT_EVT_BB_DISCONNECTED,mem_fifo_temp + call ui_ipc_send_event + call init_lmp_work + call l2cap_init_work +ifdef SIMPLE_PAIRING + call sp_initialize +endif + fetch 1,mem_state + set0 state_inconn + store 1,mem_state + call stop_encryption + fetch 1,mem_state_map + compare 0x0,pdata,0xc0 + branch quit_connection_not_clear_mark,true + set0 mark_rxbuf_inuse,mark +quit_connection_not_clear_mark: + fetch 1,mem_cur_arq + bbit0 wack,quit_connection_not_clear_tx +quit_connection_not_clear_tx: + fetch 1,mem_op + rtnbit0 op_txl2cap + set0 mark_tx_l2cap,mark + rtn + +slave_newconn_once: + bpatch patch09_0,mem_patch09 + fetch 1,extm_newconn_am_addr + rtn blank + icopy am_addr + call slave_conn_recv_packet + nrtn match + force type_null,type + call slave_conn_send_packet + deposit am_addr + store 1,mem_amaddr /* now the new am_addr is official */ + force 0,pdata + store 1,extm_newconn_am_addr + rtn + + +/******************************************/ +/******** Time consuming task ***********/ +/******************************************/ +prepare_tx: + bpatch patch09_1,mem_patch09 + bmark0 mark_sco_flag,prepare_tx_acl + force type_hv3,type + bmark0 mark_esco_edr_enable,prepare_tx_hv3 + force type_2ev3,type +prepare_tx_hv3: + bmark0 mark_esco,prepare_tx_sco + call check_amaddr_is_esco + nbranch prepare_tx_acl,true +prepare_tx_esco: + fetch 1,mem_sco_flag + bbit1 sco_first_pck_flag,prepare_tx_acl + set1 sco_first_pck_flag,pdata + store 1,mem_sco_flag + branch set_wait_ack /* send esco only at the first attempt */ + +prepare_tx_sco: + nrtn attempt /* send sco only at the first attempt */ +prepare_tx_acl: + call context_check_all_wack //abandon mark_retransmit, use context_check_all_wack instead. + nbranch prepare_tx_no_retransmit,zero + fetch 1,mem_cur_arq + bbit0 wack,prepare_tx_pollnull /* other wack, tx buffer in use, but not me */ +prepare_tx_retransmit: + bmark1 mark_loopback,prepare_tx_loopback + fetch 1,mem_debug_config + bbit1 debug_tx_pattern,prepare_tx_txpat + fetch 2,mem_retransmission_cnt + increase -1,pdata + store 2,mem_retransmission_cnt + branch prepare_tx_nomore_retransmit,blank + fetch 1,mem_last_type + iforce type + rtn + +prepare_tx_nomore_retransmit: + bpatch patch09_2,mem_patch09 + call clear_got_tx +prepare_tx_no_retransmit: + call check_amaddr_is_esco + branch prepare_tx_pollnull,true + call send_lmp + branch prepare_tx_sendlmp,user + fetch 1,mem_op + bbit1 op_txl2cap,prepare_tx_sendl2cap + bmark1 mark_loopback,prepare_tx_loopback + fetch 1,mem_debug_config + bbit1 debug_tx_pattern,prepare_tx_txpat +prepare_tx_pollnull: + force type_poll,type /* POLL for master */ + rtn master + force type_null,type /* default is NULL */ + rtn +prepare_tx_loopback: + bpatch patch09_3,mem_patch09 + fetch 1,mem_rx_type + iforce type + rtnne 1 + force type_null,type + rtn +prepare_tx_txpat: + fetch 1,test_mode_packet_type + and pdata,0xf,type + set1 mark_loopback,mark + rtn +prepare_tx_sendlmp: + force type_lmp,type + branch set_wait_ack +prepare_tx_sendl2cap: + call tx_l2cap_type + +set_wait_ack: + bpatch patch09_4,mem_patch09 + fetcht 1,mem_cur_arq + set1 wack,temp + storet 1,mem_cur_arq + deposit type + store 1,mem_last_type + setarg 0xffff + store 2,mem_retransmission_cnt + rtn + +tx_l2cap_type: + bpatch patch09_5,mem_patch09 + fetch 1,mem_state_map + isolate1 smap_edr,pdata + fetch 2,mem_tx_len + branch tx_l2cap_type_edr,true + force type_dm1,type /* DM1 */ + sub pdata,17,null + rtn positive + force type_dh1,type /* DH1 */ + sub pdata,27,null + rtn positive + force type_dm3,type /* DM3 */ + sub pdata,121,null + rtn positive + force type_dm5,type /* DM5 */ + sub pdata,224,null + rtn positive + force type_dh5,type /* DH5 */ + rtn +tx_l2cap_type_edr: + force type_dm1,type + sub pdata,17,null + rtn positive + force type_dh1,type /*2-DH1*/ + sub pdata,54,null + rtn positive + force type_dm3,type /*2-DH3*/ + arg 367,temp + isub temp,null + nrtn positive + force type_dm5,type /*2-DH5*/ + arg 679,temp + isub temp,null + nrtn positive + force type_dh5,type /*3-DH5*/ + rtn + + +/******************************************/ +/*********** Receive Packet *************/ +/******************************************/ + + + +slave_receive_master_slot: + fetch 1,mem_state + bbit0 state_insniff,slave_receive_notsniff + fetch 2,mem_tsniff + branch slave_receive_notsniff,blank /* role switch */ + nbranch slave_receive_sniff,attempt +slave_receive_notsniff: + call rf_setup_time_master_slot +slave_receive_access: + add clke_bt,1,bt_clk +slave_receive_sniff: + enable swfine + fetch 2,mem_rx_window + rshift pdata,pdata + fetcht 2,mem_param_pll_setup + iadd temp,pdata + call ahead_window + call fetch_extm_bt_adr + force 0x03,freq_mode /* connection hop */ + call rx_radio_freq + call init_rx_packet_flags + call prep_crypt + bpatch patch09_6,mem_patch09 + fetch 2,mem_rx_window + rshift pdata,pdata + call ahead_window + call start_receiver + enable decode_fec0 + fetch 2,mem_rx_window + arg param_clke_cal,temp + iadd temp,stop_watch + correlate null,timeout + copy clke,temp + storet 6,mem_sync_clke + disable decode_fec0 + nrtn sync + arg param_clke_cal,clke_rt + copy bt_clk,clke_bt + branch lpm_adjust_clk,wake + rtn + + +slave_conn_recv_packet: + bpatch patch09_7,mem_patch09 + call slave_receive_master_slot +tws_slave_conn_recv_packet: + call rf_debug_active_sync_line, sync + nbranch shutdown_radio,sync + call save_rssi + bmark0 mark_testmode,receive_packet + fetch 2,mem_tst_pktcnt_sync + increase 1,pdata + store 2,mem_tst_pktcnt_sync +receive_packet: + rshift bt_clk,temp + or temp,0x40,white_init +receive_packet_whitened: + bpatch patch0a_0,mem_patch0a + enable enable_white + enable enable_hec + enable decode_fec1 + parse demod,bucket,3 /* get am_addr */ + rshift8 pwindow,pdata + store 1,mem_temp_am_addr + parse demod,bucket,4 /* get type */ + inject bucket,7 /* align up to pwindow */ + copy pwindow,pdata + store 1,mem_rx_type + parse demod,bucket,3 /* get arq */ + rshift8 pwindow,pdata + store 1,mem_temp_arq + jam 0,mem_temp_force_nack + fetch 1,mem_rx_type + sub pdata,3,null + branch receive_packet_noedr,positive + beq 7,receive_packet_noedr /* esco packet */ + fetch 1,mem_state_map + isolate1 smap_edr,pdata + setflag true,PSK,radio_ctrl +receive_packet_noedr: + bpatch patch0a_1,mem_patch0a + parse demod,bucket,8 /* cycle thru hec */ + disable decode_fec1 + disable enable_hec /* at this moment, 1 seqn + 8 hec is in shift */ + call rf_debug_active_crc_error_line, crc_failed + branch error_header,crc_failed /* if hec error, nothing is valid */ + bmark0 mark_testmode,receive_packet_amchk + fetch 2,mem_tst_pktcnt_hec + increase 1,pdata + store 2,mem_tst_pktcnt_hec +receive_packet_amchk: + fetch 1,mem_temp_am_addr + compare 0,pdata,0x07 /* check for broadcast */ + setflag true,mark_am_addr_broadcast,mark /* received a broadcast message, can fire ar_addr if during unpark_req */ + branch am_addr_ok,true + icompare 0x07,am_addr + branch am_addr_match,true + bmark0 mark_esco,end_of_packet + fetcht 1,mem_acl_amaddr + icompare 0x7,temp + nbranch end_of_packet,true + call load_context_to_acl + call init_rx_packet_header_flags +am_addr_match: + enable match +am_addr_ok: + bpatch patch0a_2,mem_patch0a + fetch 1,mem_rx_type + icopy type + bmark1 mark_am_addr_broadcast,arqn_bypass /* arqn doesn't make sense */ + fetcht 1,mem_temp_arq + fetch 1,mem_cur_arq + set0 flow,pdata + isolate1 flow,temp + setflag true,flow,pdata + isolate1 arqn,temp + setflag true,arqn,pdata + store 1,mem_cur_arq + isolate0 arqn,temp + branch arqn_bypass,true + call clear_got_tx +arqn_bypass: + bpatch patch0a_3,mem_patch0a + deposit type + arg 0,temp + call reserve_slot + beq type_poll,process_poll + beq type_null,process_null /* null */ + beq type_fhs,process_fhs + fetcht 1,mem_temp_arq + fetch 1,mem_cur_arq + icompare 0x04,temp /* bit 2 is seqn */ + nbranch rx_type_dispatch,true /* different then it's new */ + bmark0 mark_am_addr_broadcast,failed_seqn /* seqn failed, and not broadcast */ + bbit0 bcast1,rx_type_dispatch /* first broadcast never fail seqn */ +failed_seqn: + set1 mark_old_packet,mark +rx_type_dispatch: + bpatch patch0a_4,mem_patch0a + deposit type + beq type_dm1, process_dm1 + beq type_dh1, process_dh1 + beq type_3dh1, process_3dh1 + beq type_hv3, process_hv3 + beq type_2ev3,process_2ev3 + arg 4,temp + call reserve_slot + beq type_dm3, process_dm3 + beq type_dh3, process_dh3 + arg 8,temp + call reserve_slot + beq type_dm5, process_dm5 + beq type_dh5, process_dh5 + rtn + +process_2ev3: + bmark0 mark_sco_flag,ack_payload + bmark0 mark_esco,process_hv3 + + fetch 1,mem_sco_flag + bbit1 sco_rcv_flag,ack_payload +process_hv3: + isolate0 PSK,radio_ctrl + branch process_sco_noedr,true + disable enable_white + enable decode_fec0 + add clkn_bt,2,timeup + correlate clkn_bt,meet + nbranch error_payload,sync + enable enable_white +process_sco_noedr: + enable decode_fec0 + enable enable_crc + enable encrypt + arg mem_sco_indata,contw + fetch 2,mem_sco_rx_packet_len + icopy loopcnt +get_hev_data_loop: + parse demod,bucket,8 + rshift3 pwindow,pdata + istore 1,contw + loop get_hev_data_loop +process_sco_data_end: + bpatch patch0a_5,mem_patch0a + fetch 1,mem_sco_flag + set1 sco_rcv_full_packet_flag,pdata + store 1,mem_sco_flag + bmark0 mark_esco,end_of_packet + parse demod,bucket,16 /* cycle through the crc */ + nsetflag crc_failed,mark_esco_rxok,mark + call rf_debug_active_crc_error_line,crc_failed + branch error_payload,crc_failed + fetch 1,mem_sco_flag + set1 sco_rcv_flag,pdata + store 1,mem_sco_flag + branch ack_payload + +process_null: +process_poll: + call tws_handle_poll + call check_amaddr_is_esco + nbranch process_poll_null_end,true + setflag true,mark_esco_rxok,mark +process_poll_null_end: + branch end_of_packet + +process_dm5: +process_dm3: + set1 mark_longpacket,mark +process_dm1: + enable decode_fec2 + branch process_dmh + +process_dh5: +process_dh3: + set1 mark_longpacket,mark +process_3dh1: + set1 PSK3M,radio_ctrl +process_dh1: + enable decode_fec0 +process_dmh: + bpatch patch0a_6,mem_patch0a + bmark1 mark_rxbuf_inuse,end_of_packet /* buffer in use, nack */ + isolate0 PSK,radio_ctrl + branch process_dmh_noedr,true + disable enable_white + enable decode_fec0 + disable decode_fec2 + add clkn_bt,2,timeup + correlate clkn_bt,meet + nbranch error_payload,sync + set1 mark_longpacket,mark + enable enable_white +process_dmh_noedr: + bpatch patch0a_7,mem_patch0a + enable encrypt + enable enable_crc + parse demod,bucket,3 /* parse in lch+l2cap flow */ + rshift8 pwindow,pdata + store 1,mem_lch_code /* for loopback */ + parse demod,bucket,5 /* parse in 5 bit packetlength */ + bmark1 mark_longpacket,process_dmh_long + rshift3 pwindow,loopcnt + rshift3 loopcnt,loopcnt + branch process_dmh_common +process_dmh_long: + parse demod,bucket,5 /* multi slot packet length of dh3 dh5 dm3 dm5 */ + rshift pwindow,loopcnt + parse demod,bucket,3 /* undefined+bit 9 of length */ +process_dmh_common: + bpatch patch0b_0,mem_patch0b + //storer loopcnt,2,mem_len + deposit loopcnt + store 2,mem_len + branch process_dmh_data_end,blank + isub mask3ff,null + branch error_payload,positive /* packet too large, discard */ + bpatch patch0b_1,mem_patch0b + set0 mark_fhs_eir,mark + fetch 1,mem_tws_state + beq TWS_STATE_SLAVE_CONNECTED,process_dmh_common_packet_tws + beq TWS_STATE_MASTER_CONNECTED,process_dmh_common_packet_tws + beq TWS_STATE_MASTER_LISTEN,process_dmh_common_packet_tws +process_dmh_common_packet: + fetch 1,mem_lch_code + and_into 0x03,pdata + beq LLID_LMP,process_lmp + beq LLID_L2CAP_START,process_dmh_data_l2cap_start_pkt + beq LLID_L2CAP_CONT,process_dmh_data_l2cap_continue_pkt + branch error_payload + +process_dmh_common_packet_tws: + bmark1 mark_old_packet,tws_handle_old_packet + branch process_dmh_common_packet + +process_lmp: + fetch 2,mem_len + sub pdata,0x70,null //lmp buffer size + nbranch error_payload,positive + bmark1 mark_old_packet,ack_payload + arg mem_rxbuf,contw //lmp_data or test packet + branch process_dmh_data + + +process_dmh_data_l2cap_start_pkt: + bpatch patch0b_2,mem_patch0b + bmark1 mark_old_packet,ack_payload + fetch 2,mem_len + fetcht 2,mem_l2cap_rx_max_lenth + isub temp,null + branch error_payload,positive + arg mem_alloc_block,rega + call queue_get_len + branch end_of_packet,blank + fetch 2,mem_l2cap_rxbuff1_len + bne 0,l2cap_rxbuff_len_error + fetcht 2,mem_len + setarg 620 + isub temp,null + branch process_dmh_data_into_buff_normal,positive +process_dmh_data_into_buff_normal: + arg mem_alloc_block,rega + call queue_get_read_ptr + copy contr,contw + branch process_dmh_data + +l2cap_rxbuff_len_error: + fetch 1,mem_l2cap_rxbuff_len_error + increase 1,pdata + store 1,mem_l2cap_rxbuff_len_error + bne 20, end_of_packet + jam 0,mem_l2cap_rxbuff_len_error + setarg 0 + store 2,mem_l2cap_rxbuff1_len + branch process_dmh_data_into_buff_normal + + +process_l2cap_continue_check_len: + fetcht 2,mem_len + iadd temp,temp + fetch 2,mem_l2cap_rx_max_lenth + isub temp,null + rtn + +tws_end_of_packet0: + fetch 1,mem_tws_state + bne TWS_STATE_SLAVE_CONNECTED,end_of_packet + fetch 1,mem_tws_slave_wait_master_first_polling_flag + branch end_of_packet,blank + branch tws_handle_old_packet + +process_dmh_data_l2cap_continue_pkt: + bpatch patch0b_3,mem_patch0b + bmark1 mark_old_packet,ack_payload + fetch 2,mem_len + fetcht 2,mem_l2cap_rx_max_lenth + isub temp,null + branch error_payload,positive + + fetch 2,mem_l2cap_rxbuff1_len + branch tws_end_of_packet0,blank + call process_l2cap_continue_check_len + nbranch end_of_packet,positive + arg mem_alloc_block,rega + call queue_get_len + branch end_of_packet,blank + arg mem_alloc_block,rega + call queue_get_read_ptr + copy contr,contw + fetch 2,mem_l2cap_rxbuff1_len + iadd contw,contw +process_dmh_data: + parse demod,bucket,8 + rshift3 pwindow,pdata + istore 1,contw + loop process_dmh_data +process_dmh_data_end: + bpatch patch0b_4,mem_patch0b + parse demod,bucket,16 /* cycle through the crc */ + + call rf_debug_active_crc_error_line,crc_failed + + fetch 1,mem_tws_state + beq TWS_STATE_SLAVE_CONNECTED,process_dmh_data_end_tws + beq TWS_STATE_MASTER_LISTEN,process_dmh_data_end_tws + beq TWS_STATE_MASTER_CONNECTED,process_dmh_data_end_tws + + branch error_payload_crc,crc_failed + branch process_dmh_packet + +tws_remind_crc_failed_flag: + // remind the packet crc failed flag + jam 1,mem_tws_last_rcv_phone_packet_crc_fail + rtn crc_failed + jam 0,mem_tws_last_rcv_phone_packet_crc_fail + rtn + +tws_update_local_packet_rcv_flag: + jam 1,mem_tws_local_rcv_packet + rtnmark1 mark_old_packet + nrtn crc_failed + jam 0,mem_tws_local_rcv_packet + rtn + +tws_update_remote_packet_rcv_flag: + // check if is a new packet + rtnmark1 mark_old_packet + + fetch 1,mem_tws_last_send_ack + rtn blank + call tws_m_clear_rcv_ack_flag + branch tws_m_clear_last_send_ack_flag + +process_dmh_data_end_tws: + call tws_remind_crc_failed_flag + call tws_update_local_packet_rcv_flag + call tws_update_remote_packet_rcv_flag + fetch 1,mem_tws_state + beq TWS_STATE_SLAVE_CONNECTED,tws_send_ack_process + branch tws_wait_ack_process + +tws_print_log_info_end_of_packet: + // set flag + arg LOG_POINT_2000,rega + fetcht 2,mem_tws_last_rcv_phone_packet_crc_fail + call debug_log_print + + // set flag + arg LOG_POINT_2001,rega + fetcht 2,mem_tws_local_rcv_packet + call debug_log_print + + call print_log_old_packet + call print_log_crc_error_packet + rtn + +print_log_old_packet: + rtnmark0 mark_old_packet + // set flag + arg LOG_POINT_2010,rega + copy clke_bt,temp + call debug_log_print + rtn + +print_log_crc_error_packet: + nrtn crc_failed + // set flag + arg LOG_POINT_2011,rega + copy clke_bt,temp + call debug_log_print + rtn + + +process_dmh_packet: + bmark1 mark_testmode,process_dmh_cont + bmark1 mark_old_packet,redundant_payload + fetch 1,mem_lch_code + compare 3,pdata,3 + branch process_dmh_cont,true + fetch 2,mem_len + branch process_dmh_cont,blank +process_dmh_l2cap_packet: + bpatch patch0b_5,mem_patch0b + fetch 2,mem_l2cap_rxbuff1_len + fetcht 2,mem_len + iadd temp,pdata + store 2,mem_l2cap_rxbuff1_len + branch assert,blank + arg mem_alloc_block,rega + call queue_get_read_ptr + copy contr,contw + //fetchr rega, 2,mem_l2cap_pwrite + ifetcht 2,contw + increase 4,temp + fetch 2,mem_l2cap_rxbuff1_len + isub temp,null + call push_l2cap_to_queue,zero + branch process_dmh_cont + +push_l2cap_to_queue: + increase 2,contw + //get cid + ifetch 2,contw + arg L2CAP_signal_channel,temp + isub temp,null + branch push_l2cap_queue,zero + copy pdata,rega + call l2cap_get_channel_info_by_local_cid + //copy regc,regd //ptr to l2cap context + ifetch 1,regc + bne PSM_AVDTP,push_l2cap_queue + fetch 2,mem_avdtpmedia_l2capch_ptr + isub regc,null + branch push_media_queue,zero + branch push_l2cap_queue + +process_dmh_cont: + bpatch patch0b_6,mem_patch0b + fetcht 1,mem_state_map + fetch 1,mem_lch_code + compare 3,pdata,0x03 + setflag true,smap_rxlmp,temp + nsetflag true,smap_rxl2cap,temp + storet 1,mem_state_map + nbranch process_dmh_cont_rxbuf_not_use,true + set1 mark_rxbuf_inuse,mark +process_dmh_cont_rxbuf_not_use: + bmark0 mark_testmode,ack_payload + isolate1 smap_rxlmp,temp + branch ack_payload,true + fetch 2,mem_tst_pktcnt_crc + increase 1,pdata + store 2,mem_tst_pktcnt_crc + set1 mark_loopback,mark + set0 smap_rxl2cap,temp + set0 mark_rxbuf_inuse,mark + storet 1,mem_state_map +ack_payload: + bpatch patch0b_7,mem_patch0b + // Check rcv packet + fetch 1,mem_rx_type + beq type_poll,ack_payload_normal + beq type_null,ack_payload_normal + fetch 1,mem_tws_state + beq TWS_STATE_MASTER_CONNECTED,ack_payload_tws + beq TWS_STATE_MASTER_LISTEN,ack_payload_tws + beq TWS_STATE_SLAVE_SWITCH_LISTEN,ack_payload_force_nack +ack_payload_normal: + fetch 1,mem_temp_force_nack // Use for some case to force nack remote + beq 1,ack_payload_normal_force_nack + fetcht 1,mem_temp_arq + fetch 1,mem_cur_arq + set1 arqnx,pdata +ack_payload_normal_after_ack: + isolate1 seqn,temp /* if accept, seqn always copies from the header */ + setflag true,seqn,pdata + isolate1 mark_am_addr_broadcast,mark + setflag true,bcast1,pdata + store 1,mem_cur_arq + fetch 2,mem_len + nbranch end_of_packet,blank + fetch 1,mem_state_map + set0 smap_rxl2cap,pdata//better to do this in l2cap_flow_ctrl_stop + store 1,mem_state_map + fetch 1,mem_lch_code + compare 0x01,pdata,0x07 + //call l2cap_flow_ctrl_stop,true + branch end_of_packet + +bt_force_nack_remote: + jam 1,mem_temp_force_nack + rtn + +ack_payload_normal_force_nack: + // set flag + arg LOG_POINT_2012,rega + fetcht 1,mem_tws_state + call debug_log_print + + fetcht 1,mem_temp_arq + fetch 1,mem_cur_arq + set0 arqnx,pdata + branch ack_payload_normal_after_ack + +ack_payload_tws: + bpatch patch0c_0,mem_patch0c + call check_amaddr_is_esco + branch ack_payload_force_nack,true + call tws_check_m_rcv_packet_success + call tws_m_set_last_send_ack_flag,user + ncall bt_force_nack_remote,user + + branch ack_payload_normal + +ack_payload_force_nack: + call bt_force_nack_remote + + branch ack_payload_normal + +error_header: + bpatch patch0c_1,mem_patch0c + disable match + fetch 2,mem_rx_hec_err + increase 1,pdata + store 2,mem_rx_hec_err + branch end_of_packet +error_payload_crc: + fetch 2,mem_rx_crc_err + increase 1,pdata + store 2,mem_rx_crc_err + call rf_debug_active_crc_error_line + call discard_pkt + bmark0 mark_testmode,error_payload + set1 mark_loopback,mark +error_payload: + branch end_of_packet + +discard_pkt: + bpatch patch0c_2,mem_patch0c + fetch 1,mem_lch_code + compare 3,pdata,0x03 + nbranch discard_pkt_l2cap,true +discard_pkt_lmp: + fetcht 1,mem_state_map + set0 smap_rxlmp,temp + storet 1,mem_state_map + rtn +discard_pkt_l2cap: +// isolate1 mark_testmode,mark +// setflag true,mark_loopback,mark + fetcht 1,mem_state_map + set0 smap_rxl2cap,temp + storet 1,mem_state_map + rtn + +redundant_payload: + fetch 1,mem_cur_arq + set1 arqnx,pdata + store 1,mem_cur_arq +end_of_packet: + bpatch patch0c_3,mem_patch0c + disable encode_fec0 + disable encode_fec2 + disable decode_fec0 + disable decode_fec2 + disable enable_crc + disable encrypt + disable enable_white + branch shutdown_radio,is_rx + until null,tx_clear + nop 100 /* flush out the last bit */ + branch shutdown_radio + +process_fhs: + bpatch patch0c_4,mem_patch0c + enable enable_crc + enable decode_fec2 + parse demod,bucket,72 + isolate1 58,pdata + setflag true,mark_fhs_eir,mark + copy bt_adr,temp /* save current address to aside */ + ialigned bt_adr /* send it to access gen */ + ialigned fhs0 /* get fhs_misc */ + pulse recalc /* calc the lap just received from the other guy */ + setsect 2,0xfffff /* preset ms of shift reg as big mask */ + setsect 3,0x0ffff /* preset ms of shift reg as big mask */ + nop 32 /* 30 cycles after recalc */ + iverify fhs_parity /* check fhs_parity against ls 34 bits at shift reg, with msb 36 bits as mask */ + deposit lap + store 3,extm_lap + deposit uap + store 1,extm_uap + copy temp,bt_adr /* put the address back */ + branch fhs_parity_ok,true /* fhs parity failed */ + branch error_payload +fhs_parity_ok: + bpatch patch0c_5,mem_patch0c + parse demod,bucket,72 + ialigned fhs1 /* give host the information on class and fhs_misc */ + ialigned am_addr /* store the am_addr the master assigned us */ + ialigned nap + ialigned regb /* store external clock in regb according to clock format */ + force 0,pdata + parse demod,bucket,16 /* cycle through the crc */ + branch error_payload,crc_failed + setarg 0x0ffffffc + iand regb,pdata + store 4,mem_clke_bt + deposit fhs_class + store 3,extm_class + deposit fhs_misc + store 1,extm_fhs_misc + deposit am_addr + store 1,extm_newconn_am_addr + deposit nap + store 2,extm_nap + deposit bt_clk + inject rxf,32 + compare type_fhs,type,0x0f /* see if this was fhs packet */ + setflag true,mark_fhs_already_good,mark + branch end_of_packet + +clear_got_tx: + bpatch patch0c_6,mem_patch0c + fetch 1,mem_cur_arq + rtnbit0 wack + set0 wack,pdata + setflip seqnx,pdata + store 1,mem_cur_arq + fetch 1,mem_last_type + beq type_lmp,clear_got_txlmp + rtneq type_hv3 + rtneq type_2ev3 + fetch 1,mem_op + rtnbit0 op_txl2cap,pdata + set0 op_txl2cap,pdata + set1 op_pkt_comp,pdata + store 1,mem_op + set0 mark_tx_l2cap,mark + fetch 1,mem_device_option + rtneq dvc_op_hci + fetch 2,mem_l2cap_tx_multi_offset + nrtn blank + fetch 1,mem_op + set0 op_pkt_comp,pdata + store 1,mem_op + branch l2cap_malloc_free + +clear_got_txlmp: + bpatch patch0c_7,mem_patch0c + fetch 1,mem_lmo_header_opcode + rshift pdata,pdata + beq LMP_START_ENCRYPTION_REQ,start_encryption + beq LMP_STOP_ENCRYPTION_REQ,stop_encryption + beq LMP_UNSNIFF_REQ, lmp_exit_acl_sniff + beq LMP_ESCAPE,clear_lmp_escape + beq LMP_REMOVE_SCO_LINK_REQ,lmp_exit_sco_sniff + rtnne LMP_ACCEPTED + fetch 1,mem_lmo_payload + beq LMP_SCO_LINK_REQ,sco_link_req_by_slave + beq LMP_START_ENCRYPTION_REQ,clear_send_setup_complete + rtn + +clear_lmp_escape: + fetch 1,mem_lmo_payload + set1 7,pdata + //beq LMP_EXT_REMOVE_ESCO_REQ,stop_sco + rtn +clear_send_setup_complete: + rtn master + fetch 1,mem_state + rtnbit1 state_conn_comp + jam LMP_SETUP_COMPLETE,mem_lmo_opcode2 + rtn + +// nokia BH-105 CALLING when reconnection +sco_link_req_by_slave: + rtn master + fetch 1,mem_mode + isolate1 sco_req_by_slave,pdata + branch clean_mem_mode,true + //jam LMP_REMOVE_SCO_LINK_REQ,mem_lmo_opcode2 + rtn +clean_mem_mode: + set0 sco_req_by_slave,pdata + store 1,mem_mode + rtn + +start_encryption: + bpatch patch0d_0,mem_patch0d + fetch 1,mem_state_map + set1 smap_encryption,pdata + store 1,mem_state_map + fetch 1,core_sysctrl + set1 0,pdata + store 1,core_sysctrl + jam BT_EVT_BT_START_ENC,mem_fifo_temp + branch ui_ipc_send_event + +stop_encryption: + bpatch patch0d_1,mem_patch0d + fetch 1,mem_state_map + set0 smap_encryption,pdata + store 1,mem_state_map + fetch 1,core_sysctrl + set0 0,pdata + store 1,core_sysctrl + rtn + + +sniff_init: + bpatch patch0d_2,mem_patch0d +sniff_init_sco: + bmark0 mark_sco_flag,sniff_init_acl + add clkn_bt,0,rega + branch sniff_init_master,master + add clke_bt,0,rega + branch sniff_init_master +sniff_init_acl: + add clkn_bt,3,rega + branch sniff_init_master,master + add clke_bt,3,rega +sniff_init_master: + fetcht 2,mem_tsniff + deposit rega + set0 27,pdata + idiv temp + fetch 2,mem_dsniff + call wait_div_end + remainder regc + isub regc,pdata + branch sniff_init_nowrap,positive + iadd temp,pdata +sniff_init_nowrap: + iadd rega,pdata + store 4,mem_sniff_anchor + jam SWITCH_FLAG_INIT,mem_switch_flag + fetch 1,mem_state + set1 state_insniff,pdata + store 1,mem_state + fetch 1,mem_sniff_attempt + store 1,mem_current_sniff_attempt + setarg 0 + store 3,mem_sniff_rcv + store 3,mem_sniff_lost + store 1,mem_sniff_unint_lost + jam BT_EVT_ENTER_SNIFF,mem_fifo_temp + call ui_ipc_send_event + fetch 2,mem_rx_window_sniff + store 2,mem_rx_window + nrtn master + add am_addr,-1,queue + rtn + +sniff_exit: + bpatch patch0d_3,mem_patch0d + fetch 1,mem_state + rtnbit0 state_insniff + set0 state_insniff,pdata + store 1,mem_state + fetch 2,mem_rx_window_init + store 2,mem_rx_window + disable wake + jam BT_EVT_EXIT_SNIFF,mem_fifo_temp + branch ui_ipc_send_event + + +check_attempt: + bpatch patch0d_4,mem_patch0d + branch check_attempt_normal + fetch 1,mem_tws_state + bmark1 mark_sco_flag,check_attempt0 + beq TWS_STATE_MASTER_LISTEN,check_attempt_nomore +check_attempt0: + //beq 0x69,p_check_attempt1// When master slave connected, must protect master slave link + beq TWS_STATE_MASTER_CONNECTED,check_attempt1 + branch check_attempt_normal +check_attempt1: + fetch 1,mem_state + bbit1 state_insniff,check_attempt_normal + branch check_attempt_nomore +check_attempt_normal: + enable attempt + fetch 1,mem_state + bbit1 state_insniff,check_attempt_sniff + rtnmark1 mark_testmode /* pdata won't be blank now, try attempt */ + fetch 1,mem_cur_arq + rtnbit1 wack + fetch 1,mem_lmp_to_send + nrtn blank + fetch 1,mem_op + rtnbit1 op_txl2cap +check_attempt_nomore: + force 0,pdata + rtn + +check_attempt_sniff: + bmark0 mark_sco_flag,check_attempt_for_acl + fetch 1,mem_current_sniff_attempt + fetcht 1,mem_esco_attempt + //fetcht 1,mem_sniff_attempt + //increase -1,temp + isub temp,null + branch check_attempt_sniff_change_to_acl,zero + //beq 5,check_attempt_sniff_change_to_acl + fetch 1,mem_cur_arq + bbit1 wack,check_attempt_notimeout + bmark0 mark_esco_rxok,check_attempt_notimeout +check_attempt_sniff_change_to_acl: + call load_context_to_acl + nbranch check_attempt_notimeout,master + fetch 1,mem_lmp_to_send + nbranch check_attempt_notimeout,blank +check_attempt_sco_master: + fetch 1,mem_sco_poll + increase -1,pdata + store 1,mem_sco_poll + nbranch check_attempt_nomore,blank + jam param_sco_poll,mem_sco_poll + branch check_attempt_notimeout + +check_attempt_for_acl: + fetch 1,mem_current_sniff_attempt + bne 1,check_attempt_notimeout + fetch 1,mem_current_sniff_timeout + branch check_attempt_notimeout,blank + increase -1,pdata + store 1,mem_current_sniff_timeout + fetch 1,mem_cur_arq + rtnbit1 wack // waiting for next ack + nrtn match // waiting for next poll +check_attempt_notimeout: + fetch 1,mem_current_sniff_attempt + increase -1,pdata + store 1,mem_current_sniff_attempt + rtn + + /* enable user if sniff window vialation, queue is extra overhead */ +sniff_check_window: + bpatch patch0d_5,mem_patch0d + disable swfine + copy temp,stop_watch + call context_search_sniff_window + disable user + nrtn zero + force 0,stop_watch + enable user + rtn + +parse_l2cap: + bpatch patch0d_6,mem_patch0d +// jam 1,mem_enter_lpm_flag + set0 mark_rxbuf_inuse,mark + call parse_l2cap_buff_process +parse_l2cap_buff_process: + jam L2CAP_RX_CLEAR,mem_l2cap_rx_done + call l2cap_malloc_is_fifo_nearly_full + nrtn blank + arg mem_lcp_block,rega + call queue_get_len + rtn blank + arg mem_lcp_block,rega + call queue_get_read_ptr + call process_rx_l2cap_pkt + fetch 1,mem_l2cap_rx_done + beq L2CAP_RX_DONE,pop_l2cap_queue + rtn + +/******************************************/ +/********** Transmit Packet *************/ +/******************************************/ + +slave_send_access: + bpatch patch0d_7,mem_patch0d + add clke_bt,1,bt_clk /* slave start to use native clock */ + call fetch_extm_bt_adr + force 0x03,freq_mode /* connection frequency */ + call tx_radio_freq + call start_transmitter + call start_tx_external + branch send_access_word + +tws_slave_conn_send_packet: + call tws_check_slave_anchor_pass_or_not + branch slave_conn_send_packet_normal,user + rtn + +slave_conn_send_packet: + bpatch patch0e_0,mem_patch0e + fetch 1,mem_tws_state + beq TWS_STATE_SLAVE_CONNECTED,clear_got_tx + beq TWS_STATE_SLAVE_LISTEN,clear_got_tx + beq TWS_STATE_MASTER_CONNECTED,tws_slave_conn_send_packet + beq TWS_STATE_MASTER_LISTEN,tws_slave_conn_send_packet +slave_conn_send_packet_normal: + call rf_setup_time_slave_slot + deposit clke_bt + fetcht 4,mem_next_btclk + isub temp,pdata + rtnne 1 /* missed slave slot */ + compare type_null,type,0x1f + nbranch slave_conn_send_access,true + fetch 1,mem_rx_type + rtn blank /* null packet, do nothing */ +slave_conn_send_access: + call slave_send_access +transmit_packet: + compare type_id,type,0x1f /* is this id only ? */ + branch end_of_packet,true + rshift bt_clk,temp + or temp,0x40,white_init +transmit_packet_whitened: + bpatch patch0e_1,mem_patch0e + enable enable_white + enable enable_hec + enable encode_fec1 + set0 mark_longpacket,mark + deposit am_addr + inject mod,3 /* am_addr, temp is disabled */ + deposit type + inject mod,4 + fetch 1,mem_cur_arq /* aka mem_cur_arq */ + inject bucket,4 /* align up to flowx, arqnx, seqnx */ + inject mod,3 + enable enable_parity + inject mod,8 /* transmit parity */ + disable encode_fec1 + disable enable_parity + disable enable_hec + set0 PSK3M,radio_ctrl + arg 0,temp + call reserve_slot + bpatch patch0e_2,mem_patch0e + and type,0x1f,pdata + beq type_lmp, transmit_lmp + beq type_null, end_of_packet + beq type_poll, end_of_packet + beq type_fhs, transmit_fhs /* master mode fhs need got_tx and ack */ + beq type_dm1, transmit_dm1 + beq type_dh1, transmit_dh1 + beq type_hv3, transmit_hev + beq type_2ev3,transmit_2ev3 + beq type_3dh1, transmit_3dh1 + arg 4,temp + call reserve_slot + beq type_dm3, transmit_dm3 + beq type_dh3, transmit_dh3 + arg 8,temp + call reserve_slot + beq type_dh5, transmit_dh5 + branch transmit_dm5 /* must be 14, dm5 */ + +transmit_2ev3: + disable encrypt + enable encode_fec0 + disable enable_white + set1 PSK,radio_ctrl +// isolate1 PSK3M,radio_ctrl +// branch transmit_edr3m1,true + setarg 0xabeee + inject mod,20 +// branch transmit_hev +//transmit_edr3m1: +// setarg 0x5faeba +// inject mod,24 +// setarg 0x12 +// inject mod,6 +transmit_hev: + enable enable_white + bpatch patch0e_3,mem_patch0e + enable encode_fec0 + enable enable_crc + enable encrypt + fetchr loopcnt,2,mem_sco_tx_packet_len + arg mem_sco_outdata,contr +transmit_ev_loop: + ifetch 1,contr + inject mod,8 + loop transmit_ev_loop + bmark1 mark_esco,transmit_end + branch end_of_packet + +transmit_fhs: + bpatch patch0e_4,mem_patch0e + fetch 1,mem_fhs_am_addr /* this is the am_addr to assign to slave */ + icopy am_addr + fetch 1,mem_fhs_misc + icopy fhs_misc /* [7:6]SR [5:4]SP [3:1]PS [0]undef */ + fetch 3,mem_class /* store away class */ + icopy fhs_class + fetch 2,mem_nap + icopy nap + enable enable_crc + enable encode_fec2 + copy bt_adr,rega + call fetch_self_bt_adr + pulse recalc + nop 32 /* 30 cycles after recalc for sync word generation */ + copy bt_clk,timeup + fetch 4,mem_clkn_bt + icopy bt_clk + preload fhs0 + set1 58,pdata /* eir */ + inject mod,72 + preload fhs1 + inject mod,72 + copy timeup,bt_clk + copy rega,bt_adr + enable enable_parity + inject mod,16 /* generate CRC */ + disable enable_parity + branch end_of_packet + +transmit_lmp: /* expect the payload ready as in bb spec */ + bpatch patch0e_5,mem_patch0e + enable encrypt + enable enable_crc + enable encode_fec2 + fetch 1,mem_lmo_header_length /* this is the payload header */ + and pdata,0x1f8,temp /* temp is number of bits, check payload header format */ + arg mem_lmo_header_length,contr + increase 8,temp /* temp is in bits */ +transmit_lmp_loop: + add temp,-72,regc /* regc is remainder */ + nbranch transmit_lmp_finish,positive + ifetch 9,contr + inject mod,72 + copy regc,temp + branch transmit_lmp_loop +transmit_lmp_finish: + ifetch 9,contr + iinject mod,temp + branch transmit_end + +transmit_dm1: + enable encode_fec2 + branch transmit_dmh +transmit_dm3: +transmit_dm5: + enable encode_fec2 + set1 mark_longpacket,mark + branch transmit_dmh + +transmit_3dh1: + set1 PSK3M,radio_ctrl +transmit_dh1: + enable encode_fec0 + branch transmit_dmh + +transmit_dh3: +transmit_dh5: + set1 PSK3M,radio_ctrl + enable encode_fec0 + set1 mark_longpacket,mark + +transmit_dmh: + bpatch patch0e_6,mem_patch0e + fetch 1,mem_state_map + bbit0 smap_edr,transmit_noedr + sub type,3,null + branch transmit_noedr,positive + disable encrypt + disable encode_fec2 + enable encode_fec0 + disable enable_white + set1 PSK,radio_ctrl + isolate1 PSK3M,radio_ctrl + branch transmit_edr3m,true + setarg 0xabeee + inject mod,20 + branch transmit_edr_sync_end +transmit_edr3m: + setarg 0x5faeba + inject mod,24 + setarg 0x12 + inject mod,6 +transmit_edr_sync_end: + enable enable_white + set1 mark_longpacket,mark +transmit_noedr: + enable encrypt + enable enable_crc + bmark1 mark_loopback,transmit_loopback + fetch 1,mem_tx_lch + inject mod,3 + //fetchr loopcnt,2,mem_tx_len + fetch 2,mem_tx_len + iforce loopcnt + bmark1 mark_longpacket,transmit_long + inject mod,5 + branch transmit_stuff +transmit_long: + inject mod,13 +transmit_stuff: + fetch 1,mem_device_option + beq dvc_op_hci,transmit_stuff_hci + deposit loopcnt + branch transmit_end,blank + fetch 2,mem_txptr + iforce contr +transmit_stuff_loop: + ifetch 1,contr + inject mod,8 + loop transmit_stuff_loop + branch transmit_end +transmit_stuff_hci: + fetch 2,mem_txptr + iforce contu +transmit_stuff_hci_loop: + ifetch 1,contu + inject mod,8 + loop transmit_stuff_hci_loop +transmit_end: + enable enable_parity + inject mod,16 + disable enable_parity + call set_wait_ack + fetch 1,mem_state_map + bbit0 smap_edr,end_of_packet + force 0,pdata + inject mod,6 /* edr trailer */ + branch end_of_packet + + +transmit_loopback: + bpatch patch0e_7,mem_patch0e + bmark1 mark_longpacket,transmit_loopback_long +transmit_loopback_short: + fetch 1,mem_lch_code + inject mod,3 /* LLID and FLOW */ + fetch 1,mem_len /* take packet length */ + iforce regc + inject mod,5 + branch transmit_loopback_cont +transmit_loopback_long: + fetch 1,mem_lch_code + inject mod,3 /* LLID and FLOW */ + fetch 2,mem_len /* take packet length */ + iforce regc + inject mod,13 +transmit_loopback_cont: + arg mem_rxbuf,contr +transmit_loopback_loop: + copy regc,null + branch transmit_loopback_end,zero + ifetch 1,contr + inject mod,8 + increase -1,regc + branch transmit_loopback_loop +transmit_loopback_end: + fetch 2,mem_tst_pktcnt_dmh + increase 1,pdata + store 2,mem_tst_pktcnt_dmh + branch transmit_end + + +apply_switch_clke: + fetch 4,mem_clke_bt + add pdata,7,rega + fetch 2,mem_slot_offset + nbranch apply_switch_nozero,blank + increase -3,rega + branch apply_switch_wait_loop +apply_switch_nozero: + mul32 pdata,12,pdata + fetcht 2,core_rthalfslot + increase 1,temp +apply_switch_loop: + isub temp,pdata + nbranch apply_switch_bt,positive + increase -1,rega + branch apply_switch_loop +apply_switch_bt: + sub pdata,0,pdata +apply_switch_wait_loop: + until null,oneslot + compare 0,clkn_bt,3 + nbranch apply_switch_wait_loop,true + iforce clke_rt + copy rega,clke_bt + iforce clke_rt + rtn + + +calc_slot_offset: + bpatch patch0f_0,mem_patch0f + until null,halfslot + deposit clke + iforce contr + rshift16 pdata,pdata + isub clkn_bt,loopcnt + and_into 3,loopcnt /* bt portion */ + nbranch calc_bt_portion,zero + force 0,pdata + branch calc_skip_bt +calc_bt_portion: + arg 3750,temp + force 0,pdata +calc_slot_offset_loop: + iadd temp,pdata + loop calc_slot_offset_loop +calc_skip_bt: + iadd contr,pdata /* add rt portion */ + div pdata,12 + call wait_div_end + quotient pdata + store 2,mem_slot_offset + rtn + +calc_clke_offset: + bpatch patch0f_1,mem_patch0f + deposit clke + copy clkn,temp + isub temp,null + nsetflag positive,44,pdata + isub temp,temp + setarg 3750 + isolate0 15,temp + branch calc_clke_pos,true + setarg -61786 + iadd temp,temp +calc_clke_pos: + storet 6,mem_le_clk_offset + storet 6,mem_clk_offset + rtn + +calc_clke: + disable clknt + fetch 6,mem_le_clk_offset + branch calc_clke2,le +calc_clke_tws: + fetch 6,mem_clk_offset +calc_clke2: + iadd clkn,alarm + increase 10,alarm + setarg 3750 + isub alarm,pdata + isolate0 15,pdata + branch calc_clke_pos_adj,true + setarg 0xf15a + iadd alarm,alarm +calc_clke_pos2: + copy alarm,clke + rtn +calc_clke_pos_adj: /* add 2 clock */ + force 0,null + branch calc_clke_pos2 + +/******************************************/ +/********* RF related functions ***********/ +/******************************************/ + + +calc_radio_freq: + bpatch patch0f_2,mem_patch0f + call set_sync_on + copy bt_clk,pdata + and_into 0x180,pdata + compare 3,freq_mode,0x07 + nbranch freq_not_connection,true /* don't do the hack if not in connection */ + rshift3 pdata,pdata + iadd freq_index,pdata + branch do_hop_mod_now +freq_not_connection: + copy freq_index,pdata +do_hop_mod_now: + div pdata,79 + pulse recalc /* now is good time to recalc id */ + call wait_div_end + remainder rega + add rega,-40,temp + branch odd_half,positive + lshift rega,temp + branch freq_result +odd_half: + lshift temp,temp + increase 1,temp +freq_result: + bpatch patch0f_3,mem_patch0f + fetch 1,mem_mode + bbit0 afh_change,afh_process_con +afh_process_0: + fetch 4, mem_afh_instant + isub bt_clk, null + branch afh_process_con,positive + call afh_clear + fetch 1,mem_afh_new_mod + rtn blank + fetch 1,mem_mode + set1 afh_enable,pdata + store 1,mem_mode + fetch 5,mem_afh_map_new + store 5,mem_afh_map_lo + ifetch 5,contr + store 5,mem_afh_map_hi + call afh_process_freq_map +afh_process_con: + fetch 1,mem_mode + rtnbit0 afh_enable + isolate1 1,bt_clk + branch afh_same_channel,true /* at odd slot, use the same as last even */ + rshift3 temp,rega + and temp,7,queue + setarg mem_afh_map_lo + iadd rega, rega + ifetch 1, rega + qisolate0 pdata + branch afh_process_1,true /* not in map, do afh */ + deposit temp + branch afh_process_end +afh_process_1: + //fetchr regb,1,mem_afh_used + fetch 1,mem_afh_used + copy pdata,regb + deposit bt_clk + and_into 0x180, pdata + rshift3 pdata,pdata + iadd freq_index,pdata + idiv regb + setarg mem_afh_map + call wait_div_end + remainder rega + iadd rega,contr + ifetch 1,contr +afh_process_end: + store 1,mem_afh_index + iforce temp + rtn + +afh_same_channel: + fetch 1, mem_afh_index /* last afh index */ + iforce temp + rtn + +afh_clear: + fetch 1,mem_mode + set0 afh_enable,pdata + set0 afh_change,pdata + store 1,mem_mode + rtn +/* +fixed_frequency: + fetcht 1,mem_fixed_freq + rtn +*/ +afh_process_freq_map: + bpatch patch0f_4,mem_patch0f + arg mem_afh_map,contw + force 10,loopcnt + call memset0 + arg mem_afh_map,contw + force 0,regC + force 2,queue +process_freq_3: + fetch 5,mem_afh_map_lo + iforce temp + compare 2,queue,0xff + branch process_freq_1,true + rshift temp,temp +process_freq_1: + isolate0 0,temp + branch process_freq_0,true + deposit regC + istore 1,contw +process_freq_0: + rshift2 temp,temp + increase 2,regC + compare 40,regC,0xfe + nbranch process_freq_2,true + fetch 5,mem_afh_map_hi + iforce temp + compare 2,queue,0xff + branch process_freq_2,true + rshift temp,temp +process_freq_2: + sub regC,78,null + branch process_freq_1,positive + force 1,regC + increase -1,queue + nbranch process_freq_3,zero + arg mem_afh_map,rega + deposit contw + isub rega,pdata + store 1,mem_afh_used + rtn + +rx_radio_freq: + bpatch patch0f_5,mem_patch0f + call calc_radio_freq + fetch 1,mem_debug_config + bbit0 debug_rx_fixed_freq,rx_radio_freq_now + fetcht 1,mem_rx_fixed_freq +rx_radio_freq_now: + branch set_freq_rx + + +tx_radio_freq: + bpatch patch0f_6,mem_patch0f + call calc_radio_freq + fetch 1,mem_debug_config + bbit0 debug_tx_fixed_freq,tx_radio_freq_now + fetcht 1,mem_tx_fixed_freq +tx_radio_freq_now: + branch set_freq_tx + + +fetch_giac: + force 0,uap + fetch 3,mem_glap + iforce lap + rtn + +fetch_page_bt_adr: + fetch 1,mem_hci_puap + icopy uap + fetch 3,mem_hci_plap + icopy lap + rtn + +fetch_self_bt_adr: + bpatch patch0f_7,mem_patch0f + fetch 2,mem_nap + icopy nap + fetch 1,mem_uap + icopy uap + fetch 3,mem_lap + icopy lap /* copy self_adr,bt_adr */ /* use own address */ + rtn + +fetch_extm_bt_adr: + bpatch patch10_0,mem_patch10 + fetch 2,mem_pnap + icopy nap + fetch 1,mem_puap + icopy uap + fetch 3,mem_plap + icopy lap + rtn + + +fetch_diac: + bmark1 mark_all_diac,fetch_diac_do + rtnmark0 mark_inquiry_state + rtnmark0 mark_periodical_diac +fetch_diac_do: + and_into -256,lap + pulse recalc + nop 32 + rtn + + +shutdown_radio: + bpatch patch10_1,mem_patch10 + call rf_shutdown_radio_for_debug + branch shutdown_radio0,is_rx + jam 0xd4, 0x8955 + nop 4 + jam 0xd2, 0x8955 + nop 4 + jam 0xd1, 0x8955 + nop 4 + fetch 1,mem_tx_power + beq TX_POWER_0DB,shutdown_radio_0db + beq TX_POWER_3DB,shutdown_radio_3db + beq TX_POWER_5DB,shutdown_radio_5db + beq TX_POWER_f3DB,shutdown_radio_f3db + beq TX_POWER_f5DB,shutdown_radio_f5db +shutdown_radio_5db: +shutdown_radio_0db: + jam 0xd0, 0x8955 + jam 0xe0, 0x8956 +shutdown_radio0: + force 0,radio_ctrl + disable is_rx + disable is_tx + pulse packet_end + jam 0x0,rfen_mdm + jam 0x0,rfen_tx + jam 0x0,rfen_rx + jam 0,rfen_sn + jam 0x70,rfen_msc + fetch 1,rfen_adc + set0 0,pdata + store 1,rfen_adc + rtn + +shutdown_radio_f5db: +shutdown_radio_f3db: +shutdown_radio_3db: + jam 0xd0,0x8955 + jam 0xc0,0x8956 + branch shutdown_radio0 + + +set_sync_on: + bpatch patch10_2,mem_patch10 + jam 0x77,rfen_msc + jam 0x03,rfen_sn + nop 10 + jam 0x83,rfen_sn + jam 0x7f,rfen_msc + jam 0xa7,rfen_sn + rtn + + +set_freq_rx: + bpatch patch10_3,mem_patch10 + /* IF is +2MHz */ + storet 1,mem_last_freq + add temp,rx_freq_offset,rega /* index to frequency */ + branch rf_write_freq +rf_rx_enable: + bpatch patch10_4,mem_patch10 + call rf_debug_active_rx_line + jam 0xcf,rfen_tx + nop 10 /* wait adc clk48 ready */ + jam 0xff,rfen_rx + jam 0xaf,rfen_sn + jam 0xff,rfen_msc + nop 10 + jam 0xa0,rfen_mdm + rtn + +set_offset_sfreq: + add temp,tx_freq_offset,rega /* index to frequency */ + rtn + +set_freq_tx: + bpatch patch10_5,mem_patch10 + storet 1,mem_last_freq + add temp,0,rega /* index to frequency */ + fetch 1,mem_sfreq_enable + ncall set_offset_sfreq,blank + call rf_write_freq + fetch 2,mem_param_pll_setup + call sleep +rf_tx_enable: + fetch 1,rfen_adc + set1 0,pdata + store 1,rfen_adc + jam 0x3c,rfen_rx + jam 0xe0,rfen_tx + nop 10 /* wait LDOs to turn ON*/ + jam 0x01, rfen_mdm + jam 0x3d, rfen_mdm + nop 10 /* wait tx blocks to turn ON*/ + jam 0xb7,rfen_sn + nop 10 /* wait tx lo buffer to turn ON*/ + jam 0x7d, rfen_mdm + fetch 1,mem_tx_power + beq TX_POWER_0DB,set_tx_power_0db + beq TX_POWER_3DB,set_tx_power_3db + beq TX_POWER_5DB,set_tx_power_5db + beq TX_POWER_f3DB,set_tx_power_f3db + beq TX_POWER_f5DB,set_tx_power_f5db +set_tx_power_0db: + jam 0xf0,0x8956 + call txon_common + jam 0xd8,0x8955 + rtn + +set_tx_power_3db: + jam 0xdf,0x8956 + call txon_common + jam 0xdf,0x8955 + rtn + +set_tx_power_5db: + jam 0xff,0x8956 + call txon_common + jam 0xdf,0x8955 + rtn + +set_tx_power_f3db: + jam 0xce,0x8956 + call txon_common + jam 0xd8,0x8955 + rtn + +set_tx_power_f5db: + jam 0xcb,0x8956 + call txon_common + jam 0xd8,0x8955 + rtn + +txon_common: + nop 4 + jam 0xd1,0x8955 + nop 4 + jam 0xd2,0x8955 + nop 4 + jam 0xd4,0x8955 + rtn + + +initialize_radio: + jam clksel_rc,core_clksel +initialize_radio_wait: + fetch 2,mem_rf_init_ptr + bbit0 14,initialize_radio_wait + iforce contr + arg 0x8900,temp +initialize_radio_loop: + ifetch 1,contr + beq 0xff,initialize_radio_cont + ior temp,contw + ifetch 1,contr + istore 1,contw + branch initialize_radio_loop +initialize_radio_cont: + bpatch patch10_6,mem_patch10 + fetch 1,mem_sfreq_enable + ncall sfreq_init,blank + call lpm_cal_xtal_startup + call switchto_dpllclk +// ncall check_dpll,wake + setarg param_dpll_start_delay + iadd clkn_bt,pdata + store 4,mem_dpll_clkn + set1 RESET,radio_ctrl + force 0,radio_ctrl + ncall do_rccal,wake + branch set_rccal + + /* rega is frequency, 00=2400Mhz */ +rf_write_freq: + bpatch patch10_7,mem_patch10 + setarg 2400 + iadd rega,temp + fetch 1,mem_fcomp_mul + jam 0x04,rf_pll_rstn + imul32 temp,pdata + fetcht 1,mem_fcomp_div + idiv temp + call wait_div_end + quotient rega /* rega is FLOOR(FVCO/fcomp) */ + remainder pdata + lshift16 pdata,pdata + lshift4 pdata,pdata /* pdata is frac * 2^20 */ + idiv temp + call wait_div_end + quotient pdata /* pdata is frac *2^20/fcomp */ + lshift8 pdata,pdata + lshift pdata,pdata + ior rega,pdata + store 4,rf_pll_intg + jam 0x44,rf_pll_rstn + jam 0xc4,rf_pll_rstn + rtn + +// For same freq rx/tx +sfreq_init: + jam 0xff,0x8907 //7~5 000:0M IF 011:1M IF 111:2M IF + //jam 0x80,0x8065 //no_toggle + //jam 0x80,0x8909 //tx_iq_swap + jam 0x4f,0x8912 + rtn + +do_rccal: + bpatch patch11_0,mem_patch11 + fetch 1,rfen_adc + set1 1,pdata + store 1,rfen_adc + setarg 250000 + call sleep /* wait clkpll&xtal stable */ + jam 0x7f,rfen_rx + nop 130 + jam 0x30,rf_rccal_ctrl + jam 0xd0,rfen_tx + jam 0x70,rf_rccal_ctrl + jam 0xf0,rf_rccal_ctrl + force 50,loopcnt +do_rccal_loop: + fetch 1,rf_rccal_result + bbit1 5,do_rccal_end + loop do_rccal_loop +do_rccal_end: + store 1,mem_rf_rccal + jam 0,rfen_tx + jam 0,rfen_rx + fetch 1,rfen_adc + set0 1,pdata + store 1,rfen_adc +ifndef ROMCODE + jam 0x30,mem_rf_rccal +endif + rtn + +set_rccal: + bpatch patch11_1,mem_patch11 + fetch 1,mem_rf_rccal + set1 5,pdata + store 1,rf_rccal_ctrl + fetcht 1,rf_bpf_ctrim + and_into 7,temp + lshift3 pdata,pdata + ior temp,pdata + store 1,rf_bpf_ctrim + fetch 1,rf_bpf_ib + set0 bpf_rccal,pdata + store 1,rf_bpf_ib + fetch 1,rf_adc_rccal + set0 adc_rccal,pdata + store 1,rf_adc_rccal + rtn + +save_rssi: + bpatch patch11_2,mem_patch11 + fetch 2,rf_afc_d2a + rshift4 pdata,pdata + rshift3 pdata,pdata + sub pdata,0,pdata + and_into 0xff,pdata + div pdata,10 + call wait_div_end + quotient pdata + lshift4 pdata,pdata + remainder temp + ior temp,pdata + store 1,mem_rssi /* bcd value */ + rtn + +switchto_rcclk: + jam 0xa,core_clksel + jam 0,rfen_ck + fetch 3,core_lpm_ctrl + until null,lpo_edge + store 3,core_lpm_reg + jam 0xfc,core_lpm_reg + jam lpmreg_sel_ctrl,core_lpm_wr + nop 1000 + rtn + +switchto_dpllclk: + jam clksel_rc,core_clksel + fetch 1,rf_clkpll_frac+2 + set0 4,pdata + set0 5,pdata + store 1,rf_clkpll_frac+2 + jam 0x00,rfen_ck + jam 0x00,rfen_msc + jam 0x70,rfen_msc + jam 0xff,rfen_ck + fetch 1,rf_clkpll_frac+2 + set1 4,pdata + set1 5,pdata + store 1,rf_clkpll_frac+2 + call init_lpm_ctrl + fetch 1,rf_clkpll_int + set1 7,pdata + store 1,rf_clkpll_int + set0 7,pdata + store 1,rf_clkpll_int + set1 7,pdata + store 1,rf_clkpll_int + jam clksel_xtal,core_clksel + fetch 1,rf_clkpll_frac+2 + and_into 0xcf,pdata + store 1,rf_clkpll_frac+2 + or_into 0x30,pdata + store 1,rf_clkpll_frac+2 + rtn + +check_dpll: + nop 1000 + jam clksel_xtal,core_clksel + nop 10 + jam 0x00,core_bist_ctrl + jam ccnt_start,core_misc_ctrl +check_dpll_loop: + fetch 1,core_perf_status + bbit0 1,check_dpll_loop + fetcht 3,core_ccnt_counter + jam clksel_dpll,core_clksel + nop 10 + jam ccnt_start,core_misc_ctrl +check_dpll_loop2: + fetch 1,core_perf_status + bbit0 1,check_dpll_loop2 + fetch 3,core_ccnt_counter + isub temp,pdata + branch check_dpll_pos,positive + sub pdata,0,pdata +check_dpll_pos: + store 2,mem_dpll_error + sub pdata,70,null +check_dpll_assert: + nbranch check_dpll_assert,positive + rtn + +xtal_fast_wake: + setarg 0xf0f + branch lpm_write_config + +init_lpm_ctrl: + setarg 0x80f + branch lpm_write_config + + + +start_receiver: + bpatch patch11_3,mem_patch11 + call rf_rx_enable + disable is_tx + enable is_rx + pulse init_encrypt + rtn + +prep_crypt: + bpatch patch11_4,mem_patch11 + fetch 1,mem_state_map + isolate1 smap_encryption,pdata + setflag true,0,pdata + fetcht 1,core_sysctrl + and temp,0xfe,temp + ior temp,pdata + store 1,core_sysctrl + arg mem_kc,contr + ifetch 9,contr + iforce kc_ls + ifetch 7,contr + iforce kc_ms + fetch 1,mem_key_size + add pdata,-1,g1l + pulse kc_p_activate /* immediately start calculating primary Key */ + rtn + +wait_access_clke_rt: + bpatch patch11_5,mem_patch11 + enable decode_fec0 + arg param_conn_access,timeup + correlate clke_rt,meet /* keep correlating until sync is found, stop on no other condition */ +wait_access_end: + deposit clke + store 6,mem_sync_clke + disable decode_fec0 + nbranch shutdown_radio,sync + arg param_clke_cal,clke_rt + increase 1,clke_bt + and_into 0x1fc,clke_bt + rtn + + + +wait_access_mhalfbnd: + enable decode_fec0 +wait_access_mhalfbnd_correlate: + correlate null,mhalfbnd /* keep correlating until sync is found, or clke half */ + branch wait_access_end,sync + compare 0x02,clke_bt,0x02 + nbranch wait_access_mhalfbnd_correlate,true + branch wait_access_end + +wait_access_clkn_rt: + bpatch patch11_6,mem_patch11 + arg param_conn_access,timeup /* found sync must occur within this time */ + enable decode_fec0 + correlate clkn_rt,meet /* keep correlating until sync is found, or until clkn_rt timeup */ + disable decode_fec0 + nbranch shutdown_radio,sync + rtn + +wait_access_forever: + bpatch patch11_7,mem_patch11 + enable decode_fec0 + correlate null,timeout /* keep correlating until sync is found, or timeout */ + disable decode_fec0 + nbranch shutdown_radio,sync + arg param_clke_cal,clke_rt + and_into 0x1fc,clke_bt + rtn + + /* reserve slots for mult-slot packet */ +reserve_slot: + deposit bt_clk + iadd temp,timeup + //storer timeup,4,mem_next_btclk + copy timeup,pdata + store 4,mem_next_btclk + and type,0xf,pdata + rtn + + /* pdata = clks ahead of bt_clk */ +ahead_window: + copy pdata,temp + bpatch patch12_0,mem_patch12 + copy temp,pdata + call clk2bt + lshift16 bt_clk,pdata + set1 44,pdata + call clk_diff + set0 44,pdata + call get_clk + call clk_diff + rtn user + call clk2rt + iforce stop_watch + until null,timeout + rtn + + +setup_clk: + bpatch patch12_1,mem_patch12 + branch setup_clkn,clknt + until clke_rt,meet +skip_setup_clke: + copy clke_bt,temp + branch setup_clknbt +setup_clkn: + branch skip_setup_clkn,attempt + until clkn_rt,meet +skip_setup_clkn: + copy clkn_bt,temp +setup_clknbt: + branch setup_clk11,user + compare 1,temp,3 + nbranch setup_clk,true +setup_complete: + bpatch patch12_2,mem_patch12 + fetch 1,mem_state + rtnbit0 state_inconn + fetch 4,mem_next_btclk + isub temp,pdata + nrtn positive + sub pdata,0xff,null + branch setup_clk,positive + rtn +setup_clk11: + compare 3,temp,3 + nbranch setup_clk,true + branch setup_complete + +rf_setup_time: + bpatch patch12_3,mem_patch12 + fetchr timeup,2,mem_param_rf_setup + branch setup_clk + +rf_setup_time_slave_slot: + disable user + branch rf_setup_time + +rf_setup_time_master_slot: + enable user + branch rf_setup_time + +start_transmitter: + bpatch patch12_4,mem_patch12 + call prep_crypt + disable is_rx + enable is_tx + rtn + + + +start_tx_native: + bpatch patch12_5,mem_patch12 + arg param_tx_setup,timeup + until clkn_rt,meet /* wait until start_tx time */ + pulse init_encrypt + rtn + +start_rx_native: + bpatch patch12_6,mem_patch12 + arg param_rx_setup,timeup + until clkn_rt,meet + rtn + + +start_tx_external: + bpatch patch12_7,mem_patch12 + arg param_tx_setup,timeup + until clke_rt,meet /* wait until start_tx time */ + pulse init_encrypt + rtn + +send_access_word: + bpatch patch13_0,mem_patch13 + call rf_debug_active_tx_line + preload access /* load in access word ready to be sent */ + enable encode_fec0 + set1 TXGFSK,radio_ctrl + inject mod,72 + disable encode_fec0 + rtn + + +scan_mode_whiten: + copy xin,temp + or_into 0x60,temp /* extend xin with 5->1, 6->1 */ + copy temp,white_init + rtn + + + + /* return blank if free amaddr is found */ +get_free_amaddr: + bpatch patch13_1,mem_patch13 + fetch 1,mem_current_amaddr + increase 1,pdata + bne param_esco_addr,get_free_amaddr_cont + force 1,pdata +get_free_amaddr_cont: + store 1,mem_current_amaddr + iforce am_addr + rtn + +get_clk: + copy clkn,temp + rtn master + copy clke,temp + rtn + +get_clkbt: + deposit clkn_bt + rtn master + deposit clke_bt + rtn + + +supervision_update: + bpatch patch13_2,mem_patch13 + fetcht 4,mem_supervision_timer + call get_clkbt + isub temp,timeup /* and to 28 bits */ + deposit timeup + fetcht 2,mem_supervision_to + lshift temp,temp + isub temp,pdata + rtn + +supervision_flush: + bpatch patch13_3,mem_patch13 + call get_clkbt + store 4,mem_supervision_timer + rtn + +assert: + bpatch patch13_4,mem_patch13 + branch assert + +sleep: + rtn blank + /* sleep pdata clocks, only even clocks are accurate */ + rshift pdata,pdata + increase -3,pdata +sleep_loop: + increase -1,pdata + nbranch sleep_loop,zero + force 0,pdata + rtn + + + +init_param: + /* clear specified sched ram */ + arg 0x10,loopcnt + arg 0,contw + call memset0 + arg mem_le_state,contw + arg 10,loopcnt + call memset0 + jam 0,mem_sp_calc + jam 0,mem_fifo_temp + jam 0,mem_le_testtype + jam 0,mem_debug_config + jam 0,mem_lmp_conn_state + bpatch patch13_5,mem_patch13 + jam 0,mem_connection_options + jam 0,mem_tester_emulate + jam 0,mem_tester_cnt + setarg param_glap + store 3,mem_glap + setarg param_acl_pktlen + store 2,mem_acl_pktlen + jam param_sco_pktlen,mem_sco_pktlen + jam param_acl_pktcnt,mem_acl_pktcnt + jam param_sco_pktcnt,mem_sco_pktcnt + setarg param_hci_version + store 3,mem_hci_version + jam 0x60,mem_fhs_misc /* R1 for 1.28s ps interval,P2 */ + jam param_max_slot,mem_max_slot + jam 0x02,mem_fw_ver /* set firmware version */ +ifdef SIMPLE_PAIRING + fetch 1,mem_ssp_enable + ncall init_memp,blank +endif +ifdef SECURE_CONNECTION + fetch 1,mem_le_secure_connect_enable + ncall init_memp_256,blank +endif + bpatch patch13_6,mem_patch13 +init_param_cont: + rtn wake + setarg 0 + store 2,mem_tx_len + rshift clkn_bt,pdata + store 4,mem_last_clkn + rtn + + + +/* +init_250k: + enable le + setarg 0x8e89be + lshift8 pdata,pdata + or_into 0xd6,pdata + iforce access + jam 7,0x8914 // enable ble + jam 0xa0,0x890a + jam 0x8f,0x890d // enable 250k + jam 0x0f,0x8911 + jam 0x87,0x8912 // disable agc + rtn +*/ + +/*****************************************LPO************************************************/ + + +kscan_init: + call kscan_row_add_bcc_check + call kscan_col_add_bcc_check + arg mem_kscan_row_gpio_pin,regc + fetchr loopcnt,1,mem_kscan_row_nums + call kscan_row_state_init + arg mem_kscan_col_gpio_pin,regc + fetchr loopcnt,1,mem_kscan_col_nums +kscan_col_state_init: + ifetcht 1,regc + call gpio_config_input + increase 1,regc + loop kscan_col_state_init + rtn +kscan_row_state_init: + ifetcht 1,regc + call gpio_out_active + increase 1,regc + loop kscan_row_state_init + rtn + + +kscan_get_col_state_commom: + arg mem_kscan_col_gpio_pin, regc + fetchr loopcnt,1,mem_kscan_col_nums +kscan_get_col_state_commom_loop: + ifetcht 1, regc + call gpio_get_bit + rtn true + increase 1,regc + loop kscan_get_col_state_commom_loop + rtn + +kscan_no_keypress: + jam NO_GET_KEYPRESS,mem_get_keypress_flag + jam NO_GET_KEYPRESS,mem_get_keypress_flag_record + rtn +kscan_get_keypress: + jam GET_KEYPRESS,mem_get_keypress_flag + jam GET_KEYPRESS,mem_get_keypress_flag_record + branch kscan_init + +kscan_enter_first_step: + arg mem_kscan_col_gpio_pin, regc + fetchr loopcnt,1,mem_kscan_col_nums + arg 0,rega +kscan_get_col_state_loop: + ifetcht 1, regc + call gpio_get_bit + branch kscan_avoid_shake, true //low , in + increase 1,regc + increase 1,rega + loop kscan_get_col_state_loop + rtn +kscan_avoid_shake: + call delay_10ms + ifetcht 1, regc + call gpio_get_bit + branch kscan_confirm_col_num,true + branch kscan_no_keypress +kscan_confirm_col_num: + storer rega,1,mem_col_scanned + storer rega,1,mem_col_scanned_record + arg 0,rega + branch kscan_enter_second_step + +kscan_confirm_row_num: + storer rega,1,mem_row_scanned + storer rega,1,mem_row_scanned_record + jam 0,mem_row_cnt + branch kscan_get_keypress + +kscan_enter_second_step: + arg mem_kscan_row_gpio_pin,regc + fetchr loopcnt,1,mem_kscan_row_nums + jam 0,mem_row_cnt +kscan_row_output_reverse_loop: + fetch 1,mem_row_cnt + ifetcht 1,regc + ixor rega,null + branch kscan_row_output_reverse1,zero + set1 gpio_active_bit,temp +kscan_row_output_reverse1: + increase 1,pdata + store 1,mem_row_cnt + call gpio_out_active + increase 1,regc + loop kscan_row_output_reverse_loop + call kscan_get_col_state_commom + branch kscan_confirm_row_num,true + increase 1,rega + fetch 1,mem_kscan_row_nums + isub rega,null + branch kscan_no_keypress,zero + branch kscan_enter_second_step + + +keyscan_check_fail: + fetch 1,mem_keyscan_switch + beq KEYSCAN_FAIL,app_check_keyscan + rtn + +kscan_row_add_bcc_check: + fetch 1,mem_kscan_row_nums + arg mem_kscan_row_gpio_pin,contr +kscan_add_bcc_check_common: + call p_calc_bcc + copy contr,contw + istoret 1,contw + rtn +kscan_col_add_bcc_check: + fetch 1,mem_kscan_row_nums + arg mem_kscan_col_gpio_pin,contr + branch kscan_add_bcc_check_common + + +keyscan_check: + fetch 1,mem_keyscan_switch + rtneq KEYSCAN_OFF + branch keyscan_check1 + +keyscan_check1: + call keyscan_row_check_bcc + nbranch keyscan_check_fail,user + call keyscan_col_check_bcc + nbranch keyscan_check_fail,user + call kscan_init + branch kscan_enter_first_step + + +//input:contr is calc bcc data ptr +//pdata:data length + +p_calc_bcc: + arg 0,temp + copy pdata,loopcnt +p_calc_bcc1: + ifetch 1,contr + ixor temp,temp + loop p_calc_bcc1 + rtn +keyscan_row_check_bcc: + fetch 1,mem_kscan_row_nums + arg mem_kscan_row_gpio_pin,contr + branch keyscan_check_bcc + +keyscan_col_check_bcc: + fetch 1,mem_kscan_row_nums + arg mem_kscan_col_gpio_pin,contr + branch keyscan_check_bcc + +keyscan_check_bcc: + call disable_user + call p_calc_bcc +keyscan_length_0: + ifetch 1,contr + ixor temp,pdata + nrtn blank + branch enable_user + +lpmstate: + jam 0xc8,core_sysctrl // enable lpo clock + setarg 0xee21 + store 2,core_clkoff // disable unused peripherals + fetch 4,core_gpio_in + store 4,mem_saved_gpio_in + fetch 1,core_lpm_ldocnt + bbit0 gpio_latch,loadcode // power up boot + enable wake + bbit0 cold_wake,lpmwake + disable wake + deposit auxcnt + nbranch lpmwake,blank // sleep interrupted, wakeup + fetch 1,core_lpm_ldotrim + bbit1 reload_code,lpmwake + arg param_hibernate_clks,temp + until null,lpo_edge + branch lpm_enter_sleep +lpmwake: + call lpm_write_ctrl2 + jam lpmreg_sel_ctrl2,core_lpm_wr + fetch 3,core_lpm_xtalcnt + store 3,core_lpm_reg + ifetch 1,contr + or_into isogate_mask,pdata // open all isolation gate&power switch + istore 1,contw + until null,lpo_edge // until switch value written + jam lpmreg_sel_ctrl2,core_lpm_wr + fetch 1,core_lpm_isogate + set1 enable_retmem,pdata + store 1,core_lpm_isogate + until null,lpo_edge + call lpm_load_context,wake + fetch 1,core_lpm_reg+2 + set0 gpio_latch,pdata // enable gpio fuction + store 1,core_lpm_reg+2 + nbranch loadcode,wake // wakeup from hibernate + call load_ucode + call keyscan_check + call app_check_keyscan + fetch 1,core_lpm_ldotrim + bbit1 reload_code,loadcode + rtn + +lpm_load_context: + call lpm_read_retention + fetch 1,mem_saved_spidctrl + store 1,core_spid_ctrl + arg mem_saved_gpio,contr + arg core_gpio_conf,contw + call memcpy32 + arg core_gpio_conf1,contw + call memcpy8 + fetch 8,mem_saved_mark + iforce mark +lpm_load_context_wakeup: + fetch 5,core_gpio_wakeup_low + store 5,mem_gpio_wakeup_low + fetch 5,core_gpio_wakeup_high + istore 5,contw + rtn + +lpm_save_context: + deposit mark + store 8,mem_saved_mark + arg core_gpio_conf,contr + arg mem_saved_gpio,contw + call memcpy32 + arg core_gpio_conf1,contr + call memcpy8 + fetch 1,core_spid_ctrl + store 1,mem_saved_spidctrl + branch lpm_write_gpio_wakeup + +lpo_calibration: + fetch 1,core_bist_ctrl + nbranch lpo_cal_inited,blank + fetch 3,mem_clks_per_lpo + nrtn blank + jam 0xc0,core_bist_ctrl + jam ccnt_start,core_dma_start +lpo_cal_inited: + fetch 1,core_perf_status + rtnbit0 1 + fetch 3,core_ccnt_counter + store 3,mem_clks_per_lpo + rtn + + + /* temp is synced clke */ +lpm_adjust_clk: + bpatch patch13_7,mem_patch13 + deposit clke + call clk_diff_rt + fetcht 4,mem_sleep_counter_all + sub temp,0xff,null + rtn positive // interval too small + lshift8 pdata,pdata + lshift4 pdata,pdata + idiv temp + call wait_div_end + quotient pdata + arg param_lpm_adjmax,temp + call ceiling + store 1,mem_lpm_adjust + nbranch lpm_adjust_positive,user + sub pdata,0,pdata +lpm_adjust_positive: + fetcht 3,mem_clks_per_lpo + iadd temp,pdata + store 3,mem_clks_per_lpo +lpm_clear_counter: + setarg 0 + store 4,mem_sleep_counter_all + rtn + + + +lpm_close_patchram: + fetch 1,mem_lpm_config+2 + set1 reload_code,pdata + store 1,mem_lpm_config+2 + fetch 1,mem_lpm_memory_choose + store 1,mem_lpm_xtalcnt + 4 + rtn + + + + /* temp is lpo counter for doze */ +lpm_doze: + fetch 1,mem_lpm_config+2 + set1 reload_code,pdata + store 1,mem_lpm_config+2 + branch lpm_hibernate_normal + + + + /* no retention memory at all */ +lpm_hibernate: + bpatch patch14_0,mem_patch14 + arg param_hibernate_clks,temp + fetch 1,mem_lpm_config+1 + set0 7,pdata /* lowest lpo */ + store 1,mem_lpm_config+1 +lpm_hibernate_normal: + bpatch patch14_1,mem_patch14 + call ipc_check_ack + call lpm_write_gpio_wakeup + fetch 1,mem_lpm_hibernate_switch + store 1,mem_lpm_xtalcnt + 4 + fetch 1,mem_lpm_xtalcnt + 2 + set1 cold_wake,pdata + store 1,mem_lpm_xtalcnt + 2 + + /* temp is lpo clocks to sleep */ +lpm_sleep: + bpatch patch14_2,mem_patch14 + fetch 1,mem_lpm_loadcode_switch + ncall lpm_close_patchram,blank + call xtal_fast_wake + fetch 4,mem_sleep_counter_all + iadd temp,pdata + store 4,mem_sleep_counter_all + call lpm_save_context + call lpm_write_ctrl2 + jam lpmreg_sel_ctrl2,core_lpm_wr + fetch 5,mem_lpm_xtalcnt + store 4,core_lpm_reg + rshift32 pdata,rega + deposit clkn + store 6,mem_sleep_clkn + until null,lpo_edge + call lpm_read_retention + storer rega,1,core_lpm_isogate +lpm_enter_sleep: + jam lpmreg_sel_counter,core_lpm_wr + until null,lpo_edge + storet 4,core_lpm_reg + until null,never + + /* trigger clock to ram, make cs high active */ +lpm_read_retention: + jam 0x6c,core_clkoff+1 + jam 0x80,core_ucode_ctrl + fetch 4,core_ucode_data + jam 0,core_ucode_ctrl + fetch 4,0x4000 + fetch 4,0x10000 + rtn + +lpm_recover_clk: + bpatch patch14_3,mem_patch14 + setarg 0 + copy auxcnt,null + branch lpm_recover_timeout,zero + fetch 1,core_lpm_xtalcnt + fetcht 1,core_lpm_buckcnt + isub temp,null + branch lpm_recover_xtal,positive + deposit temp +lpm_recover_xtal: + isub auxcnt,pdata + increase 1,pdata +lpm_recover_timeout: + increase 6,pdata + until null,lpo_edge + iadd lpo_time,pdata + fetcht 4,mem_sleep_counter + iadd temp,pdata + fetcht 3,mem_clks_per_lpo + imul32 temp,pdata + rshift8 pdata,pdata + rshift4 pdata,pdata + increase param_lpm_fix,pdata + arg 3750,temp + idiv temp + call wait_div_end + quotient pdata + lshift16 pdata,pdata + remainder temp + ior temp,pdata + fetcht 6,mem_sleep_clkn + call clk_add + until null,lpo_edge + copy temp,clkn + fetch 6,mem_context + coffset_clk_offset + call calc_clke2 + rtn + +lpm_dispatch: + bpatch patch14_4,mem_patch14 + fetch 1,mem_lpm_mode + rtn blank + call l2cap_malloc_is_fifo_empty + nrtn blank + call le_fifo_check_empty + nrtn blank + arg mem_alloc_block,rega + call queue_get_len + fetcht 1,mem_l2cap_rx_malloc_num + isub temp,null + nrtn zero + call lpo_calibration + fetch 3,mem_clks_per_lpo + rtn blank + fetch 1,mem_ssp_enable + branch lpm_dispatch_next,blank + fetch 1,mem_sp_local_key_invalid // simple pairing is not ready + rtn blank +lpm_dispatch_next: + fetch 1,mem_le_sc_calc + nrtn blank + call lpm_check_wake_lock + nrtn blank + call ipc_check_enter_lpm + nrtn blank + fetch 1,mem_context + compare 3,pdata,0x7 /* sco won't sleep */ + nbranch lpm_dispatch_unconn,true + fetch 2,mem_context + coffset_tsniff + rtn blank /* role switch */ + rtn wake + bpatch patch14_5,mem_patch14 + fetcht 1,mem_lpm_current_mult + fetch 2,mem_context + coffset_tsniff + imul32 temp,pdata + rshift4 temp,temp + rshift2 temp,temp + isub temp,pdata + fetcht 4,mem_context + coffset_sniff_anchor + iadd temp,pdata + fetcht 1,mem_lpm_overhead + isub temp,pdata + lshift16 pdata,alarm + bpatch patch14_6,mem_patch14 + fetch 2,mem_context + coffset_rx_window + rshift pdata,pdata + call clk2bt + deposit alarm + call clk_diff + copy clke,temp + call clk_diff_rt + rtn user +lpm_dispatch_sleep: + call clk2lpo +lpm_dispatch_lpo: + bpatch patch14_7,mem_patch14 + fetch 1,mem_lpm_xtalcnt + isub temp,null + branch lpm_clear_counter,positive + storet 4,mem_sleep_counter + // wake flag for cm0 check + jam 0,mem_wake_flag + call app_will_enter_lpm + fetcht 4,mem_sleep_counter + branch lpm_sleep + +lpm_dispatch_unconn: + bpatch patch15_0,mem_patch15 + fetch 1,mem_context + rtnbit1 state_inconn // wont sleep in connection + rtnbit1 state_inpage // wont sleep when paging + fetch 1,mem_ssp_enable + branch lpm_unconn_nossp,blank + fetch 1,mem_sp_local_key_invalid // simple pairing is not ready + rtn blank +lpm_unconn_nossp: + fetch 1,mem_le_adv_enable + nbranch lpm_unconn_cont,blank + fetch 1,mem_scan_mode + rtn blank +lpm_unconn_cont: + fetch 2,mem_lpm_interval + rtn blank +lpm_sleep_btclk: + fetcht 1,mem_lpm_overhead + isub temp,pdata + arg 7500,temp /* 1.25ms */ + imul32 temp,pdata + branch lpm_dispatch_sleep + +lpm_set_mult: + bpatch patch15_1,mem_patch15 + disable wake + fetch 1,mem_state + rtnbit0 state_insniff + nbranch lpm_not_match,match + call lpm_match + fetch 2,mem_rx_window_sniff + store 2,mem_rx_window + fetch 1,mem_cur_arq + bbit1 wack,lpm_mult_short + bmark0 mark_lpm_mult_enable,lpm_mult_short + call l2cap_malloc_is_fifo_empty + nbranch lpm_mult_short,blank + fetch 1,mem_spp_reject_justwork_flag + bbit1 SHORT_MULT_FLAG,lpm_mult_short +lpm_mult_wait_timeout: + jam 0,mem_lpm_current_mult + bmark0 mark_lpm_mult_enable,lpm_mult_short + fetch 1,mem_lpm_mult_cnt + branch lpm_mult_long,blank + increase -1,pdata + store 1,mem_lpm_mult_cnt + rtn + + +classic_bt_set_mult_short_flag: + arg SHORT_MULT_FLAG,queue + branch classic_bluetooth_set_flag + +classic_bt_clr_mult_short_flag: + arg SHORT_MULT_FLAG,queue + branch classic_bluetooth_clr_flag + + + +lpm_match: + jam 0,mem_sniff_unint_lost + fetch 3,mem_sniff_rcv + increase 1,pdata + store 3,mem_sniff_rcv + rtn + +lpm_not_match: + fetcht 2,mem_rx_window_sniff + rshift temp,temp + fetch 2,mem_rx_window + iadd temp,pdata + store 2,mem_rx_window +lpm_lost: + jam 0,mem_lpm_current_mult + fetch 3,mem_sniff_lost + increase 1,pdata + store 3,mem_sniff_lost + fetch 1,mem_sniff_unint_lost + increase 1,pdata + store 1,mem_sniff_unint_lost + rtn + +lpm_mult_short: + jam 0,mem_lpm_current_mult + fetch 1,mem_lpm_mult_timeout + store 1,mem_lpm_mult_cnt + rtn + +lpm_mult_long: + fetcht 1,mem_lpm_mult + storet 1,mem_lpm_current_mult + rtn + +lpm_cal_xtal_startup: + fetch 1,mem_lpm_xtalcnt + nrtn blank + jam clksel_rc,core_clksel + setarg 0xf0c + call lpm_write_config + setarg 200000 + call sleep + until null,lpo_edge + copy lpo_time,alarm + call xtal_fast_wake + jam clksel_xtal,core_clksel + nop 10 + until null,lpo_edge + deposit lpo_time + isub alarm,pdata + increase 0x30,pdata + arg 0xff,temp + call ceiling + store 1,mem_lpm_xtalcnt + nop 30000 + nop 30000 + nop 30000 + rtn + +lpm_cal_xtal_startup_by_snooze: + fetch 1,mem_lpm_xtalcnt + nrtn blank +// jam 0xff,core_xtal_stable_time + jam clksel_rc,core_clksel + call xtal_fast_wake + setarg 1000 + iadd lpo_time,alarm + snooze + deposit lpo_time + nop 12000 //delay about 1ms + nop 12000 //delay about 1ms + nop 12000 //delay about 1ms + nop 12000 //delay about 1ms + nop 12000 //delay about 1ms + nop 12000 //delay about 1ms + nop 12000 //delay about 1ms + nop 12000 //delay about 1ms + nop 12000 //delay about 1ms + isub alarm,pdata + add pdata,0x30,pdata + arg 0xff,temp + call ceiling + store 1,mem_lpm_xtalcnt + nop 30000 + nop 30000 + nop 30000 + rtn + + + + /* pdata is lpm_reg[11:0] */ +lpm_write_config: + arg 0xfff,contw + iand contw,contw + fetch 1,mem_lpm_config + and_into 0xf0,pdata + lshift8 pdata,pdata + ior contw,pdata + call lpm_write_ctrl + store 2,core_lpm_reg + ifetch 2,contr + istore 2,contw + rtn + + +lpm_write_gpio_wakeup: + bpatch patch15_2,mem_patch15 + until null,lpo_edge + jam lpmreg_sel_gpiolow,core_lpm_wr + until null,lpo_edge + fetch 4,mem_gpio_wakeup_low + store 4,core_lpm_reg + jam lpmreg_sel_gpiohigh,core_lpm_wr + until null,lpo_edge + fetch 4,mem_gpio_wakeup_high + store 4,core_lpm_reg + rtn + +lpm_write_ctrl: + until null,lpo_edge + jam lpmreg_sel_ctrl,core_lpm_wr + until null,lpo_edge + rtn + +lpm_write_ctrl2: + until null,lpo_edge + jam lpmreg_sel_ctrl2,core_lpm_wr + until null,lpo_edge + rtn + + + +lpm_get_wake_lock: + fetch 2,mem_lpm_wake_lock + qset1 pdata + store 2,mem_lpm_wake_lock + rtn + +lpm_put_wake_lock: + fetch 2,mem_lpm_wake_lock + qset0 pdata + store 2,mem_lpm_wake_lock + rtn + + + +lpm_check_wake_lock: + bpatch patch15_3,mem_patch15 + call app_check_wake_lock + //fetchr rega,2,mem_lpm_wake_lock + fetch 2,mem_lpm_wake_lock + copy pdata,rega + fetch 1,mem_state_map + isolate1 smap_rxlmp,pdata + setflag true,wake_lock_lmp_rx,rega + fetch 1,mem_lmo_opcode1 + fetcht 1,mem_lmo_opcode2 + iadd temp,pdata + fetcht 1,mem_lmp_to_send + iadd temp,pdata + nsetflag blank,wake_lock_lmp_tx,rega + bpatch patch15_4,mem_patch15 + fetch 1,mem_le_tx_buff_used + nsetflag blank,wake_lock_ble_tx,rega + fetch 2,mem_l2cap_rxbuff1_len + fetcht 2,mem_l2cap_rxbuff2_len + iadd temp,pdata + nsetflag blank,wake_lock_l2cap_rx,rega + fetch UTIL_FIFO_LEN,mem_ipc_fifo_bt2c51 + nsetflag blank,wake_lock_ipc_bt2c51,rega + fetch UTIL_FIFO_LEN,mem_ipc_fifo_c512bt + nsetflag blank,wake_lock_ipc_c512bt,rega + fetch 1,mem_hci_cmd + nsetflag blank,wake_lock_cmd,rega + fetch 1,mem_device_option + compare dvc_op_module,pdata,0xff + call lpm_uart_wake_lock,true + bpatch patch15_5,mem_patch15 + setarg -8 + iand rega,rega + copy rega,pdata + store 2,mem_lpm_wake_lock + rtn blank + rtn match + enable wake + rtn + +lpm_uart_wake_lock: + fetch 2,core_uart_rx_items + nsetflag blank,wake_lock_uart_rx ,rega + fetch 2,core_uart_tx_items + nsetflag blank,wake_lock_uart_tx ,rega + rtn + +lpm_shut_down: + call lpm_write_ctrl + fetch 4,core_lpm_ctrl + set0 27,pdata + store 4,core_lpm_reg + branch assert + +lpm_enable_exen_output: + call lpm_write_ctrl2 + fetch 4,core_lpm_xtalcnt + set1 20,pdata + store 4,core_lpm_reg + rtn + +lpm_disable_exen_output: + call lpm_write_ctrl2 + fetch 4,core_lpm_xtalcnt + set0 20,pdata + store 4,core_lpm_reg + rtn + +check_bt_disabled: + fetch 2,mem_chip_functions + bbit1 bt_disabled,assert + rtn +check_ble_disabled: + fetch 2,mem_chip_functions + bbit1 ble_disabled,assert + rtn +check_module_disabled: + fetch 2,mem_chip_functions + bbit1 module_disable,assert + rtn + +test_init: + setarg test_proc + store 2,mem_cb_bt_process + setarg test_sleep + store 2,mem_cb_bb_event_process + setarg test_proc + store 2,mem_cb_idle_process + rtn wake +// jam ui_led_start,mem_led_switch + rtn + +test_proc: + fetch 1,mem_state + bbit0 state_insniff,check_test_cond + set1 mark_lpm_mult_enable,mark + fetch 6,mem_sniff_rcv + store 6,mem_local_name + branch ui_led_blink_stop + + +test_sleep: + deposit regc + rtnne BT_EVT_BUTTON_LONG_PRESSED +test_sleep_loop: +// call ui_button_polling + fetch 1,mem_button_last_state1 + beq 1,test_sleep_loop + call ui_led_off + branch lpm_hibernate + + +test_tx: + force 2,temp + increase -2,temp + call set_sync_on + call set_freq_tx + disable enable_white + enable encode_fec0 + set1 TXGFSK,radio_ctrl + call start_transmitter +test_tx_loop: + fetch 1,0 + inject mod,8 + branch test_tx_loop + + +check_amaddr_is_esco: + fetch 1,mem_esco_amaddr + icompare 0xff,am_addr + rtn + +load_context_to_acl: + rtnmark0 mark_esco +load_context_to_acl_no_mark: + call check_amaddr_is_esco + nrtn true +load_to_acl: + call clear_got_tx + fetch 1,mem_cur_arq + store 1,mem_esco_arq + fetch 1,mem_acl_arq + store 1,mem_cur_arq + + fetch 1,mem_acl_amaddr + iforce am_addr + + fetch 1,mem_last_type + store 1,mem_last_type_esco + fetch 1,mem_last_type_acl + store 1,mem_last_type + + setarg 0xffff + store 2,mem_retransmission_cnt + set1 mark_esco_rxok,mark + rtn + +load_context_to_esco: + rtnmark0 mark_esco + //fetch 1,mem_mode + //rtnbit0 sco_in_sniff + rtnmark0 mark_sco_flag + rtnmark0 mark_enter_sco_sniff +load_context_to_esco0: + fetch 1,mem_cur_arq + store 1,mem_acl_arq + fetch 1,mem_esco_arq + store 1,mem_cur_arq + + deposit am_addr + store 1,mem_acl_amaddr + fetch 1,mem_esco_amaddr + iforce am_addr + + set0 mark_esco_rxok,mark + fetch 1,mem_last_type + store 1,mem_last_type_acl + fetch 1,mem_last_type_esco + store 1,mem_last_type + jam 0x04,mem_sco_flag //enable sco_transaction_begin_flag + rtn + + + // Check connection + // Change user flag +bt_check_have_classic_link_in_connecting: + call context_search_have_link + nbranch disable_user,user// No link + //call context_load + //fetch 1,mem_state + //bbit1 state_inpage,enable_user// In page allow adv, but not allow le scan + branch enable_user + +bt_wake_up_m0_light_sleep: + enable bt_trig + nop 1 + disable bt_trig + rtn + + Index: tag/Soft/Librarier/bt_rom/program/c51.prog =================================================================== --- /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/c51.prog (nonexistent) +++ /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/c51.prog (working copy) @@ -0,0 +1,50 @@ +ifdef C51 +download_pdata: + force 9,loopcnt +download_pdata_loop: + store 1,core_docd_pdata + rshift8 pdata,pdata + loop download_pdata_loop + rtn +download_c51: + jam 5,core_docd_ctrl + force 0,pdata + store 2,core_docd_paddr + setsect 0,0x30002 + setsect 1,0x3de00 + setsect 2,0x36e47 + setsect 3,0x3f763 + call download_pdata + setsect 0,0x38175 + setsect 1,0xb3 + setsect 2,0x103a0 + setsect 3,0x1e202 + call download_pdata + setsect 0,0x44e0 + setsect 1,0x13c04 + setsect 2,0x3effe + setsect 3,0x20643 + call download_pdata + setsect 0,0xe01c + setsect 1,0x2f908 + setsect 2,0x3f0f0 + setsect 3,0x402 + call download_pdata + setsect 0,0x3be0e + setsect 1,0x3fc49 + setsect 2,0x2e10b + setsect 3,0x9efb + call download_pdata + setsect 0,0xbfe8 + setsect 1,0x3944 + setsect 2,0x10809 + setsect 3,0x5d0 + call download_pdata + setsect 0,0x180f0 + setsect 1,0x48b7 + setsect 2,0xf1 + setsect 3,0x8bfa + call download_pdata + jam 3,core_docd_ctrl + rtn +endif Index: tag/Soft/Librarier/bt_rom/program/debug.prog =================================================================== --- /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/debug.prog (nonexistent) +++ /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/debug.prog (working copy) @@ -0,0 +1,169 @@ + +//rega-- need print value +//temp--value +debug_log_print: + bpatch patch1d_7,mem_patch1d + fetch 1,mem_param_debug_log_func_enable + rtn blank + //Step1: judge initial flag + fetch 3,mem_param_debug_log_initial_flag_addr + ifetch 1,pdata + rtnne DEBUG_LOG_INITIAL_SUCCESS_FLAG + //Step2: combine send value + arg 0xffff,pdata + iand temp,temp + copy rega,pdata// real need send value + lshift16 pdata,pdata + ior temp,pdata + store 4,mem_debug_log_temp_point + + //Step3: get print log lock +debug_log_print_get_lock: + fetcht 3,mem_param_debug_log_lock_flag_respin_addr + setarg 1 + istore 1,temp // I'm interested + + + fetcht 3,mem_param_debug_log_lock_victim_addr + setarg DEBUG_LOG_LOCK_VICTIM_RESPIN + istore 1,temp // you go first +debug_log_print_get_lock_wait: + fetch 3,mem_param_debug_log_lock_flag_cm0_addr + ifetch 1,pdata + branch debug_log_print_get_lock_wait_end,blank + + fetch 3,mem_param_debug_log_lock_victim_addr + ifetch 1,pdata + bne DEBUG_LOG_LOCK_VICTIM_RESPIN,debug_log_print_get_lock_wait_end + branch debug_log_print_get_lock_wait +debug_log_print_get_lock_wait_end: + + //Step4: set value to write ptr, do not think overflow, for code size + fetch 3,mem_param_debug_log_write_index_addr + ifetcht 1,pdata + call debug_log_wptr_loopback//for safe + fetch 3,mem_param_debug_log_buffer_start_addr + lshift2 temp,temp// get buffer real index + iadd temp,pdata + // pdata is real write ptr + fetcht 4,mem_debug_log_temp_point// real need send value + istoret 4,pdata + //Step5: update write index + fetch 3,mem_param_debug_log_write_index_addr + ifetcht 1,pdata + increase 1,temp + call debug_log_wptr_loopback + //sub temp,10,null + //ncall ice_break,positive +//ifdef DEBUG_LOG_JUDGE_OVERFLOW + fetch 1,mem_param_debug_log_read_index_addr + ifetch 1,pdata + isub temp,null + // if write ptr equal read ptr, we do not update ptr, only lost one log + // if we donot do this, will loss BUFFER SIZE log + branch debug_log_print_end,zero +//endif + // save write index + fetch 3,mem_param_debug_log_write_index_addr + istoret 1,pdata + +debug_log_print_end: + //Step6: free print log lock +debug_log_print_free_lock: + fetcht 3,mem_param_debug_log_lock_flag_respin_addr + setarg 0 + istore 1,temp + rtn + +//input:temp +//output:temp +//used: pdata,temp,rega +debug_log_wptr_loopback: + fetch 3,mem_param_debug_log_buffer_end_addr + fetchr rega,3,mem_param_debug_log_buffer_start_addr + isub rega,pdata + rshift2 pdata,pdata + isub temp,null + nrtn zero + arg 0,temp + rtn + + + + + +// Rf debug + + +rf_debug_active_rx_line: + fetch 1,mem_rf_debug_enable + rtn blank + fetch 1,mem_rf_debug_rf_rx_debug_gpio + branch rf_debug_gpio_active + +rf_debug_inactive_rx_line: + fetch 1,mem_rf_debug_enable + rtn blank + fetch 1,mem_rf_debug_rf_rx_debug_gpio + branch rf_debug_gpio_inactive + + + +rf_debug_active_tx_line: + fetch 1,mem_rf_debug_enable + rtn blank + fetch 1,mem_rf_debug_rf_tx_debug_gpio + branch rf_debug_gpio_active + +rf_debug_inactive_tx_line: + fetch 1,mem_rf_debug_enable + rtn blank + fetch 1,mem_rf_debug_rf_tx_debug_gpio + branch rf_debug_gpio_inactive + +rf_debug_active_sync_line: + fetch 1,mem_rf_debug_enable + rtn blank + fetch 1,mem_rf_debug_rf_sync_detect_debug_gpio + branch rf_debug_gpio_active + +rf_debug_inactive_sync_line: + fetch 1,mem_rf_debug_enable + rtn blank + fetch 1,mem_rf_debug_rf_sync_detect_debug_gpio + branch rf_debug_gpio_inactive + + +rf_debug_active_crc_error_line: + fetch 1,mem_rf_debug_enable + rtn blank + fetch 1,mem_rf_debug_rf_crc_error_debug_gpio + branch rf_debug_gpio_active + +rf_debug_inactive_crc_error_line: + fetch 1,mem_rf_debug_enable + rtn blank + fetch 1,mem_rf_debug_rf_crc_error_debug_gpio + branch rf_debug_gpio_inactive + + + +// in pdata: gpio +rf_debug_gpio_active: + arg GPIO_OUT_CONSTANT_ACTIVE,temp + branch gpio_config_function_int + +rf_debug_gpio_inactive: + arg GPIO_OUT_CONSTANT_INACTIVE,temp + branch gpio_config_function_int + + +rf_shutdown_radio_for_debug: + call rf_debug_inactive_rx_line + call rf_debug_inactive_tx_line + call rf_debug_inactive_sync_line + branch rf_debug_inactive_crc_error_line + + + + Index: tag/Soft/Librarier/bt_rom/program/hci_main.prog =================================================================== --- /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/hci_main.prog (nonexistent) +++ /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/hci_main.prog (working copy) @@ -0,0 +1,273 @@ +/*********************************/ +/********** HCI *****************/ +/*********************************/ + + +hci_init: + rtn + + + +process_cmd: + fetch 1,mem_hci_cmd + rtn blank + fetch 1,mem_lmo_opcode2 + nrtn blank + call cmd_check_plap + nbranch process_cmd_conn_handle,zero + fetch 1,mem_hci_cmd + beq hci_cmd_remote_name_req,cmd_namereq + beq hci_cmd_pair,cmd_pair + beq hci_cmd_nopair,cmd_nopair + beq hci_cmd_linkkey,cmd_has_key + beq hci_cmd_nokey,cmd_no_key + beq hci_cmd_reject_conn,cmd_disconn + beq hci_cmd_role_switch,cmd_role_switch + beq hci_cmd_accept_conn,cmd_accept_conn + beq hci_cmd_accept_with_switch,cmd_accept_with_switch + beq hci_cmd_detach,cmd_detach + beq hci_cmd_in_sniff,cmd_in_sniff + beq hci_cmd_exit_sniff,cmd_exit_sniff +process_cmd_conn_handle: + call cmd_check_handle + nrtn blank + fetch 1,mem_hci_cmd + beq hci_cmd_auth,cmd_auth + beq hci_cmd_startencrypt,cmd_start_encrypt + beq hci_cmd_stopencrypt,cmd_stop_encrypt + beq hci_cmd_setup_sco,cmd_setup_sco + beq hci_cmd_disconn_sco,cmd_disconn_sco + beq hci_cmd_accept_sco_conn,cmd_accept_sco_conn + beq hci_cmd_remote_feature_req,cmd_feature_req + beq hci_cmd_remote_ext_features_req,cmd_ext_feature_req + beq hci_cmd_remote_version_req,cmd_version_req + beq hci_cmd_io_cap,cmd_io_cap + rtnne hci_cmd_disconn + call lmp_disconnect +cmd_exit: + jam 0,mem_hci_cmd + rtn + +cmd_check_plap: + fetch 6,mem_hci_plap + fetcht 6,mem_plap + isub temp,null + rtn + + /* return pdata=0 if handle match */ +cmd_check_handle: + fetch 1,mem_hci_conn_handle + fetcht 1,mem_conn_handle + isub temp,pdata + rtn + +cmd_accept_conn: + jam LMP_ACCEPTED,mem_lmo_opcode2 + jam LMP_HOST_CONNECTION_REQ,mem_lmi_opcode2 + call tid_set_reply + branch cmd_exit + +cmd_accept_with_switch: + branch cmd_accept_sco_conn,master + set1 mark_accept_switch,mark +cmd_role_switch: + jam LMP_SLOT_OFFSET,mem_lmo_opcode2 + set1 mark_switch_initiated,mark + nbranch cmd_exit,master + jam LMP_SWITCH_REQ ,mem_lmo_opcode2 + fetch 1,mem_connection_options + set0 CONNECTION_SWITCH,pdata + store 1,mem_connection_options + branch cmd_exit + + +cmd_namereq: + jam LMP_NAME_REQ,mem_lmo_opcode2 + jam 0,mem_name_offset + branch cmd_exit + +//enable ssp master sm +cmd_ssp: + jam SP_FLAG_COMMIT,mem_master_sp_flag + jam SP_MASTER_STAT_START_SKIP,mem_master_sp_state + branch cmd_exit + +cmd_pair: + fetch 1,mem_op + bbit1 op_inrand_req,cmd_pair_passive + call tid_initiate + jam LMP_IN_RAND,mem_lmo_opcode2 + branch cmd_exit +cmd_pair_passive: + set0 op_inrand_req,pdata + store 1,mem_op + call lmp_accept_inrand + setarg 0 + setflag master,smap_lmptid,pdata + store 1,mem_lmo_tid2 + branch cmd_exit + +cmd_nopair: + jam PAIRING_NOT_ALLOWED,mem_disconn_reason_send + jam LMP_DETACH,mem_lmo_opcode2 + fetch 1,mem_state + bbit1 state_inconn,cmd_exit + force HCI_ERROR_PAIRING_NOT_ALLOWED,temp + branch cmd_exit + + +cmd_has_key: + call linkkey_set + fetch 1,mem_op + bbit1 op_auth_req,cmd_send_aurand + bbit1 op_send_sres,cmd_send_sres + bbit1 op_inrand_req,cmd_pair_passive + branch cmd_exit +cmd_send_sres: + set0 op_send_sres,pdata + store 1,mem_op + jam LMP_SRES,mem_lmo_opcode2 + branch cmd_exit + +cmd_no_key: + fetch 1,mem_op + bbit1 op_send_sres,cmd_no_key_reject + branch cmd_exit +cmd_no_key_reject: + set0 op_send_sres,pdata + store 1,mem_op + jam LMP_NOT_ACCEPTED,mem_lmo_opcode2 + jam LMP_AU_RAND,mem_lmi_opcode2 + jam KEY_MISSING,mem_lmo_reason2 + branch cmd_exit + + +cmd_auth: + fetch 1,mem_op + set1 op_auth_req,pdata + store 1,mem_op + fetch 1,mem_state + bbit1 state_linkkey,cmd_auth_sendaurand + branch cmd_exit + +cmd_send_aurand: +cmd_auth_sendaurand: + call tid_initiate + jam LMP_AU_RAND,mem_lmo_opcode2 + branch cmd_exit + +cmd_start_encrypt: + jam LMP_ENCRYPTION_MODE_REQ,mem_lmo_opcode2 + branch cmd_exit + +cmd_stop_encrypt: + jam LMP_ENCRYPTION_MODE_REQ ,mem_lmo_opcode2 + branch cmd_exit + +cmd_feature_req: + jam LMP_FEATURES_REQ,mem_lmo_opcode2 + jam hci_cmd_wait_remote_feature,mem_hci_cmd + rtn + +cmd_ext_feature_req: + jam LMP_EXT_FEATURES_REQ,mem_lmo_opcode2 + jam hci_cmd_wait_remote_ext_feature,mem_hci_cmd + rtn + +cmd_version_req: + jam LMP_VERSION_REQ,mem_lmo_opcode2 + branch cmd_exit + +cmd_in_sniff: + fetch 2,mem_ui_state_map + rtnbit1 UI_STATE_BT_SNIFF + jam LMP_SNIFF_REQ,mem_lmo_opcode2 + + setarg 0 + store 2,mem_acl_dsniff + fetch 2,mem_sniff_param_interval + lshift pdata,pdata + store 2,mem_acl_tsniff + fetch 1,mem_sniff_param_attempt + store 1,mem_acl_attempt + fetch 1,mem_sniff_param_timeout + store 1,mem_acl_timeout + + arg mem_sniff_payload,contw + setarg 0 + isolate1 27,clke_bt + setflag true,1,pdata /* use init 2 if bit27 of clke is 1 */ + istore 1,contw + setarg 0 /* dsniff */ + istore 2,contw + fetch 2,mem_sniff_param_interval /* tsniff */ + istore 2,contw + fetch 1,mem_sniff_param_attempt /* attempt */ + istore 2,contw + fetch 1,mem_sniff_param_timeout /* timeout */ + istore 2,contw + branch cmd_exit + +cmd_exit_sniff: + fetch 2,mem_ui_state_map + rtnbit0 UI_STATE_BT_SNIFF + jam LMP_UNSNIFF_REQ,mem_lmo_opcode2 + branch cmd_exit + + +cmd_setup_esco: + call new_conn_handle + store 1,mem_sco_handle + jam LMP_EXT_ESCO_LINK_REQ,mem_lmo_opcode2 + branch cmd_exit + +cmd_setup_sco: + jam LMP_SCO_LINK_REQ,mem_lmo_opcode2 + branch cmd_exit + +cmd_disconn: + call lmp_disconnect + branch cmd_exit + +cmd_disconn_esco: +cmd_disconn_sco: + jam LMP_REMOVE_SCO_LINK_REQ,mem_lmo_opcode2 + bmark0 mark_esco,cmd_exit + jam LMP_EXT_REMOVE_ESCO_REQ,mem_lmo_opcode2 + jam 0x13,mem_disconn_reason_send + branch cmd_exit + +cmd_accept_sco_conn: + branch cmd_accept_sco_conn_master,master + jam LMP_ACCEPTED,mem_lmo_opcode2 + jam LMP_SCO_LINK_REQ,mem_lmi_opcode2 + bmark0 mark_esco,cmd_exit + //fetch 1,mem_esco_type + jam LMP_EXT_ACCEPTED ,mem_lmo_opcode2 + jam LMP_EXT_ESCO_LINK_REQ,mem_lmi_opcode2 + branch cmd_exit +cmd_accept_sco_conn_master: + call new_conn_handle + store 1,mem_sco_handle + fetch 1,mem_conn_handle + store 1,mem_sco_asso_handle + jam LMP_SCO_LINK_REQ,mem_lmo_opcode2 + bmark0 mark_esco,cmd_exit + rtn + + +cmd_io_cap: + jam LMP_IO_CAP_RES,mem_lmo_opcode2 + branch cmd_exit + +cmd_detach: + jam LMP_DETACH,mem_lmo_opcode2 + jam OTHER_END_TERMINATED,mem_disconn_reason_send + branch cmd_exit + + + + + + + Index: tag/Soft/Librarier/bt_rom/program/headset.prog =================================================================== --- /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/headset.prog (nonexistent) +++ /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/headset.prog (working copy) @@ -0,0 +1,187 @@ + +ifdef COMPILE_HEADSET + +headset_init: + rtn wake + call headset_clear_parms + setarg headset_cb_bb_event_process + store 2,mem_cb_bb_event_process + setarg headset_evt_100ms_timer + store 2,mem_cb_event_timer + setarg headset_cb_idle_process + store 2,mem_cb_idle_process + setarg headset_cb_bt_process + store 2,mem_cb_bt_process + setarg headset_cb_check_wakelock + store 2,mem_cb_check_wakelock + rtn + +headset_poweron: + jam APP_STATE_POWERON,mem_poweron_state + branch vp_play_poweron + // branch vp_wait_end + +headset_poweroff: + jam APP_STATE_NULL,mem_poweron_state + call vp_wait_end + branch app_enter_hibernate + +headset_poweroff_wait: + jam APP_STATE_POWEROFF_WAIT,mem_poweron_state + branch vp_play_poweroff + +headset_clear_parms: + bpatch patch1e_0,mem_patch1e + jam HF_STATE_WAITING_RFCOMM_CONN, mem_hf_state + jam HFP_NONO, mem_hf_call_state + jam HF_CMD_IDLE,mem_hf_command + jam HFP_DEFAULT_MIC_VLM,mem_hf_vlm_mic + jam HFP_DEFAULT_SPEAKER,mem_hf_vlm_speaker + call HFP_clear_sco_params + setarg 0 + store 2,mem_rfc_server_state + setarg mem_xmem_hf_state_end + arg mem_xmem_hf_state_start,contw + isub contw,loopcnt + branch clear_mem + +headset_check_reconnet: + call nv_ng_load_nvram + call nv_get_last_record_ptr + ifetch 6,regc + store 6,mem_hci_plap + copy contr,regc + branch app_bt_start_discovery,blank + setarg 0xffffff + fetcht 3,mem_hci_plap + isub temp,null + nbranch headset_reconnet,zero + fetcht 3,mem_hci_plap+3 + isub temp,null + branch app_bt_start_discovery,zero +headset_reconnet: + copy regc,contr + arg 16,loopcnt + arg mem_link_key,contw + call memcpy + branch app_bt_start_reconnect + + +headset_cb_idle_process: + call saradc_read_hvin_wait + call vp_check_get_data + branch media_queue + + +headset_cb_bt_process: + rtn + +headset_cb_bb_event_process: + copy regc,pdata + beq BT_EVT_PINCODE_REQ,headset_evt_pincode_req + beq BT_EVT_BB_DISCONNECTED,headset_evt_bb_disconnect + beq BT_EVT_LINKKEY_GENERATE,app_bt_store_reconn_info + beq BT_EVT_RECONN_PAGE_TIMEOUT,headset_evt_page_timeout + beq BT_EVT_BT_START_ENC,headset_evt_bt_start_enc + beq BT_EVT_HFP_CONNECTED,headset_evt_connected + beq BT_EVT_HFP_UP_TO_MAX_VLM,headset_evt_up_to_max_vlm +// beq BT_EVT_ENTER_SNIFF,p_evt_enter_sniff +// beq BT_EVT_EXIT_SNIFF,p_evt_exit_sniff +// beq BT_EVT_BUTTON_DOWN,headset_evt_button_down +// beq BT_EVT_BUTTON_UP,headset_evt_button_up + rtn + +headset_evt_up_to_max_vlm: + branch vp_play_max_volume + +headset_evt_bt_start_enc: + fetch 2,mem_ui_state_map + bbit1 UI_STATE_BT_RECONNECT,upper_init_reconnect + rtn + +headset_evt_pincode_req: + jam 4,mem_pin_length + setarg 0x3030 + store 2,mem_pin + istore 2,contw + branch app_bt_set_pincode + + +headset_evt_bb_disconnect: + call headset_clear_parms + fetch 2,mem_app_disconn_reason + isolate1 APP_DISC_AFTER_HP_CONNECT,pdata + call vp_play_disconnect,true + call tws_hp_evt_bb_disconnect + call app_disconn_reason_clear + fetch 1,mem_tws_role + rtnne TWS_SET_NONE + branch app_bt_start_discovery + +headset_evt_page_timeout: + branch app_bt_start_discovery + +headset_evt_connected: + call vp_play_connect + fetch 2,mem_app_disconn_reason_flag + set1 APP_DISC_AFTER_HP_CONNECT,pdata + store 2,mem_app_disconn_reason_flag + fetch 2,mem_avdtpsignal_l2capch_ptr + nrtn blank + jam 4,mem_a2dp_reconnct_delay_timer + rtn + +headset_cb_check_wakelock: + fetch 1,core_dac_ctrl + bbit1 DAC_ENABLE,app_get_lpm_wake_lock + bmark1 mark_esco,app_get_lpm_wake_lock + fetch 1,mem_telephone_dialing_state + bne HFP_DIALING_STATE_NO,app_get_lpm_wake_lock + fetch 1,mem_saradc_flag + bne 0, app_get_lpm_wake_lock + branch app_put_lpm_wake_lock + +headset_evt_100ms_timer: + call vp_play_phone_number_timer + call headset_discovery_timer +// call ui_button_polling + call headset_timer_l2cap_reconnect_audio + call headset_led_timer1 + call headset_led_timer2 + branch headset_timer_connect_avrcp_timer + +headset_timer_l2cap_reconnect_audio: + arg mem_a2dp_reconnct_delay_timer,regc + call timer_single_step + nrtn user + branch upper_int_reconnect_audio + +headset_timer_connect_avrcp_timer: + arg mem_hp_avctp_timer,regc + call timer_single_step + nrtn user + branch upper_int_reconnect_avctp + +headset_discovery_timer: + arg mem_discovery_timer_count,regc + call timer_single_step2 + nrtn user + call app_bt_stop_discovery + branch app_enter_hibernate + +headset_led_timer1: + arg mem_led_gpio1+LED_TIMER_MEM_OFFSET,regc + call timer_single_step + nrtn user + arg mem_led_gpio1,regb + branch ui_led_blink_check + +headset_led_timer2: + arg mem_led_gpio2+LED_TIMER_MEM_OFFSET,regc + call timer_single_step + nrtn user + arg mem_led_gpio2,regb + branch ui_led_blink_check + +endif + Index: tag/Soft/Librarier/bt_rom/program/hid.prog =================================================================== --- /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/hid.prog (nonexistent) +++ /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/hid.prog (working copy) @@ -0,0 +1,65 @@ +/** +* the following API is to send the HID data +* +*/ + +/** +* the following API is to process the hid rx data +* +*/ +//handle the hid data + +l2cap_call_proc_hid: + call hid_rx_process + branch l2cap_rx_reset_state + +hid_rx_process: + bpatch patch1e_1,mem_patch1e + fetch 2,mem_l2cap_payload_ptr + copy pdata,contr + ifetch 1,contr + and pdata,0x0f,temp + rshift4 pdata,pdata //hidtype + beq hid_type_set_idle,hid_rx_process_handshake + beq hid_type_set_protocol,hid_rx_process_handshake + beq hid_type_data,hid_rx_process_data + beq HID_TYPE_SET_REPORT,hid_rx_process_set_report + beq HID_TYPE_CONTROL,hid_rx_process_hid_control + rtn + +hid_rx_process_hid_control: + copy temp,pdata + beq HID_CONTROL_P_VIRTUALCABLEUNPLUG,hid_rx_process_virtual_cable_unplug + beq HID_CONTROL_P_SUSPEND,hid_rx_process_suspend + rtn + +hid_rx_process_virtual_cable_unplug: + jam BT_EVT_VIRTUAL_CABLE_UNPLUG,mem_fifo_temp + branch ui_ipc_send_event +hid_rx_process_suspend: + rtn + +hid_rx_process_set_report: + arg 0x01,rega + call l2cap_malloc_server_channel + setarg 0x00 + istore 1,contw + rtn + +hid_rx_process_handshake: + arg 1,rega//payload length + call l2cap_malloc_server_channel + setarg 0 + istore 1,contw + jam BT_EVT_HID_HANDSHAKE,mem_fifo_temp + branch ui_ipc_send_event + +hid_rx_process_data: + ifetch 1,contr + beq HID_REPORT_ID_KB,hid_rx_process_data_hid_kb + rtn + +hid_rx_process_data_hid_kb: + copy contr,rega + rtn + Index: tag/Soft/Librarier/bt_rom/program/hsphfp.prog =================================================================== --- /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/hsphfp.prog (nonexistent) +++ /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/hsphfp.prog (working copy) @@ -0,0 +1,1407 @@ +ifdef COMPILE_HFP_HSP + + + +HFP_clear_sco_params: + bpatch patch1e_2,mem_patch1e + rtnmark1 mark_sco_flag + setarg mem_xmem_sco_end + arg mem_xmem_sco_start,contw + isub contw,loopcnt + branch clear_mem + + +HFP_evt_update_state: + setarg HFP_CIEVIND_CALL + call HFP_get_indicator_value + beq CIEV_CALL_NO,HFP_update_state_nocallActive + beq CIEV_CALL_ACT,HFP_update_state_callActived + rtn + +HFP_update_state_nocallActive: + bpatch patch1e_3,mem_patch1e + setarg HFP_CIEVIND_CALLSETTUP + call HFP_get_indicator_value + beq CIEV_CALLST_IMG,HFP_update_incomming + beq CIEV_CALLST_OUG,HFP_update_outgoing + beq CIEV_CALLST_RE_ALTD,HFP_update_outgoing + fetch 1,mem_hf_call_state + rtneq HFP_NONO + jam HFP_NONO,mem_hf_call_state + branch hfp_dialing_clear + +HFP_update_incomming: + fetch 1,mem_hf_call_state + rtneq HFP_INCOMMING + jam HFP_INCOMMING,mem_hf_call_state +HFP_evt_incomming: + jam BT_EVT_HFP_INCOMMING,mem_fifo_temp + branch ui_ipc_send_event + +HFP_evt_nono: + jam BT_EVT_HFP_NONO ,mem_fifo_temp + branch ui_ipc_send_event + +HFP_evt_outgoing: + jam BT_EVT_HFP_OUTGOING,mem_fifo_temp + branch ui_ipc_send_event +HFP_evt_callactive: + jam BT_EVT_HFP_CALLACTIVE,mem_fifo_temp + branch ui_ipc_send_event +HFP_evt_callimg: + jam BT_EVT_HFP_CALLIMG,mem_fifo_temp + branch ui_ipc_send_event +HFP_evt_callogg: + jam BT_EVT_HFP_CALLOGG,mem_fifo_temp + branch ui_ipc_send_event +HFP_evt_calmulty: + jam BT_EVT_HFP_CALMULTY,mem_fifo_temp + branch ui_ipc_send_event + +HFP_update_outgoing: + fetch 1,mem_hf_call_state + rtneq HFP_OUTGOING + jam HFP_OUTGOING,mem_hf_call_state + branch HFP_evt_outgoing + +HFP_update_state_callActived: + bpatch patch1e_4,mem_patch1e + setarg HFP_CIEVIND_CALLHELD + call HFP_get_indicator_value + beq CIEV_HELD_NO,HFP_update_state_nocallheld + fetch 1,mem_hf_call_state + rtneq HFP_CALMULTY + jam HFP_CALMULTY,mem_hf_call_state + branch HFP_evt_calmulty + +HFP_update_callincomming: + fetch 1,mem_hf_call_state + rtneq HFP_CALLIMG + jam HFP_CALLIMG,mem_hf_call_state + branch HFP_evt_callimg + +HFP_update_calloutgoing: + fetch 1,mem_hf_call_state + rtneq HFP_CALLOGG + jam HFP_CALLOGG,mem_hf_call_state + branch HFP_evt_callogg + +HFP_update_state_nocallheld: + setarg HFP_CIEVIND_CALLSETTUP + call HFP_get_indicator_value + beq CIEV_CALLST_IMG,HFP_update_callincomming + beq CIEV_CALLST_OUG,HFP_update_calloutgoing + beq CIEV_CALLST_RE_ALTD,HFP_update_calloutgoing + fetch 1,mem_hf_call_state + rtneq HFP_CALLACTIVE + jam HFP_CALLACTIVE,mem_hf_call_state + call HFP_evt_callactive + +hfp_dialing_stop: + jam 0,mem_telephone_dialing_timer + jam HFP_DIALING_STATE_STOP , mem_telephone_dialing_state + rtn + +hfp_dialing_clear: + jam 0,mem_telephone_dialing_timer + jam HFP_DIALING_STATE_NO , mem_telephone_dialing_state + rtn + +hfp_dialing_start: + jam BT_EVT_HFP_START_DIALING,mem_fifo_temp + call ui_ipc_send_event + jam HFP_DIALING_STATE_START,mem_telephone_dialing_state + jam 0,mem_phone_num_count + jam 1,mem_telephone_dialing_timer + rtn + +//input : +// pdata indicator index +//output: +// pdata value +HFP_get_indicator_value: + arg mem_AG_indicator,contr + iadd contr,contr + ifetch 1,contr + rtn + + + +HFP_send_answer_call: + call HFP_send_credit_return +send_ATA: //send ATA + setarg mem_at_command_data + store 2, mem_at_rfcomm_data_ptr + icopy contw + setarg 0x415441 + istore 3,contw + setarg 0x0D + istore 1,contw + setarg 0x04 + branch send_AT_cmd_body_end + + +HFP_send_hang_up: + call HFP_send_credit_return +send_AT_CHUP: //send AT chup + setarg mem_at_command_data + store 2, mem_at_rfcomm_data_ptr + icopy contw + setarg 0x2b5441 + istore 3,contw + setarg 0x554843 + istore 3,contw + setarg 0x0D50 + istore 2,contw + setarg 0x08 + branch send_AT_cmd_body_end + + + +send_AT_vgs: //send AT chup + bpatch patch1e_5,mem_patch1e + call HFP_send_credit_return + setarg mem_at_command_data + store 2, mem_at_rfcomm_data_ptr + icopy contw + setarg 0x2b5441 + istore 3,contw + setarg 0x534756 + istore 3,contw + setarg 0x3d + istore 1,contw + fetch 1,mem_hf_vlm_speaker + rshift pdata,pdata + sub pdata,9,null + branch send_AT_vgs_body_one_byte,positive +send_AT_vgs_body_two_byte: + arg 0x31,temp + istoret 1,contw + add pdata,38,pdata + istore 1,contw + setarg 0x0d + istore 1,contw + setarg 0x0a + branch send_AT_cmd_body_end +send_AT_vgs_body_one_byte: + add pdata,0x30,pdata + istore 1,contw + setarg 0x0d + istore 1,contw + setarg 0x09 +send_AT_cmd_body_end: + store 2,mem_current_packet_length + branch HFP_tx_rfcomm_without_credit + + +send_AT_vgm: + bpatch patch1e_6,mem_patch1e + jam HF_WAIT_VGM_OK,mem_hf_command + call HFP_send_credit_return +send_AT_vgm_body: + //store 2,mem_current_packet_length + setarg mem_at_command_data + store 2, mem_at_rfcomm_data_ptr + icopy contw + setarg 0x2b5441 + istore 3,contw + setarg 0x4d4756 + istore 3,contw + setarg 0x3d + istore 1,contw + fetch 1,mem_hf_vlm_mic + sub pdata,9,null + branch send_AT_vgm_body_one_byte,positive +send_AT_vgm_body_two_byte: + arg 0x31,temp + istoret 1,contw + add pdata,38,pdata + istore 1,contw + setarg 0x0d + istore 1,contw + setarg 0x0a + branch send_AT_cmd_body_end +send_AT_vgm_body_one_byte: + add pdata,0x30,pdata + istore 1,contw + setarg 0x0d + istore 1,contw + setarg 0x09 + branch send_AT_cmd_body_end + + +HFP_HSP_process: + bpatch patch1e_7,mem_patch1e + call l2cap_malloc_is_fifo_empty + nrtn blank + fetch 1, mem_hf_state + beq HF_STATE_HF_SEND_RECEIVE_INFO, HFP_send_receive_info + rtneq HF_STATE_WAITING_AG_INFO + beq HF_STATE_HF_SEND_AT_CLIP,HFP_send_enable_CLI + rtneq HF_STATE_WAITING_AT_CLIP + beq HF_STATE_HF_SEND_AT_CCWA, HFP_send_enable_call_waiting + rtneq HF_STATE_WAITING_AT_CCWA + beq HF_STATE_WAITING_RFCOMM_CONN, HFP_waiting_rfcomm + beq HF_STATE_HF_SEND_FEATURE, HFP_send_feature + rtneq HF_STATE_WAITING_AG_FEATURE_OK + beq HF_STATE_HF_SEND_CODECS, HFP_send_codecs + rtneq HF_STATE_WAITING_CODECS_OK + beq HF_STATE_HF_SEND_INDICATORS, HFP_send_indicators + rtneq HF_STATE_WAITING_AG_INDICATORS_OK + beq HF_STATE_HF_SEND_CURR_STATUS, HFP_send_curr_status + rtneq HF_STATE_WAITING_AG_STATUS_OK + beq HF_STATE_HF_SEND_UPDATE_STATUS, HFP_send_update_status + rtneq HF_STATE_WAITING_AG_UPDATE_STATUS_OK + beq HF_STATE_CONNECTED, HFP_connected + rtn + +HFP_connected: + bpatch patch1f_0,mem_patch1f + fetch 1,mem_hfp_battery_state + rtn blank + beq HF_STATE_WAITING_CSCS,HFP_send_cscs + beq HF_STATE_WAITING_NERC,HFP_send_nerc + beq HF_STATE_WAITING_BIA,HFP_send_bia + beq HF_STATE_WAITING_XAPL,HFP_send_xapl + beq HF_STATE_WAITING_XEVENT,HFP_send_xevent + beq HF_STATE_WAITING_ANDROID,HFP_send_android_bat + beq HF_STATE_WAITING_IPHONE,HFP_send_iphone_bat + rtn + + +HFP_set_content: + ifetch 1,contr + store 2,mem_current_packet_length + icopy loopcnt + setarg mem_at_command_data + store 2,mem_at_rfcomm_data_ptr + icopy contw + call memcpy + branch HFP_tx_rfcomm_without_credit + + +HFP_send_redial: //AT+BLDN + call HFP_send_credit_return + setarg 0x08 + call send_AT_common + setarg 0x444c42 + istore 3,contw + setarg 0x4e + istore 1,contw + branch send_0d_common + +HFP_send_recognition: + call HFP_send_credit_return +send_recognition: //AT+BVRA=1 + setarg 0x0a + call send_AT_common + setarg 0x525642 + istore 3,contw + setarg 0x313D41 + istore 3,contw + branch send_0d_common + + +HFP_send_xevent_android: + call HFP_send_credit_return + jam HF_STATE_WAITING_CSCS_OK, mem_hfp_battery_state +send_android_bat: //send ATA + setarg mem_at_command_data + store 2, mem_at_rfcomm_data_ptr + icopy contw + setarg 0x415441 + istore 3,contw + setarg 0x0D + istore 1,contw + setarg 0x04 + branch send_AT_cmd_body_end + + +HFP_send_cscs: + call HFP_send_credit_return + jam HF_STATE_WAITING_CSCS_OK, mem_hfp_battery_state +send_AT_CSCS: //AT+CSCS="UTF-8" + setarg 0x10 + call send_AT_common + setarg 0x435343 + istore 3,contw + setarg 0x223D53 + istore 3,contw + setarg 0x465455 + istore 3,contw + setarg 0x22382D + istore 3,contw + branch send_0d_common + +HFP_send_nerc: + call HFP_send_credit_return + jam HF_STATE_WAITING_NERC_OK, mem_hfp_battery_state +send_AT_NERC: //AT+NREC=0 + setarg 0x0a + call send_AT_common + setarg 0x45524E + istore 3,contw + setarg 0x303D43 + istore 3,contw + branch send_0d_common + +HFP_send_bia: + call HFP_send_credit_return + jam HF_STATE_WAITING_BIA_OK, mem_hfp_battery_state +send_AT_BIA: //AT+BIA=1,1,1,1,0,0,0 + setarg 0x15 + call send_AT_common + setarg 0x414942 + istore 3,contw + setarg 0x2C313D + istore 3,contw + setarg 0x312C31 + istore 3,contw + setarg 0x2C312C + istore 3,contw + setarg 0x302C30 + istore 3,contw + setarg 0x302C + istore 2,contw + branch send_0d_common + +HFP_send_xapl: + call HFP_send_credit_return + jam HF_STATE_WAITING_XAPL_OK, mem_hfp_battery_state +send_AT_XAPL: //AT+XAPL=AB-12-0100,1 + setarg 0x15 + call send_AT_common + setarg 0x504158 + istore 3,contw + setarg 0x413D4C + istore 3,contw + setarg 0x312D42 + istore 3,contw + setarg 0x302D32 + istore 3,contw + setarg 0x303031 + istore 3,contw + setarg 0x312C + istore 2,contw + branch send_0d_common + +HFP_send_xevent: + call HFP_send_credit_return + jam HF_STATE_WAITING_XEVENT_OK, mem_hfp_battery_state +send_AT_XEVENT: //AT+XEVENT=AB-12-0100,1 + setarg 0x17 + call send_AT_common + setarg 0x564558 + istore 3,contw + setarg 0x544E45 + istore 3,contw + setarg 0x42413D + istore 3,contw + setarg 0x32312D + istore 3,contw + setarg 0x31302D + istore 3,contw + setarg 0x2C3030 + istore 3,contw + setarg 0x31 + istore 1,contw + branch send_0d_common + +HFP_send_android_bat: + jam HF_STATE_WAITING_ANDROID_OK, mem_hfp_battery_state + call HFP_send_credit_return +send_AT_ANDROID: //AT+XEVENT=1,1,8 + setarg 0x10 + call send_AT_common + setarg 0x564558 + istore 3,contw + setarg 0x544E45 + istore 3,contw + setarg 0x2C313D + istore 3,contw + setarg 0x2C31 + istore 2,contw + fetch 1,mem_battery_vol + add pdata,0x30,pdata + istore 1,contw + branch send_0d_common + +HFP_send_iphone_bat: + jam HF_STATE_WAITING_IPHONE_OK, mem_hfp_battery_state + call HFP_send_credit_return +send_AT_IPHONE: //AT+IPHONEACCEV=1,1,8 + setarg 0x15 + call send_AT_common + setarg 0x485049 + istore 3,contw + setarg 0x454E4F + istore 3,contw + setarg 0x434341 + istore 3,contw + setarg 0x3D5645 + istore 3,contw + setarg 0x312C31 + istore 3,contw + setarg 0x2C + istore 1,contw + fetch 1,mem_battery_vol + add pdata,0x30,pdata + istore 1,contw + branch send_0d_common + +HFP_waiting_rfcomm: + //fetch 1,mem_hf_ready + fetch 2,mem_rfc_server_state + and pdata,0xe0,pdata + rtnne 0xe0 + jam HF_STATE_HF_SEND_FEATURE, mem_hf_state //start the hands free process + rtn + +HFP_send_feature: + fetch 2,mem_remote_credits + rtn blank + call HFP_send_credit_return + jam HF_STATE_WAITING_AG_FEATURE_OK, mem_hf_state +send_AT_BRSF: //send AT+BRSF= + setarg 0x0c + call send_AT_common + setarg 0x535242 + istore 3,contw + setarg 0x3D46 + istore 2,contw + fetch 3, mem_UI_HF_brsf_feature + istore 3, contw +send_0d_common: + setarg 0x0D + istore 1,contw + branch HFP_tx_rfcomm_without_credit + + +HFP_send_receive_info: + call HFP_send_credit_return + jam HF_STATE_WAITING_AG_INFO, mem_hf_state +send_AT_CHLD: //AT+CHLD=? + setarg 0x0a + call send_AT_common + setarg 0x4843 + istore 2,contw + setarg 0x3d444c + istore 3,contw + setarg 0x0d3f + istore 2,contw + branch HFP_tx_rfcomm_without_credit /* check FC then send out AT+CKPD */ + + +HFP_send_enable_CLI: + call HFP_send_credit_return + jam HF_STATE_WAITING_AT_CLIP, mem_hf_state +send_AT_CLIP: //AT+CLIP=1 + setarg 0x0a + call send_AT_common + setarg 0x4c43 + istore 2,contw + setarg 0x3d5049 + istore 3,contw + setarg 0x0d31 + istore 2,contw + branch HFP_tx_rfcomm_without_credit /* check FC then send out AT+CKPD */ + +HFP_send_enable_call_waiting: + call HFP_send_credit_return + jam HF_STATE_WAITING_AT_CCWA, mem_hf_state +send_AT_CCWA: //AT+CCWA=1 + setarg 0x0a + call send_AT_common + setarg 0x4343 + istore 2,contw + setarg 0x3d4157 + istore 3,contw + setarg 0x0d31 + istore 2,contw + branch HFP_tx_rfcomm_without_credit /* check FC then send out AT+CKPD */ + +HFP_send_codecs: + call HFP_send_credit_return + jam HF_STATE_WAITING_CODECS_OK, mem_hf_state +send_AT_BAC: + fetch 1,mem_codec_msbc_support + branch send_AT_BAC_msbc_not_support,blank +//send AT+BAC=1,2 + setarg 0x0b + call send_AT_common + setarg 0x434142 + istore 3,contw + setarg 0x2c313d + istore 3,contw + setarg 0x0D32 + istore 2,contw + branch HFP_tx_rfcomm_without_credit + +send_AT_BAC_msbc_not_support: +//send AT+BAC=1 + setarg 0x09 + call send_AT_common + setarg 0x434142 + istore 3,contw + setarg 0x0d313d + istore 3,contw + branch HFP_tx_rfcomm_without_credit + +send_AT_BCS: //send AT+BCS + setarg 0x09 + call send_AT_common + setarg 0x534342 + istore 3,contw + setarg 0x3d + istore 1,contw + fetch 1,mem_codec_type + add pdata,0x30,pdata + istore 1,contw + setarg 0x0D + istore 1,contw + branch HFP_tx_rfcomm_without_credit + +send_AT_common: + store 2,mem_current_packet_length + setarg mem_at_command_data + store 2, mem_at_rfcomm_data_ptr + icopy contw + setarg 0x2B5441 //AT+ + istore 3,contw + rtn + +HFP_send_indicators: + call HFP_send_credit_return + jam HF_STATE_WAITING_AG_INDICATORS_OK, mem_hf_state +send_AT_CIND: //send AT+CIND=? + setarg 0x0a + store 2,mem_current_packet_length + setarg mem_at_command_data + store 2, mem_at_rfcomm_data_ptr + icopy contw + setarg 0x2B5441 + istore 3,contw + setarg 0x4e4943 + istore 3,contw + setarg 0x3f3D44 + istore 3,contw + setarg 0x0D + istore 1,contw + branch HFP_tx_rfcomm_without_credit + +HFP_send_curr_status: + call HFP_send_credit_return + jam HF_STATE_WAITING_AG_STATUS_OK, mem_hf_state +send_AT_CIND2: //send AT+CIND? + //send AT+CIND? + setarg 0x09 + store 2,mem_current_packet_length + setarg mem_at_command_data + store 2, mem_at_rfcomm_data_ptr + icopy contw + setarg 0x2B5441 + istore 3,contw + setarg 0x4e4943 + istore 3,contw + setarg 0x0d3f44 + istore 3,contw + branch HFP_tx_rfcomm_without_credit + +HFP_send_update_status: + call HFP_send_credit_return + jam HF_STATE_WAITING_AG_UPDATE_STATUS_OK, mem_hf_state +send_AT_CMER: //AT+CMER=3,0,0,1 + setarg 0x10 + store 2,mem_current_packet_length + setarg mem_at_command_data + store 2, mem_at_rfcomm_data_ptr + icopy contw + setarg 0x2B5441 /* 0x41542B434B50443D32 */ + istore 3,contw + setarg 0x454d43 + istore 3,contw + setarg 0x333d52 + istore 3,contw + setarg 0x2c302c + istore 3,contw + setarg 0x312c30 + istore 3,contw + setarg 0x0d + istore 1, contw + branch HFP_tx_rfcomm_without_credit /* check FC then send out AT+CKPD */ + + +HFP_send_credit_return: + bpatch patch1f_1,mem_patch1f + call rfc_get_rfcomm_snd_adss + fetchr regd,2,mem_rfc_l2capch_ptr + branch rfc_send_uih_without_payload + + +//if search cr/lr,return user,or not user +//input: +// queue +// contr +//output: +// user +HFP_check_result_code_start: +HFP_check_result_code_end: + disable user +HFP_check_result_code: + copy queue,pdata + increase -2,pdata + nrtn positive + increase -1,queue + ifetch 1,contr + bne 0x0D, HFP_check_result_code + increase -1,queue + ifetch 1,contr + bne 0x0A, HFP_check_result_code + enable user + rtn + + +//fetch 1, mem_rfc_paylead_length +//input: +// queue -- payload length +// mem_at_payload_ptr -- payload memory point +//AT_command_process_test: +// setarg mem_at_command_test +// store 2,mem_at_payload_ptr +// force 13,queue +HFP_process_rfcomm_packet: + bpatch patch1f_2,mem_patch1f + deposit queue + rtn zero + fetcht 2,mem_at_payload_ptr + copy temp,contr + call HFP_check_result_code_start + nrtn user + copy contr,pdata + store 2,mem_at_command_ptr + call HFP_check_result_code_end + nrtn user + //store the next AT result code header point + copy contr,pdata + store 2,mem_at_payload_ptr + call HFP_handle_at_result_code + branch HFP_process_rfcomm_packet + + +//input: +// contr +//output: +// temp +//modify: +// rega,regb,contr +HFP_translate_ascii_to_hex: + bpatch patch1f_3,mem_patch1f + call HFP_FindComma + increase -2,contr + copy contr,rega + force 1,regb + force 0,temp +HFP_translate_calculate: + ifetch 1,rega + increase -1,rega + rtneq 0x3d //'=' + rtneq 0x3a //':' + rtneq 0x2c //',' + beq 0x20,HFP_translate_calculate + pincrease -48 + imul32 regb,pdata //pdata = pdata*regb + iadd temp,temp + mul32 regb,10,regb + branch HFP_translate_calculate + +HFP_FindComma: + ifetch 1,contr + rtneq 0x0d //at_cr + rtneq 0x2c //',' + branch HFP_FindComma + + +HFP_is_result_error: + //disable user + fetch 2,mem_at_command_ptr + icopy contr + ifetch 1,contr + rtnne 0x45 + ifetch 1,contr + rtnne 0x52 + ifetch 1,contr + rtnne 0x52 + ifetch 1,contr + rtnne 0x4F + ifetch 1,contr + rtnne 0x52 + enable user + call HFP_result_ok_cmd + rtn + +HFP_is_result_ring: + //disable user + fetch 2,mem_at_command_ptr + icopy contr + ifetch 1,contr + rtnne 0x52 + ifetch 1,contr + rtnne 0x49 + ifetch 1,contr + rtnne 0x4e + ifetch 1,contr + rtnne 0x47 + enable user + rtn + //jam HFP_EVT_HFP_RING,mem_fifo_temp + //branch ui_ipc_send_event + +HFP_is_result_ciev: + //disable user + fetch 2,mem_at_command_ptr + icopy contr + ifetch 1,contr + rtnne 0x2b + ifetch 1,contr + rtnne 0x43 + ifetch 1,contr + rtnne 0x49 + ifetch 1,contr + rtnne 0x45 + ifetch 1,contr + rtnne 0x56 + enable user + call HFP_translate_ascii_to_hex + increase 2,rega //temp + setarg mem_AG_indicator_map + iadd temp,temp + increase -1,temp + ifetch 1,temp + arg mem_AG_indicator,temp + iadd temp,pdata + store 2,mem_at_command_ptr //temporary store the addr point + copy rega,contr + call HFP_FindComma + call HFP_translate_ascii_to_hex + fetch 2, mem_at_command_ptr + istoret 1,pdata + branch HFP_evt_update_state + + +HFP_is_result_cind: + //disable user + fetch 2,mem_at_command_ptr + icopy contr + ifetch 1,contr + rtnne 0x2b + ifetch 1,contr + rtnne 0x43 + ifetch 1,contr + rtnne 0x49 + ifetch 1,contr + rtnne 0x4e + ifetch 1,contr + rtnne 0x44 + enable user + increase 2,contr + ifetch 1,contr + beq 0x28, HFP_is_result_cind0 //'(',return if cind=? + branch HFP_is_result_cind1 //HFP_is_result_cind1 + +//input: +// contr -- payload addr point +HFP_is_result_cind1: + bpatch patch1f_4,mem_patch1f + force 7,loopcnt + storer contr,2,mem_at_command_ptr +HFP_is_result_cind1_loopcnt: + fetch 2,mem_at_command_ptr + icopy contr + call HFP_translate_ascii_to_hex + increase 2,rega + copy rega,contr + call HFP_FindComma + copy contr,pdata + store 2,mem_at_command_ptr + copy temp,rega //indicator value + copy loopcnt,temp + sub temp,7,temp + call HFP_get_indicator_index + arg mem_AG_indicator,temp + iadd temp,temp + copy rega,pdata + istore 1,temp + loop HFP_is_result_cind1_loopcnt + branch HFP_evt_update_state + + +//input: +// temp -- indicator map index +//output: +// pdata -- indicator index +HFP_get_indicator_index: + setarg mem_AG_indicator_map + iadd temp,temp + ifetch 1,temp + rtn + +HFP_find_double_quote: + ifetch 1,contr + rtneq 0x22 //'"' + branch HFP_find_double_quote + +HFP_is_result_cind0: + bpatch patch1f_5,mem_patch1f + force 7,loopcnt +HFP_is_result_cind0_loopcnt: + call HFP_find_double_quote //first '"' + storer contr,2,mem_at_command_ptr + call HFP_indicator_service + branch HFP_is_result_cind0_loopcnt_end,user2 + call HFP_indicator_call_callheld_callsetup + branch HFP_is_result_cind0_loopcnt_end,user2 + call HFP_indicator_signal + branch HFP_is_result_cind0_loopcnt_end,user2 + call HFP_indicator_roam + branch HFP_is_result_cind0_loopcnt_end,user2 + call HFP_indicator_battchg +HFP_is_result_cind0_loopcnt_end: + call HFP_find_double_quote //second '"' + loop HFP_is_result_cind0_loopcnt + rtn + +HFP_indicator_service: + disable user2 + fetch 2,mem_at_command_ptr + icopy contr + ifetch 1,contr + rtnne 0x73 //'s' + ifetch 1,contr + rtnne 0x65 //'e' + ifetch 1,contr + rtnne 0x72 //'r' + ifetch 1,contr + rtnne 0x76 //'v' + enable user2 + force HFP_CIEVIND_SERVICE,rega + branch HFP_indicator_store + + +HFP_indicator_battchg: + disable user2 + fetch 2,mem_at_command_ptr + icopy contr + ifetch 1,contr + rtnne 0x62 //'b' + ifetch 1,contr + rtnne 0x61 //'a' + ifetch 1,contr + rtnne 0x74 //'t' + ifetch 1,contr + rtnne 0x74 //'t' + ifetch 1,contr + rtnne 0x63 //'c' + enable user2 + force HFP_CIEVIND_BATTCHA,rega + branch HFP_indicator_store + +HFP_indicator_call_callheld_callsetup: + bpatch patch1f_6,mem_patch1f + disable user2 + fetch 2,mem_at_command_ptr + icopy contr + ifetch 1,contr + rtnne 0x63 //'c' + ifetch 1,contr + rtnne 0x61 //'a' + ifetch 1,contr + rtnne 0x6c //'l' + ifetch 1,contr + rtnne 0x6c //'l' + ifetch 1,contr + enable user2 + beq 0x68,HFP_indicator_callheld //'h' + beq 0x22,HFP_indicator_call + beq 0x73,HFP_indicator_callsetup + rtn + +HFP_indicator_callsetup: + force HFP_CIEVIND_CALLSETTUP,rega + branch HFP_indicator_store +HFP_indicator_call: + increase -1,contr + force HFP_CIEVIND_CALL,rega + branch HFP_indicator_store +HFP_indicator_callheld: + force HFP_CIEVIND_CALLHELD,rega +HFP_indicator_store: + copy loopcnt,pdata + sub pdata,7,pdata + arg mem_AG_indicator_map,temp + iadd temp,temp + copy rega,pdata + istore 1,temp + rtn + +HFP_indicator_roam: + disable user2 + fetch 2,mem_at_command_ptr + icopy contr + ifetch 1,contr + rtnne 0x72 //'r' + ifetch 1,contr + rtnne 0x6f //'o' + ifetch 1,contr + rtnne 0x61 //'a' + ifetch 1,contr + rtnne 0x6d //'m' + enable user2 + force HFP_CIEVIND_ROAM,rega + branch HFP_indicator_store + + +HFP_indicator_signal: + disable user2 + fetch 2,mem_at_command_ptr + icopy contr + ifetch 1,contr + rtnne 0x73 //'s' + ifetch 1,contr + rtnne 0x69 //'i' + ifetch 1,contr + rtnne 0x67 //'g' + ifetch 1,contr + rtnne 0x6e //'n' + enable user2 + force HFP_CIEVIND_SIGNAL,rega + branch HFP_indicator_store + + +HFP_is_result_brsf: + //disable user + fetch 2,mem_at_command_ptr + icopy contr + ifetch 1,contr + rtnne 0x2b + ifetch 1,contr + rtnne 0x42 + ifetch 1,contr + rtnne 0x52 + ifetch 1,contr + rtnne 0x53 + ifetch 1,contr + rtnne 0x46 + enable user + call HFP_translate_ascii_to_hex + storet 2,mem_agoption + rtn + +HFP_is_result_chld: + //disable user + fetch 2,mem_at_command_ptr + icopy contr + ifetch 1,contr + rtnne 0x2b + ifetch 1,contr + rtnne 0x43 + ifetch 1,contr + rtnne 0x48 + ifetch 1,contr + rtnne 0x4c + ifetch 1,contr + rtnne 0x44 + enable user + rtn + +HFP_handler_error: + fetch 1,mem_hf_state + beq HF_STATE_CONNECTED,HFP_battery_process + fetch 1,mem_hf_state + beq HF_STATE_WAITING_CODECS_OK,HFP_AG_CODECS_error + rtn + + +HFP_is_result_ok: + fetch 2,mem_at_command_ptr + icopy contr + ifetch 1,contr + rtnne 0x4F + ifetch 1,contr + rtnne 0x4B + enable user + call HFP_result_ok_cmd +HFP_result_ok_handle: + bpatch patch1f_7,mem_patch1f + fetch 1,mem_hf_state + beq HF_STATE_WAITING_AG_UPDATE_STATUS_OK, HFP_AG_UPDATE_STATUS_OK + beq HF_STATE_WAITING_AG_INFO, HFP_AG_receive_info_ok + beq HF_STATE_WAITING_AT_CLIP, HFP_AG_enable_CLIP_ok + beq HF_STATE_WAITING_AT_CCWA,HFP_AG_enable_call_waiting_ok + beq HF_STATE_WAITING_AG_FEATURE_OK, HFP_AG_FEATURE_OK + beq HF_STATE_WAITING_CODECS_OK,HFP_AG_CODECS_OK + beq HF_STATE_WAITING_AG_INDICATORS_OK, HFP_AG_INDICATORS_OK + beq HF_STATE_WAITING_AG_STATUS_OK, HFP_AG_STATUS_OK + beq HF_STATE_WAITING_AG_UPDATE_STATUS_OK, HFP_AG_UPDATE_STATUS_OK + beq HF_STATE_CONNECTED,HFP_battery_process + rtn + +HFP_battery_process: + fetch 1,mem_hfp_battery_state + beq HF_STATE_WAITING_CSCS_OK,hfp_battery_process_increase + beq HF_STATE_WAITING_NERC_OK,hfp_battery_process_increase + beq HF_STATE_WAITING_BIA_OK,hfp_battery_process_increase + beq HF_STATE_WAITING_XAPL_OK,hfp_battery_process_increase + beq HF_STATE_WAITING_XEVENT_OK,hfp_battery + beq HF_STATE_WAITING_ANDROID_OK,hfp_battery_process_increase + beq HF_STATE_WAITING_IPHONE_OK,hfp_battery_clear + rtn + +hfp_battery_process_increase: + increase 1,pdata + store 1,mem_hfp_battery_state + rtn + +hfp_battery_clear: + jam 0,mem_hfp_battery_state + rtn + +hfp_battery: + jam HF_STATE_WAITING_ANDROID,mem_hfp_battery_state + rtn + +HFP_result_ok_cmd: + bpatchx patch20_0,mem_patch20 + fetch 1,mem_hf_command + beq HF_WAIT_ACCEPT_CALL_OK,HFP_acceptcall + beq HF_WAIT_HANGUP_OK,HFP_hangup + beq HF_WAIT_VGS_OK,HFP_vgs_ok + beq HF_WAIT_VGM_OK,HFP_vgm_ok + rtn + +HFP_acceptcall: +HFP_hangup: +HFP_vgm_ok: + jam HF_CMD_IDLE,mem_hf_command + rtn +HFP_vgs_ok: + jam HF_CMD_IDLE,mem_hf_command + rtn + + +HFP_AG_FEATURE_OK: + jam HF_STATE_HF_SEND_CODECS, mem_hf_state + rtn +HFP_AG_CODECS_error: +HFP_AG_CODECS_OK: + jam HF_STATE_HF_SEND_INDICATORS, mem_hf_state + rtn +HFP_AG_INDICATORS_OK: + jam HF_STATE_HF_SEND_CURR_STATUS, mem_hf_state + rtn +HFP_AG_STATUS_OK: + jam HF_STATE_HF_SEND_UPDATE_STATUS, mem_hf_state + rtn +HFP_AG_UPDATE_STATUS_OK: + jam HF_STATE_HF_SEND_RECEIVE_INFO, mem_hf_state + rtn +HFP_AG_receive_info_ok: + jam HF_STATE_HF_SEND_AT_CLIP, mem_hf_state + rtn +HFP_AG_enable_CLIP_ok: + jam HF_STATE_HF_SEND_AT_CCWA,mem_hf_state + rtn +HFP_AG_enable_call_waiting_ok: + call send_AT_vgs + jam HF_STATE_WAITING_CSCS,mem_hfp_battery_state + jam HF_STATE_CONNECTED, mem_hf_state + jam CODEC_TYPE_CVSD,mem_codec_type + jam BT_EVT_HFP_CONNECTED,mem_fifo_temp + branch ui_ipc_send_event + +HFP_is_result_vgm_vgs: + //disable user + fetch 2,mem_at_command_ptr + icopy contr + ifetch 1,contr + rtnne 0x2b + ifetch 1,contr + rtnne 0x56 + ifetch 1,contr + rtnne 0x47 + ifetch 1,contr + enable user + beq 0x4d,HFP_vgm_changed + beq 0x53,HFP_vgs_changed + rtn + +HFP_vgs_changed: + call HFP_translate_ascii_to_hex + lshift temp,temp + storet 1,mem_hf_vlm_speaker + rtn + +HFP_vgm_changed: + call HFP_translate_ascii_to_hex + storet 1,mem_hf_vlm_mic + rtn + +HFP_is_xapl: + fetch 2,mem_at_command_ptr + icopy contr + ifetch 1,contr + rtnne 0x2b + ifetch 1,contr + rtnne 0x58 + ifetch 1,contr + rtnne 0x41 + ifetch 1,contr + rtnne 0x50 + ifetch 1,contr + rtnne 0x4c + ifetch 1,contr + rtnne 0x3d + enable user + branch HFP_handler_error + +HFP_is_bcs: + fetch 2,mem_at_command_ptr + icopy contr + ifetch 1,contr + rtnne 0x2b + ifetch 1,contr + rtnne 0x42 + ifetch 1,contr + rtnne 0x43 + ifetch 1,contr + rtnne 0x53 + ifetch 1,contr + rtnne 0x3a + enable user +HFP_is_bcs_20: + ifetch 1,contr + beq 0x20,HFP_is_bcs_20 + beq 0x31,HFP_set_codec_type_cvsd + beq 0x32,HFP_set_codec_type_msbc + branch HFP_handler_error + +HFP_set_codec_type_msbc: + jam CODEC_TYPE_mSBC,mem_codec_type + branch send_AT_BCS +HFP_set_codec_type_cvsd: + jam CODEC_TYPE_CVSD,mem_codec_type + branch send_AT_BCS + + +HFP_is_result_ccwa: + fetch 2,mem_at_command_ptr + icopy contr + ifetch 1,contr + rtnne 0x2b + ifetch 1,contr + rtnne 0x43 + ifetch 1,contr + rtnne 0x43 + ifetch 1,contr + rtnne 0x57 + ifetch 1,contr + rtnne 0x41 + enable user + branch HFP_is_result_clip_loop + +HFP_is_result_clip: + bpatchx patch20_1,mem_patch20 + //disable user + fetch 2,mem_at_command_ptr + icopy contr + ifetch 1,contr + rtnne 0x2b + ifetch 1,contr + rtnne 0x43 + ifetch 1,contr + rtnne 0x4c + ifetch 1,contr + rtnne 0x49 + ifetch 1,contr + rtnne 0x50 + enable user + call HFP_is_result_clip_loop + fetch 1,mem_telephone_dialing_state + rtnne HFP_DIALING_STATE_NO + branch hfp_dialing_start + +HFP_is_result_clip_loop: + ifetch 1,contr + bne 0x22,HFP_is_result_clip_loop + force 0,rega + force 0x30,regb + arg mem_phone_number,contw +HFP_is_result_clip_phone_num: + ifetch 1, contr + beq 0x22,HFP_is_result_clip_end + increase 1,rega + isub regb,pdata + istore 1,contw + branch HFP_is_result_clip_phone_num +HFP_is_result_clip_end: + deposit rega + store 1,mem_phone_num_len + rtn + + +HFP_handle_at_result_code: + bpatchx patch20_2,mem_patch20 + disable user + call HFP_is_result_ok + rtn user + call HFP_is_result_error + branch HFP_handler_error,user + storer queue,2,mem_temp + call HFP_send_credit_return + fetchr queue,2,mem_temp + call HFP_is_result_brsf + rtn user + call HFP_is_result_ciev + rtn user + call HFP_is_result_ring + rtn user + call HFP_is_result_cind + rtn user + call HFP_is_result_chld + rtn user + call HFP_is_result_vgm_vgs + rtn user + call HFP_is_result_clip + rtn user + call HFP_is_result_ccwa + rtn user + call HFP_is_xapl + rtn user + call HFP_is_bcs + rtn user + fetch 2,mem_cb_hfp_result_code + branch callback_func + + +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// +HFP_tx_rfcomm_without_credit: + bpatchx patch20_3,mem_patch20 + fetch 2,mem_remote_credits + rtn blank + increase -1,pdata + store 2,mem_remote_credits + + fetchr regd,2,mem_rfc_l2capch_ptr + + fetch 1,mem_HIUfcs_SPP + store 1,mem_rfcomm_send_fcs + setarg RSP_TX_UIH + store 1,mem_rfcomm_send_frame_type + call rfc_get_rfcomm_snd_adss + fetch 2,mem_current_packet_length + increase 4,pdata //fcs + rfcommhead + l2caphead == 8 + icopy rega + call l2cap_malloc_server_channel + fetch 1,mem_rfcomm_send_adss + istore 1,contw + fetch 1,mem_rfcomm_send_frame_type + istore 1,contw + call rfc_tx_write_length + fetch 2,mem_current_packet_length + copy pdata,loopcnt + //arg mem_AT_CKPD,contr + fetch 2, mem_at_rfcomm_data_ptr + copy pdata,contr + call memcpy + fetch 1,mem_rfcomm_send_fcs + istore 1,contw + jam 0,mem_credit_given //whatever mem_credit_given is set to 0 + setarg 0 + store 2,mem_current_packet_length + rtn + + + + +HFP_clear_dac_mem: + fetchr loopcnt,2,core_dac_len + increase 1,loopcnt + fetch 2,core_dac_saddr + copy pdata,contw + fetch 1,core_dac_ctrl + bbit0 DAC_MRAM_SEL,clear_mem_fast + set1 MRAM_HIGH_BIT,contw + branch clear_mem_fast + +HFP_voice_start_notify: + jam HFP_EVT_ESCO_START,mem_fifo_temp + call ipc_tx_HFP_event + jam 1,mem_sco_transaction_enable + rtn + +HFP_voice_start: + bpatchx patch20_4,mem_patch20 + call m0_sco_data_buffer_init + fetch 1,mem_audio_allow + sub pdata,AVD_AUDIO_FORBID,null + ncall avd_stop_sbc_dac,zero + fetch 1,mem_vp_enable + rtnne VP_STATE_DISENABLE + // protect m0 + jam LOCAL_SCO_WORK_IN_PROCESS,mem_local_sco_in_process_flag + nop 20 + call HFP_voice_start_init_process + jam LOCAL_SCO_WORK_DONE,mem_local_sco_in_process_flag + rtn + +HFP_voice_start_init_process: + fetch 1,mem_codec_type + beq CODEC_TYPE_CVSD,cvsd_init + beq CODEC_TYPE_mSBC,mSBC_init + rtn + +HFP_voice_stop_notify: + jam HFP_EVT_ESCO_STOP,mem_fifo_temp + call ipc_tx_HFP_event + jam 0,mem_sco_transaction_enable + rtn + +HFP_voice_stop: + bpatchx patch20_5,mem_patch20 + // protect m0 + jam LOCAL_SCO_WORK_IN_PROCESS,mem_local_sco_in_process_flag + nop 20 + call HFP_voice_stop_init_process + jam LOCAL_SCO_WORK_DONE,mem_local_sco_in_process_flag + rtn + +HFP_voice_stop_init_process: + call audio_dac_stop + call audio_adc_stop + fetch 1,mem_codec_type + beq CODEC_TYPE_CVSD,cvsd_stop + beq CODEC_TYPE_mSBC,mSBC_stop + rtn + +HFP_get_vol: + bpatchx patch20_6,mem_patch20 + fetch 1,mem_hf_vlm_speaker + arg HFP_SPEAKER_MAX_VLM,temp + isub temp,null + branch HFP_get_max_vol,positive + increase 2,pdata + lshift2 pdata,temp + rtn +HFP_get_max_vol: + arg 0x7f,temp + rtn + +HFP_adjust_max_volume: + jam HFP_SPEAKER_MAX_VLM,mem_hf_vlm_speaker + jam BT_EVT_HFP_UP_TO_MAX_VLM,mem_fifo_temp + branch ui_ipc_send_event + +HFP_adjust_min_volume: + jam 0,mem_hf_vlm_speaker + jam BT_EVT_HFP_DOWN_TO_MIN_VLM,mem_fifo_temp + branch ui_ipc_send_event +endif Index: tag/Soft/Librarier/bt_rom/program/ipc.prog =================================================================== --- /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/ipc.prog (nonexistent) +++ /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/ipc.prog (working copy) @@ -0,0 +1,349 @@ + + +ipc_init: + bpatchx patch20_7,mem_patch20 + fetch 1,mem_ipc_enable + rtn blank + call ipc_notify_m0_wakeup_flag_init + call mram_clkon + nop 40 + jam MCU_STATE_IDLE,mem_ipc_mcu_state + jam MCU_PHASE_IDLE,mem_ipc_mcu_phase + call ipc_clear_mem_block + fetch 3,mem_param_ipc_to_m0_buf_start_addr + fetcht 3,mem_param_ipc_to_m0_wptr_addr + istore 3,temp + fetcht 3,mem_param_ipc_to_m0_rptr_addr + istore 3,temp + + fetch 3,mem_param_ipc_to_bt_buf_start_addr + fetcht 3,mem_param_ipc_to_bt_wptr_addr + istore 3,temp + fetcht 3,mem_param_ipc_to_bt_rptr_addr + istore 3,temp + rtn + +ipc_clear_mem_block: + bpatchx patch21_0,mem_patch21 + fetch 3,mem_param_ipc_mem_block_end_addr + fetcht 3,mem_param_ipc_mem_block_start_addr + copy temp,contw + isub contw,loopcnt + branch clear_mem + +ipc_notify_m0_wakeup_flag_init: + jam 0,mem_wake_flag + rtn wake + jam 1,mem_wake_flag + rtn + +ipc_lock_m0_lmp_wait_work_flag: + fetch 2,mem_m0_lpm_flag + set1 6,pdata + store 2,mem_m0_lpm_flag + rtn + +ipc_check_m0_state: + fetch 1,mem_ipc_mcu_state + rtnne MCU_STATE_STOP + jam MCU_STATE_IDLE, mem_ipc_mcu_state + + jam BT_EVT_WAKEUP,mem_fifo_temp + branch ipc_tx_bt_event + +ipc_100ms_timer_work: + fetch 1,mem_app_evt_timer_count + rtn blank + arg BT_EVT_100MS_UINT,temp + iadd temp,pdata + store 1,mem_fifo_temp + branch ipc_tx_bt_event + +/*********************IPC RX**********************/ + +// input: contr, contw,loopcnt +// output: null +// affect: rega, regc +ipc_rx_block_read: + bpatchx patch21_1,mem_patch21 + call ipc_rx_byte_read + istore 1,contw + loop ipc_rx_block_read + copy contw,regc +ipc_rx_block_read_end: + call ipc_rx_rptr_loopback + deposit contr + fetcht 3,mem_param_ipc_to_bt_rptr_addr + istore 3,temp + rtn + + +// input: contr +// output: pdata +// affect: rega +ipc_rx_byte_read: + call ipc_rx_rptr_loopback + ifetch 1,contr + rtn +// input: contr +// output: contr +// affect: rega +ipc_rx_rptr_loopback: + // store contr + copy contr,rega + fetch 3,mem_param_ipc_to_bt_buf_end_addr + copy rega,contr + isub contr,null + nrtn zero + fetch 3,mem_param_ipc_to_bt_buf_start_addr + copy pdata,contr + rtn + +// input: +// output: pdata,temp,zero +// affect: rega +ipc_rx_items_inquire: + fetcht 3,mem_param_ipc_to_bt_rptr_addr + ifetch 3,temp + copy pdata,rega + + fetcht 3,mem_param_ipc_to_bt_wptr_addr + ifetch 3,temp // here should not use ifetcht + copy pdata,temp + copy rega,pdata +ipc_check_items: + isub temp,null + rtn + +// input: +// output: pdata,temp,zero +// affect: rega +ipc_tx_items_inquire: + fetcht 3,mem_param_ipc_to_m0_rptr_addr + ifetch 3,temp + copy pdata,rega + + fetcht 3,mem_param_ipc_to_m0_wptr_addr + ifetch 3,temp // here should not use ifetcht + copy pdata,temp + copy rega,pdata + branch ipc_check_items + +ipc_check_enter_lpm: + fetch 1,mem_ipc_enable + rtn blank + bpatchx patch21_2,mem_patch21 + fetch 2,mem_m0_lpm_flag + nbranch setarg1,blank + call ipc_rx_items_inquire + nbranch setarg1,zero + call ipc_tx_items_inquire + nbranch setarg1,zero + jam MCU_STATE_LPM,mem_ipc_mcu_state + call ipc_check_ack0 + nbranch setarg1,blank + branch setarg0 + + +// input: contr +// output: pdata +// affect: rega +ipc_rx_block_clear: + call ipc_rx_byte_read + loop ipc_rx_block_read + branch ipc_rx_block_read_end + + + // store contr + copy contr,rega + fetch 3,mem_param_ipc_to_bt_buf_end_addr + isub rega,null + copy rega,contr + nrtn zero + fetch 3,mem_param_ipc_to_bt_buf_start_addr + copy pdata,contr + rtn +/******************IPC TX***************************/ +//input:contw +//used: pdata,contw,contr +ipc_tx_wptr_loopback: + fetch 3,mem_param_ipc_to_m0_buf_end_addr + isub contw,null + nrtn zero + fetch 3,mem_param_ipc_to_m0_buf_start_addr + copy pdata,contw + rtn + +//input:temp,contw +//used: pdata,contw,rega,contr +ipc_tx_byte_write: + call ipc_tx_wptr_loopback + istoret 1,contw + rtn + +//input:loopcnt,contr +//used: pdata,contw,rega,contr,regb +ipc_tx_block_write: + ifetcht 1,contr + copy contr,regb + call ipc_tx_byte_write + copy regb,contr + loop ipc_tx_block_write +ipc_tx_block_write_end: + call ipc_tx_wptr_loopback + deposit contw + fetcht 3,mem_param_ipc_to_m0_wptr_addr + istore 3,temp + rtn + +//input:loopcnt +ipc_check_tx_buf_is_enough: + bpatchx patch21_3,mem_patch21 + disable user + + fetcht 3,mem_param_ipc_to_m0_wptr_addr + ifetch 3,temp + copy pdata,contw + + fetcht 3,mem_param_ipc_to_m0_rptr_addr + ifetch 3,temp + copy pdata,regb +ipc_check_tx_buffer_ptr: + increase 1,contw + call ipc_tx_wptr_loopback + copy regb,pdata + isub contw,null + branch ipc_check_tx_buffer_not_enouth,zero + loop ipc_check_tx_buffer_ptr + enable user + rtn +ipc_check_tx_buffer_not_enouth: + fetch 2,mem_ipc_loss_packet + increase 1,pdata + store 2,mem_ipc_loss_packet + rtn + +ipc_rx_process: + bpatchx patch21_4,mem_patch21 + fetch 1,mem_ipc_enable + rtn blank + call ipc_rx_items_inquire + rtn zero // no data + icopy contr + call ipc_rx_byte_read + beq IPC_TYPE_CMD,ipc_rx_cmd + beq IPC_TYPE_BLE,ipc_rx_ble + branch assert + +//receive cmd control +ipc_rx_cmd: + bpatchx patch21_5,mem_patch21 + call ipc_rx_byte_read + call ipc_rx_byte_read + store 1,mem_fifo_temp + call ipc_rx_block_read_end + fetch 1,mem_fifo_temp + branch ui_ipc_send_cmd + //beq BT_CMD_LE_UPDATE_CONN,le_send_update_paramter + //beq BT_CMD_MTU_EXCHANGE,le_send_update_ATT_MTU + //beq BT_CMD_START_ADV,app_ble_start_adv + //beq BT_CMD_LOAD_FLASH_PARAMS,load_le_ltk + //rtn + + + + +//ble data to send +ipc_rx_ble: + bpatchx patch21_6,mem_patch21 + copy contr,rega + call le_fifo_check_full + nrtn blank + fetch 2,mem_ui_state_map + isolate0 UI_STATE_BLE_CONNECTED,pdata + branch ipc_rx_ble_discard_packet,true + copy rega,contr + call ipc_rx_byte_read + store 1,mem_ipc_le_data_len + call ipc_rx_byte_read + store 2,mem_le_att_handle + call ipc_rx_byte_read + copy contr,pdata + store 3, mem_temp + fetchr rega,1,mem_ipc_le_data_len + increase -2,rega + fetchr temp,2,mem_le_att_handle + call le_att_malloc_tx_notify + fetchr loopcnt,1,mem_ipc_le_data_len + increase -2,loopcnt + fetch 3,mem_temp + icopy contr + branch ipc_rx_block_read + +ipc_rx_ble_discard_packet: + copy rega,contr + call ipc_rx_byte_read + icopy loopcnt + branch ipc_rx_block_clear + + +ipc_tx_common: + bpatchx patch21_7,mem_patch21 + fetch 1,mem_ipc_enable + rtn blank + call bt_wake_up_m0_light_sleep + fetchr loopcnt,1,mem_ipc_tx_data_len + call ipc_check_tx_buf_is_enough + nrtn user + fetchr loopcnt,1,mem_ipc_tx_data_len + + fetcht 3,mem_param_ipc_to_m0_wptr_addr + ifetch 3,temp + copy pdata,contw + fetch 2,mem_ipc_tx_data_ptr + icopy contr + branch ipc_tx_block_write + +ipc_tx_bt_event: + bpatchx patch22_0,mem_patch22 + fetch 1,mem_ipc_enable + rtn blank + call bt_wake_up_m0_light_sleep + force 3,loopcnt + call ipc_check_tx_buf_is_enough + nrtn user + fetcht 3,mem_param_ipc_to_m0_wptr_addr + ifetch 3,temp + copy pdata,contw + arg IPC_TYPE_EVT,temp + call ipc_tx_byte_write + force 1,temp + call ipc_tx_byte_write + fetchr temp,1,mem_fifo_temp + call ipc_tx_byte_write + branch ipc_tx_block_write_end + +ipc_tx_bt_ble_test: + jam 10,mem_ipc_tx_data_len + setarg mem_ipc_test_buff +ipc_tx_buffer: + store 2,mem_ipc_tx_data_ptr + branch ipc_tx_common + + +ipc_HFP_evt_received: + jam 1,pdata + arg IPC_TYPE_HFP,regb + arg mem_fifo_temp,regc + branch ipc_tx_common + + +ipc_check_ack: + jam 0,mem_wake_flag +ipc_check_ack0: + nop 30 + fetch 1,mem_ipc_mcu_state + beq MCU_STATE_STOP,setarg0 + beq MCU_STATE_IDLE,setarg1 + branch ipc_check_ack0 + Index: tag/Soft/Librarier/bt_rom/program/l2cap.prog =================================================================== --- /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/l2cap.prog (nonexistent) +++ /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/l2cap.prog (working copy) @@ -0,0 +1,1340 @@ +/************************************/ +/*initialize L2CAP related variables*/ +/************************************/ +l2cap_init: + branch l2cap_init_wake,wake +l2cap_init_work: + setarg mem_l2cap_xmem_end + arg mem_l2cap_xmem_start,contw + isub contw,loopcnt + call clear_mem + call l2cap_init_queue +l2cap_init_wake: + bpatchx patch22_1,mem_patch22 + setarg mem_l2cap_mem_end + arg mem_l2cap_mem_start,contw + isub contw,loopcnt + call clear_mem + rtn wake + setarg mem_avctp_xmem_end + arg mem_avctp_xmem_start,contw + isub contw,loopcnt + call clear_mem + setarg mem_avdtp_xmem_end + arg mem_avdtp_xmem_start,contw + isub contw,loopcnt + call clear_mem + setarg mem_sdp_mem_end + arg mem_sdp_mem_start,contw + isub contw,loopcnt + call clear_mem + setarg mem_uppersm_xmem_end + arg mem_uppersm_xmem_start,contw + isub contw,loopcnt + call clear_mem + setarg mem_hid_xmem_end + arg mem_hid_xmem_end,contw + isub contw,loopcnt + call clear_mem + setarg mem_l2cap_mem_end + arg mem_l2cap_mem_start,contw + isub contw,loopcnt + call clear_mem + setarg mem_rfc_xmem_end + arg mem_rfc_xmem_start,contw + isub contw,loopcnt + branch clear_mem + +l2cap_init_queue: + bpatchx patch22_2,mem_patch22 + jam BLOCK_MAX_NUM,mem_l2cap_rx_malloc_num + setarg L2CAP_ONE_RXBUFF_LENTH + store 2,mem_l2cap_rx_max_lenth + setarg mem_l2cap_rxbuff1 + call init_all_queue + fetchr loopcnt,1,mem_l2cap_rx_malloc_num +// arg mem_l2cap_queue_ptr,rege + arg mem_l2cap_rxbuff1,regb +// fetchr rege,2,mem_l2cap_rx_max_lenth +queue_loop: +// ifetchr regb, 3,rege + arg mem_alloc_block,rega + call queue_insert +// increase 3,rege + fetch 2,mem_l2cap_rx_max_lenth + iadd regb,regb + loop queue_loop + rtn + +init_all_queue: + setarg mem_alloc_block + call queue_init + setarg mem_media_block + call queue_init + setarg mem_lcp_block +//input: pdata +queue_init: + copy pdata,contw + add pdata,BLOCK_DATA_OFFSET,pdata + istore 2,contw + istore 2,contw + istore 2,contw +// add pdata,BLOCK_MAX_LEN,pdata + fetcht 1,mem_l2cap_rx_malloc_num + mul32 temp,3,temp + iadd temp,pdata + istore 2,contw + arg BLOCK_MAX_LEN+1,loopcnt + branch clear_mem +/* +//input:pdata +queue_get_wrtie_ptr: + add rega,BLOCK_WPTR_OFFSET,pdata + ifetcht 2,pdata + ifetch 3,temp + branch get_pdata_contw +*/ +//input:rega +//input:regc +//output:regc +queue_unit_increase: + add rega,BLOCK_END_OFFSET,temp + ifetch 2,temp //get store addr's value + isub regc,null + nrtn zero + add rega,BLOCK_HEADER_OFFSET,temp + ifetchr regc,2,temp + rtn + +//input1:rega --- mem block +//input2:regb --- block ptr +queue_insert: + bpatchx patch22_3,mem_patch22 + add rega,BLOCK_WPTR_OFFSET,pdata + ifetcht 2,pdata + istorer regb,3,temp//store rxbuffer addr to wptr(start) + add temp,3,regc + call queue_unit_increase + add rega,BLOCK_WPTR_OFFSET,pdata + istorer regc,2,pdata + + add rega,BLOCK_CUR_LEN_OFFSET,temp + ifetch 1,temp + increase 1,pdata + istore 1,temp + rtn + + +//input:rega +//ouput:contr +queue_get_read_ptr: + add rega,BLOCK_RPTR_OFFSET,pdata + ifetcht 2,pdata + ifetch 3,temp + branch get_pdata_contr + +//input1:rega --- mem block +//output:regb --- block ptr +queue_free: +queue_delete: + bpatchx patch22_4,mem_patch22 + add rega,BLOCK_RPTR_OFFSET,pdata + ifetcht 2,pdata + ifetchr regb,3,temp + setarg 0 + istore 3,temp + add temp,3,regc + call queue_unit_increase + add rega,BLOCK_RPTR_OFFSET,pdata + istorer regc,2,pdata + + add rega,BLOCK_CUR_LEN_OFFSET,temp + ifetch 1,temp + increase -1,pdata + istore 1,temp + rtn + + +//mem_media_block,mem_media_block:blank -- empty mem_alloc_block:blank -- full +//input --- rega +queue_get_len: + increase BLOCK_CUR_LEN_OFFSET,rega + ifetch 1,rega + rtn + +push_l2cap_queue: + setarg 0 + store 2,mem_l2cap_rxbuff1_len + arg mem_alloc_block,rega + call queue_delete + arg mem_lcp_block,rega + branch queue_insert + +pop_l2cap_queue: + arg mem_lcp_block,rega + call queue_delete + arg mem_alloc_block,rega + branch queue_insert + +push_media_queue: + // set flag + arg LOG_POINT_1605,rega + fetcht 1,mem_media_cur_len + call debug_log_print + setarg 0 + store 2,mem_l2cap_rxbuff1_len + arg mem_alloc_block,rega + call queue_delete + arg mem_media_block,rega + branch queue_insert + + +pop_media_queue: + arg mem_media_block,rega + call queue_delete + arg mem_alloc_block,rega + call queue_insert + call a2dp_check_need_cal_media_frame_info +// jam 0,mem_media_release + rtn + +media_queue: +// fetch 1,mem_init_a2dp_dac +// ncall p_hp_stero_init,blank +// call l2cap_malloc_is_fifo_nearly_full +// nrtn blank + arg mem_media_block,rega + call queue_get_len + rtn blank + + // fetch 1,mem_media_release +// rtn blank + call l2cap_call_proc_avdtp_media + fetch 1 ,mem_l2cap_rx_done + rtnne L2CAP_RX_DONE + call pop_media_queue + branch media_queue + +process_rx_l2cap_pkt: + copy contr,temp + bpatchx patch22_5,mem_patch22 + ifetch 2,contr + store 2,mem_l2cap_rx_pkt_length + ifetch 2,contr + store 2,mem_l2cap_rx_cid + deposit contr + store 2,mem_l2cap_payload_ptr + fetch 2, mem_l2cap_rx_pkt_length + branch l2cap_rx_reset_state,blank +// fetch 1,mem_l2cap_rx_cid+1 +// bne 1,p_process_rx_l2cap_pkt0 +// jam 1,mem_special_cid +//p_process_rx_l2cap_pkt0: + fetch 2,mem_l2cap_rx_cid + arg L2CAP_signal_channel,temp + isub temp,null + branch l2cap_call_proc_signal,zero + fetch 2,mem_l2cap_rx_cid + beq L2CAP_signal_channel,l2cap_call_proc_signal +process_normal_rx_l2cap_pkt: + copy pdata,rega + call l2cap_get_channel_info_by_local_cid + copy regc,regd //ptr to l2cap context + + // set flag + arg LOG_POINT_1502,rega + //fetcht 2,clke + ifetcht 1,regc + call debug_log_print + + + bpatchx patch22_6,mem_patch22 + ifetch 1,regc + beq PSM_SDP,l2cap_call_proc_sdp + beq PSM_RFCOMM,l2cap_call_proc_rfcomm + beq PSM_HID_control,l2cap_call_proc_hid + beq PSM_HID_interrupt,l2cap_call_proc_hid + beq PSM_AVCTP,l2cap_call_proc_avctp + + bne PSM_AVDTP,l2cap_rx_reset_state + bpatchx patch22_7,mem_patch22 + fetch 2,mem_avdtpsignal_l2capch_ptr + isub regc,null + branch l2cap_call_proc_avdtp,zero + fetch 2,mem_avdtpmedia_l2capch_ptr + isub regc,null +// branch l2cap_call_proc_avdtp_media,zero + branch assert,zero + branch assert + +process_listen_tws_rx_l2cap_pkt: + fetch 2,mem_l2cap_rx_cid + fetcht 2,mem_avdtp_signal + isub temp,null + branch l2cap_call_proc_avdtp,zero + fetcht 2,mem_avdtp_media + isub temp,null +// branch l2cap_call_proc_avdtp_media,zero + branch assert,zero + branch l2cap_rx_reset_state + +l2cap_call_proc_signal: + call l2cap_malloc_is_fifo_full + nrtn blank + call l2cap_process_signal_pkt + branch l2cap_rx_reset_state + +l2cap_call_proc_sdp: + call l2cap_malloc_is_fifo_empty + nrtn blank// not process this packet until fifo empty + call l2cap_malloc_sdp_channel + call sdp_process + call l2cap_get_sdp_tx_buff + fetch 2,mem_sdp_tx_pkt_length + branch l2cap_call_proc_no_reply,blank + istore 2,contw + branch l2cap_rx_reset_state + + + +l2cap_call_proc_rfcomm: + call l2cap_malloc_is_fifo_full + nrtn blank + call l2cap_rfc_process + branch l2cap_rx_reset_state + +l2cap_call_proc_no_reply: + bpatchx patch23_0,mem_patch23 + call l2cap_malloc_discard + //fall through +l2cap_rx_reset_state: + jam L2CAP_RX_DONE,mem_l2cap_rx_done + rtn + +l2cap_process_signal_pkt: + bpatchx patch23_1,mem_patch23 + // debug + fetch 2,mem_l2cap_payload_ptr + iforce contr + ifetcht 1,contr + // set flag + arg LOG_POINT_1500,rega + call debug_log_print + + force 0,regb + fetch 2,mem_l2cap_rx_pkt_length + copy pdata,regc + fetch 2,mem_l2cap_payload_ptr + iforce contr + bpatchx patch23_2,mem_patch23 + ifetch 1,contr + beq signal_info_req,l2cap_proc_signal_info_req + beq signal_info_rsp,l2cap_proc_signal_info_rsp + beq signal_cmd_reject,l2cap_proc_signal_cmd_reject + beq signal_connect_req,l2cap_proc_signal_connect_req + beq signal_connect_rsp,l2cap_proc_signal_connect_rsp + beq signal_config_req,l2cap_proc_signal_config_req + beq signal_config_rsp,l2cap_proc_signal_config_rsp + beq signal_disconnect_req,l2cap_proc_signal_disconnect_req + beq signal_disconnect_rsp,l2cap_proc_signal_disconnect_rsp + beq signal_echo_req,l2cap_proc_signal_echo_req + beq signal_echo_rsp,l2cap_proc_signal_echo_rsp + branch assert + +l2cap_proc_signal_info_req: + ifetch 1,contr + store 1,mem_l2cap_signal_ident + increase 2,contr + ifetch 2,contr + beq L2CAP_SIG_EXT_FEATRUE,l2cap_send_signal_info_req_ext + beq L2CAP_SIG_FIX_FEATRUE,l2cap_send_signal_info_req_fix + branch assert + +l2cap_send_signal_info_req_ext: + arg 12,rega + call l2cap_malloc_signal_channel + setarg signal_info_rsp + istore 1,contw + fetch 1,mem_l2cap_signal_ident + istore 1,contw + setarg 0x020008 + istore 6, contw + setarg 0x0280 + istore 4, contw + rtn +l2cap_send_signal_info_req_fix: + arg 16,rega + call l2cap_malloc_signal_channel + setarg signal_info_rsp + istore 1,contw + fetch 1,mem_l2cap_signal_ident + istore 1,contw + setarg 0x3000c + istore 6, contw + setarg 0x0006 + istore 8, contw + rtn + +/* Respond to the command reject signal sent from the remote BD. */ +l2cap_proc_signal_cmd_reject: + rtn +/* Respond to an L2CAP connection request from remote BD. (generate a connection_rsp) */ +l2cap_proc_signal_connect_req: + ifetch 1,contr + store 1,mem_l2cap_signal_ident + increase 2,contr + ifetch 2,contr + store 1,mem_l2cap_temp_ch_psm + ifetcht 2,contr + storet 2,mem_l2cap_temp_remote_cid + copy pdata,regc + bpatchx patch23_3,mem_patch23 + copy regc,pdata + call l2cap_check_psm + nbranch assert,user + branch l2cap_proc_signal_connect_req_allow_psm + +l2cap_check_psm: + beq PSM_SDP,enable_user + beq PSM_RFCOMM,enable_user + beq PSM_HID_control,enable_user + beq PSM_HID_interrupt,enable_user + beq PSM_AVCTP,enable_user + beq PSM_AVDTP,enable_user + beq PSM_ATT,enable_user + branch disable_user + +l2cap_proc_signal_connect_req_allow_psm: + fetch 1,mem_l2cap_temp_ch_psm + beq PSM_AVDTP,l2cap_proc_signal_connect_req_avdtp +l2cap_proc_signal_connect_req_allow_psm2: + call l2cap_get_tws_fix_local_cid + store 2,mem_l2cap_temp_local_cid + setarg 0 + set1 L2CAP_CHANNEL_STATE_CONN_REQ,pdata + store 1,mem_l2cap_temp_ch_state + call l2cap_create_empty_channel + fetch 6,mem_l2cap_temp_ch_info + istore 6,regc + call l2cap_save_server_ptr + fetch 1,mem_l2cap_temp_ch_psm + beq PSM_SDP,l2cap_send_connect_res_pending + branch l2cap_send_connect_res_succ + +l2cap_proc_signal_connect_req_avdtp: + fetch 2,mem_avdtpsignal_l2capch_ptr + branch l2cap_proc_signal_connect_req_allow_psm2,blank + fetchr regc,2,mem_avdtpsignal_l2capch_ptr + add regc,offset_lc_state,regc + ifetch 1,regc + beq 0x3f ,l2cap_proc_signal_connect_req_allow_psm2 + branch l2cap_send_conn_res_refused_no_resources + + +l2cap_prepare_send_connect_res_succ: + fetch 1,mem_l2cap_pending_count + rtn blank + call l2cap_malloc_is_fifo_full + nrtn blank + call l2cap_get_active_pending_info + nrtn user + copy contr,rega + ifetch 1,contr + store 1,mem_l2cap_signal_ident + ifetch 4,contr + ifetchr regc,2,contr + arg 0x50,temp + iadd temp,temp + copy clkn_bt,pdata + isub temp,null + nrtn positive + setarg 0 + istore 7,rega //clear pending info + ifetch 1,regc + bne PSM_SDP,assert + add regc,offset_lc_state,contr + ifetcht 1,contr + arg 0,rega + set1 L2CAP_CHANNEL_STATE_CONN_REQ,rega + arg 0,regb + set1 L2CAP_CHANNEL_STATE_CONN_RES,regb + + copy rega,pdata + ior regb,pdata + iand temp,pdata + isub rega,null + nbranch assert,zero + nrtn zero + fetch 1,mem_l2cap_pending_count + increase -1,pdata + store 1,mem_l2cap_pending_count + ifetch 6,regc + store 6,mem_l2cap_temp_ch_info + branch l2cap_send_connect_res_succ + +l2cap_send_conn_res_refused_no_resources: + arg L2CAP_CONNECTION_REFUSED_NO_RESOURCES,regd + arg 0,rege + branch l2cap_send_connect_res + +//regc:ptr to l2cap_channel_context +l2cap_send_connect_res_succ: + bpatchx patch23_4,mem_patch23 + fetch 1,mem_l2cap_prepare_confreq_count + increase 1,pdata + store 1,mem_l2cap_prepare_confreq_count + increase offset_lc_state,regc + ifetch 1,regc + set1 L2CAP_CHANNEL_STATE_CONN_RES,pdata + istore 1,regc + arg L2CAP_CONNECTION_SUCCESSFUL,regd + arg 0,rege + branch l2cap_send_connect_res +l2cap_send_connect_res_pending: + bpatchx patch23_5,mem_patch23 + call l2cap_get_empty_pending_info + fetch 1,mem_l2cap_signal_ident + istore 1,contw + copy clkn_bt,pdata + istore 4,contw + istorer regc,2,contw + arg L2CAP_CONNECTION_PENDING,regd + arg L2CAP_authorization_pending,rege + fetch 1,mem_l2cap_pending_count + increase 1,pdata + store 1,mem_l2cap_pending_count +l2cap_send_connect_res: + bpatchx patch23_6,mem_patch23 + arg 12,rega + call l2cap_malloc_signal_channel + setarg signal_connect_rsp + istore 1,contw + fetch 1,mem_l2cap_signal_ident + istore 1,contw + setarg 8 + istore 2,contw + fetch 2,mem_l2cap_temp_local_cid + istore 2,contw + fetch 2,mem_l2cap_temp_remote_cid + istore 2,contw + istorer regd,2,contw + istorer rege,2,contw + rtn + +l2cap_proc_signal_connect_rsp: + ifetch 1,contr + store 1,mem_l2cap_signal_ident + increase 2,contr + ifetch 2,contr + store 2,mem_l2cap_temp_remote_cid + ifetcht 2,contr + storet 2,mem_l2cap_temp_local_cid + bpatchx patch23_7,mem_patch23 + ifetch 2,contr + beq L2CAP_CONNECTION_SUCCESSFUL,l2cap_proc_signal_connect_rsp_success + rtneq L2CAP_CONNECTION_PENDING + branch l2cap_proc_signal_connect_rsp_refused + +l2cap_proc_signal_connect_rsp_success: + fetchr rega,2,mem_l2cap_temp_local_cid + call l2cap_get_channel_info_by_local_cid + nbranch assert,user + add regc,offset_lc_remote_cid,contw + fetch 2,mem_l2cap_temp_remote_cid + istore 2,contw + increase offset_lc_state,regc + ifetch 1,regc + set1 L2CAP_CHANNEL_STATE_CONN_RES,pdata + istore 1,regc + fetch 1,mem_l2cap_prepare_confreq_count + increase 1,pdata + store 1,mem_l2cap_prepare_confreq_count + rtn + +l2cap_proc_signal_connect_rsp_refused: + fetchr rega,2,mem_l2cap_temp_local_cid + call l2cap_get_channel_info_by_local_cid + ifetch 6,regc + store 6,mem_l2cap_temp_ch_psm + fetchr rega,2,mem_l2cap_temp_local_cid + call l2cap_destory_channel + call l2cap_clear_server_ptr + branch upper_reset_sm + +l2cap_proc_signal_config_req: + ifetch 1,contr + store 1,mem_l2cap_signal_ident + increase 2,contr + ifetch 2,contr + store 2,mem_l2cap_temp_local_cid + copy pdata,rega + call l2cap_get_channel_info_by_local_cid + ifetch 6,regc + store 6,mem_l2cap_temp_ch_psm + nbranch assert,user + increase offset_lc_state,regc + ifetch 1,regc + set1 L2CAP_CHANNEL_STATE_RCV_CFG_REQ,pdata + set1 L2CAP_CHANNEL_STATE_SND_CFG_RES,pdata + istore 1,regc +l2cap_proc_signal_config_res: + bpatchx patch24_0,mem_patch24 + arg 10,rega + call l2cap_malloc_signal_channel + setarg signal_config_rsp + istore 1,contw + fetch 1,mem_l2cap_signal_ident + istore 1,contw + setarg 6 + istore 2,contw + fetch 2,mem_l2cap_temp_remote_cid + istore 2,contw + setarg 0 + istore 2,contw + setarg L2CAP_CONNECTION_SUCCESSFUL + istore 2,contw + rtn + +l2cap_proc_signal_config_rsp: + ifetch 1,contr + store 1,mem_l2cap_signal_ident + increase 2,contr + ifetch 2,contr + store 2,mem_l2cap_temp_local_cid + copy pdata,rega + call l2cap_get_channel_info_by_local_cid + increase offset_lc_state,regc + ifetch 1,regc + set1 L2CAP_CHANNEL_STATE_RCV_CFG_RES,pdata + istore 1,regc + rtn + +l2cap_prepare_send_config_req: + bpatchx patch24_1,mem_patch24 + fetch 1,mem_l2cap_prepare_confreq_count + rtn blank + call l2cap_malloc_is_fifo_full + nrtn blank + arg 0,rega + set1 L2CAP_CHANNEL_STATE_CONN_REQ,rega + set1 L2CAP_CHANNEL_STATE_CONN_RES,rega + arg 0,regb + set1 L2CAP_CHANNEL_STATE_SND_CFG_REQ,regb + call l2cap_check_channel_state + nrtn user + + increase 1,contr + copy contr,contw + ifetch 1,contr + set1 L2CAP_CHANNEL_STATE_SND_CFG_REQ,pdata + istore 1,contw + + fetch 1,mem_l2cap_prepare_confreq_count + increase -1,pdata + store 1,mem_l2cap_prepare_confreq_count + + ifetch 6,regc + store 6,mem_l2cap_temp_ch_info + call l2cap_get_req_id + call l2cap_load_channel_param +l2cap_send_config_req: + bpatchx patch24_2,mem_patch24 + arg 12,rega + call l2cap_malloc_signal_channel + setarg signal_config_req + istore 1,contw + fetch 1,mem_ML2CAP_comm_id + istore 1,contw + setarg 8 + istore 2,contw + fetch 2,mem_l2cap_temp_remote_cid + istore 2,contw + setarg 0 + istore 2,contw + setarg 1 + istore 1,contw + setarg 2 + istore 1,contw + istorer rege,2,contw + rtn + +l2cap_load_channel_param: + bpatchx patch24_3,mem_patch24 + fetch 1,mem_l2cap_temp_ch_psm + arg L2CAP_config_MTU_SDP,rege + rtneq PSM_SDP + arg L2CAP_config_MTU_RFCOMM,rege + rtneq PSM_RFCOMM + arg L2CAP_config_MTU_MEDIA,rege + rtneq PSM_AVDTP + arg L2CP_config_MTU_OTHER,rege + rtn + +l2cap_proc_signal_disconnect_req: + ifetch 1,contr + store 1,mem_l2cap_signal_ident + increase 2,contr + ifetch 2,contr + store 2,mem_l2cap_temp_local_cid + copy pdata,rega + call l2cap_get_channel_info_by_local_cid + ifetch 6,regc + store 6,mem_l2cap_temp_ch_psm + copy regc,regd + nbranch check_51cmd_disconnect,user + call l2cap_send_signal_disconnect_res + fetchr rega,2,mem_l2cap_temp_local_cid + call l2cap_destory_channel + copy regd,regc + branch l2cap_clear_server_ptr +l2cap_send_signal_disconnect_res: + arg 8,rega + call l2cap_malloc_signal_channel + setarg signal_disconnect_rsp + istore 1,contw + fetch 1,mem_l2cap_signal_ident + istore 1,contw + setarg 4 + istore 2,contw + fetch 2,mem_l2cap_temp_local_cid + istore 2,contw + fetch 2,mem_l2cap_temp_remote_cid + istore 2,contw + rtn + +l2cap_proc_signal_disconnect_rsp: + ifetch 1,contr + store 1,mem_l2cap_signal_ident + increase 2,contr + ifetch 2,contr + store 2,mem_l2cap_temp_local_cid + ifetch 2,contr + copy pdata,rega + branch l2cap_destory_channel + +/* received an echo request from remote BD. Will echo the 1st 1 byte back, */ +l2cap_proc_signal_echo_req: +l2cap_send_signal_echo_rsp: + ifetch 1,contr + store 1,mem_l2cap_signal_ident + arg 4,rega + call l2cap_malloc_signal_channel + setarg signal_echo_rsp + istore 1,contw + fetch 1,mem_l2cap_signal_ident + istore 3,contw + rtn + +l2cap_proc_signal_echo_rsp: + rtn + +l2cap_proc_signal_info_rsp: + rtn + + +//l2cap command id, 0 is not allowed +l2cap_get_req_id: + bpatchx patch24_4,mem_patch24 + fetch 1,mem_ML2CAP_comm_id + increase 1,pdata + bne 0,l2cap_get_req_id_ok + increase 1,pdata +l2cap_get_req_id_ok: + store 1,mem_ML2CAP_comm_id + rtn + + +/*********************************************************/ +//char* malloc(short len) +//input: rega -> len +//rtn: regb -> pbuff;return from pdata +//val: queue -> i +//val: timeup -> buff_cnt +/*********************************************************/ +l2cap_malloc: + bpatchx patch24_5,mem_patch24 + arg 0,regb + call l2cap_malloc_is_fifo_full + nbranch assert,blank//assert when fifo full + call l2cap_malloc_get_full_map + //sub temp,0xff,null + //branch assert,zero +ifdef DEBUG_MALLOC + call l2cap_malloc_log_get_ptr + copy rega,pdata + istore 2,contw + sub pdata,1024,null + branch assert,positive + branch assert,blank +endif + arg mem_tx_buff0,regb//pbuff = buff0; + arg 0,queue // i = 0; +l2cap_malloc_loop: + fetcht 1,mem_used_map + qisolate1 temp + branch l2cap_malloc_next,true//if(1 == (used_map & (1 << i)))goto next; + call l2cap_malloc_enough + sub timeup,0,null// (0 - timeup) + branch l2cap_malloc_next,positive//if(buff_cnt <= 0)goto next; + call l2cap_malloc_into_fifo + branch l2cap_malloc_rtn//return (pbuff); +l2cap_malloc_next: + increase 128,regb//pbuff += BUFF_SIZE;//point to next buff + increase 1,queue + setarg 8//BUFF_MAX_COUNT + isub queue,null //BUFF_MAX_COUNT - i + branch l2cap_malloc_loop,positive//while(i < buff_max_count) + arg 0,regb//return NULL +l2cap_malloc_rtn: + call l2cap_malloc_get_full_map +ifdef DEBUG_MALLOC + call l2cap_malloc_log_get_ptr + copy regb,pdata + istore 2,contw +endif + copy regb,pdata + branch assert,blank + rtn//return pointer via pdata + +/*********************************************************/ +//void* l2cap_malloc_fifo_out(void) +//output:len -> temp +//output:ptr ->pdata +//only get ptr,not free +/*********************************************************/ +l2cap_malloc_fifo_out: + bpatchx patch24_6,mem_patch24 + call l2cap_malloc_fifo_get_first_ptr + increase 1,contr + ifetch 2,contr //ptr ->pdata + rtn + +/*********************************************************/ +//void free_first_buff_in_fifo(void) +//only free the first one +/*********************************************************/ +l2cap_malloc_free: + bpatchx patch24_7,mem_patch24 + call l2cap_malloc_fifo_get_first_ptr + copy contr,contw + copy contr,temp + setarg 0 + istore 3,contw +ifdef DEBUG_MALLOC + call l2cap_malloc_log_get_ptr + setarg 0xaa + istore 1,contw + istoret 1,contw +endif + rtn +/*********************************************************/ +//void l2cap_malloc_discard(void) +//discard the latest malloc +/*********************************************************/ +l2cap_malloc_discard: + bpatchx patch25_0,mem_patch25 + call l2cap_malloc_is_fifo_empty + branch assert,blank + fetch 3,mem_tx_fifo2 + store 3,mem_tx_fifo3 + fetch 3,mem_tx_fifo1 + store 3,mem_tx_fifo2 + fetch 3,mem_tx_fifo0 + store 3,mem_tx_fifo1 + rtn +/*********************************************************/ +//bool fifo_is_full(void) +//blank == 1: not full +//blank == 0: full +/*********************************************************/ +l2cap_malloc_is_fifo_full: + bpatchx patch25_1,mem_patch25 + fetch 1,mem_used_map + rtneq 0xff + fetch 3,mem_tx_fifo0 + rtn +/*********************************************************/ +//bool fifo_nearly_full(void) +//blank == 1: nearly full +//blank == 0: not nearly full +/*********************************************************/ +l2cap_malloc_is_fifo_nearly_full: + fetch 3,mem_tx_fifo1 + rtn +/*********************************************************/ +//bool fifo_is_empty(void) +//blank == 1: empty +//blank == 0: not empty +/*********************************************************/ +l2cap_malloc_is_fifo_empty: + fetch 3,mem_tx_fifo3 + rtn +/*********************************************************/ +//char* l2cap_malloc_fifo_get_first_ptr(void) +//output:contr -->ptr +/*********************************************************/ +l2cap_malloc_fifo_get_first_ptr: + bpatchx patch25_2,mem_patch25 + call l2cap_malloc_is_fifo_empty + branch assert,blank // fifo is empty + arg mem_tx_fifo0,contr +ifdef DEBUG_MALLOC + arg 5,loopcnt +l2cap_malloc_free_loop: + increase -1,loopcnt + copy loopcnt,pdata + branch assert,blank +else +l2cap_malloc_free_loop: +endif + ifetch 3,contr + branch l2cap_malloc_free_loop,blank + increase -3,contr + rtn + +/*********************************************************/ +//char* l2cap_malloc_get_full_map(void) +//output:mem_used_map -->full_map +//add all maps into one +/*********************************************************/ +l2cap_malloc_get_full_map: + bpatchx patch25_3,mem_patch25 + arg 4,loopcnt + arg mem_tx_fifo0_map,contr + arg 0,temp +l2cap_malloc_get_full_map_loop: + ifetch 3,contr + and pdata,0xff,pdata + ior temp,temp + loop l2cap_malloc_get_full_map_loop + storet 1,mem_used_map + rtn +/*********************************************************/ +//void buff_into_fifo(char buff_index, char buff_cnt, short len) +//input: rega -> len +//input: regc -> buff_index +//input: timeup -> buff_cnt +//val:temp -> (fifo->map) +/*********************************************************/ +l2cap_malloc_into_fifo: + bpatchx patch25_4,mem_patch25 + call l2cap_malloc_is_fifo_full + nbranch assert,blank //fifo full + call l2cap_malloc_is_fifo_empty + branch l2cap_malloc_into_fifo_no_push,blank//fifo empty, no need to push + fetch 3,mem_tx_fifo1 + store 3,mem_tx_fifo0 + ifetch 3,contr//mem_tx_fifo2 + istore 3,contw//mem_tx_fifo1 + ifetch 3,contr//mem_tx_fifo3 + istore 3,contw//mem_tx_fifo2 + setarg 0 + istore 3,contw//mem_tx_fifo3 +l2cap_malloc_into_fifo_no_push: + arg 0,temp + copy timeup,pdata + iadd queue,pdata +l2cap_malloc_into_fifo_loop: + qset1 temp//fifo->map |= 1 << i; + increase 1,queue + isub queue,null + nbranch l2cap_malloc_into_fifo_loop,zero + //map in temp + lshift8 regb,pdata + ior temp,pdata + store 3,mem_tx_fifo3 + rtn + +/*********************************************************/ +//char is_size_enough(char buff_index, short len) +//input: rega -> len +//input: queue -> buff_index +//rtn: timeup -> buff_cnt +//val: max_size_fom_buff_index -> temp +//val: i -> loopcnt +/*********************************************************/ +l2cap_malloc_enough: + bpatchx patch25_5,mem_patch25 + call l2cap_malloc_get_full_map + copy queue,regc//restore buff_index to regc + arg 0,temp + arg 0,timeup//default return val + //increase 1,queue +l2cap_malloc_enough_loop: + copy queue,pdata + beq 8,l2cap_malloc_enough_end + fetch 1,mem_used_map + qisolate1 pdata + branch l2cap_malloc_enough_end,true + increase 128,temp + increase 1,queue + copy rega,pdata + isub temp,null + branch l2cap_malloc_enough_end,zero//(max_size_fom_buff_index == len) + branch l2cap_malloc_enough_loop,positive//(max_size_fom_buff_index < len) +l2cap_malloc_enough_end: + copy temp,pdata + isub rega,null + nbranch l2cap_malloc_enough_rtn,positive// max_size_fom_buff_index - len > 0 + copy queue,pdata//i + copy regc,temp//buff_index + isub temp,timeup//return (i - buff_index) +l2cap_malloc_enough_rtn: + copy regc,queue//restore buff_index to queue + rtn + +ifdef DEBUG_MALLOC +l2cap_malloc_log_get_ptr: + fetch 2,mem_tx_malloc_log + increase 2,pdata + store 2,mem_tx_malloc_log + sub pdata,62,null + nbranch l2cap_malloc_log_clean,positive + increase -2,pdata + iadd contw,contw + rtn +l2cap_malloc_log_clean: + jam 0x00,mem_tx_malloc_log + branch l2cap_malloc_log_get_ptr +endif + +l2cap_malloc_signal_channel: + bpatchx patch25_6,mem_patch25 + call l2cap_malloc + istorer rega,2,pdata + setarg 1 + istore 2,contw + rtn + +//regd:ptr to l2cap context +//input rega length +l2cap_malloc_server_channel: + bpatchx patch25_7,mem_patch25 + call l2cap_malloc + istorer rega,2,pdata + add regd,offset_lc_remote_cid,regb + ifetcht 2,regb + istoret 2,contw + rtn + + +l2cap_malloc_sdp_req: + bpatchx patch26_0,mem_patch26 + fetch 2,mem_sdp_transactionid_local + increase 1,pdata + store 2,mem_sdp_transactionid_local + branch l2cap_malloc_server_channel + +l2cap_malloc_sdp_channel: + bpatchx patch26_1,mem_patch26 + arg SDP_MALLOC_SIZE,rega + call l2cap_malloc_server_channel + store 2,mem_sdp_tx_buff_ptr + increase 4,pdata + store 2,mem_sdp_tx_payload_ptr + setarg 0 + store 2,mem_sdp_tx_pkt_length + rtn + +l2cap_get_sdp_tx_buff: + fetch 2,mem_sdp_tx_buff_ptr + branch l2cap_util_pdata_to_contw + +l2cap_get_sdp_tx_payload: + fetch 2,mem_sdp_tx_payload_ptr + branch l2cap_util_pdata_to_contw + +l2cap_util_pdata_to_contw: + branch assert,blank + copy pdata,contw + rtn + +//regd:psm +l2cap_send_server_conn: + bpatchx patch26_2,mem_patch26 + setarg 0 + store 6,mem_l2cap_temp_ch_info + call l2cap_get_req_id + arg 8,rega + call l2cap_malloc_signal_channel + setarg signal_connect_req + istore 1,contw + fetch 1,mem_ML2CAP_comm_id + istore 1,contw + setarg 0x0004 + istore 2,contw + istorer regd,2,contw + call l2cap_get_random_local_cid + istore 2,contw + store 2,mem_l2cap_temp_local_cid + fetch 1,mem_l2cap_temp_ch_state + set1 L2CAP_CHANNEL_STATE_CONN_REQ + store 1,mem_l2cap_temp_ch_state + storer regd,1,mem_l2cap_temp_ch_psm + call l2cap_create_empty_channel + fetch 6,mem_l2cap_temp_ch_info + istore 6,regc + rtn + +//regd:l2cap channel ptr +l2cap_send_server_disconnct: + bpatchx patch26_3,mem_patch26 + call l2cap_get_req_id + arg 8,rega + call l2cap_malloc_signal_channel + setarg signal_disconnect_req + istore 1,contw + fetch 1,mem_ML2CAP_comm_id + istore 1,contw + setarg 0x0004 + istore 2,contw + add regd,offset_lc_remote_cid,contr + ifetch 2,contr + istore 2,contw + add regd,offset_lc_local_cid,contr + ifetch 2,contr + istore 2,contw + rtn + + + + + +l2cap_create_empty_channel: + bpatchx patch26_4,mem_patch26 + arg L2CAP_CHANNEL_COUNT,temp + arg mem_l2cap_ch_info,contr +l2cap_create_channel_loop: + ifetch 6,contr + branch l2cap_create_channel_rtn,blank + increase -1,temp + nbranch l2cap_create_channel_loop,zero + branch assert //no free channel +l2cap_create_channel_rtn: + add contr,-6,regc + fetch 1,mem_l2cap_active_ch_count + increase 1,pdata + store 1,mem_l2cap_active_ch_count + rtn + +//rega: local channel +l2cap_destory_channel: + bpatchx patch26_5,mem_patch26 + arg L2CAP_CHANNEL_COUNT,temp + arg mem_l2cap_ch_info,contr +l2cap_destory_channel_loop: + ifetch 2,contr + ifetch 2,contr + increase 2,contr + isub rega,null + branch l2cap_destory_channel_rtn,zero + increase -1,temp + nbranch l2cap_destory_channel_loop,zero + rtn +l2cap_destory_channel_rtn: + add contr,-6,contw + setarg 0 + istore 6,contw + fetch 1,mem_l2cap_active_ch_count + increase -1,pdata + store 1,mem_l2cap_active_ch_count + rtn + +//rega:prepare channel state; regb:this step +l2cap_check_channel_state: + bpatchx patch26_6,mem_patch26 + arg L2CAP_CHANNEL_COUNT,temp + arg mem_l2cap_ch_info,contr +l2cap_check_channel_loop: + increase 1,contr + ifetch 1,contr + beq 0,l2cap_check_channel_loop_fast_loop + copy pdata,regc + increase 4,contr + copy rega,pdata + ior regb,pdata + iand regc,pdata + isub rega,null + branch l2cap_check_channel_rtn,zero +l2cap_check_channel_next: + increase -1,temp + nbranch l2cap_check_channel_loop,zero + branch disable_user +l2cap_check_channel_rtn: + increase -6,contr + copy contr,regc + branch enable_user +l2cap_check_channel_loop_fast_loop: + increase 4,contr + branch l2cap_check_channel_next + +//rega:local cid +l2cap_get_channel_info_by_local_cid: + bpatchx patch26_7,mem_patch26 + arg L2CAP_CHANNEL_COUNT,temp + arg mem_l2cap_ch_info,contr +l2cap_get_channel_info_local_loop: + increase 2,contr + ifetch 2,contr + increase 2,contr + isub rega,null + branch l2cap_get_channel_info_rtn,zero + increase -1,temp + nbranch l2cap_get_channel_info_local_loop,zero + branch disable_user +l2cap_get_channel_info_rtn: + increase -6,contr + copy contr,regc + branch enable_user + +//rega:local cid +l2cap_get_channel_info_by_remote_cid: + bpatchx patch27_0,mem_patch27 + arg L2CAP_CHANNEL_COUNT,temp + arg mem_l2cap_ch_info,contr +l2cap_get_channel_info_remote_loop: + increase 4,contr + ifetch 2,contr + isub rega,null + branch l2cap_get_channel_info_rtn,zero + increase -1,temp + nbranch l2cap_get_channel_info_remote_loop,zero + branch disable_user + + +//rega:psm +l2cap_get_channel_info_by_psm: + arg L2CAP_CHANNEL_COUNT,temp + arg mem_l2cap_ch_info,contr +l2cap_get_channel_info_by_psm_loop: + ifetch 1,contr + increase 5,contr + isub rega,null + branch l2cap_get_channel_info_rtn,zero + increase -1,temp + nbranch l2cap_get_channel_info_by_psm_loop,zero + branch disable_user + + +l2cap_check_empty_channel_info: + fetch 1,mem_l2cap_active_ch_count + beq 0,enable_user + branch disable_user + +l2cap_get_random_local_cid: + random rega + and rega,0x1f,rega + xor rega,0x40,rega + call l2cap_get_channel_info_by_local_cid + branch l2cap_get_random_local_cid,user + copy rega,pdata + rtn + +l2cap_get_tws_fix_local_cid: + fetchr rega,2,mem_l2cap_temp_remote_cid +l2cap_get_tws_fix_local_cid_loop: + increase 1,rega + call l2cap_get_channel_info_by_local_cid + branch l2cap_get_tws_fix_local_cid_loop,user + copy rega,pdata + rtn + +l2cap_get_empty_pending_info: + fetch 7,mem_l2cap_pending_info + branch l2cap_get_empty_pending_info_rtn,blank + ifetch 7,contr + branch l2cap_get_empty_pending_info_rtn,blank + ifetch 7,contr + branch l2cap_get_empty_pending_info_rtn,blank + branch disable_user +l2cap_get_empty_pending_info_rtn: + add contr,-7,contw + branch enable_user + +l2cap_get_active_pending_info: + fetch 7,mem_l2cap_pending_info + nbranch l2cap_get_active_pending_info_rtn,blank + ifetch 7,contr + nbranch l2cap_get_active_pending_info_rtn,blank + ifetch 7,contr + nbranch l2cap_get_active_pending_info_rtn,blank + branch disable_user +l2cap_get_active_pending_info_rtn: + increase -7,contr + branch enable_user + +l2cap_clear_server_ptr: + bpatchx patch27_1,mem_patch27 + fetch 1,mem_l2cap_temp_ch_psm + beq PSM_RFCOMM,l2cap_clear_rfcomm_ptr + beq PSM_AVCTP,l2cap_clear_avr_ptr + beq PSM_AVDTP,l2cap_clear_a2dp_ptr + rtn + +l2cap_clear_rfcomm_ptr: + setarg 0 + store 2,mem_rfc_l2capch_ptr + branch headset_clear_parms + +l2cap_clear_avr_ptr: + setarg 0 + store 2,mem_avr_l2capch_ptr + rtn +l2cap_clear_a2dp_ptr: + fetch 2,mem_avdtpsignal_l2capch_ptr + isub regc,null + branch l2cap_clear_a2dp_singal_ptr,zero + fetch 2,mem_avdtpmedia_l2capch_ptr + isub regc,null + branch l2cap_clear_a2dp_media_ptr,zero + branch assert +l2cap_clear_a2dp_singal_ptr: + setarg 0 + store 2,mem_avdtpsignal_l2capch_ptr + rtn +l2cap_clear_a2dp_media_ptr: + setarg 0 + store 2,mem_avdtpmedia_l2capch_ptr + rtn + + + +l2cap_save_server_ptr: + bpatchx patch27_2,mem_patch27 + fetch 1,mem_l2cap_temp_ch_psm + beq PSM_RFCOMM,l2cap_save_rfcomm_ptr + beq PSM_AVCTP,l2cap_save_avr_ptr + beq PSM_AVDTP,l2cap_save_a2dp_ptr + rtn +l2cap_save_rfcomm_ptr: + storer regc,2,mem_rfc_l2capch_ptr + rtn +l2cap_save_avr_ptr: + storer regc,2,mem_avr_l2capch_ptr + jam 0,mem_hp_avctp_timer + rtn +l2cap_save_a2dp_ptr: + jam 0,mem_a2dp_reconnct_delay_timer + fetch 2,mem_avdtpsignal_l2capch_ptr + nbranch l2cap_save_a2dp_media_ptr,blank + storer regc,2,mem_avdtpsignal_l2capch_ptr + fetch 1,mem_l2cap_temp_local_cid + store 2,mem_avdtp_signal + rtn +l2cap_save_a2dp_media_ptr: + storer regc,2,mem_avdtpmedia_l2capch_ptr + fetch 1,mem_l2cap_temp_local_cid + store 2,mem_avdtp_media + rtn + +l2cap_clear_nochannel_watchdog: + jam 0,mem_l2cap_channel_disconnect_timer + rtn + +l2cap_trigger_nochannel_waicthdog: + fetch 1,mem_l2cap_channel_disconnect_timer + rtn blank + jam 15,mem_l2cap_channel_disconnect_timer + rtn + + Index: tag/Soft/Librarier/bt_rom/program/le.prog =================================================================== --- /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/le.prog (nonexistent) +++ /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/le.prog (working copy) @@ -0,0 +1,1592 @@ +ifdef COMPILE_LE +//******************************************// +//*************LE INIT ****************// +//******************************************// + + +le_init_conn: + bpatchx patch27_3,mem_patch27 + disable wake + call le_pairing_mode_init + jam 1,mem_app_state + jam 1,mem_le_conn_handle + jam 3,mem_le_state + jam 1,mem_le_arq + setarg -1 + store 2,mem_le_event_count + force 0,pdata + store 1,mem_le_conn_sm + store 1,mem_le_ch + store 1,mem_le_op + store 3,mem_sniff_rcv + store 3,mem_sniff_lost + store 5,mem_le_pcnt_tx + set1 39,pdata + store 5,mem_le_pcnt_rx + jam 1,mem_le_txheader + jam 0,mem_le_txlen + branch le_supervision_flush + +le_init_master: + bpatchx patch27_4,mem_patch27 + enable master + jam lemode_master,mem_le_mode + jam 1,mem_le_att_handle + jam 1,mem_le_search_handle_start + setarg 0xffff + store 2,mem_le_search_handle_end + force 0,pdata + store 5,mem_le_pcnt_rx + set1 39,pdata + store 5,mem_le_pcnt_tx + branch le_init_conn + + +le_init_slave: + bpatchx patch27_5,mem_patch27 + disable master + jam lemode_slave,mem_le_mode + jam 0,mem_le_adv_enable + jam 0,mem_lpm_current_mult + branch le_init_conn + + + +//******************************************// +//*************LE main process*********// +//******************************************// +le_dispatch: + call le_enable + call le_scan + call le_adv + branch le_disable + +le_conn_dispatch: + bpatchx patch27_6,mem_patch27 + call le_enable + call app_process_ble + fetch 1,mem_le_mode + beq lemode_master,le_master_dispatch + branch le_slave_dispatch + +//******************************************// +//***********LE master process*********// +//******************************************// + +le_master_dispatch: + enable master + call le_supervision_update + branch le_master_disconn,positive + call check_ble_disabled + call le_setup + call le_prepare_tx + disable match + call le_transmit_receive_sifs + nrtn match + fetch 1,mem_le_conn_rcv + increase 1,pdata + store 1,mem_le_conn_rcv + call le_acknowledge + call le_conn_sm_master + disable master + rtn + +le_master_disconn: + call le_disconnect + disable master + rtn + +//******************************************// +//***********LE slave process***********// +//******************************************// +le_slave_dispatch: +ifdef SECURE_CONNECTION + call sp_calc_sequence_256 + call le_secure_connect_sm +endif + disable attempt + call le_supervision_update + branch le_slave_disconn,positive + call check_ble_disabled + call le_setup + call le_receive_slave + nbranch le_slave_unsync,match +le_slave_match: + bpatchx patch27_7,mem_patch27 + call le_got_first_packet + call le_acknowledge + call le_prepare_tx + call le_transmit_norx + call le_parse + call le_check_md + branch le_slave_more_data,user +le_slave_cont: + bpatchx patch28_0,mem_patch28 + call le_pairing_sm + call check_51cmd + fetch 1,mem_le_op + bbit1 op_disconn,le_slave_disconn +le_slave_unsync: + bpatchx patch28_1,mem_patch28 +// call le_savelist + call le_lpm_set_mult + call le_update_channel_map + call le_update_param + branch calc_clke_offset + +le_check_md: + disable user + bmark1 mark_ble_rx_md,enable_user + bmark1 mark_ble_tx_md,enable_user + rtn + + +le_slave_more_data: + enable attempt + call le_transmit_receive_sifs_notx + branch le_slave_match,match + branch le_slave_cont + +le_slave_disconn: + bpatchx patch28_2,mem_patch28 + call le_att_destroy_notify_pool + //fall through +le_disconnect: + call le_clear_connection_info + call app_disconn_reason_collect_ble +ifdef SECURE_CONNECTION + call sp_initialize_256 +endif + jam BT_EVT_LE_DISCONNECTED,mem_fifo_temp + branch ui_ipc_send_event + +le_clear_connection_info: + jam 0,mem_le_conn_handle + jam lemode_idle,mem_le_mode + jam 0,mem_le_state + jam 0,mem_app_state + jam FLAG_LE_PAIRING_NULL,mem_le_pairing_state + jam FLAG_LE_ENC_NULL,mem_le_enc_state + rtn + +le_got_first_packet: + fetch 1,mem_le_conn_rcv + increase 1,pdata + store 1,mem_le_conn_rcv + fetch 1,mem_le_state + rtnbit1 lestate_got_first_packet + set1 lestate_got_first_packet + store 1,mem_le_state + setarg 0 + store 4,mem_le_transmit_window + rtn + +le_enable: + bpatchx patch28_3,mem_patch28 + enable le + jam 7,rfen_ulp /* enable ulp */ + branch check_ble_disabled + +le_disable: + bpatchx patch28_4,mem_patch28 + disable le + jam 3,rfen_ulp + arg 0,stop_watch + rtn + +le_prep: + bpatchx patch28_5,mem_patch28 + disable enable_crc + disable enable_white + fetch 3,mem_le_crcinit + iforce crc24_init + fetch 1,mem_le_ch_mapped + reverse pdata,temp + set1 1,temp + rshift temp,white_init + rtn + + +lerx_setfreq: + bpatchx patch28_6,mem_patch28 + call le_setfreq + call set_freq_rx + fetch 2,mem_param_pll_setup + call sleep + branch rf_rx_enable + +letx_setfreq: + branch rf_tx_enable,match + call le_setfreq + branch set_freq_tx +le_setfreq: + call set_sync_on + fetch 1, mem_le_testtype + nbranch le_ctf_test,blank + fetch 1,mem_le_ch_mapped + sub pdata,36,null + branch le_ctf_normal,positive + force 0,temp + rtneq 37 + force 24,temp + rtneq 38 + force 78,temp + rtn + +le_ctf_normal: + sub pdata,10,null + branch le_ctf_low,positive + increase 1,pdata + +le_ctf_low: + lshift pdata,pdata + add pdata,2,temp + rtn + +le_ctf_test: + fetch 1,mem_le_ch_mapped + lshift pdata,temp + rtn + +le_sca_map: + arg 500,temp + rtn blank + arg 250,temp + rtneq 1 + arg 150,temp + rtneq 2 + arg 100,temp + rtneq 3 + arg 75,temp + rtneq 4 + arg 50,temp + rtneq 5 + arg 40,temp + rtneq 6 + arg 20,temp + rtn + + + +le_adv_access: + setarg 0x8e89be + lshift8 pdata,pdata + or_into 0xd6,pdata + iforce access + setarg 0x555555 + store 3,mem_le_crcinit + rtn + +le_setup: + bpatchx patch28_7,mem_patch28 + enable swfine + fetch 4,mem_le_access + iforce access + call le_map_channel + setarg 0x200 + branch le_setup_master,master + fetch 2,mem_le_receive_window + rshift pdata,pdata +le_setup_master: + arg param_rx_ahead,temp + iadd temp,pdata + call ahead_window + deposit clke + rtn + +le_next_adv_channel: + fetch 1,mem_le_ch_mapped + increase 1,pdata + store 1,mem_le_ch_mapped + rtnne 40 + jam 37,mem_le_ch_mapped + rtn + +le_context_nexthop: + bpatchx patch29_0,mem_patch29 + add rega,coffset_mode,contr + ifetch 1,contr + rtnbit0 mode_le + add rega,coffset_le_event_cnt,contw + ifetch 2,contw + increase 1,pdata + istore 2,contw + add rega,coffset_le_hop,contr + ifetch 1,contr + add rega,coffset_le_ch,contw + ifetcht 1,contw + iadd temp,pdata + sub pdata,36,null + branch le_nexthop_nowrap,positive + increase -37,pdata +le_nexthop_nowrap: + istore 1,contw + rtn + + +le_calc_channel_map: + bpatchx patch29_1,mem_patch29 + fetch 5,mem_le_channel_map + force 0,temp + force 37,loopcnt +le_count_channels_loop: + bbit0 0,le_count_channels_notused + increase 1,temp +le_count_channels_notused: + rshift pdata,pdata + loop le_count_channels_loop + add temp,-1,pdata + store 1,mem_le_channels + rtn + +le_map_channel: + fetch 1,mem_le_ch + iforce queue + fetcht 5,mem_le_channel_map + qisolate1 temp + branch le_map_channel_end,true +le_map_channel_next: + fetch 1,mem_le_channels + isub queue,pdata + branch le_map_channel_cont,positive + sub pdata,-1,queue + branch le_map_channel_next +le_map_channel_cont: + copy queue,loopcnt + force 0,queue +le_map_channel_loop: + qisolate1 temp + branch le_map_channel_skip,true + increase 1,loopcnt +le_map_channel_skip: + deposit loopcnt + branch le_map_channel_end,blank + increase 1,queue + increase -1,loopcnt + branch le_map_channel_loop +le_map_channel_end: + deposit queue + store 1,mem_le_ch_mapped + rtn + + +le_wait_tx: + branch le_wait_master,master + until null,timeout + rtn + +le_wait_master: + arg 0xea0,timeup + until clkn_rt,meet + rtn + +le_receive_adv: + bpatchx patch29_2,mem_patch29 + disable swfine + fetchr timeup,2,mem_le_scan_window + branch le_receive_packet + + +le_receive_slave: + bpatchx patch29_3,mem_patch29 + enable swfine + fetch 2,mem_le_receive_window + fetcht 4,mem_le_transmit_window + iadd temp,timeup +le_receive_packet: + call lerx_setfreq +le_receive_rxon: + call le_prep + disable match + enable decode_fec0 + enable is_rx + disable is_tx + copy timeup,stop_watch + correlate null,timeout + branch le_receive_on_attempt,attempt + copy clke,temp + storet 6,mem_sync_clke +le_receive_on_attempt: + nbranch end_of_packet,sync + branch le_receive_skip,attempt + arg param_clke_cal_le,clke_rt + copy bt_clk,clke_bt + fetch 1,mem_le_state + bbit0 lestate_got_first_packet,le_receive_skip + call lpm_adjust_clk,wake +le_receive_skip: + call save_rssi + enable enable_white + enable enable_crc + parse demod,bucket,8 + rshift3 pwindow,pdata + store 1,mem_le_rxbuf + parse demod,bucket,8 + rshift3 pwindow,pdata + istore 1,contw + and pdata,0x3f,loopcnt + branch lerx_nopayload,zero + +lerx_loop: + parse demod,bucket,8 + rshift3 pwindow,pdata + istore 1,contw + loop lerx_loop + +lerx_nopayload: + bpatchx patch29_4,mem_patch29 + parse demod,bucket,24 + enable swfine + arg param_sifs,stop_watch // start SIFS timer after last bit of crc + rshift32 pdata,pdata + rshift16 pdata,pdata + istore 3,contw + branch end_of_packet,crc_failed + enable match + fetch 1,mem_sfreq_enable + nbranch lerx_nopayload_skip_write_freq,blank + fetch 1,mem_last_freq + add pdata,0,rega + call rf_write_freq /* set frequency to tx mode freq */ +lerx_nopayload_skip_write_freq: + disable decode_fec0 + branch set_sync_on + +le_transmit_receive_sifs: + bpatchx patch29_5,mem_patch29 + call le_transmit +le_transmit_receive_sifs_notx: + fetcht 1,mem_last_freq + call set_freq_rx + call rf_rx_enable + enable swfine + arg 5000,timeup // about 417us + branch le_receive_rxon + +le_transmit_norx: + call le_transmit + branch end_of_packet + +le_transmit: + bpatchx patch29_6,mem_patch29 + call le_prep + call letx_setfreq + call rf_debug_active_tx_line + set1 TXGFSK,radio_ctrl + enable encode_fec0 + enable is_tx + disable is_rx + call le_wait_tx + rshift16 access,pdata + rshift8 pdata,pdata + rshift4 pdata,pdata + inject mod,40 + enable enable_white + enable enable_crc + fetch 1,mem_le_txheader + inject mod,8 + ifetch 1,contr + and pdata,0x3f,loopcnt + inject mod,8 + branch letr_nopayload,zero +letr_loop: + ifetch 1,contr + inject mod,8 + loop letr_loop + +letr_nopayload: + enable enable_parity + inject mod,24 + disable enable_parity + until null,tx_clear + nop 100 /* flush out the last bit */ + disable encode_fec0 + rtn + +le_send_adv_ind: + bpatchx patch29_7,mem_patch29 + fetch 1,mem_le_adv_type + beq ADV_DIRECT_IND,le_send_adv_direct_ind + fetch 1,mem_le_adv_own_addr_type + lshift4 pdata,pdata + lshift2 pdata,pdata + store 1,mem_le_txheader + fetcht 1,mem_le_adv_data_len + add temp,6,pdata + store 1,mem_le_txlen + fetch 6,mem_le_lap + store 6,mem_le_txpayload + copy temp,loopcnt + arg mem_le_adv_data,contr + call memcpy + branch le_send_adv_transmit +le_send_adv_direct_ind: + fetcht 2,mem_le_notify_handle + call le_att_check_notification_enable + copy rega,contw + setarg 1 + istore 1,contw + fetch 1,mem_le_adv_direct_addr_type + lshift4 pdata,pdata + lshift2 pdata,pdata + increase 1,pdata + store 1,mem_le_txheader + setarg 12 + store 1,mem_le_txlen + fetch 6,mem_le_lap + store 6,mem_le_txpayload + fetch 6,mem_hci_plap + istore 6,contw +le_send_adv_transmit: + fetch 1,mem_le_adv_transmit + increase 1,pdata + store 1,mem_le_adv_transmit + arg 1800,stop_watch + disable match + branch le_transmit_receive_sifs + +le_send_scan_request: + bpatchx patch2a_0,mem_patch2a + fetch 1,mem_le_scan_type + rtnne LE_SCAN_TYPE_ACTIVE,pdata + fetch 1,mem_le_adv_transmit + increase 1,pdata + store 1,mem_le_adv_transmit + arg 0x0c03,temp// length + SCAN_REQ PDU + fetch 1,mem_le_scan_own_addr_type + nsetflag blank,LE_SENDER_ADDR_BIT,temp + copy regA,pdata + nsetflag blank,LE_RECEIVER_ADDR_BIT,temp + storet 2,mem_le_txheader + fetch 6,mem_le_lap + istore 6,contw + fetch 6,mem_le_plap + istore 6,contw + branch le_transmit_receive_sifs + + +le_send_scan_response: + arg SCAN_RSP,temp + fetch 1,mem_le_adv_own_addr_type + nsetflag blank,LE_SENDER_ADDR_BIT,temp + storet 1,mem_le_txheader + fetcht 1,mem_le_scan_data_len + add temp,6,pdata + store 1,mem_le_txlen + fetch 6,mem_le_lap + store 6,mem_le_txpayload + arg mem_le_scan_data,contr + copy temp,loopcnt + call memcpy + branch le_transmit_norx + + +le_connect_request: + bpatchx patch2a_1,mem_patch2a + force -1,pdata + setsect 2,1 + store 5,mem_le_channel_map + call le_calc_channel_map + force 4,loopcnt + arg mem_le_access,contw + call generate_random_loop + fetch 2,mem_le_conn_superto + store 2,mem_le_superto +le_con_req_hop_retry: + random pdata + and_into 0xf,pdata + sub pdata,4,null + branch le_con_req_hop_retry,positive + store 1,mem_le_hop + store 1,mem_tmp1 + fetcht 2,mem_le_conn_interval + storet 2,mem_le_tsniff + copy temp,regc // tsniff in regc + add clkn_bt,7,pdata // leave space for offset + idiv regc + call wait_div_end + remainder rega + isub rega,pdata + iadd regc,pdata + fetcht 2,mem_le_dsniff + iadd temp,pdata + store 4,mem_le_anchor + isub clkn_bt,rega + increase -6,rega // window offset + arg 0x2205,regb // length & CONN_REQ PDU + fetch 1,mem_le_conn_own_addr_type + nsetflag blank,LE_SENDER_ADDR_BIT,regb + fetch 1,mem_le_conn_peer_addr_type + nsetflag blank,LE_RECEIVER_ADDR_BIT,regb + storer regb,2,mem_le_txheader + fetch 6,mem_le_lap + istore 6,contw//own addr + fetch 6,mem_le_plap + istore 6,contw// peer addr + fetch 4,mem_le_access + istore 4,contw + random pdata + istore 2,contw /* crc init */ + random pdata + istore 1,contw + force 2,pdata /* window size */ + istore 1,contw + rshift2 rega,pdata + istore 2,contw /* window offset */ + rshift2 regc,pdata + istore 2,contw /* conn Interval */ + fetch 2,mem_le_conn_latency /* slave latency */ + istore 2,contw + fetch 2,mem_le_conn_superto + istore 2,contw + fetch 5,mem_le_channel_map + istore 5,contw /* channel map */ + fetch 1,mem_le_hop + arg param_le_sca,temp + ior temp,pdata + istore 1,contw + call le_transmit_norx + setarg mem_le_txheader + add pdata,18,contr + ifetch 3,contr + store 3,mem_le_crcinit + rtn + +le_init_adv: + disable master + branch le_adv_access + + + +le_update_param: + fetch 1,mem_le_state + rtnbit0 lestate_update_param + fetch 2,mem_le_event_count + fetcht 2,mem_le_instant + isub temp,pdata + store 2,mem_pdatatemp + nrtn positive + fetch 1,mem_le_state + set0 lestate_update_param,pdata + set0 lestate_got_first_packet,pdata + store 1,mem_le_state + fetch 4,mem_le_anchor + fetcht 2,mem_le_tsniff + storet 2,mem_temp + isub temp,rega + fetch 1,mem_le_new_param + store 1,mem_le_window_size + ifetcht 2,contr + ifetch 2,contr + lshift2 pdata,pdata + store 2,mem_le_tsniff + lshift2 temp,temp + iadd temp,pdata + ifetcht 4,contr + storet 4,mem_le_slave_latency // and superTO + iadd rega,pdata + copy pdata,regab + fetch 2,mem_le_tsniff + fetcht 2,mem_temp //last sniff + isub temp,pdata //last sniff - new sniff + fetcht 2,mem_pdatatemp + imul32 temp,pdata + iadd regab,pdata + store 4,mem_le_anchor + branch le_receive_window_size + +le_update_channel_map: + fetch 1,mem_le_state + rtnbit0 lestate_update_map + fetch 2,mem_le_event_count + fetcht 2,mem_le_instant + isub temp,pdata + nrtn positive + fetch 1,mem_le_state + set0 lestate_update_map,pdata + store 1,mem_le_state + fetch 5,mem_le_new_map + store 5,mem_le_channel_map + branch le_calc_channel_map + + +le_acknowledge: + bpatchx patch2a_2,mem_patch2a + call le_supervision_flush + call le_check_wak + fetch 1,mem_le_rxbuf + isolate1 md,pdata + setflag true,mark_ble_rx_md,mark + rshift pdata,pdata + ixor temp,pdata + isolate1 nesn,pdata + setflag true,mark_old_packet,mark /* retransmit */ + fetch 1,mem_le_rxbuf+1 + branch le_ack_unenc,blank /* empty packet, no decryption */ + fetch 1,mem_le_state + bbit0 lestate_encryption,le_ack_unenc + rtnmark1 mark_old_packet + call load_sk + call le_decrypt + setflag blank,mark_le_mic_ok,mark + nrtn blank +le_ack_unenc: + rtnmark1 mark_old_packet + set1 mark_le_mic_ok,mark + fetcht 1,mem_le_arq + setflip nesn,temp + storet 1,mem_le_arq + rtn + //branch le_parse + +le_check_wak: + fetcht 1,mem_le_arq + isolate0 wak,temp + rtn true + fetch 1,mem_le_rxbuf + lshift pdata,pdata + ixor temp,pdata + rtnbit0 sn /* received NESN is same as SN, NAK */ + set0 wak,temp + setflip sn,temp + storet 1,mem_le_arq + compare 3,temp,3 + nrtn true + fetch 1,mem_le_txpayload + beq LL_START_ENC_REQ,le_set_enc + fetch 1,mem_le_enc_state + beq FLAG_LE_ENC_PAUSE,le_clear_enc + rtn + +le_set_enc: + fetch 1,mem_le_state + set1 lestate_encryption,pdata + store 1,mem_le_state + rtn + +le_clear_enc: + bpatchx patch2a_3,mem_patch2a + jam FLAG_LE_ENC_NULL,mem_le_enc_state + arg 0,pdata + store 4,mem_le_last_mic + store 5,mem_le_pcnt_tx + set1 39,pdata + store 5,mem_le_pcnt_rx + fetch 1,mem_le_state + set0 lestate_encryption,pdata + store 1,mem_le_state + rtn + +le_wait_adv: + call le_next_adv_channel + call le_receive_adv + fetch 1,mem_le_adv_waitcnt + increase 1,pdata + store 1,mem_le_adv_waitcnt + rtn + +le_scan: + fetch 1,mem_le_scan_enable + rtnne LE_SCAN_ENABLE + arg le_scan_interval_timer,queue + call timer_check + nrtn blank + fetch 2,mem_le_scan_interval + fetcht 2,mem_le_scan_window + isub temp,pdata + arg le_scan_interval_timer,queue + call timer_init + disable master + call le_init_adv + call le_wait_adv + nrtn match + bpatchx patch2a_4,mem_patch2a + + fetch 6,mem_le_rxbuf+2 + store 6,mem_le_plap + + fetch 1,mem_le_adv_rcv + increase 1,pdata + store 1,mem_le_adv_rcv + call le_create_conn + rtn master + call le_send_scan_request + nrtn match + fetch 1,mem_le_scanrsp_rcv + increase 1,pdata + store 1,mem_le_scanrsp_rcv + fetch 9,mem_le_rxbuf+8 + store 9,mem_tmp_buffer + rtn + +le_create_conn: + fetch 1,mem_cmd_le_create_conn + rtnne hci_cmd_le_create_conn + fetch 6,mem_le_plap + fetcht 6,mem_le_conn_peer_addr + isub temp,null + nrtn zero + call context_new + nrtn zero + call le_connect_request + call le_init_master + jam 0,mem_hci_cmd + jam 0,mem_le_peer_sca + fetch 1,mem_device_option + bne dvc_op_dongle,le_create_conn_ndongle + jam CONN_SM_SEND_WRITE_REQ,mem_le_conn_sm +le_create_conn_ndongle: + jam 0,mem_le_scan_enable + jam 0,mem_cmd_le_create_conn + branch context_save + +le_scan_check_sender_addr_type: + arg 1,regA// sender_addr_type + fetch 1,mem_le_rxbuf + rtnbit1 LE_SENDER_ADDR_BIT + arg 0,regA + rtn + + +le_prepare_tx: + bpatchx patch2a_5,mem_patch2a + fetch 1,mem_le_arq + rtnbit1 wak + call le_check_tx_md + //update tx packet here + call le_fifo_get_first_tx_ptr //no packet to send + branch le_send_empty,blank + ifetch 1,contr + ifetchr rega,1,contr + isub rega,pdata + arg LE_MAX_PAKET_LEN,temp + call not_greater_than + copy pdata,temp + ifetchr type,1,contr + copy rega,pdata + iadd contr,contr + arg mem_le_txpayload,contw + copy temp,loopcnt + call memcpy + call le_update_tx_type + call le_send_packet + + call le_fifo_get_first_tx_ptr + ifetch 1,contr + copy pdata,rega + copy contr,regd + ifetchr regb,1,contr + isub regb,pdata + arg LE_MAX_PAKET_LEN,temp + call not_greater_than + iadd regb,pdata + istore 1,regd + isub rega,null + nrtn zero + branch le_fifo_release_first_node + + +le_check_tx_md: + fetch 1,mem_le_more_data + branch le_clear_md,blank + call le_check_continue + rtnmark1 mark_ble_tx_md + call le_fifo_get_second_tx_ptr //no packet to send + branch le_clear_md,blank + set1 mark_ble_tx_md,mark + rtn + +le_check_continue: + call le_fifo_get_first_tx_ptr //no packet to send + branch le_clear_md,blank + ifetch 1,contr //pdata:length + ifetcht 1,contr //temp:offest + isub temp,pdata //pdata:length - offset + sub pdata,LE_MAX_PAKET_LEN,null + branch le_clear_md,positive //27 > length -offset + set1 mark_ble_tx_md,mark + rtn + +le_clear_md: + set0 mark_ble_tx_md,mark + rtn + + +le_update_tx_type: + copy rega,pdata + rtn blank + arg LLID_CONTINUE,type + rtn + +le_send_empty: + force 0,temp + force 1,type + +le_send_packet: + bpatchx patch2a_6,mem_patch2a + storet 1,mem_le_txlen + fetcht 1,mem_le_arq + set1 wak,temp + and temp,0xfc,pdata + ior type,pdata + store 1,mem_le_arq + and_into 0x1f,pdata + isolate1 mark_ble_tx_md,mark + setflag true,md,pdata + store 1,mem_le_txheader + fetch 1,mem_le_txlen + rtn blank + + fetch 7,mem_le_txheader+1 + fetch 1,mem_le_state + rtnbit0 lestate_encryption + call load_sk + branch le_encrypt + +le_parse: + rtnmark1 mark_old_packet + rtnmark0 mark_le_mic_ok + + call le_fifo_check_full + nrtn blank + fetch 1,mem_le_rxbuf + and pdata,0x3,pdata + store 1,mem_le_packet_llid + ifetch 1,contr + and pdata,0x1f,pdata + store 1,mem_le_packet_size + rtn blank //empty rtn + storer contr,2,mem_le_payload_ptr + fetch 1,mem_le_packet_llid + beq LLID_LE_LL,le_parse_ll +le_parse_l2cap: + bpatchx patch2a_7,mem_patch2a + call le_check_l2cap_complete + nrtn user + fetch 2,mem_le_payload_ptr + copy pdata,contr + ifetch 2,contr //l2cap len + store 2,mem_le_l2cap_size + ifetch 2,contr + beq LE_L2CAP_CID_ATT,le_parse_att + beq LE_L2CAP_CID_SMP,le_parse_smp + beq LE_L2CAP_CID_SIGNAL,le_parse_signaling + rtn + +le_check_l2cap_complete: + fetch 1,mem_le_packet_llid + beq LLID_START,le_check_l2cap_llid_start + beq LLID_CONTINUE,le_check_l2cap_llid_continue + rtn + +le_check_l2cap_llid_start: + fetch 2,mem_le_payload_ptr + copy pdata,contr + ifetch 2,contr + store 2,mem_le_l2cap_size + fetcht 1,mem_le_packet_size + storet 1,mem_le_packet_len_recved + increase 4,pdata + isub temp,null + branch enable_user,zero + fetchr loopcnt,1,mem_le_packet_size + arg mem_le_l2capbuf,contw + fetch 2,mem_le_payload_ptr + copy pdata,contr + call memcpy + branch disable_user + +le_check_l2cap_llid_continue: + fetch 1,mem_le_packet_len_recved + arg mem_le_l2capbuf,contw + iadd contw,rega + fetcht 1,mem_le_packet_size + iadd temp,pdata + store 1,mem_le_packet_len_recved + fetchr loopcnt,1,mem_le_packet_size + copy rega,contw + fetch 2,mem_le_payload_ptr + copy pdata,contr + call memcpy + setarg mem_le_l2capbuf + store 2,mem_le_payload_ptr //update ptr->mem_le_l2capbuff + fetch 2,mem_le_l2cap_size + increase 4,pdata + fetcht 1,mem_le_packet_len_recved + isub temp,null + branch enable_user,zero + branch disable_user + +le_parse_ll: + bpatchx patch2b_0,mem_patch2b + fetch 1,mem_le_rxbuf+2 + beq LL_CONNECTION_UPDATE_REQ,le_parse_connection_update_req + beq LL_CHANNEL_MAP_REQ,le_parse_channel_map_req + beq LL_TERMINATE_IND,le_parse_terminate_ind + beq LL_ENC_REQ,le_parse_enc_req + beq LL_ENC_RSP,le_parse_enc_rsp + beq LL_START_ENC_REQ,le_parse_start_enc_req + beq LL_START_ENC_RSP,le_parse_start_enc_rsp + beq LL_UNKNOWN_RSP,le_parse_unknown_rsp + beq LL_FEATURE_REQ,le_parse_feature_req + beq LL_FEATURE_RSP,le_parse_feature_rsp + beq LL_PAUSE_ENC_REQ,le_parse_pause_enc_req + beq LL_PAUSE_ENC_RSP,le_parse_pause_enc_rsp + beq LL_VERSION_IND,le_parse_version_ind + beq LL_REJECT_IND,le_parse_reject_ind + beq LL_PING_REQ,le_parse_ping_req + beq LL_PING_RSP,le_parse_ping_rsp + arg 2,rega + arg LLID_LE_LL,type + call le_fifo_malloc_tx + setarg LL_UNKNOWN_RSP + istore 1,contw + fetch 1,mem_le_rxbuf+2 + istore 1,contw + rtn + + + +le_parse_connection_update_req: + ifetch 9,contr + store 9,mem_le_new_param + ifetch 2,contr + store 2,mem_le_instant + fetch 1,mem_le_state + set1 lestate_update_param,pdata + store 1,mem_le_state + rtn + +le_parse_channel_map_req: + ifetch 5,contr + store 5,mem_le_new_map + ifetch 2,contr + store 2,mem_le_instant + fetch 1,mem_le_state + set1 lestate_update_map,pdata + store 1,mem_le_state + rtn + +le_parse_terminate_ind: + setarg 20 + store 2,mem_le_superto + rtn + +le_send_terminate_remote_user_ended_conn: + jam HCI_ERROR_REMOTE_USER_ENDED_CONNECTION,mem_temp +le_send_terminate_ind: + call le_parse_terminate_ind + arg 2,rega + arg LLID_LE_LL,type + call le_fifo_malloc_tx + setarg LL_TERMINATE_IND + istore 1,contw + fetch 1,mem_temp + istore 1,contw + rtn + +le_parse_enc_req: + ifetch 8,contr + store 8,mem_le_rand + ifetch 2,contr + store 2,mem_le_ediv + ifetch 8,contr + store 8,mem_le_skdm + ifetch 4,contr + store 4,mem_le_ivm + bpatchx patch2b_1,mem_patch2b + fetch 1,mem_le_pairing_state + beq FLAG_LE_PAIRING_AFTER_AUTH,le_parse_enc_req_after_auth +//call load_device_list_mode_4 + fetch 1,mem_ltk_exists + beq 0,le_ltk_lost +le_parse_enc_req_ltk_exist: +le_parse_enc_req_after_auth: + jam FLAG_LE_RCV_ENC_START,mem_le_enc_state + call le_send_enc_rsp + call le_send_start_enc_req + branch generate_sk + +le_ltk_lost: + jam FLAG_LE_ENC_NULL,mem_le_enc_state +// jam FLAG_LE_PAIRING_START,mem_le_pairing_state + branch le_send_reject_ind + +le_send_reject_ind: + arg 2,rega + arg LLID_LE_LL,type + call le_fifo_malloc_tx + setarg LL_REJECT_IND + istore 1,contw + setarg LE_ERR_PIN_OR_KEY_MISSING + istore 1,contw + rtn + +le_send_enc_rsp: + arg mem_le_skds,contw + force 8,loopcnt + call generate_random_loop + arg mem_le_ivs,contw + force 4,loopcnt + call generate_random_loop + arg 13,rega + arg LLID_LE_LL,type + call le_fifo_malloc_tx + setarg LL_ENC_RSP + istore 1,contw + fetch 8,mem_le_skds + istore 8,contw + fetch 4,mem_le_ivs + istore 4,contw + rtn + +le_send_start_enc_req: + arg LL_START_ENC_REQ,regc + branch le_send_ll_one_lenth + +le_send_start_enc_rsp: + arg LL_START_ENC_RSP,regc + branch le_send_ll_one_lenth + +le_send_ll_one_lenth: + bpatchx patch2b_2,mem_patch2b + arg 1,rega + arg LLID_LE_LL,type + call le_fifo_malloc_tx + copy regc,pdata + istore 1,contw + rtn + +le_parse_enc_rsp: + ifetch 8,contr + store 8,mem_le_skds + ifetch 4,contr + store 4,mem_le_ivs + branch generate_sk + +le_parse_start_enc_req: + fetch 1,mem_le_state + set1 lestate_encryption,pdata + store 1,mem_le_state + rtn + +le_parse_start_enc_rsp: + rtn master + jam BT_EVT_LE_START_ENC,mem_fifo_temp + call ui_ipc_send_event + jam FLAG_LE_SEND_START_ENC_RSP,mem_le_enc_state + branch le_send_start_enc_rsp + +le_parse_feature_req: + arg 9,rega + arg LLID_LE_LL,type + call le_fifo_malloc_tx + setarg LL_FEATURE_RSP + istore 1,contw + setarg param_le_features + istore 8,contw + rtn + +le_parse_pause_enc_req: + jam FLAG_LE_ENC_PAUSE,mem_le_enc_state + call le_send_pause_enc_rsp + jam BT_EVT_LE_PAUSE_ENC,mem_fifo_temp + branch ui_ipc_send_event + +le_send_pause_enc_rsp: + arg LL_PAUSE_ENC_RSP,regc + branch le_send_ll_one_lenth + +le_parse_version_ind: + rtn master + arg 6,rega + arg LLID_LE_LL,type + call le_fifo_malloc_tx + setarg LL_VERSION_IND + istore 1,contw + setarg param_le_version + istore 3,contw + setarg param_le_subversion + istore 2,contw + rtn + +le_parse_feature_rsp: +le_parse_unknown_rsp: +le_parse_pause_enc_rsp: +le_parse_reject_ind: +le_parse_ping_rsp: + rtn + +le_parse_ping_req: + arg LL_PING_RSP,regc + branch le_send_ll_one_lenth + + + +le_supervision_update: + fetcht 4,mem_le_supervision_timer + call get_clkbt + isub temp,timeup /* and to 28 bits */ + deposit timeup + fetcht 2,mem_le_superto + lshift4 temp,temp + lshift temp,temp + isub temp,pdata + rtn + +le_supervision_flush: + call get_clkbt + store 4,mem_le_supervision_timer + rtn + + + +le_adv: + bpatchx patch2b_3,mem_patch2b + fetch 1,mem_le_adv_enable + rtn blank + arg le_adv_interval_timer,queue + call timer_check + nrtn blank + disable master + enable swfine + call le_init_adv + call le_next_adv_channel + call le_send_adv_ind + nbranch le_adv_not_match,match + fetch 1,mem_le_req_rcv + increase 1,pdata + store 1,mem_le_req_rcv + fetch 1,mem_le_rxbuf + and pdata,0x0f,pdata + beq SCAN_REQ,le_send_scan_response + beq CONNECT_REQ,parse_connect_req +le_adv_not_match: + nop 10000 + fetch 1,mem_le_ch_mapped + bne 39,le_adv + arg le_adv_interval_timer,queue + fetch 2,mem_le_adv_interval_max + branch timer_init + + +le_receive_window_size: + bpatchx patch2b_4,mem_patch2b + fetch 1,mem_le_peer_sca + call le_sca_map + fetch 2,mem_le_tsniff + imul32 temp,pdata + arg 375,temp + imul32 temp,pdata + arg 100000,temp + idiv temp + fetch 1,mem_le_window_size + arg 20000,temp + imul32 temp,pdata + store 4,mem_le_transmit_window + fetch 2,mem_rx_window_sniff + call wait_div_end + quotient temp + iadd temp,pdata + store 2,mem_le_receive_window + rtn + +parse_connect_req: + bpatchx patch2b_5,mem_patch2b + fetch 6,mem_le_rxbuf+8 + fetcht 6,mem_le_lap + isub temp,null + nrtn zero + call le_scan_check_sender_addr_type + copy regA,pdata + store 1,mem_le_conn_peer_addr_type + fetch 7,mem_le_rxbuf+21 + store 7,mem_tmp_buffer + ifetch 8,contr + istore 8,contw + fetch 6,mem_le_rxbuf+2 + store 6,mem_le_plap + increase 6,contr + ifetch 8,contr + store 8,mem_le_access // and crcinit & window size + ifetcht 2,contr // transmit offset + lshift2 temp,temp + ifetch 2,contr // connInterval + lshift2 pdata,pdata + store 2,mem_le_tsniff + store 4,mem_le_anchor + isub temp,pdata + add pdata,-2,clke_bt + ifetch 9,contr + store 9,mem_le_slave_latency// and super to & channel map + ifetch 1,contr + rshift4 pdata,temp + rshift temp,temp + storet 1,mem_le_peer_sca + and_into 0x1f,pdata + store 1,mem_le_hop + call le_receive_window_size + fetch 4,mem_le_transmit_window + arg 15000,temp + iadd temp,pdata + store 4,mem_le_transmit_window //add transmit window delay 1.25ms + call le_calc_channel_map + call le_init_slave + call context_new + nrtn zero + call calc_clke_offset + call le_l2cap_reset_signaling_identifier + jam BT_EVT_LE_CONNECTED,mem_fifo_temp + call ui_ipc_send_event + branch context_save + + +le_data_send_write_req: + jam 0x2,mem_le_handle_data_len + setarg 0x0001 + store 2,mem_le_handle_data + jam CONN_SM_WAIT_WRITE_RES,mem_le_conn_sm + rtn + +le_data_wait_write_res: + rtn +le_data_wait_write_res1: + rtn +le_conn_sm_master: + fetch 1,mem_device_option + rtnne dvc_op_dongle + fetch 1,mem_le_conn_sm + beq CONN_SM_SEND_WRITE_REQ,le_data_send_write_req + beq CONN_SM_WAIT_WRITE_RES,le_data_wait_write_res + beq CONN_SM_WAIT_WRITE_RES1,le_data_wait_write_res1 + rtn + + +le_lpm_set_mult: + disable wake + branch le_lpm_set_mult_attempt,attempt + nbranch le_lpm_lost,match +le_lpm_set_mult_attempt: + call lpm_match + fetch 2,mem_rx_window_sniff + store 2,mem_le_receive_window + fetch 1,mem_le_rxbuf + compare 1,pdata,3 + nbranch lpm_mult_short,true // rx not empty, short interval + fetch 1,mem_le_txheader + compare 1,pdata,3 + nbranch lpm_mult_short,true // tx not empty, short interval + fetch 1,mem_le_state + bbit1 lestate_update_param,lpm_mult_short + branch lpm_mult_wait_timeout + +le_lpm_lost: + fetcht 2,mem_rx_window_sniff + rshift temp,temp + fetch 2,mem_le_receive_window + iadd temp,pdata + store 2,mem_le_receive_window + branch lpm_lost + + + /* rega = ad type to search, return zero when found */ +le_search_adtype: + fetch 1,mem_le_rxbuf + 1 + arg mem_le_rxbuf + 8,contr + iadd contr,loopcnt +le_search_adtype_loop: + ifetcht 1,contr + ifetch 1,contr + isub rega,null + rtn zero + add temp,-1,pdata + iadd contr,contr + deposit loopcnt + isub contr,null + branch le_search_adtype_loop,positive + force 1,null + rtn + +//rega:len regd:signaling opcode +le_fifo_malloc_tx_l2cap_signaling: + bpatchx patch2b_6,mem_patch2b + call le_l2cap_update_signaling_identifier + arg LE_L2CAP_CID_SIGNAL,regb + call le_fifo_malloc_tx_l2cap + istorer regd,1,contw + fetch 1,mem_le_signaling_identifier + istore 1,contw + rtn + +le_l2cap_update_signaling_identifier: + fetch 1,mem_le_signaling_identifier + //beq 0xff,le_l2cap_signaling_identifier_set_1 + pincrease 1 + store 1,mem_le_signaling_identifier + rtnne 0 +le_l2cap_reset_signaling_identifier: + jam 1,mem_le_signaling_identifier + rtn + + + +//rega:len regb:cid +le_fifo_malloc_tx_l2cap: + bpatchx patch2b_7,mem_patch2b + force LLID_L2CAP_START,type + increase 4,rega + call le_fifo_malloc_tx + increase -4,rega + istorer rega,2,contw //l2cap size + istorer regb,2,contw //cid + rtn +//rega:len type:llid +le_fifo_malloc_tx: + bpatchx patch2c_0,mem_patch2c + sub rega,118,null //check max len + nbranch assert,positive + fetch 1,mem_le_tx_buff_used + arg 1,temp + arg LE_TX_BUFF_COUNT,loopcnt +le_fifo_malloc_tx_loop: + iand temp,null + branch le_fifo_malloc_tx_got_empty,zero + lshift temp,temp + loop le_fifo_malloc_tx_loop + branch assert //no empty buff +le_fifo_malloc_tx_got_empty: + ixor temp,pdata + store 1,mem_le_tx_buff_used + sub loopcnt,LE_TX_BUFF_COUNT,pdata + lshift3 pdata,pdata + lshift4 pdata,pdata + arg mem_le_tx_buffer0,temp + iadd temp,temp +le_fifo_tx_find_empty_ptr: + arg 0,loopcnt + arg mem_le_tx_ptr0,contr +le_fifo_tx_find_empty_ptr_loop: + ifetch 2,contr + branch le_fifo_tx_found_empty_ptr,blank + copy loopcnt,pdata + increase 1,loopcnt + bne LE_TX_BUFF_COUNT,le_fifo_tx_find_empty_ptr_loop + branch assert +le_fifo_tx_found_empty_ptr: + bpatchx patch2c_1,mem_patch2c + increase -2,contr + istoret 2,contr + copy temp,contw + istorer rega,1,contw //lengh + setarg 0 + istore 1,contw //offset + istorer type,1,contw + rtn + + +le_fifo_get_first_tx_ptr: + bpatchx patch2c_2,mem_patch2c + fetch 2,mem_le_tx_ptr0 + copy pdata,contr + rtn + +le_fifo_get_second_tx_ptr: + fetch 2,mem_le_tx_ptr1 + copy pdata,contr + rtn + + +le_fifo_get_last_tx_ptr: + bpatchx patch2c_3,mem_patch2c + call le_fifo_get_last_tx_ptr0 + copy pdata,contr + rtn +le_fifo_get_last_tx_ptr0: + fetch 2,mem_le_tx_ptr3 + nrtn blank + fetch 2,mem_le_tx_ptr2 + nrtn blank + fetch 2,mem_le_tx_ptr1 + nrtn blank + fetch 2,mem_le_tx_ptr0 + rtn + +le_fifo_get_first_l2cap_ptr: + call le_fifo_get_first_tx_ptr + increase 3,contr + rtn + +le_fifo_get_first_att_ptr: + call le_fifo_get_first_tx_ptr + increase 7,contr + rtn + +le_fifo_get_last_att_ptr: + call le_fifo_get_last_tx_ptr + increase 7,contr + rtn + +le_fifo_get_last_l2cap_ptr: + call le_fifo_get_last_tx_ptr + increase 3,contr + rtn + + + +le_fifo_check_full: + fetch 2,mem_le_tx_ptr3 + rtn +le_fifo_check_empty: + fetch 2,mem_le_tx_ptr0 + rtn + + +le_fifo_release_first_node: + bpatchx patch2c_4,mem_patch2c + fetch 2,mem_le_tx_ptr0 + arg mem_le_tx_buffer0,temp + isub temp,pdata + rshift4 pdata,pdata + rshift3 pdata,queue + fetch 1,mem_le_tx_buff_used + qset0 pdata + store 1,mem_le_tx_buff_used + arg 0,loopcnt +le_fifo_release_first_node_loop: + lshift loopcnt,pdata + arg mem_le_tx_ptr1,temp + iadd temp,temp + ifetch 2,temp + increase -2,temp + istore 2,temp + copy loopcnt,pdata + increase 1,loopcnt + bne LE_TX_BUFF_UPDATE_LOOPCNT,le_fifo_release_first_node_loop + setarg 0 + istore 2,temp + rtn + + +le_parse_signaling: + ifetch 1,contr + rtn + + +//regc:the ptr that connection parameter, +//include ConnIntervalMin,ConnIntervalMax, +// ConnSlaveLatency,ConnSupervisionTimeout +le_l2cap_tx_update_req: + arg 0x0c,rega + arg L2CAP_CONNECTION_PARAMETER_UPDATE_REQUEST,regd + call le_fifo_malloc_tx_l2cap_signaling + setarg 0x08 + istore 2,contw + ifetch 8,regc + istore 8,contw + rtn + + + +else + +endif Index: tag/Soft/Librarier/bt_rom/program/le_att.prog =================================================================== --- /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/le_att.prog (nonexistent) +++ /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/le_att.prog (working copy) @@ -0,0 +1,736 @@ + + +le_parse_att: + bpatchx patch2c_5,mem_patch2c + ifetch 3,contr + store 3,mem_le_att_opcode + beq ATTOP_EXCHANGE_MTU_REQUEST,le_parse_att_exchange_mtu_request + beq ATTOP_EXCHANGE_MTU_RESPONSE,le_parse_att_exchange_mtu_response + beq ATTOP_FIND_INFORMATION_REQUEST,le_parse_att_find_information_request + beq ATTOP_FIND_BY_TYPE_VALUE_REQUEST,le_parse_att_find_by_type_value_request + beq ATTOP_READ_BY_TYPE_REQUEST,le_parse_att_read_by_type_request + beq ATTOP_READ_REQUEST,le_parse_att_read_request + beq ATTOP_READ_BLOB_REQUEST,le_parse_att_read_blob_request + beq ATTOP_READ_BY_GROUP_TYPE_REQUEST,le_parse_att_read_by_group_type_request + beq ATTOP_WRITE_REQUEST,le_parse_att_write_request + beq ATTOP_PREPARE_WRITE_REQUEST,le_parse_att_prepare_write_request + beq ATTOP_EXECUTE_WRITE_REQUEST,le_parse_att_execute_write_request + beq ATTOP_WRITE_COMMAND,le_parse_att_write_command + rtn + + +le_parse_att_exchange_mtu_request: + force 3,rega + force LE_L2CAP_CID_ATT,regb + call le_fifo_malloc_tx_l2cap + setarg ATTOP_EXCHANGE_MTU_RESPONSE + istore 1,contw + setarg param_le_mtu + istore 2,contw + rtn + + +le_parse_att_exchange_mtu_response: + rtn + +le_parse_att_find_information_request: + rshift8 pdata,pdata + store 2,mem_le_search_handle_start + ifetch 2,contr + store 2,mem_le_search_handle_end + arg 2,timeup + fetcht 2,mem_le_search_handle_start + storet 2,mem_temp + call le_init_attlist_search +le_send_att_find_information_res_loop: + call le_att_check_handle_end + nbranch le_send_att_find_information_res_end,positive + nbranch le_send_att_find_information_res_write_handle_info,user + force 20,rega + force LE_L2CAP_CID_ATT,regb + call le_fifo_malloc_tx_l2cap + setarg ATTOP_FIND_INFORMATION_RESPONSE + istore 1,contw + setarg 1 + istore 1,contw + disable user + call store_contw +le_send_att_find_information_res_write_handle_info: + fetcht 2,mem_temp + call le_att_get_handle_info + call get_contw + fetch 2,mem_temp + istore 2,contw + fetch 1,mem_le_cur_uuid_lenth + copy pdata,loopcnt + call memcpy_fast + call store_contw + increase -1,timeup + branch le_send_att_find_information_res_end,zero +le_send_att_find_information_res_next: + call le_att_next_handle + branch le_send_att_find_information_res_loop +le_send_att_find_information_res_end: + branch le_send_att_error_response_notfound,user + branch le_send_auto_len_by_mem + +le_parse_att_find_by_type_value_request: + rshift8 pdata,pdata + store 2,mem_le_search_handle_start + ifetch 2,contr + store 2,mem_le_search_handle_end + + ifetch 2,contr + store 2,mem_le_search_uuid + call store_contr + arg mem_le_search_att_type_length,contw + fetch 2,mem_le_l2cap_size + increase -7,pdata + call le_get_search_common2 +le_send_att_find_by_type_value_response: + fetcht 2,mem_le_search_uuid + setarg UUID_GATT_PRIMARY_SERVICE + isub temp,null + branch le_send_att_find_by_type_value_res_primary,zero + branch le_send_att_error_response_notfound + +le_send_att_find_by_type_value_res_primary: + //jam LE_FIND_BY_TYPE_VAL_RES_NOT_FOUND,mem_le_search_res + arg LE_FIND_BY_TYPE_VAL_RES_NOT_FOUND,timeup + fetcht 2,mem_le_search_handle_start + storet 2,mem_temp + call le_att_get_handle_info + nbranch le_send_att_error_response_notfound,blank +le_send_att_find_primary_search_loop: + fetcht 2,mem_temp + call le_att_get_handle_info + nbranch le_send_att_error_response_notfound2,blank + copy contr,rega + fetch 1,mem_le_curr_att_len + copy pdata,loopcnt + fetcht 1,mem_le_search_att_type_length + isub temp,null + nbranch le_send_att_find_primary_search_loop1,zero + arg mem_le_search_att_type,regb + call string_compare + branch le_send_att_find_primary_search_end_start_handle_found,zero + fetch 2,mem_le_cur_uuid + fetcht 2,mem_le_search_uuid + isub temp,null + branch le_send_att_find_primary_search_end_ending_handle_found,zero +le_send_att_find_primary_search_loop1: + fetch 2,mem_temp + increase 1,pdata + store 2,mem_temp + branch le_send_att_find_primary_search_loop +le_send_att_error_response_notfound2: + copy timeup,pdata + beq LE_FIND_BY_TYPE_VAL_RES_FOUND_STARTING_HANDLE,le_send_att_find_primary_search_end_ending_handle_found + branch le_send_att_error_response_notfound +le_send_att_find_primary_search_end_start_handle_found: + fetch 2,mem_le_cur_uuid + fetcht 2,mem_le_search_uuid + isub temp,null + nbranch le_send_att_find_primary_search_loop1,zero + arg LE_FIND_BY_TYPE_VAL_RES_FOUND_STARTING_HANDLE,timeup + fetcht 2,mem_temp + storet 2,mem_le_cur_handle_start + branch le_send_att_find_primary_search_loop1 +le_send_att_find_primary_search_end_ending_handle_found: + copy timeup,pdata + beq LE_FIND_BY_TYPE_VAL_RES_NOT_FOUND,le_send_att_find_primary_search_loop1 + arg LE_FIND_BY_TYPE_VAL_RES_FOUND_ENDING_HANDLE,timeup + fetcht 2,mem_temp + increase -1,temp + storet 2,mem_le_cur_handle_end +le_send_att_find_primary_search_end: + arg 5,rega + force LE_L2CAP_CID_ATT,regb + call le_fifo_malloc_tx_l2cap + setarg ATTOP_FIND_BY_TYPE_VALUE_RESPONSE + istore 1,contw + fetch 2,mem_le_cur_handle_start + istore 2,contw + fetch 2,mem_le_cur_handle_end + istore 2,contw + rtn + + + +le_parse_att_read_by_type_request: + rshift8 pdata,pdata + store 2,mem_le_search_handle_start + ifetch 2,contr + store 2,mem_le_search_handle_end + call le_get_search_att_uuid + +le_send_att_read_by_type_response: + fetcht 2,mem_le_search_handle_start + storet 2,mem_temp + call le_init_attlist_search + fetcht 2,mem_le_search_uuid + setarg UUID_GATT_CHARACTERISTIC + isub temp,null + nbranch le_send_att_read_by_type_res_not_characteristic,zero + arg 2,timeup +le_send_att_read_by_type_response_loop: + call le_att_check_handle_end + nbranch le_send_att_read_by_type_response_end,positive + fetcht 2,mem_temp + call le_att_get_handle_info + beq 1,le_send_att_read_by_type_response_end + call le_att_same_uuid + nbranch le_send_att_read_by_type_response_next_handle,zero + nbranch le_send_att_read_by_type_res_found_next,user + disable user + arg 20,rega + force LE_L2CAP_CID_ATT,regb + call le_fifo_malloc_tx_l2cap + setarg ATTOP_READ_BY_TYPE_RESPONSE + istore 1,contw + copy contw,alarm + increase 1,contw + call le_send_att_read_by_type_write_properties + call le_att_next_handle + call le_att_get_handle_info + call le_send_att_read_by_type_write_uuid + fetch 1,mem_le_cur_uuid_lenth + increase 5,pdata + istore 1,alarm + fetch 1,mem_le_cur_uuid_lenth + beq 16,le_send_att_read_by_type_response_end + increase -1,timeup + branch le_send_att_read_by_type_response_end,zero +le_send_att_read_by_type_response_next_handle: + call le_att_next_handle + branch le_send_att_read_by_type_response_loop +le_send_att_read_by_type_response_end: + branch le_send_att_error_response_notfound,user + branch le_send_auto_len_by_mem + +le_send_att_read_by_type_res_found_next: + call le_store_att_record + call le_att_next_handle + call le_att_get_handle_info + fetch 1,mem_le_cur_uuid_lenth + beq 16,le_send_att_read_by_type_response_end + call get_contw + fetch 2,mem_temp + increase -1,pdata + istore 2,contw + call le_write_att_record_common + call le_send_att_read_by_type_write_uuid + increase -1,timeup + branch le_send_att_read_by_type_response_end,zero + branch le_send_att_read_by_type_response_next_handle + +le_send_att_read_by_type_res_not_characteristic: + fetcht 2,mem_le_search_handle_start + storet 2,mem_temp +le_send_att_read_by_type_res_not_char_loop: + call le_att_check_handle_end + nbranch le_send_att_error_response_notfound,positive + call le_att_get_handle_info + beq 1,le_send_att_error_response_notfound + call le_att_same_uuid + nbranch le_send_att_read_by_type_res_not_char_next,zero + arg 20,rega + force LE_L2CAP_CID_ATT,regb + call le_fifo_malloc_tx_l2cap + setarg ATTOP_READ_BY_TYPE_RESPONSE + istore 1,contw + fetch 1,mem_le_curr_att_len + copy pdata,loopcnt + increase 2,pdata + istore 1,contw + fetch 2,mem_temp + istore 2,contw + call get_contr + call memcpy_fast + call store_contw + branch le_send_auto_len_by_mem +le_send_att_read_by_type_res_not_char_next: + call le_att_next_handle + branch le_send_att_read_by_type_res_not_char_loop + +le_send_att_read_by_type_write_properties: + fetch 2,mem_temp + istore 2,contw + fetch 1,mem_le_curr_att_len + copy pdata,loopcnt + call get_contr + call memcpy_fast + branch store_contw +le_send_att_read_by_type_write_uuid: + call get_contw + fetch 2,mem_temp + istore 2,contw + call store_contw + fetch 1,mem_le_cur_uuid_lenth + copy pdata,loopcnt + call get_contw + call get_contr + isub loopcnt,contr + increase -1,contr + call memcpy_fast + branch store_contw + +le_parse_att_read_request: + fetcht 2,mem_le_att_handle + fetch 2,mem_le_pairing_handle + nbranch le_parse_att_read_request_check_pairing,blank +le_send_att_read_response: + storet 2,mem_le_search_handle_start + call le_att_get_handle_ptr + branch le_send_att_error_response_notfound,blank + ifetch 1,contr + sub pdata,22,null + branch le_send_att_read_response_less,positive + force 22,pdata +le_send_att_read_response_less: + copy pdata,regd + call store_contr + add regd,1,rega + force LE_L2CAP_CID_ATT,regb + call le_fifo_malloc_tx_l2cap + setarg ATTOP_READ_RESPONSE + istore 1,contw + copy regd,loopcnt + call get_contr + branch memcpy + +le_parse_att_read_request_check_pairing: + isub temp,null + branch le_send_att_read_response_error_insufficient_auth,zero + branch le_send_att_read_response + +le_send_att_read_response_error_insufficient_auth: + fetch 1,mem_le_pairing_mode + beq LE_PAIRING_MODE_NONE,le_send_att_read_response + fetch 1,mem_le_state + bbit1 lestate_encryption,le_send_att_read_response + jam ATT_ERR_INSUFFICIENT_AUTHENTICATION,mem_le_err_code + branch le_send_att_error_response + +le_parse_att_read_blob_request: + ifetch 2,contr + store 2,mem_le_att_offset +le_send_att_read_blob_response: + arg 20,rega + force LE_L2CAP_CID_ATT,regb + call le_fifo_malloc_tx_l2cap + setarg ATTOP_READ_BLOB_RESPONSE + istore 1,contw + fetch 2,mem_le_att_offset + iforce rega + fetcht 2,mem_le_att_handle + call le_att_get_handle_ptr + branch le_send_att_error_response_notfound,blank + ifetch 1,contr + isub rega,loopcnt + nbranch le_send_att_error_response_notfound,positive + sub loopcnt,22,null + branch le_send_att_read_blob_response_less,positive + force 22,loopcnt +le_send_att_read_blob_response_less: + deposit rega + iadd contr,contr + call memcpy_fast + call store_contw + branch le_send_auto_len_by_mem + +le_parse_att_read_multiple_request: + rtn + +le_parse_att_read_by_group_type_request: + rshift8 pdata,pdata + store 2,mem_le_search_handle_start + ifetch 2,contr + store 2,mem_le_search_handle_end + call le_get_search_att_type + arg 2,timeup + fetcht 2,mem_le_search_handle_start + storet 2,mem_temp + call le_init_attlist_search +le_send_att_read_by_group_type_response_loop: + call le_att_check_handle_end + nbranch le_send_att_read_by_group_type_end0,positive + fetcht 2,mem_temp + call le_att_get_handle_info + beq 1,le_send_att_read_by_group_type_end1 + + call le_att_same_type + nbranch le_send_att_read_by_group_type_next_handle,zero + copy timeup,pdata + beq 0,le_send_att_read_by_group_type_end1 + nbranch le_send_att_read_by_group_type_store_write_record,user //un first + disable user + //first att uuid + arg 20,rega + force LE_L2CAP_CID_ATT,regb + call le_fifo_malloc_tx_l2cap + setarg ATTOP_READ_BY_GROUP_TYPE_RESPONSE + istore 1,contw + fetch 1,mem_le_curr_att_len + increase 4,pdata + istore 1,contw + call store_contw + branch le_send_att_read_by_group_type_store_record +le_send_att_read_by_group_type_store_write_record: + fetch 1,mem_le_curr_att_len + beq 16,le_send_att_read_by_group_type_end1 + fetch 2,mem_temp + increase -1,pdata + store 2,mem_le_cur_handle_end + call le_write_att_record +le_send_att_read_by_group_type_store_record: + fetch 2,mem_temp + store 2,mem_le_cur_handle_start + call le_store_att_record + increase -1,timeup +le_send_att_read_by_group_type_next_handle: + call le_att_next_handle + branch le_send_att_read_by_group_type_response_loop +le_send_att_read_by_group_type_end0: //> att handle end + fetch 2,mem_temp + store 2,mem_le_cur_handle_end + branch le_send_att_read_by_group_type_end_common +le_send_att_read_by_group_type_end1: //>att max list handle or diff len + fetch 2,mem_temp + increase -1,pdata + store 2,mem_le_cur_handle_end +le_send_att_read_by_group_type_end_common: + branch le_send_att_error_response_notfound,user + call le_write_att_record + branch le_send_auto_len_by_mem + +le_send_att_error_response_notfound: + jam ATT_ERR_ATTRIBUTE_NOT_FOUND,mem_le_err_code +le_send_att_error_response: + force 5,rega + force LE_L2CAP_CID_ATT,regb + call le_fifo_malloc_tx_l2cap + setarg ATTOP_ERROR_RESPONSE + istore 1,contw + fetch 1,mem_le_att_opcode + istore 1,contw + fetch 2,mem_le_search_handle_start + istore 2,contw + fetch 1,mem_le_err_code + istore 1,contw + rtn + +le_parse_att_write_request: + arg le_send_att_response,regc + branch le_att_parse_write + +le_parse_att_write_command: + arg 0,regc + branch le_att_parse_write + +le_send_att_response: + force 1,rega + force LE_L2CAP_CID_ATT,regb + call le_fifo_malloc_tx_l2cap + setarg ATTOP_WRITE_RESPONSE + istore 1,contw + rtn + +le_parse_att_prepare_write_request: + rtn + +le_parse_att_execute_write_request: + rtn + +/*inline base support*/ + +le_Ipc_tx: + fetch 1,mem_ipc_enable + rtn blank + fetch 2,mem_le_payload_ptr + increase 3,pdata + store 2,mem_ipc_tx_data_ptr + icopy contw + setarg IPC_TYPE_BLE + istore 1,contw + fetcht 1,mem_le_l2cap_size + increase -1,temp + istoret 1,contw + fetch 2,mem_le_att_handle + istore 2,contw + increase 2,temp + storet 1,mem_ipc_tx_data_len + branch ipc_tx_common + +//regc:callback ptr +le_att_parse_write: + bpatchx patch2c_6,mem_patch2c + call le_ipc_tx + fetch 2,mem_le_payload_ptr + copy pdata,contr + add contr,7,regb + fetcht 2,mem_le_att_handle + call le_att_get_handle_info + branch le_att_deal_write_cont,blank + branch le_att_deal_write_callback +le_att_deal_write_cont: + fetch 1,mem_le_curr_att_len + fetcht 2,mem_le_l2cap_size + increase -3,temp + call not_greater_than + copy pdata,loopcnt + call get_contr + copy contr,contw + copy regb,contr + call memcpy +le_att_deal_write_check_characteristic: + fetch 2,mem_le_cur_uuid + arg CLIENT_CHARACTERTIC_CONFIGURATION,temp + isub temp,null + nbranch le_att_deal_write_callback,zero + disable user + ifetch 1,regb + ncall enable_user,blank + fetcht 2,mem_le_att_handle + increase -1,temp + call le_att_create_notify_switch,user + ncall le_att_clear_notify_switch,user +le_att_deal_write_callback: + copy regc,pdata + rtn blank + copy regc,pc + rtn + +le_init_attlist_search: + fetch 2,mem_ui_le_uuid_table + iforce contr + enable user + rtn + +//temp:handle +le_att_get_handle_ptr2: + + fetch 2,mem_ui_le_uuid_table + iforce contr +le_att_get_handle_loop1: + ifetch 2,contr + rtn blank + isub temp,null + rtn zero + ifetch 1,contr + iadd contr,contr + ifetch 1,contr // length + iadd contr,contr + branch le_att_get_handle_loop1 +le_att_get_handle_ptr_found: + ifetch 1,contr + iadd contr,contr + rtn + +le_att_get_handle_info: + fetch 2,mem_ui_le_uuid_table + iforce contr + copy temp,rega +le_att_get_handle_loop: + ifetch 2,contr + branch le_att_unfind_handle,blank + isub rega,null + branch le_att_finded_handle, zero + ifetch 1,contr // length + iadd contr,contr + ifetch 1,contr //length + iadd contr,contr + branch le_att_get_handle_loop +le_att_unfind_handle: + branch setarg1 +le_att_finded_handle: + ifetch 1,contr + store 1,mem_le_cur_uuid_lenth + copy pdata,loopcnt + arg mem_le_cur_uuid,contw + call memcpy_fast + ifetch 1,contr + store 1,mem_le_curr_att_len + call store_contr + branch setarg0 + + +le_att_check_handle_end: + fetcht 2,mem_temp + fetch 2,mem_le_search_handle_end + isub temp,null + rtn + +le_att_same_uuid: + fetcht 1,mem_le_search_uuid_length + arg mem_le_search_uuid,rega + branch le_att_check_same_common +le_att_same_type: + fetcht 1,mem_le_search_att_type_length + arg mem_le_search_att_type,rega +le_att_check_same_common: + fetch 1,mem_le_cur_uuid_lenth + copy pdata,loopcnt + isub temp,null + nrtn zero + arg mem_le_cur_uuid ,regb + branch string_compare + +le_write_att_record: + call get_contw + fetch 2,mem_le_cur_handle_start + istore 2,contw + fetch 2,mem_le_cur_handle_end + istore 2,contw +le_write_att_record_common: + fetch 1,mem_tmp_buffer + copy pdata,loopcnt + call memcpy_fast + branch store_contw + +le_store_att_record: + fetch 1,mem_le_curr_att_len + store 1, mem_tmp_buffer + copy pdata,loopcnt + call get_contr + branch memcpy_fast + +le_att_next_handle: + fetcht 2,mem_temp + increase 1,temp + storet 2,mem_temp + rtn + +/* handle in temp, return pointer in contr to length, blank not found */ +le_att_get_handle_ptr: + bpatchx patch2c_7,mem_patch2c + call le_att_get_handle_ptr2 + branch le_att_get_handle_ptr_found,zero + rtn + +le_send_auto_len_by_mem: + bpatchx patch2d_0,mem_patch2d + call get_contw + call le_fifo_get_last_att_ptr + copy contw,pdata + isub contr,rega + call le_fifo_get_last_l2cap_ptr + istorer rega,2,contr + increase 4,rega + call le_fifo_get_last_tx_ptr + istorer rega,1,contr + rtn + +le_clean_att_list_handle_enable: + fetcht 2,mem_le_notify_handle + call le_att_check_notification_enable + copy rega,contw + setarg 0 + istore 1,contw + rtn + +// temp ->handle,output-> pdata,output :contr->rega +le_att_check_notification_enable: + bpatchx patch2d_1,mem_patch2d + increase 1,temp + call le_att_get_handle_ptr + increase -2,contr + ifetch 2,contr + arg CLIENT_CHARACTERTIC_CONFIGURATION,temp + isub temp,null + nrtn zero + increase 1,contr + copy contr,rega + ifetch 1,contr + rtn + +le_get_search_att_uuid: + call store_contr + arg mem_le_search_uuid_length,contw + branch le_get_search_common +le_get_search_att_type: + call store_contr + arg mem_le_search_att_type_length,contw +le_get_search_common: + fetch 2,mem_le_l2cap_size + increase -5,pdata +le_get_search_common2: + istore 1,contw + copy pdata,loopcnt + call get_contr + branch memcpy_fast + +//rga:len temp:handle;rgea,regb,regc already used +le_att_malloc_tx_notify: + copy temp,regc + arg LE_L2CAP_CID_ATT,regb + increase 3,rega + call le_fifo_malloc_tx_l2cap + increase -3,rega + setarg ATTOP_HANDLE_VALUE_NOTIFICATION + istore 1,contw + copy regc,temp + istoret 2,contw + rtn + +//handle:temp user:state is enabled +le_att_check_notify_switch: + arg mem_notify_handle_pool,contr + arg 4,loopcnt +le_att_check_notify_loop: + ifetch 1,contr + isub temp,null + branch enable_user,zero + loop le_att_check_notify_loop + branch disable_user + +//handle:temp +le_att_clear_notify_switch: + arg mem_notify_handle_pool,contr + arg 4,loopcnt +le_att_clear_notify_loop: + ifetch 1,contr + isub temp,null + call le_att_clear_notify,zero + loop le_att_clear_notify_loop + rtn +le_att_clear_notify: + add contr,-1,contw + setarg 0 + istore 1,contw + rtn + +//handle:temp +le_att_create_notify_switch: + arg mem_notify_handle_pool,contr + arg 4,loopcnt +le_att_creat_notify_loop: + ifetch 1,contr + branch le_att_create_notify,blank + loop le_att_creat_notify_loop + rtn +le_att_create_notify: + add contr,-1,contw + istoret 1,contw + rtn + +le_att_destroy_notify_pool: + setarg 0 + store 4,mem_notify_handle_pool + rtn + + +le_send_update_ATT_MTU: + force 2,rega + force LE_L2CAP_CID_ATT,regb + call le_fifo_malloc_tx_l2cap + setarg ATTOP_EXCHANGE_MTU_REQUEST + istore 1,contw + setarg param_le_mtu + istore 2,contw + rtn + +le_send_update_paramter: + arg mem_le_connection_updata_param,regc + branch le_l2cap_tx_update_req + Index: tag/Soft/Librarier/bt_rom/program/le_smp.prog =================================================================== --- /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/le_smp.prog (nonexistent) +++ /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/le_smp.prog (working copy) @@ -0,0 +1,536 @@ + + +le_pairing_mode_init: + bpatchx patch2d_2,mem_patch2d + fetch 1,mem_le_pairing_mode + beq LE_PAIRING_MODE_NONE, le_set_no_pairing + beq LE_PAIRING_MODE_LAGACY_JUSTWORK,le_set_pairing_mode_lagacy_just_work + beq LE_PAIRING_MODE_LAGACY_PASSKEY,le_set_pairing_mode_lagacy_passkey +ifdef SECURE_CONNECTION + beq LE_PAIRING_MODE_SECURE_CONNECT_JUSTWORK,le_set_pairing_mode_secure_justwork + beq LE_PAIRING_MODE_SECURE_CONNECT_NUMERIC,le_set_pairing_mode_secure_numeric + beq LE_PAIRING_MODE_SECURE_CONNECT_PASSKEY,le_set_pairing_mode_secure_passkey +endif + rtn + +ifdef SECURE_CONNECTION +le_set_pairing_mode_secure_justwork: + jam FLAG_LE_BONDING_MITM_SECURE,mem_le_pres_auth + branch le_set_noinputnooutput +le_set_pairing_mode_secure_numeric: + jam FLAG_LE_BONDING_MITM_SECURE,mem_le_pres_auth + jam FLAG_IOCAP_DISPLAYYESNO,mem_le_pres_iocap + rtn +le_set_pairing_mode_secure_passkey: + jam FLAG_LE_BONDING_MITM_SECURE,mem_le_pres_auth + branch le_set_displayonly +endif +le_set_no_pairing: + jam FLAG_LE_NO_BONDING_NO_MITM,mem_le_pres_auth +le_set_noinputnooutput: + jam FLAG_IOCAP_NOINPUTNOOUTPUT,mem_le_pres_iocap + rtn +le_set_pairing_mode_lagacy_just_work: + jam FLAG_LE_BONDING_MITM,mem_le_pres_auth + branch le_set_noinputnooutput +le_set_pairing_mode_lagacy_passkey: + jam FLAG_LE_BONDING_MITM,mem_le_pres_auth +le_set_displayonly: + jam FLAG_IOCAP_DISPLAYONLY,mem_le_pres_iocap + rtn + + +le_secure_connection_enable: + fetch 1,mem_le_pres_auth + set1 LE_AUTH_SECURE_CONNECTION_PAIRING_BIT,pdata + store 1,mem_le_pres_auth + rtn +le_secure_connection_disable: + fetch 1,mem_le_pres_auth + set0 LE_AUTH_SECURE_CONNECTION_PAIRING_BIT,pdata + store 1,mem_le_pres_auth + rtn + +le_parse_smp: + bpatchx patch2d_3,mem_patch2d + ifetch 1,contr + beq SMP_PAIRING_REQUEST,le_parse_smp_pairing_request +// beq SMP_PAIRING_RESPONSE,le_parse_smp_pairing_response + beq SMP_PAIRING_CONFIRM,le_parse_smp_pairing_confirm + beq SMP_PAIRING_RANDOM,le_parse_smp_pairing_random + beq SMP_PAIRING_FAILED,le_parse_smp_pairing_failed + beq SMP_ENCRYPTION_INFORMATION,le_parse_smp_encryption_information + beq SMP_MASTER_IDENTIFICATION,le_parse_smp_master_identification + beq SMP_IDENTITY_INFORMATION,le_parse_smp_identity_information + beq SMP_IDENTITY_ADDRESS_INFORMATION,le_parse_smp_identity_address_information + beq SMP_SIGNING_INFORMATION,le_parse_smp_signing_information + beq SMP_SECURITY_REQUEST,le_parse_smp_security_request +ifdef SECURE_CONNECTION + beq SMP_PAIRING_PUBLIC_KEY,le_parse_smp_public_key + beq SMP_PAIRING_DHKEY_CHECK,le_parse_smp_dhkey_check +endif + rtn + + + +le_send_smp_security_request: + force 2,rega + force LE_L2CAP_CID_SMP,regb + call le_fifo_malloc_tx_l2cap + setarg SMP_SECURITY_REQUEST + istore 1,contw + fetch 1,mem_le_pres_auth + istore 1,contw + rtn + +le_parse_smp_pairing_request: + store 1,mem_le_preq + ifetch 6,contr + istore 6,contw + fetch 1,mem_le_pairing_mode + beq LE_PAIRING_MODE_NONE,le_smp_pairing_fail_reason_not_support_pairing + call le_send_smp_pairing_response + call le_check_master_support_secure_connect + jam FLAG_LE_PAIRING_RCV_PAIRING_REQ,mem_le_pairing_state + fetch 1,mem_le_preq_iocap + beq FLAG_IOCAP_DISPlAYONLY,le_set_tk_0 + beq FLAG_IOCAP_DISPLAYYESNO,le_set_tk_0 + beq FLAG_IOCAP_NOINPUTNOOUTPUT,le_set_tk_0 + fetch 1,mem_le_pairing_mode + beq LE_PAIRING_MODE_LAGACY_PASSKEY,le_parse_smp_pairing_req_passkey + rtneq LE_PAIRING_MODE_SECURE_CONNECT_PASSKEY +le_set_tk_0: + arg 0,pdata + store 4,mem_le_tk + rtn + +le_parse_smp_pairing_req_passkey: + fetch 1,mem_le_fixed_passkey_flag + nbranch le_parse_smp_pairing_req_fixed_passkey,blank +le_genernate_tk: + arg mem_le_tk,rega + copy rega,contw + arg 3,loopcnt + call generate_random_loop + fetch 2,mem_le_tk + 2 + and_into 0x7,pdata + store 2,mem_le_tk + 2 +le_parse_smp_pairing_req_fixed_passkey: + jam BT_EVT_LE_TK_GENERATE,mem_fifo_temp + branch ui_ipc_send_event + +le_check_master_support_secure_connect: + fetch 1,mem_le_preq_auth + rtnbit1 LE_AUTH_SECURE_CONNECTION_PAIRING_BIT + fetch 1,mem_le_pairing_mode + rtnbit0 LE_PAIRING_MODE_SECURE_CONNECT_BIT + branch app_ble_disconnect + +le_send_smp_pairing_response: + fetcht 1,mem_le_pres_init_key_distribution + fetch 1,mem_le_preq_init_key_distribution + isolate1 LE_INITATOR_IRK_BIT,pdata + setflag true,LE_INITATOR_IRK_BIT,temp + storet 1,mem_le_pres_init_key_distribution + fetcht 1,mem_le_pres_resp_key_distribution + setflag true,LE_INITATOR_IRK_BIT,temp + storet 1,mem_le_pres_resp_key_distribution + force 7,rega + force LE_L2CAP_CID_SMP,regb + call le_fifo_malloc_tx_l2cap + setarg SMP_PAIRING_RESPONSE + istore 1,contw + fetch 6,mem_le_pres_iocap + istore 6,contw + rtn + + +le_parse_smp_pairing_confirm: +ifdef SECURE_CONNECTION + copy contr,rega + fetch 1,mem_le_pairing_mode + beq LE_PAIRING_MODE_SECURE_CONNECT_PASSKEY,le_parse_smp_pairing_confirm_secure_passkey + copy rega,contr +endif + arg mem_le_rconfirm,contw + call memcpy16 + branch le_send_smp_pairing_confirm +ifdef SECURE_CONNECTION +le_parse_smp_pairing_confirm_secure_passkey: + copy rega,contr + arg mem_le_rconfirm,contw + call memcpy16 + jam LE_SP_FLAG_COMMIT_256,mem_le_secure_connect_flag + jam LE_SC_STAT_PASSKEY_WAIT_CONFIRM,mem_le_secure_connect_state + rtn +endif + + +le_send_smp_pairing_confirm: +ifdef SECURE_CONNECTION + fetch 1,mem_le_pairing_mode + bbit1 LE_PAIRING_MODE_SECURE_CONNECT_BIT,le_send_smp_pairing_confirm_sc +endif + call generate_confirm + force 17,rega + force LE_L2CAP_CID_SMP,regb + call le_fifo_malloc_tx_l2cap + setarg SMP_PAIRING_CONFIRM + istore 1,contw + branch store_aes_result + + +ifdef SECURE_CONNECTION +le_send_smp_pairing_confirm_sc: + arg mem_le_srand,contw + call generate_random + call function_f4_cb + force 17,rega + force LE_L2CAP_CID_SMP,regb + call le_fifo_malloc_tx_l2cap + setarg SMP_PAIRING_CONFIRM + istore 1,contw + branch load_inverse_result + +endif + + +le_parse_smp_pairing_random: +ifdef SECURE_CONNECTION + copy contr,rega + fetch 1,mem_le_pairing_mode + bbit1 LE_PAIRING_MODE_SECURE_CONNECT_BIT,le_parse_smp_pairing_random_sc + copy rega,contr +endif + call authenticate_rconfirm + branch le_parse_smp_pairing_random_success,zero +le_send_pairing_confirm_value_failed: + jam PAIRING_FAILED_CONFIRM_VALUE_FAILED,mem_le_ll_pairing_fail_reason +le_send_pairing_failed: + force 2,rega + force LE_L2CAP_CID_SMP,regb + call le_fifo_malloc_tx_l2cap + setarg SMP_PAIRING_FAILED + istore 1,contw + fetch 1,mem_le_ll_pairing_fail_reason + istore 1,contw +le_parse_smp_pairing_failed: + jam FLAG_LE_PAIRING_NULL,mem_le_pairing_state + jam BT_EVT_LE_PAIRING_FAIL,mem_fifo_temp + branch ui_ipc_send_event + +le_smp_pairing_fail_reason_not_support_pairing: + jam PAIRING_FAILED_PAIRING_NOT_SUPPORTED,mem_le_ll_pairing_fail_reason + branch le_send_pairing_failed + + +ifdef SECURE_CONNECTION +le_parse_smp_pairing_random_sc: + arg mem_le_mrand,contw + copy rega,contr + call memcpy16 + fetch 1,mem_le_pairing_mode + beq LE_PAIRING_MODE_SECURE_CONNECT_PASSKEY,le_parse_smp_pairing_random_sc_passkey + call function_g2 +// jam LE_SC_STAT_RECEIVE_RANDOM,mem_le_secure_connect_state +// jam LE_SP_FLAG_COMMIT_256,mem_le_secure_connect_flag + call le_send_smp_pairing_random + fetch 1,mem_le_pairing_mode + rtnne LE_PAIRING_MODE_SECURE_CONNECT_NUMERIC + jam BT_EVT_LE_GKEY_GENERATE,mem_fifo_temp + branch ui_ipc_send_event + +le_parse_smp_pairing_random_sc_passkey: + call function_f4_ca + arg mem_AES_CMAC_temp,contw + call load_inverse_result + arg mem_AES_CMAC_temp,rega + arg mem_le_rconfirm ,regb + arg 16,loopcnt + call string_compare + nbranch le_send_pairing_confirm_value_failed,zero + branch le_send_smp_pairing_random +endif + +le_parse_smp_pairing_random_success: + call generate_stk + jam BT_EVT_LE_PAIRING_SUCCESS,mem_fifo_temp + call ui_ipc_send_event + jam 1,mem_ltk_exists + jam FLAG_LE_PAIRING_AFTER_AUTH,mem_le_pairing_state + +le_send_smp_pairing_random: + force 17,rega + force LE_L2CAP_CID_SMP,regb + call le_fifo_malloc_tx_l2cap + setarg SMP_PAIRING_RANDOM + istore 1,contw + arg mem_le_srand,contr + branch memcpy16 + +le_parse_smp_encryption_information: + arg mem_le_peer_ltk,contw + branch memcpy16 + +le_send_smp_encryption_information: + force 17,rega + force LE_L2CAP_CID_SMP,regb + call le_fifo_malloc_tx_l2cap + setarg SMP_ENCRYPTION_INFORMATION + istore 1,contw + arg mem_le_ltk,contr + branch memcpy16 + +le_send_smp_master_identification: + arg mem_le_ediv,contw + force 10,loopcnt + call generate_random_loop + force 11,rega + force LE_L2CAP_CID_SMP,regb + call le_fifo_malloc_tx_l2cap + setarg SMP_MASTER_IDENTIFICATION + istore 1,contw + fetch 2,mem_le_ediv + istore 2,contw + fetch 8,mem_le_rand + istore 8,contw + rtn + +le_send_smp_identity_information: + force 17,rega + force LE_L2CAP_CID_SMP,regb + call le_fifo_malloc_tx_l2cap + setarg SMP_IDENTITY_INFORMATION + istore 1,contw + setarg 0 + istore 8,contw + istore 8,contw + rtn + + +le_send_smp_identity_address_information: + force 8,rega + force LE_L2CAP_CID_SMP,regb + call le_fifo_malloc_tx_l2cap + setarg SMP_IDENTITY_ADDRESS_INFORMATION + istore 1,contw + fetch 1,mem_le_conn_own_addr_type + istore 1,contw + fetch 6,mem_le_lap + istore 6,contw + rtn + +le_parse_smp_master_identification: +le_parse_smp_identity_information: +le_parse_smp_identity_address_information: +le_parse_smp_signing_information: +le_parse_smp_security_request: + rtn + +ifdef SECURE_CONNECTION +le_parse_smp_public_key: + arg mem_le_pubkey_remote_x_256,contw + call memcpy64 + jam LE_SP_FLAG_COMMIT_256,mem_le_secure_connect_flag + jam LE_SC_STAT_RECEIVE_PUBLIC_KEY,mem_le_secure_connect_state + rtn + +le_parse_smp_dhkey_check: + arg mem_sp_confirm_remote,contw + call memcpy16 + jam LE_SC_STAT_RECEIVE_DHKEY,mem_le_secure_connect_state + jam LE_SP_FLAG_COMMIT_256,mem_le_secure_connect_flag + rtn + +le_send_smp_pairing_public_key: + force 65,rega + force LE_L2CAP_CID_SMP,regb + call le_fifo_malloc_tx_l2cap + setarg SMP_PAIRING_PUBLIC_KEY + istore 1,contw + arg mem_le_pubkey_local_x_256,contr + branch memcpy64 + +le_send_smp_pairing_dhkey_check: + call function_f6_eb + force 17,rega + force LE_L2CAP_CID_SMP,regb + call le_fifo_malloc_tx_l2cap + setarg SMP_PAIRING_DHKEY_CHECK + istore 1,contw + branch load_inverse_result + +endif + + +le_pairing_sm: + bpatchx patch2d_4,mem_patch2d + fetch 1,mem_le_pairing_state + beq FLAG_LE_PAIRING_START,le_pairing_sm_start + beq FLAG_LE_PAIRING_AFTER_AUTH,le_pairing_sm_after_auth + beq FLAG_LE_PARING_SEND_ENC_INFORMATION,le_pairng_sm_send_enc_information + beq FLAG_LE_PARING_SEND_MASTER_IDENTIFICATION,le_pairng_sm_send_master_indentification + beq FLAG_LE_PARING_SEND_INDENTITY_INFORMATION,le_pairng_sm_send_indentity_information + rtn + + +le_pairing_sm_start: + jam FLAG_LE_PAIRING_SEND_RECURITY_REQ,mem_le_pairing_state + branch le_send_smp_security_request + +le_pairing_sm_after_auth: + fetch 1,mem_le_enc_state + beq FLAG_LE_SEND_START_ENC_RSP,le_pairing_sm_after_auth_start_enc +// jam FLAG_LE_ENC_END,mem_le_enc_state + rtn + +le_pairing_sm_after_auth_start_enc: + jam FLAG_LE_PARING_SEND_ENC_INFORMATION,mem_le_pairing_state + jam BT_EVT_LE_ENC_INFO,mem_fifo_temp + call ui_ipc_send_event + branch le_send_smp_encryption_information + +le_pairng_sm_send_enc_information: + jam FLAG_LE_PARING_SEND_MASTER_IDENTIFICATION,mem_le_pairing_state + branch le_send_smp_master_identification + +le_pairng_sm_send_master_indentification: + fetch 1,mem_le_preq_init_key_distribution + isolate0 LE_INITATOR_IRK_BIT,pdata + branch le_parse_start_enc_rsp_after_auth_end,true + jam FLAG_LE_PARING_SEND_INDENTITY_INFORMATION,mem_le_pairing_state + branch le_send_smp_identity_information + +le_pairng_sm_send_indentity_information: + call le_send_smp_identity_address_information + branch le_parse_start_enc_rsp_after_auth_end +/* + fetch 1,mem_le_conn_peer_addr_type + beq MASTER_PUBLIC_ADDR,app_ble_store_reconn_info + fetch 1,mem_le_plap+5 + compare 0xc0,pdata,0xc0 + branch app_ble_store_reconn_info,true + rtn +*/ +le_parse_start_enc_rsp_after_auth_end: + jam FLAG_LE_ENC_END,mem_le_enc_state + jam FLAG_LE_PAIRING_END,mem_le_pairing_state + rtn + + + +ifdef SECURE_CONNECTION + +le_secure_connect_sm: + bpatchx patch2d_5,mem_patch2d + fetch 1,mem_le_pairing_mode + rtnbit0 LE_PAIRING_MODE_SECURE_CONNECT_BIT + fetch 1,mem_le_secure_connect_flag + rtnne LE_SP_FLAG_COMMIT_256 + jam SP_FLAG_STANDBY,mem_le_secure_connect_flag + fetch 1,mem_le_secure_connect_state + beq LE_SC_STAT_RECEIVE_PUBLIC_KEY,le_sc_sm_receive_public_key + beq LE_SC_STAT_WAIT_SEND_PUBLIC_KEY,le_sc_sm_wait_send_public_key + beq LE_SC_STAT_SEND_PUBLIC_KEY,le_sc_sm_send_public_key + beq LE_SC_STAT_RECEIVE_DHKEY,le_sc_sm_receive_dhkey + beq LE_SC_STAT_WAIT_CONFIRM_GKEY,le_sc_sm_wait_confirm_gkey + beq LE_SC_STAT_PASSKEY_WAIT_CONFIRM,le_sc_sm_passkey_wait_confirm + rtn + + +le_sc_sm_passkey_wait_confirm: + fetch 1,mem_authentication_passkey_times + copy pdata,queue + increase 1,pdata + store 1,mem_authentication_passkey_times + fetch 4,mem_le_tk + qisolate1 pdata + setarg 0x80 + setflag true,0,pdata + store 1,mem_passkey_1bit + branch le_sc_sm_ready_send_pairing_confirm + +le_sc_sm_wait_confirm_gkey: + fetch 1,mem_le_sc_confirm_gkey_flag + jam FLAG_LE_SC_CONFRIM_NULL,mem_le_sc_confirm_gkey_flag + beq FLAG_LE_SC_CONFRIM_GKEY_OK,le_sc_confirm_gkey_ok + jam LE_SP_FLAG_COMMIT_256,mem_le_secure_connect_flag + rtn + +le_sc_confirm_gkey_ok: + jam BT_EVT_LE_PAIRING_SUCCESS,mem_fifo_temp + call ui_ipc_send_event + jam FLAG_LE_PAIRING_AFTER_AUTH,mem_le_pairing_state + branch le_send_smp_pairing_dhkey_check + +le_sc_sm_receive_dhkey: + fetch 1,mem_sp_dhkey_invalid + beq SP_KEY_VALID_256,le_dhkey_ready + jam LE_SP_FLAG_COMMIT_256,mem_le_secure_connect_flag + rtn + +le_dhkey_ready: + call function_f5 +// arg mem_le_r,contw +// force 2,loopcnt +// call memset0 + fetch 1,mem_le_pairing_mode + beq LE_PAIRING_MODE_SECURE_CONNECT_PASSKEY ,le_dhkey_ready_common + call le_set_tk_0 +le_dhkey_ready_common: + call function_f6_ea + arg mem_AES_CMAC_temp,rega + arg mem_sp_confirm_remote ,regb + arg 16,loopcnt + call string_compare + branch le_dhkey_check_ok,zero +le_dhkey_check_fail: + jam PAIRING_FAILED_DHKEY_CHECK_FAILED,mem_le_ll_pairing_fail_reason + branch le_send_pairing_failed + + +le_dhkey_check_ok: + call sp_calc_check_publickey_256 + nbranch le_dhkey_check_fail,zero + jam 1,mem_ltk_exists + fetch 1,mem_le_pairing_mode + beq LE_PAIRING_MODE_SECURE_CONNECT_JUSTWORK,le_sc_confirm_gkey_ok + beq LE_PAIRING_MODE_SECURE_CONNECT_PASSKEY ,le_sc_confirm_gkey_ok + jam LE_SP_FLAG_COMMIT_256,mem_le_secure_connect_flag + jam LE_SC_STAT_WAIT_CONFIRM_GKEY,mem_le_secure_connect_state + rtn + +le_sc_sm_send_public_key: + fetch 1,mem_le_pairing_mode + beq LE_PAIRING_MODE_SECURE_CONNECT_PASSKEY,le_sc_sm_send_public_key_passkey + jam 0,mem_passkey_1bit +le_sc_sm_ready_send_pairing_confirm: + branch le_send_smp_pairing_confirm + +le_sc_sm_send_public_key_passkey: +// jam LE_SP_FLAG_COMMIT_256,mem_le_secure_connect_flag +// jam LE_SC_STAT_PASSKEY_WAIT_CONFIRM,mem_le_secure_connect_state +// branch p_ng_event_le_get_passkey + jam 0,mem_authentication_passkey_times + branch le_parse_smp_pairing_req_passkey + + +le_sc_sm_receive_public_key: + jam LE_SP_FLAG_COMMIT_256,mem_le_secure_connect_flag + fetch 1,mem_le_sc_local_key_invalid + beq SP_KEY_VALID_256,le_public_key_ready +// jam LE_SP_FLAG_COMMIT_256,mem_le_secure_connect_flag + rtn + +le_public_key_ready: + jam LE_SC_STAT_WAIT_SEND_PUBLIC_KEY,mem_le_secure_connect_state + jam SP_KEY_INVALID,mem_sp_dhkey_invalid + branch sp_dhkey_calc_256 + +le_sc_sm_wait_send_public_key: + jam LE_SP_FLAG_COMMIT_256,mem_le_secure_connect_flag + jam LE_SC_STAT_SEND_PUBLIC_KEY,mem_le_secure_connect_state + branch le_send_smp_pairing_public_key + +endif + Index: tag/Soft/Librarier/bt_rom/program/lmp.prog =================================================================== --- /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/lmp.prog (nonexistent) +++ /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/lmp.prog (working copy) @@ -0,0 +1,2900 @@ + +/******************************************/ +/************* LMP Parse **************/ +/******************************************/ +init_lmp: + rtn wake +init_lmp_work: + bpatchx patch2d_6,mem_patch2d + setarg 0 + store 1,mem_lmp_to_send + store 1,mem_reconn_lmp_sm + store 1,mem_lmo_opcode1 + store 1,mem_lmo_opcode2 + store 1,mem_connection_options + store 1,mem_pairing_auth + store 1,mem_esco_amaddr + jam SWITCH_FLAG_INIT,mem_switch_flag + jam 0,mem_switch_fail_master_count + jam NULL_ENCRYP,mem_wait_encryption +init_lmp_reinit: + jam 0,mem_pairing_auth + jam 0,mem_sp_localsm + jam 0,mem_lmp_conn_state + fetch 1,mem_device_option + rtnne dvc_op_hci,pdata + jam 0,mem_link_key_exists + //fall through +parse_rx_done: + rtn + +parse_lmp: + bpatchx patch2d_7,mem_patch2d + call setlocalsm_master,master //use this flag in hci + ncall setlocalsm_slave,master + fetch 1,mem_lmo_opcode2 + ncall lmo_fifo_process,blank + fetch 1,mem_lmo_opcode2 + nrtn blank +parse_lmp_tws: + fetch 1,mem_state_map + rtnbit0 smap_rxlmp + set0 smap_rxlmp,pdata + set0 mark_rxbuf_inuse,mark + store 1,mem_state_map + fetch 1,mem_rxbuf + fetcht 1,mem_state_map + isolate1 smap_lmptidinit,pdata + setflag true,smap_lmptid,temp + storet 1,mem_state_map + and_into 0x2,temp //smap_lmptid only + storet 1,mem_lmo_tid2 + fetcht 1,mem_state_map + rshift pdata,pdata /* align lmp_opcode */ + store 1,mem_lmi_opcode2 +parse_lmp_process: + bpatchx patch2e_0,mem_patch2e + // set flag + arg LOG_POINT_1000,rega + fetcht 2,mem_rxbuf + call debug_log_print + fetch 1,mem_lmi_opcode2 + beq LMP_ESCAPE,parse_lmp_escape//multi + beq LMP_ACCEPTED,parse_lmp_accepted//multi + beq LMP_NOT_ACCEPTED,parse_lmp_not_accepted//multi + beq LMP_SET_AFH, parse_lmp_set_afh + beq LMP_CLKOFFSET_REQ, parse_lmp_clkoffset_req + beq LMP_ENCRYPTION_MODE_REQ, parse_lmp_encryption_mode_req + beq LMP_ENCRYPTION_KEY_SIZE_REQ,parse_lmp_crypt_key + beq LMP_AUTO_RATE,parse_lmp_auto_rate + beq LMP_TEST_CONTROL,parse_lmp_test_control//multi + beq LMP_TEST_ACTIVATE,parse_lmp_test_activate + beq LMP_SETUP_COMPLETE,parse_lmp_setup_complete + beq LMP_SUPERVISION_TIMEOUT,parse_lmp_supervision_timeout + beq LMP_FEATURES_REQ,parse_lmp_features_req + beq LMP_HOST_CONNECTION_REQ,parse_lmp_conn_req + beq LMP_VERSION_REQ,parse_lmp_version_req + beq LMP_VERSION_RES,parse_lmp_version_res + beq LMP_DETACH,parse_lmp_detach + beq LMP_MAX_SLOT,parse_lmp_max_slot + beq LMP_MAX_SLOT_REQ,parse_lmp_max_slot_req + beq LMP_NAME_REQ,parse_lmp_name_req + beq LMP_NAME_RES,parse_lmp_name_res + beq LMP_FEATURES_RES,parse_lmp_features_res + beq LMP_COMB_KEY,parse_lmp_comb_key + beq LMP_AU_RAND, parse_lmp_au_rand + beq LMP_IN_RAND,parse_lmp_in_rand + beq LMP_SRES,parse_lmp_sres + beq LMP_INCR_POWER_REQ,parse_lmp_incr_power + beq LMP_DECR_POWER_REQ,parse_lmp_decr_power + beq LMP_MAX_POWER, parse_lmp_max_power + beq LMP_MIN_POWER, parse_lmp_min_power + beq LMP_PAGE_MODE_REQ, parse_lmp_page_mode_req + beq LMP_PAGE_SCAN_MODE_REQ, parse_lmp_page_scan_mode_req + beq LMP_PREFERRED_RATE, parse_lmp_preferred_rate + beq LMP_SLOT_OFFSET, parse_lmp_slot_offset + beq LMP_SNIFF_REQ, parse_lmp_sniff_req + beq LMP_START_ENCRYPTION_REQ, parse_lmp_start_encryption_req + beq LMP_STOP_ENCRYPTION_REQ, parse_lmp_stop_encryption_req + beq LMP_SWITCH_REQ, parse_lmp_switch_req + beq LMP_TEMP_RAND, parse_lmp_temp_rand + beq LMP_TEMP_KEY, parse_lmp_temp_key + beq LMP_TIMING_ACCURACY_REQ, parse_lmp_timing_accuracy_req + beq LMP_TIMING_ACCURACY_RES, parse_lmp_timing_accuracy_res + beq LMP_UNIT_KEY, parse_lmp_unit_key + beq LMP_UNSNIFF_REQ, parse_lmp_unsniff_req + beq LMP_USE_SEMI_PERMANENT_KEY, parse_lmp_use_semi_permanend_key + beq LMP_ENCAPSULATED_HEADER,parse_lmp_encapsulated_header + beq LMP_ENCAPSULATED_PAYLOAD,parse_lmp_encapsulated_payload + beq LMP_SIMPLE_PAIRING_CONFIRM,parse_simple_pairing_confirm + beq LMP_SIMPLE_PAIRING_NUMBER,parse_lmp_simple_pairing_number + beq LMP_DHKEY_CHECK,parse_dhkey_check + beq LMP_CLKOFFSET_RES, parse_lmp_clkoffset_res + beq LMP_ENC_KEY_SIZE_MASK_REQ,parse_enc_key_size_mask_req + beq LMP_SCO_LINK_REQ, parse_lmp_sco_link_req + beq LMP_REMOVE_SCO_LINK_REQ,parse_remove_sco_link + beq LMP_QUALITY_OF_SERVICE_REQ,parse_quality_of_server_req + beq LMP_QUALITY_OF_SERVICE,parse_quality_of_server +/* lmp is not recognized, check to see if we respond to all messages */ +/* rejecting the unrecognized message with PDU not recognized */ +reject_unknown_packet: + jam UNKNOWN_LMP_PDU,mem_lmo_reason2 +reject_lmp_packet: + jam LMP_NOT_ACCEPTED,mem_lmo_opcode2 + rtn + +parse_lmpext_remove_esco_req: + call lmp_exit_sco_sniff + jam LMP_EXT_ACCEPTED,mem_lmo_opcode2 + jam LMP_EXT_REMOVE_ESCO_REQ,mem_lmi_opcode2 + rtn + +parse_lmpext_esco_link_req_master: + jam 1,mem_neogotiation_state + branch app_bt_esco_req + +parse_lmpext_esco_link_req: + branch parse_lmpext_esco_link_req_master,master + fetch 1,mem_rxbuf+2 + store 1,mem_sco_handle + + fetch 1,mem_rxbuf+3 + store 1,mem_esco_amaddr + + fetch 1,mem_rxbuf+5 + lshift pdata,pdata + store 2,mem_sco_dsniff + + fetch 1,mem_rxbuf+6 + lshift pdata,pdata + store 2,mem_sco_tsniff + + fetch 1,mem_rxbuf+7 + store 1,mem_sco_wsniff + + fetch 1,mem_rxbuf+8 + store 1,mem_sco_tx_packet_type + + fetch 1,mem_rxbuf+9 + store 1,mem_sco_rx_packet_type + + fetch 2, mem_rxbuf+10 + store 2,mem_sco_tx_packet_len + fetch 2, mem_rxbuf+12 + store 2,mem_sco_rx_packet_len + + fetch 1,mem_rxbuf+14 + store 1,mem_air_mode + beq AIR_MODE_CVSD ,parse_lmpext_esco_link_req_cvsd + beq AIR_MODE_TRANSPARENT_DATA,parse_lmpext_esco_link_req_msbc + branch lmpext_esco_reject +parse_lmpext_esco_link_req_cvsd: + fetch 1,mem_codec_type + beq CODEC_TYPE_CVSD,parse_lmpext_esco_link_req2 + branch lmpext_esco_reject + +parse_lmpext_esco_link_req_msbc: + fetch 1,mem_codec_type + beq CODEC_TYPE_mSBC,parse_lmpext_esco_link_req2 + branch lmpext_esco_reject + +parse_lmpext_esco_link_req2: + fetch 1,mem_sco_rx_packet_type + beq esco_type_ev3,lmpext_esco_accept_ev3 + beq esco_type_2ev3,lmpext_esco_accept_2ev3 +lmpext_esco_reject: + jam LMP_NOT_ACCEPTED_EXT,mem_lmo_opcode2 +lmpext_esco_link_req_end: + jam LMP_EXT_ESCO_LINK_REQ,mem_lmi_opcode2 + rtn +lmpext_esco_accept_2ev3: + set1 mark_esco_edr_enable,mark +lmpext_esco_accept_ev3: + jam LMP_EXT_ACCEPTED,mem_lmo_opcode2 + branch lmpext_esco_link_req_end + + +parse_lmp_sco_link_req: + branch app_bt_sco_req,master + fetch 1,mem_rxbuf+1 + store 1,mem_sco_handle + + fetch 1,mem_rxbuf+3 + lshift pdata,pdata + store 2,mem_sco_dsniff + + fetch 1,mem_rxbuf+4 + lshift pdata,pdata + store 2,mem_sco_tsniff + + fetch 1,mem_rxbuf+5 + store 1,mem_sco_rx_packet_type + store 1,mem_sco_tx_packet_type + + fetch 1,mem_rxbuf+6 + store 1,mem_air_mode + + beq AIR_MODE_CVSD ,parse_lmp_sco_link_req_cvsd + beq AIR_MODE_TRANSPARENT_DATA,parse_lmp_sco_link_req_msbc + branch parse_lmp_sco_link_req_reject +parse_lmp_sco_link_req_cvsd: + fetch 1,mem_codec_type + beq CODEC_TYPE_CVSD,parse_lmp_sco_link_req2 + branch parse_lmp_sco_link_req_reject + +parse_lmp_sco_link_req_msbc: + fetch 1,mem_codec_type + beq CODEC_TYPE_mSBC,parse_lmp_sco_link_req2 +parse_lmp_sco_link_req_reject: + jam LMP_NOT_ACCEPTED,mem_lmo_opcode2 + jam LMP_SCO_LINK_REQ,mem_lmi_opcode2 + rtn + +parse_lmp_sco_link_req2: + setarg 30 + store 2,mem_sco_rx_packet_len + store 2,mem_sco_tx_packet_len + jam LMP_ACCEPTED,mem_lmo_opcode2 + jam LMP_SCO_LINK_REQ,mem_lmi_opcode2 + rtn + +lmp_exit_sco_sniff: + call load_context_to_acl + set0 mark_sco_flag,mark + set0 mark_esco_edr_enable,mark + set0 mark_esco,mark + set0 mark_enter_sco_sniff,mark + fetch 1,mem_mode + set0 sco_in_sniff,pdata + store 1,mem_mode + call HFP_clear_sco_params + jam 5,mem_max_slot + call sniff_exit + call HFP_voice_stop + call HFP_voice_stop_notify + fetch 1,mem_mode + rtnbit0 acl_in_sniff + branch lmp_enter_acl_sniff + +parse_remove_sco_link: + call lmp_exit_sco_sniff + jam LMP_REMOVE_SCO_LINK_REQ,mem_lmi_opcode2 + jam LMP_ACCEPTED,mem_lmo_opcode2 + rtn + +parse_quality_of_server_req: + jam LMP_QUALITY_OF_SERVICE_REQ,mem_lmi_opcode2 + jam LMP_ACCEPTED,mem_lmo_opcode2 + rtn + +parse_quality_of_server: + rtn + +parse_lmp_clkoffset_req: + jam LMP_CLKOFFSET_RES,mem_lmo_opcode2 + rtn + +parse_enc_key_size_mask_req: + jam LMP_ENC_KEY_SIZE_MASK_RES,mem_lmo_opcode2 + rtn + +parse_lmp_set_afh: + fetch 4,mem_rxbuf+1 + lshift pdata,pdata + store 4,mem_afh_instant + fetch 1,mem_rxbuf+5 + store 1,mem_afh_new_mod + fetch 5,mem_rxbuf+6 + store 5,mem_afh_map_new + fetch 5,mem_rxbuf+11 + istore 5,contw + fetch 1,mem_mode + set1 afh_change,pdata + store 1,mem_mode + rtn +parse_lmp_escape: + bpatchx patch2e_1,mem_patch2e + fetch 1,mem_rxbuf+1 + set1 7,pdata + store 1,mem_lmi_opcode2 + beq LMP_EXT_ACCEPTED,parse_lmpext_accepted + beq LMP_NOT_ACCEPTED_EXT,parse_lmpext_not_accepted + beq LMP_SNIFF_SUBRATING_REQ, parse_lmp_sniff_subrating_req + beq LMP_SNIFF_SUBRATING_RES, parse_lmp_sniff_subrating_res + beq LMP_PACKET_TYPE_TABLE_REQ,parse_lmpext_packet_type_table_req + beq LMP_EXT_FEATURES_REQ,parse_lmpext_features_req + beq LMP_EXT_FEATURES_RES,parse_lmpext_features_res + beq LMP_EXT_CHN_CLASSIFICATION_REQ,parse_lmpext_chn_classification_req + beq LMP_PAUSE_ENCRYPTION_REQ,parse_lmpext_pause_encrypt + beq LMP_RESUME_ENCRYPTION_REQ,parse_lmpext_resume_encrypt + beq LMP_IO_CAP_REQ,parse_lmpext_iocap_req + beq LMP_IO_CAP_RES,parse_lmpext_iocap_res + beq LMP_EXT_REMOVE_ESCO_REQ,parse_lmpext_remove_esco_req + beq LMP_EXT_ESCO_LINK_REQ,parse_lmpext_esco_link_req + rtneq LMP_EXT_FEATURES_RES + + +reject_unknown_ext_packet: + jam LMP_NOT_ACCEPTED_EXT,mem_lmo_opcode2 + jam UNKNOWN_LMP_PDU,mem_lmo_reason2 + + rtn +parse_lmpext_chn_classification_req: + jam LMP_NOT_ACCEPTED_EXT,mem_lmo_opcode2 + jam NOT_SUPPORT_CHN_CLASSIFICATION,mem_lmo_reason2 + rtn + +parse_lmpext_iocap_req: + call iocap_lmpext_load + fetch 1,mem_device_option + beq dvc_op_hci,iocap_lmpext_hci + jam LMP_IO_CAP_RES,mem_lmo_opcode2 + rtn + +parse_lmpext_iocap_res: + call iocap_lmpext_load + fetch 1,mem_device_option + beq dvc_op_hci,iocap_lmpext_hci + branch iocap_lmpext_common + +iocap_lmpext_load: + arg mem_sp_iocap_remote,contw + fetch 3, mem_rxbuf+2 + istore 3,contw + rtn + +iocap_lmpext_hci: +iocap_lmpext_common: + call check_localsm +ifdef SIMPLE_PAIRING + branch master_set_mem_master_sp_flag,true//is un very ok to use master flag,but we have to add many codes if wo don't +endif + rtn +parse_lmpext_accepted: + fetch 1,mem_rxbuf+3 + set1 7,pdata + store 1,mem_lmi_accepted_opcode + beq LMP_PACKET_TYPE_TABLE_REQ,parse_lmpext_accepted_ptt + beq LMP_EXT_ESCO_LINK_REQ,parse_lmpext_accepted_esco_link + beq LMP_EXT_REMOVE_ESCO_REQ,parse_lmpext_remove_esco_link + rtn + +parse_lmp_accept_remove_sco_link: +parse_lmpext_remove_esco_link: + branch lmp_exit_sco_sniff + +parse_lmpext_not_accepted: + fetch 1,mem_rxbuf+3 + set1 7,pdata + store 1,mem_lmi_accepted_opcode + beq LMP_PACKET_TYPE_TABLE_REQ,parse_lmpext_not_accepted_ptt + beq LMP_EXT_ESCO_LINK_REQ,HFP_clear_sco_params + rtn + +parse_lmpext_accepted_ptt: + fetch 1,mem_ptt + fetcht 1,mem_state_map + nsetflag blank,smap_edr,temp + storet 1,mem_state_map +parse_lmpext_not_accepted_ptt: + fetch 1,mem_state + rtnbit0 state_init_seq + set0 state_init_seq,pdata + store 1,mem_state + jam LMP_SETUP_COMPLETE,mem_lmo_opcode2 + rtn + +parse_lmpext_pause_encrypt: + nbranch parse_lmpext_pause_encrypt_slave, master + jam LMP_STOP_ENCRYPTION_REQ,mem_lmo_opcode2 + branch tid_reply + +parse_lmpext_pause_encrypt_slave: + jam LMP_PAUSE_ENCRYPTION_REQ, mem_lmo_opcode2 + rtn + +parse_lmpext_resume_encrypt: +//trans file to pc may cause pause/resume encrypt +//if ms is conn_sm_wait_end the controllor won't send ack after recieved start_encypt_accept + call tid_reply + branch lmp_start_encryption + +parse_lmpext_features_req: + jam LMP_EXT_FEATURES_RES,mem_lmo_opcode2 + rtn + +parse_lmpext_features_res: + fetcht 1,mem_rxbuf+4 + and temp,0x1,temp + storet 1,mem_remote_sppcap + fetch 1,mem_hci_cmd + bne hci_cmd_wait_remote_ext_feature,parse_lmpext_features_res_not_hci + jam 0,mem_hci_cmd +parse_lmpext_features_res_not_hci: + fetch 1,mem_reconn_lmp_sm + rtnne CONN_SM_WAIT_FEATURES_EXT + jam CONN_SM_SEND_CONN_REQ,mem_reconn_lmp_sm + branch process_conn_sm + +parse_lmp_accepted: + bpatchx patch2e_2,mem_patch2e + fetch 1,mem_rxbuf+1 + store 1,mem_lmi_accepted_opcode + beq LMP_HOST_CONNECTION_REQ,parse_lmp_accepted_hostconn//ok + beq LMP_IN_RAND,parse_lmp_accepted_inrand//ok + beq LMP_ENCRYPTION_MODE_REQ,parse_lmp_accepted_enc_mode//ok + beq LMP_ENCRYPTION_KEY_SIZE_REQ,parse_lmp_accepted_enc_keysize//ok + beq LMP_START_ENCRYPTION_REQ,parse_lmp_accepted_start_enc//ok + beq LMP_STOP_ENCRYPTION_REQ,parse_lmp_accepted_stop_enc//ok + beq LMP_UNSNIFF_REQ,parse_lmp_accepted_unsniff_req//ok + beq LMP_SNIFF_REQ,parse_lmp_accepted_sniff_req//ok + beq LMP_SWITCH_REQ,parse_lmp_accepted_switch + beq LMP_SCO_LINK_REQ,parse_lmp_accepted_sco_link + beq LMP_REMOVE_SCO_LINK_REQ,parse_lmp_accept_remove_sco_link + // simple pairing + beq LMP_ENCAPSULATED_HEADER,parse_lmp_accepted_encapsulated_header//ok + beq LMP_ENCAPSULATED_PAYLOAD,parse_lmp_accepted_encapsulated_payload//ok + beq LMP_SIMPLE_PAIRING_NUMBER,parse_lmp_accepted_simple_pairing_number//ok + beq LMP_DHKEY_CHECK,parse_lmp_accepted_dhkey_check//ok + rtn + +parse_lmp_not_accepted: + bpatchx patch2e_3,mem_patch2e + fetch 1,mem_rxbuf+1 + store 1,mem_lmi_accepted_opcode + beq LMP_NAME_REQ,parse_lmp_not_accepted_name_req//ok + beq LMP_HOST_CONNECTION_REQ,parse_lmp_not_accepted_hostconn//ok + beq LMP_AU_RAND,parse_lmp_not_accepted_aurand//ok + beq LMP_IN_RAND,parse_lmp_not_accepted_inrand//ok + beq LMP_SWITCH_REQ,parse_lmp_not_accepted_switch//ok + beq LMP_SCO_LINK_REQ,parse_lmp_not_accepted_sco_link_req + /* simple pairing support */ + beq LMP_SIMPLE_PAIRING_NUMBER,parse_lmp_not_accepted_simple_pairing_number//ok + beq LMP_DHKEY_CHECK,parse_lmp_not_accepted_dhkey_check//ok + beq LMP_UNSNIFF_REQ,parse_lmp_not_accepted_unsniff_req + beq LMP_SNIFF_REQ,parse_lmp_not_acdcept_sniff_req + rtn + +parse_lmp_not_accepted_switch: + jam SWITCH_FLAG_NOT_ACCEPT,mem_switch_flag + branch app_bt_role_switch + +parse_lmp_not_accepted_sco_link_req: + jam LMP_SCO_LINK_REQ,mem_lmo_opcode2 + rtn + +parse_lmpext_accepted_esco_link: + fetch 1,mem_sco_rx_packet_type + beq esco_type_ev3,send_lmpext_accept_esco_link + set1 mark_esco_edr_enable,mark +send_lmpext_accept_esco_link: + set1 mark_esco,mark +send_lmp_accepted_sco_link: +parse_lmp_accepted_sco_link: + jam 1,mem_max_slot +lmp_enter_sco_sniff: + fetch 1,mem_mode + set1 sco_in_sniff,pdata + store 1,mem_mode + bbit0 acl_in_sniff,lmp_enter_sco_sniff0 + call sniff_exit +lmp_enter_sco_sniff0: + set1 mark_sco_flag,mark + fetch 1, mem_sco_tsniff + store 2,mem_tsniff + + fetch 1,mem_sco_dsniff + store 2,mem_dsniff + + fetch 1,mem_sco_tsniff + rshift2 pdata,pdata + beq 3,lmp_enter_sco_sniff_end + increase -1,pdata +lmp_enter_sco_sniff_end: + store 1,mem_sniff_attempt + store 1,mem_current_sniff_attempt + fetcht 1,mem_sco_wsniff + rshift temp,temp + isub temp,temp + storet 1,mem_esco_attempt + jam 0,mem_sniff_timeout + call sniff_init + + jam 0x50,mem_esco_arq + jam param_sco_poll,mem_sco_poll + call HFP_voice_start + branch HFP_voice_start_notify + + +parse_lmp_accepted_switch: + branch role_switch_prepare0 + + +parse_lmp_accepted_hostconn: + fetch 1,mem_lmp_conn_state + set1 RECEIVED_CONN_REQ,pdata + store 1,mem_lmp_conn_state + jam BT_EVT_BB_CONNECTED,mem_fifo_temp + call ui_ipc_send_event + jam LMP_PACKET_TYPE_TABLE_REQ,mem_lmo_opcode2 + rtn + + +parse_lmp_not_accepted_hostconn: + jam ACL_CONNECTION_ALREADY_EXISTS,mem_disconn_reason_send + jam LMP_DETACH,mem_lmo_opcode2 + force HCI_ERROR_HOST_TIMEOUT,temp + /* clearing connection state machine */ + jam CONN_SM_STANDBY,mem_reconn_lmp_sm + /* sending error message to host */ + branch parse_rx_done,true + rtn + + +parse_lmp_accepted_inrand: + fetch 1,mem_link_key_exists + nrtn blank + call clear_linkkey + call lmp_generate_key + rtn master + set1 mark_slave_in_rand_accepted,mark + rtn + +parse_lmp_accepted_enc_mode: + nrtn master + jam LMP_ENCRYPTION_KEY_SIZE_REQ,mem_lmo_opcode2 + fetch 1,mem_state_map + rtnbit0 smap_encryption + jam LMP_STOP_ENCRYPTION_REQ,mem_lmo_opcode2 + rtn + +parse_lmp_accepted_enc_keysize: + branch lmp_start_encryption + +parse_lmp_accepted_start_enc: + fetch 1,mem_state + rtnbit1 state_conn_comp + jam LMP_SETUP_COMPLETE,mem_lmo_opcode2 + fetch 1,mem_reconn_lmp_sm + rtnne CONN_SM_ENCRYPT_WAIT + jam CONN_SM_ENCRYPT_WAIT_CLEAR,mem_reconn_lmp_sm + rtn + +parse_lmp_accepted_stop_enc: + /* again this won't work with multipoint. keep track of anyone else encrypting */ + //jam HOST_STOP_ENCRYPTION,message_queue_B0 + //jam 1,message_queue_B1 + //jam HOST_RETURN_SUCCESS,message_queue_B2 + //fetch 1,mem_lmp_state2 + //set1 MESSAGE_QUEUE,pdata + //store 1,mem_lmp_state2 + rtn + +parse_lmp_not_accepted_aurand: + fetch 1,mem_device_option + bne dvc_op_hci,parse_lmp_not_accepted_aurand_send_detach + fetch 1,mem_link_key_exists + rtn blank + fetcht 1,mem_reconn_lmp_sm + jam 0,mem_reconn_lmp_sm + jam 0,mem_link_key_exists + fetch 1,mem_rxbuf+2 + rtnne KEY_MISSING + storet 1,mem_reconn_lmp_sm + jam LOCAL_STATEMACHINE,mem_sp_localsm + fetch 2,mem_lmpext_ssp_enable + fetcht 1,mem_remote_sppcap + iand temp,pdata + branch cmd_pair,blank + branch cmd_ssp + +parse_lmp_not_accepted_aurand_send_detach: + jam BT_EVT_DISCONNECT_KEY_ERROR,mem_fifo_temp + call ui_ipc_send_event + + jam LMP_DETACH,mem_lmo_opcode2 + jam OTHER_END_TERMINATED,mem_disconn_reason_send + rtn +/*in pair remote cancel the pair*/ +parse_lmp_not_accepted_inrand: + fetch 1,mem_rxbuf+2 + beq KEY_MISSING,parse_lmp_inrand_key_missing + rtnne PAIRING_NOT_ALLOWED + jam PAIRING_NOT_ALLOWED,mem_disconn_reason_send + jam LMP_DETACH,mem_lmo_opcode2 + rtn +parse_lmp_inrand_key_missing: + jam BT_EVT_DISCONNECT_KEY_MISSING,mem_fifo_temp + call ui_ipc_send_event + jam KEY_MISSING,mem_disconn_reason_send + jam LMP_DETACH,mem_lmo_opcode2 + rtn + +parse_lmp_not_accepted_name_req: + rtn + +parse_lmp_not_accepted_simple_pairing_number: + jam SP_STAT_NULL,mem_sp_state + jam LMP_DETACH,mem_lmo_opcode2 + branch parse_rx_done + +parse_lmp_not_accepted_dhkey_check: + jam SP_STAT_NULL,mem_sp_state + jam LMP_DETACH,mem_lmo_opcode2 + branch parse_rx_done +parse_lmp_not_accepted_unsniff_req: + rtn + +parse_lmp_accepted_unsniff_req: + branch lmp_exit_acl_sniff + +parse_lmp_accepted_sniff_req: + branch lmp_enter_acl_sniff + + +parse_lmp_not_acdcept_sniff_req: + rtn + +parse_lmp_crypt_key: + fetcht 1,mem_rxbuf+1 + storet 1,mem_key_size + branch accept_lmp_msg + +parse_lmp_setup_complete: + fetch 1,mem_lmp_conn_state + set1 RECEIVED_SETUP_COMPLETE,pdata + store 1,mem_lmp_conn_state + rtnbit1 SENT_SETUP_COMPLETE + jam LMP_SETUP_COMPLETE,mem_lmo_opcode2 + branch parse_rx_done + +parse_lmp_max_slot: + //jam LMP_MAX_SLOT,mem_lmi_opcode2 + //branch accept_lmp_msg + rtn + +parse_lmp_max_slot_req: + fetch 1,mem_max_slot + fetcht 1,mem_rxbuf+1 + isub temp,null + //jam LMP_MAX_SLOT_REQ,mem_lmi_opcode2 + branch accept_lmp_msg,positive + jam LMP_NOT_ACCEPTED,mem_lmo_opcode2 + jam UNSPECIFIED_ERROR,mem_lmo_reason2 + jam LMP_MAX_SLOT_REQ,mem_lmi_opcode2 + rtn + +parse_lmp_detach: + call prepare_disconnect + branch accept_lmp_msg + +accept_lmp_msg: + jam LMP_ACCEPTED,mem_lmo_opcode2 + rtn + +parse_lmp_incr_power: + jam LMP_MAX_POWER,mem_lmo_opcode2 + rtn + +parse_lmp_decr_power: + jam LMP_MIN_POWER,mem_lmo_opcode2 + rtn + +parse_lmp_version_res: + /* continuing on with host connection state machine */ + jam CONN_SM_SEND_FEATURES ,mem_reconn_lmp_sm + /* we need to move fast and send au_rand...jumping to next part of state machine for conn */ + rtn + + +parse_lmp_auto_rate: + rtn + +parse_lmp_in_rand: + call lmp_copy_rand + jam pincode_state_wait_pincode,mem_pincode_state + fetch 1,mem_device_option + beq dvc_op_hci,parse_lmp_in_rand_hci + jam BT_EVT_PINCODE_REQ,mem_fifo_temp + call ui_ipc_send_event +parse_lmp_in_rand_hci: + call tid_check + nbranch lmp_accept_inrand,true + nbranch parse_lmp_inrand_res,master // ignore this because of not ssp temporary + jam LMP_NOT_ACCEPTED,mem_lmo_opcode2 + jam LMP_IN_RAND,mem_lmi_opcode2 + jam TRANSACTION_COLLISION,mem_lmo_reason2 + rtn +parse_lmp_inrand_res: + fetch 1,mem_op + set1 op_inrand_req,pdata + store 1,mem_op + rtn + +//store current tid +pop_tid_follow: + fetcht 1,mem_state_map + nsetflag blank,smap_lmptid,temp + storet 1,mem_state_map + rtn + +//restore current tid +push_tid_follow: + fetch 1,mem_lmo_tid2 + rshift pdata,pdata + and_into 1,pdata + rtn + +parse_lmp_au_rand: + fetch 1,mem_pairing_auth + call nv_load_device_list,blank + call push_tid_follow + store 1,mem_sres_tid + call lmp_copy_rand + jam LMP_SRES,mem_lmo_opcode2 + fetch 1,mem_link_key_exists + nrtn blank + fetch 1,mem_state + rtnbit1 state_combkey /* we have comb key, but not verified */ + jam KEY_MISSING,mem_lmo_reason2 + fetch 1,mem_device_option + bne dvc_op_hci,reject_lmp_packet + jam 0,mem_lmo_opcode2 +parse_lmp_inrand_sres: + fetch 1,mem_op + set1 op_send_sres,pdata + store 1,mem_op + rtn + +parse_lmp_sres: + arg mem_plap,rega + call function_e1 + fetch 4,mem_rxbuf+1 + fetcht 4,mem_input_store + isub temp,null + branch authentication_ok,zero + jam LMP_DETACH,mem_lmo_opcode2 + jam AUTHENTICATION_FAILURE_ERROR,mem_disconn_reason_send + rtn +authentication_ok: + call authentication_ok_common + fetch 1,mem_reconn_lmp_sm + sub pdata,CONN_SM_AUTH_WAIT,null + call authentication_ok_conn_sm,zero + fetch 1,mem_ssp_enable + branch pairing_success,blank + rtn + +authentication_ok_conn_sm: + fetch 1,mem_pairing_auth + rtnne DEFALT_PAIRING_AUTH + fetch 1,mem_state_map + rtnbit1 smap_encryption + branch host_create_conn_encrypt + +authentication_ok_common: + call copy_aco + call linkkey_ready///save link key + fetch 1,mem_op + isolate1 op_auth_req,pdata + set0 op_auth_req,pdata + store 1,mem_op + rtn + + +parse_lmp_comb_key: + arg mem_rxbuf+1,rega + arg mem_kinit,regb + arg mem_random_number,contw + call xor16 + arg mem_plap,rega + call generate_linkkey + jam LMP_AU_RAND,mem_lmo_opcode2 + fetch 1,mem_state + bbit0 state_combkey,lmp_generate_key + rtn + +parse_lmp_name_res: + fetch 2,mem_len + add pdata,-3,loopcnt //for remote name length error + fetcht 1,mem_rxbuf+1 + setarg mem_tmp_buffer + iadd temp,contw + arg mem_rxbuf+3,contr + call memcpy + fetcht 1,mem_name_offset + fetch 1,mem_rxbuf+2 + isub temp,pdata + sub pdata,14,null + branch parse_lmp_name_res_end,positive + add temp,14,pdata + store 1,mem_name_offset + jam LMP_NAME_REQ,mem_lmo_opcode2 + rtn +parse_lmp_name_res_end: + fetch 1,mem_state_map + set1 smap_name_res,pdata + store 1,mem_state_map + bbit1 smap_name_req,lmp_disconnect + //force HCI_SUCCESS,queue + //branch hci_send_name + rtn +parse_lmp_name_req: + fetch 1,mem_rxbuf+1 + store 1,mem_lmi_opcode2 //offset + jam LMP_NAME_RES,mem_lmo_opcode2 + rtn + +parse_lmp_conn_req: + branch accept_lmp_msg + + +parse_lmp_timing_accuracy_req: + jam LMP_TIMING_ACCURACY_RES,mem_lmo_opcode2 + rtn + +parse_lmp_features_req: + jam LMP_FEATURES_RES,mem_lmo_opcode2 + rtn + +parse_lmp_version_req: + jam LMP_VERSION_RES,mem_lmo_opcode2 + rtn + +parse_lmp_supervision_timeout: +// fetch 2,mem_rxbuf+1 +// store 2,mem_supervision_to + rtn + + + +parse_lmp_sniff_subrating_req: + fetch 2,mem_tsniff + iforce temp + fetch 1,mem_rxbuf+2 + store 1,mem_subsniff_rate + imul32 temp,temp + fetch 2,mem_rxbuf+3 + lshift pdata,pdata + store 2,mem_subsniff_tcmax + fetch 4,mem_rxbuf+5 + lshift pdata,pdata + store 4,mem_subsniff_instant + //product pdata + deposit temp + store 2,mem_subsniff_tsniff + rtn +parse_lmpext_packet_type_table_req: + fetcht 1,mem_ptt + fetch 1,mem_rxbuf+2 + ixor temp,null + nbranch reject_unknown_ext_packet,zero + isolate1 0,pdata + fetch 1,mem_state_map + setflag true,smap_edr,pdata + store 1,mem_state_map + jam LMP_EXT_ACCEPTED,mem_lmo_opcode2 + jam LMP_PACKET_TYPE_TABLE_REQ,mem_lmi_opcode2 + rtn + + +parse_lmp_sniff_subrating_res: + rtn + +parse_lmp_max_power: + rtn +parse_lmp_min_power: + rtn +parse_lmp_page_mode_req: + //jam LMP_PAGE_MODE_REQ,mem_lmi_opcode2 + branch accept_lmp_msg +parse_lmp_page_scan_mode_req: + //this can influence connection. need accepted + //jam LMP_PAGE_SCAN_MODE_REQ,mem_lmi_opcode2 + branch accept_lmp_msg +parse_lmp_preferred_rate: + rtn + +parse_lmp_slot_offset: + fetch 2,mem_rxbuf+1 + store 2,mem_slot_offset + rtn + +parse_lmp_sniff_req: + fetch 1,mem_mode + bbit1 acl_in_sniff,lmp_reject_sniff + bmark1 mark_sco_flag,lmp_reject_sniff + fetch 2,mem_rxbuf+6 + branch lmp_reject_sniff,blank + fetch 1,mem_hf_call_state + bne HFP_NONO,lmp_reject_sniff + fetcht 2,mem_rxbuf+4 //tsniff + arg 0x40,pdata + isub temp,pdata + branch parse_lmp_sniff_request,positive + call lmp_reject_sniff + setarg 0x40 + store 2,mem_sniff_param_interval + setarg 0x10001 + store 4,mem_sniff_param_attempt + branch app_bt_enter_sniff + + +parse_lmp_sniff_request: + fetch 2,mem_rxbuf+2 /* dsniff */ + lshift pdata,pdata + store 2,mem_acl_dsniff + fetch 2,mem_rxbuf+4 /* tsniff */ + lshift pdata,pdata + store 2,mem_acl_tsniff + fetch 2,mem_rxbuf+6 /* sniff attempt */ + store 1,mem_acl_attempt + iforce temp + fetch 2,mem_rxbuf+8 /* sniff timeout */ + store 1,mem_acl_timeout + isub temp,null + nbranch set_big_value_to_attempt,positive + store 1,mem_acl_attempt +set_big_value_to_attempt: + jam LMP_ACCEPTED,mem_lmo_opcode2 + jam LMP_SNIFF_REQ,mem_lmi_opcode2 + rtn + +lmp_reject_sniff: + jam PDU_NOT_ALLOWED,mem_lmo_reason2 + branch reject_lmp_packet + +parse_lmp_start_encryption_req: + jam BT_EVT_ENC_CONNECTED,mem_fifo_temp + call ipc_tx_bt_event + call accept_lmp_msg + call lmp_copy_rand + call function_e3 + branch start_encryption + +parse_lmp_stop_encryption_req: + call accept_lmp_msg + branch stop_encryption + + +parse_lmp_switch_req: + fetch 1,mem_role_switch_flag + nbranch parse_lmp_switch_req_not_accept,blank + fetch 4,mem_rxbuf+1 + lshift pdata,pdata + //branch parse_lmp_switch_req_not_accept + branch parse_lmp_switch_accept,master + fetcht 1,mem_link_key_exists + nbranch parse_lmp_switch_req_clear_mark,blank +parse_lmp_switch_req_not_accept: + jam LMP_NOT_ACCEPTED,mem_lmo_opcode2 + jam LMP_SWITCH_REQ,mem_lmi_opcode2 + jam PDU_NOT_ALLOWED,mem_lmo_reason2 + rtn +parse_lmp_switch_req_clear_mark: + jam LMP_SLOT_OFFSET,mem_lmo_opcode2 + jam 0,mem_reconn_lmp_sm + branch role_switch_prepare + +parse_lmp_switch_accept: + call role_switch_prepare + set1 mark_reconn_recieve_switch,mark + fetch 1,mem_connection_options + set0 CONNECTION_SWITCH,pdata + store 1,mem_connection_options + branch accept_lmp_msg + + + +parse_lmp_temp_rand: + rtn +parse_lmp_temp_key: + rtn +parse_lmp_timing_accuracy_res: + rtn + +parse_lmp_unit_key: + rtn + + +parse_lmp_unsniff_req: + jam LMP_ACCEPTED,mem_lmo_opcode2 + jam LMP_UNSNIFF_REQ,mem_lmi_opcode2 +lmp_exit_acl_sniff: + fetch 1, mem_mode + set0 acl_in_sniff,pdata + store 1,mem_mode + rtnmark1 mark_sco_flag + branch sniff_exit + +parse_lmp_use_semi_permanend_key: + rtn + +parse_lmp_encapsulated_header: + fetch 1,mem_rxbuf+1 + bne ENCAPSULATED_MAJOR_TYPE_P192,parse_lmp_encapsulated_header_reject + fetch 1,mem_rxbuf+2 + bne ENCAPSULATED_MINOR_TYPE_P192,parse_lmp_encapsulated_header_reject + fetch 1,mem_rxbuf+3 + bne ENCAPSULATED_LEN_P192,parse_lmp_encapsulated_header_reject + call check_localsm + branch parse_lmp_encapsulated_header_master,true + jam SP_STAT_KEY_RECV,mem_sp_state +parse_lmp_encapsulated_header_master: + jam LMP_ACCEPTED,mem_lmo_opcode2 + jam LMP_ENCAPSULATED_HEADER,mem_lmi_opcode2 + branch parse_rx_done + +parse_lmp_encapsulated_header_reject: + jam PDU_NOT_ALLOWED,mem_lmo_reason2 + branch reject_lmp_packet + +parse_lmp_accepted_encapsulated_header: + //jam LMP_ENCAPSULATED_PAYLOAD,mem_lmi_opcode2 + //branch accept_lmp_msg + jam LMP_ENCAPSULATED_PAYLOAD,mem_lmo_opcode2 + // branch accept_lmp_msg + rtn +parse_lmp_accepted_simple_pairing_number: + fetch 1,mem_ssp_mode_flag + beq SSP_MODE_SSP_PIN_FLAG,parse_lmp_accepted_simple_pairing_number_ssp_pin + beq SSP_MODE_PASSKEY_ENTRY_FLAG,parse_lmp_accepted_simple_pairing_number_passkey +parse_lmp_accepted_simple_pairing_number_common: + call check_localsm + rtn true + jam SP_STAT_CONFIRM_RECV,mem_sp_state + rtn + + +parse_lmp_accepted_simple_pairing_number_ssp_pin: + call g_noninit_number_confirm + jam BT_EVT_BT_GKEY_GENERATE,mem_fifo_temp + call ui_ipc_send_event + branch parse_lmp_accepted_simple_pairing_number_common + + +parse_lmp_accepted_simple_pairing_number_passkey: + call check_localsm + rtn true + fetch 1,mem_authentication_passkey_times + beq 19,authentication_passkey_end + increase 1,pdata + store 1,mem_authentication_passkey_times +// branch p_authentication_passkey + +authentication_passkey: + jam SP_FLAG_COMMIT,mem_sp_flag + jam SP_STAT_COMMIT_CALC,mem_sp_state + fetch 1,mem_authentication_passkey_times + copy pdata,queue + fetch 6,mem_pin + qisolate1 pdata + setarg 0x80 + setflag true,0,pdata + store 1,mem_passkey_1bit + rtn + +authentication_passkey_end: + jam SP_STAT_CONFIRM_RECV,mem_sp_state + rtn + +parse_lmp_accepted_dhkey_check: + call parse_lmp_accepted_dhkey_check_common +pairing_success: + fetch 1,mem_flag_pairing_state + rtn blank + jam FLAG_PAIRING_STATE_NOT_PAIRING,mem_flag_pairing_state + jam BT_EVT_BT_PAIRING_SUCCESS,mem_fifo_temp + branch ui_ipc_send_event + + +parse_lmp_accepted_dhkey_check_common: + //here must be change*** shyd + call check_localsm +ifdef SIMPLE_PAIRING + ncall g_noninit,true //when be master call g_init + call g_init,true +endif + call check_localsm + rtn true + jam SP_STAT_LINK_KEY_CALC,mem_sp_state + jam SP_FLAG_COMMIT,mem_sp_flag + rtn + +parse_simple_pairing_confirm: + arg mem_sp_confirm_remote,contw + arg mem_rxbuf+1,contr + call memcpy16 + fetch 1,mem_ssp_mode_flag + rtneq SSP_MODE_PASSKEY_ENTRY_FLAG +ifdef SIMPLE_PAIRING + branch master_set_mem_master_sp_flag +endif + +parse_lmp_encapsulated_payload: + fetch 1,mem_master_sp_state + beq SP_STAT_RANDOM_SEND,parse_encapsulated_payload_master + fetch 1,mem_sp_state + bne SP_STAT_KEY_RECV,parse_lmp_encapsulated_payload_reject +parse_encapsulated_payload_master: + fetch 1,mem_sp_remote_key_recv_count + sub pdata,0x20,contw + nbranch parse_lmp_encapsulated_payload_reject,positive + arg mem_sp_pubkey_remote,contw + iadd contw,contw + fetch 8,mem_rxbuf+1 + istore 8,contw + fetch 8,mem_rxbuf+9 + istore 8,contw + fetch 1,mem_sp_remote_key_recv_count + increase 16,pdata + store 1,mem_sp_remote_key_recv_count + bne ENCAPSULATED_LEN_P192,accept_lmp_msg +parse_lmp_encapsulated_payload_completed: + call check_localsm + branch accept_lmp_msg,true + jam SP_KEY_VALID,mem_sp_remote_key_invalid + jam SP_STAT_KEY_GENERATE,mem_sp_state + jam SP_FLAG_COMMIT,mem_sp_flag + branch accept_lmp_msg +parse_lmp_encapsulated_payload_reject: + jam PDU_NOT_ALLOWED,mem_lmo_reason2 + branch reject_lmp_packet +parse_lmp_accepted_encapsulated_payload: + fetch 1,mem_sp_local_key_send_count + beq ENCAPSULATED_LEN_P192,parse_LMP_ENCAPSULATED_PAYLOAD_all_accepted + jam LMP_ENCAPSULATED_PAYLOAD,mem_lmo_opcode2 + branch parse_rx_done + +parse_lmp_encapsulated_payload_all_accepted: + call check_localsm + branch parse_lmp_encapsulated_payload_all_accepted_master,true + fetch 1,mem_ssp_mode_flag + beq SSP_MODE_PASSKEY_ENTRY_FLAG,parse_lmp_encapsulated_payload_all_accepted_get_passkey + jam SP_FLAG_COMMIT,mem_sp_flag + jam SP_STAT_COMMIT_CALC,mem_sp_state + branch parse_rx_done + +parse_lmp_encapsulated_payload_all_accepted_get_passkey: + jam BT_EVT_BT_GET_PASSKEY,mem_fifo_temp + branch ui_ipc_send_event + +parse_lmp_encapsulated_payload_all_accepted_master: + //call sp_master_generate_local_key + branch parse_rx_done + +parse_lmp_simple_pairing_number: + fetch 1,mem_master_sp_state + beq SP_STAT_RANDOM_SEND,parse_lmp_simple_pairing_number_master + fetch 1,mem_sp_state + bne SP_STAT_RANDOM_RECV,parse_lmp_simple_pairing_number_reject +parse_lmp_simple_pairing_number_master: + arg mem_sp_random_remote,contw + fetch 8,mem_rxbuf+1 + istore 8,contw + fetch 8,mem_rxbuf+9 + istore 8,contw + call check_localsm + branch parse_lmp_simple_pairing_number_master0,true + jam SP_STAT_RANDOM_SEND,mem_sp_state + jam SP_FLAG_COMMIT,mem_sp_flag + branch accept_lmp_msg +parse_lmp_simple_pairing_number_master0: + jam SP_STAT_COMMIT_CALC,mem_master_sp_state +ifdef SIMPLE_PAIRING + branch master_set_mem_master_sp_flag +endif + //jam LMP_SIMPLE_PAIRING_NUMBER,mem_lmi_opcode2 + //branch accept_lmp_msg +parse_lmp_simple_pairing_number_reject: + jam PDU_NOT_ALLOWED,mem_lmo_reason2 + branch reject_lmp_packet + +parse_dhkey_check: + fetch 1,mem_master_sp_state + beq SP_STAT_CONFIRM_SEND,parse_dhkey_check_master + fetch 1,mem_sp_state + bne SP_STAT_CONFIRM_RECV,parse_lmp_dhkey_check_reject +parse_dhkey_check_master: + arg mem_sp_check_result,contw + arg mem_rxbuf+1,contr + call memcpy16 + call check_localsm + branch parse_dhkey_check_master0,true + fetch 1,mem_ssp_mode_flag + beq SSP_MODE_SSP_PIN_FLAG,number_comparison_mode +number_comparison_successed: + jam 0,mem_flag_mode_ssp_pin + jam SP_STAT_CONFIRM_CHECK,mem_sp_state + jam SP_FLAG_COMMIT,mem_sp_flag + jam LMP_DHKey_Check,mem_lmi_opcode2 + branch parse_rx_done + +parse_dhkey_check_master0: + jam SP_STAT_CONFIRM_CHECK,mem_master_sp_state + jam SP_FLAG_COMMIT,mem_master_sp_flag + branch parse_rx_done +parse_lmp_dhkey_check_reject: + jam PDU_NOT_ALLOWED,mem_lmo_reason2 + branch reject_lmp_packet + + +number_comparison_mode: + fetch 1,mem_flag_mode_ssp_pin + bbit1 FLAG_MODE_SSP_PIN_REVICEVE_COMPARISON_BIT ,comparison_result + set1 FLAG_MODE_SSP_PIN_RECIEVE_DHKEY_BIT,pdata + store 1,mem_flag_mode_ssp_pin + rtn + +comparison_result: + bbit1 FLAG_MODE_SSP_PIN_COMPARISON_RESULT_BIT,number_comparison_successed + jam 0,mem_flag_mode_ssp_pin + branch parse_lmp_dhkey_check_reject + + +parse_lmp_clkoffset_res: + branch parse_rx_done + +parse_lmp_encryption_mode_req: + fetch 1,mem_connection_options + set0 CONNECTION_ENCRYPT,pdata + store 1,mem_connection_options + call accept_lmp_msg + nrtn master /* do sth only if we're master */ + fetch 1,mem_rxbuf+1 + fetcht 1,mem_op + setflag blank,op_stop_enc,temp + nsetflag blank,op_start_enc,temp + storet 1,mem_op + rtn + +parse_lmp_features_res: + fetcht 8,mem_rxbuf+1 /*fix bcp(baoshijie) err*/ + fetch 1,mem_hci_cmd + bne hci_cmd_wait_remote_feature,parse_lmp_features_res_not_hci + jam 0,mem_hci_cmd +parse_lmp_features_res_not_hci: + fetch 1,mem_reconn_lmp_sm + rtnne CONN_SM_WAIT_FEATURES_RES + fetch 1,mem_device_option + beq dvc_op_hci,parse_lmp_feature_ext_sm + fetch 1,mem_connection_options + bbit0 CONNECTION_FEATURE_EXT,parse_lmp_send_conn +parse_lmp_feature_ext_sm: + jam CONN_SM_SEND_FEATURES_EXT,mem_reconn_lmp_sm + rtn +parse_lmp_send_conn: + jam CONN_SM_SEND_CONN_REQ,mem_reconn_lmp_sm + rtn +parse_lmp_test_activate: + fetch 1,mem_debug_config + store 1,mem_test_mode_old_debug_config + jam LMP_ACCEPTED,mem_lmo_opcode2 + jam LMP_TEST_ACTIVATE,mem_lmi_opcode2 + rtn +parse_lmp_test_control: + /* the 9 test control parameters are XORed with 0x55 */ + /* doing the XOR here and storing in mem_temp_payload */ + jam LMP_ACCEPTED,mem_lmo_opcode2 + jam LMP_TEST_CONTROL,mem_lmi_opcode2 + force 9,loopcnt + arg mem_rxbuf+1,contr + arg mem_temp_payload,contw +parse_lmp_test_xor: + ifetch 1,contr + xor_into 0x55,pdata + istore 1,contw + loop parse_lmp_test_xor + fetch 1,test_mode_scenario + fetcht 1,mem_tester_emulate + set0 tester_no_whitening,temp + set0 tester_pattern_test,temp + beq EXIT_TEST_MODE, parse_lmp_test_control_exit + beq PAUSE_TEST_MODE, parse_lmp_test_control_pause + beq CLOSED_LOOP_BACK_ACL, parse_lmp_test_control_loopback + beq ACL_WITHOUT_WHITENING, parse_lmp_test_control_loopback_nowhite + beq CLOSED_LOOP_BACK_SCO, parse_lmp_test_control_loopback + beq SCO_WITHOUT_WHITENING, parse_lmp_test_control_loopback_nowhite + beq ZERO_PATTERN, parse_lmp_test_control_pattern + beq ONE_PATTERN, parse_lmp_test_control_pattern + beq ALT_PATTERN, parse_lmp_test_control_pattern + beq ALT2_PATTERN, parse_lmp_test_control_pattern + beq PSEUDORANDOM, parse_lmp_test_control_pattern + rtn +parse_lmp_test_control_exit: + /* restoring old parameters */ + fetch 1,mem_tester_emulate + set1 tester_exit,pdata + set1 tester_change,pdata + store 1,mem_tester_emulate + rtn +parse_lmp_test_control_pattern: + set1 tester_pattern_test,temp + jam 5,mem_lch_code + fetch 2,test_mode_data_length + iforce loopcnt + store 2,mem_len + arg mem_rxbuf,contw + call pn9 +parse_lmp_test_control_loopback_nowhite: + set1 tester_no_whitening,temp +parse_lmp_test_control_loopback: + set1 tester_change,temp + force 0,pdata + store 1,mem_slave_rcvcnt + store 2,mem_tst_pktcnt_crc + store 2,mem_tst_pktcnt_dmh + store 2,mem_tst_pktcnt_hec + store 2,mem_tst_pktcnt_sync + fetch 1,test_mode_hopping_mode + compare FIXED_FREQ,pdata,0xff + setflag true,tester_fixed_freq,temp + storet 1,mem_tester_emulate + rtn + +parse_lmp_test_control_pause: + set0 mark_testmode,mark + jam 0,mem_tester_emulate + fetch 1,mem_debug_config + set0 debug_tx_pattern,pdata + store 1,mem_debug_config + rtn + +check_test_cond: + fetch 1,mem_tester_emulate + rtnbit0 tester_change + fetch 1,mem_tester_cnt + increase 1,pdata + store 1,mem_tester_cnt + rtnne 5 + jam 0,mem_tester_cnt + fetch 1,mem_tester_emulate + set0 tester_change,pdata + store 1,mem_tester_emulate + bbit1 tester_exit,check_test_exit + isolate1 tester_no_whitening,pdata + call test_no_white,true + ncall test_enable_white,true + fetch 1,test_mode_packet_type + compare 0x20,pdata,0x30 + fetch 1,mem_state_map + setflag true,smap_edr,pdata + store 1,mem_state_map + fetch 1,mem_tester_emulate + fetcht 1,mem_debug_config + isolate1 tester_pattern_test,pdata + setflag true,debug_tx_pattern,temp + isolate1 tester_fixed_freq,pdata + setflag true,debug_tx_fixed_freq,temp + setflag true,debug_rx_fixed_freq,temp + storet 1,mem_debug_config + fetch 1,test_mode_tx_freq + store 1,mem_tx_fixed_freq + fetch 1,test_mode_rx_freq + store 1,mem_rx_fixed_freq + set1 mark_testmode,mark + rtn + +check_test_exit: + set0 mark_testmode,mark + jam 0,mem_tester_emulate + fetch 1,mem_test_mode_old_debug_config + store 1,mem_debug_config + fetch 1,core_config + and_into 0xfb,pdata /* whitening on */ + store 1,core_config + rtn + + +lmp_copy_rand: + arg mem_rxbuf+1,contr + arg mem_random_number,contw + branch memcpy16 + +lmp_generate_key: + jam LMP_COMB_KEY,mem_lmo_opcode2 + rtn + +lmp_start_encryption: + nrtn master + jam LMP_START_ENCRYPTION_REQ,mem_lmo_opcode2 + rtn + +lmp_accept_inrand: + arg mem_lap,rega + call generate_kinit + jam LMP_ACCEPTED,mem_lmo_opcode2 + jam LMP_IN_RAND,mem_lmi_opcode2 + rtn + +lmp_disconnect: + jam 10,mem_conn_timer + jam LMP_DETACH,mem_lmo_opcode2 + jam LOCAL_HOST,mem_disconn_reason_send + rtn + +/*********************************/ +/*********lmp send*************/ +/********************************/ + /* enable user if a lmp packet is to send */ +send_lmp: + bpatchx patch2e_4,mem_patch2e + disable user + call lmo_fifo_process + fetch 1,mem_lmp_to_send + rtn blank + // set flag + arg LOG_POINT_1001,rega + fetcht 1,mem_lmp_to_send + call debug_log_print + fetch 1,mem_lmp_to_send +/* lmp message to be processed. this will either be because host??? */ +/* wants to send a lmp message or because one resulted from the LMP */ +/* processing section */ +/********* outgoing lmp lookup table *************/ + bbit1 7,send_lmp_escape + beq LMP_NAME_REQ, send_lmp_name_req + beq LMP_NAME_RES, send_lmp_name_res + beq LMP_ACCEPTED, send_lmp_accepted + beq LMP_NOT_ACCEPTED, send_lmp_not_accepted + beq LMP_FEATURES_REQ, send_lmp_features_req + beq LMP_FEATURES_RES, send_lmp_features_res + beq LMP_TIMING_ACCURACY_RES, send_lmp_timing_accuracy_res + beq LMP_VERSION_REQ, send_lmp_version_req + beq LMP_VERSION_RES, send_lmp_version_res + beq LMP_SETUP_COMPLETE, send_lmp_setup_complete + beq LMP_SUPERVISION_TIMEOUT, send_lmp_superto + beq LMP_HOST_CONNECTION_REQ,send_lmp_host_connection_req + beq LMP_IN_RAND,send_lmp_inrand + beq LMP_COMB_KEY,send_lmp_comb_key + beq LMP_AU_RAND,send_lmp_aurand + beq LMP_SRES,send_lmp_sres + beq LMP_ENCRYPTION_MODE_REQ,send_lmp_encryption_mode_req + beq LMP_ENCRYPTION_KEY_SIZE_REQ,send_lmp_encryption_key_size_req + beq LMP_START_ENCRYPTION_REQ,send_lmp_start_encryption + beq LMP_DETACH,send_lmp_detach + beq LMP_QUALITY_OF_SERVICE_REQ, send_lmp_quality_of_service_req + beq LMP_UNIT_KEY,send_lmp_unit_key + //Optional (O) + beq LMP_SCO_LINK_REQ, send_lmp_sco_link_req + beq LMP_REMOVE_SCO_LINK_REQ,send_lmp_remove_sco_link_req + beq LMP_CLKOFFSET_RES, send_lmp_clkoffset_res + beq LMP_MAX_POWER,send_lmp_nopayload_reply + beq LMP_MAX_SLOT, send_lmp_max_slot + beq LMP_MAX_SLOT_REQ, send_lmp_max_slot_req + beq LMP_MIN_POWER,send_lmp_nopayload_reply + beq LMP_SLOT_OFFSET, send_lmp_slot_offset + beq LMP_SWITCH_REQ, send_lmp_switch_req + beq LMP_SNIFF_REQ, send_lmp_sniff_req + beq LMP_STOP_ENCRYPTION_REQ, send_lmp_stop_encryption_req + beq LMP_TIMING_ACCURACY_REQ, send_lmp_timing_accuracy_req + beq LMP_UNSNIFF_REQ, send_lmp_unsniff_req + beq LMP_ENCAPSULATED_HEADER,send_lmp_encapsulated_header + beq LMP_ENCAPSULATED_PAYLOAD,send_lmp_encapsulated_payload + beq LMP_SIMPLE_PAIRING_CONFIRM,send_lmp_simple_pairing_comfirm + beq LMP_SIMPLE_PAIRING_NUMBER,send_lmp_simple_pairing_number + beq LMP_DHKEY_CHECK,send_lmp_dhkey_check + beq LMP_AUTO_RATE,send_lmp_auto_rate + beq LMP_INCR_POWER_REQ,send_incr_power_req + beq LMP_ENC_KEY_SIZE_MASK_RES,send_lmp_enc_key_size_mask_res + //master only must(M) + beq LMP_CLKOFFSET_REQ, send_lmp_clkoffset_req + beq LMP_QUALITY_OF_SERVICE, send_lmp_quality_of_service + beq LMP_TEST_ACTIVATE, send_lmp_test_activate + beq LMP_TEST_CONTROL, send_lmp_test_control +send_lmp_error: + branch assert + rtn +send_lmp_escape: + beq LMP_EXT_ACCEPTED,send_lmpext_accepted + beq LMP_EXT_FEATURES_RES,send_lmpext_features_res + beq LMP_NOT_ACCEPTED_EXT,send_lmpext_not_accepted + beq LMP_EXT_FEATURES_REQ,send_lmpext_features_req + beq LMP_PACKET_TYPE_TABLE_REQ,send_lmpext_packet_type_table_req + beq LMP_PAUSE_ENCRYPTION_REQ,send_lmpext_pause_encryption_req + beq LMP_IO_CAP_REQ,send_lmp_io_cap_req + beq LMP_IO_CAP_RES,send_lmpext_io_cap_res + beq LMP_SNIFF_SUBRATING_REQ,send_lmpext_sniff_subrating_req + beq LMP_SNIFF_SUBRATING_RES,send_lmpext_sniff_subrating_res + beq LMP_EXT_ESCO_LINK_REQ,send_lmpext_esco_req + beq LMP_EXT_REMOVE_ESCO_REQ,send_lmpext_remove_esco + beq LMP_PING_REQ,send_lmpext_ping_req + branch assert + +send_lmpext_esco_req: + jam AIR_MODE_CVSD,mem_air_mode + branch send_lmpext_esco_req_master,master + jam 0x00,mem_sco_handle + branch send_lmpext_esco_req_slave +send_lmpext_esco_req_master: + jam 0x07,mem_esco_amaddr +send_lmpext_esco_req_slave: + jam 0,mem_sco_dsniff + fetch 1, mem_features+5 + bbit0 5,send_lmpext_esco_req_ev3 +send_lmpext_esco_req_2ev3: + jam 2,mem_sco_wsniff + jam 24,mem_sco_tsniff + jam esco_type_2ev3,mem_sco_tx_packet_type + jam esco_type_2ev3,mem_sco_rx_packet_type + setarg 60 + store 2,mem_sco_tx_packet_len + store 2,mem_sco_rx_packet_len + branch send_lmpext_esco_req_end + +send_lmpext_esco_req_ev3: + jam 2,mem_sco_wsniff + jam 12, mem_sco_tsniff + jam esco_type_ev3,mem_sco_tx_packet_type + jam esco_type_ev3,mem_sco_rx_packet_type + setarg 30 + store 2,mem_sco_tx_packet_len + store 2,mem_sco_rx_packet_len +send_lmpext_esco_req_end: + force LMP_EXT_ESCO_LINK_REQ,pdata + force 16,queue + call send_lmpext + fetch 1,mem_sco_handle + istore 1,contw + fetch 1,mem_esco_amaddr + istore 1,contw + setarg 0 + istore 1,contw /* timing ctrl */ + fetch 1,mem_sco_dsniff + istore 1,contw /* Desco */ + fetch 1,mem_sco_tsniff + rshift pdata,pdata + istore 1,contw /* Tesco */ + //setarg 2 + fetch 1,mem_sco_wsniff + istore 1,contw /* Wesco */ + fetch 1,mem_sco_tx_packet_type + istore 1,contw /* M packet type EV3 */ + istore 1,contw /* S packet type EV3 */ + fetch 2,mem_sco_rx_packet_len + istore 2,contw /* M packet size */ + istore 2,contw /* S packet size */ + fetch 1,mem_air_mode + istore 1,contw + fetch 1,mem_neogotiation_state + istore 1,contw /* neogotiation state */ + nbranch send_lmp_reply,blank + branch send_lmp_reply,master + branch send_lmp_request + + +send_lmpext_remove_esco: + force 4,queue + call send_lmpext + fetch 1,mem_sco_handle + istore 1,contw + fetch 1,mem_disconn_reason_send + istore 1,contw + fetch 1,mem_esco_arq + store 1,mem_cur_arq + branch send_lmp_request + +send_lmpext_ping_req: + force 2,queue//Length + call send_lmpext + branch send_lmp_request + +/******** LMP follow messages **********/ +/****** TID follow received packet *******/ + +send_lmp_accepted: + bpatchx patch2e_5,mem_patch2e + force 2,pdata + call msg_send_lmp + fetch 1,mem_lmi_opcode + istore 1,contw + call send_lmp_follow + fetch 1,mem_lmi_opcode + beq LMP_SCO_LINK_REQ,send_lmp_accepted_sco_link + beq LMP_REMOVE_SCO_LINK_REQ,send_lmp_accept_remove_sco_link_req + beq LMP_IN_RAND,send_lmp_accepted_inrand + beq LMP_ENCRYPTION_MODE_REQ,send_lmp_accepted_enc_mode + beq LMP_ENCRYPTION_KEY_SIZE_REQ,send_lmp_accepted_enc_key + beq LMP_SNIFF_REQ,send_lmp_accept_sniff_req + beq LMP_HOST_CONNECTION_REQ,send_lmp_accepted_connection + beq LMP_DHKEY_CHECK,send_lmp_accept_dhkey_check + rtn + + +send_lmp_accept_remove_sco_link_req: + rtn + + + +send_lmp_accept_sniff_req: +lmp_enter_acl_sniff: + fetch 1,mem_mode + set1 acl_in_sniff,pdata + store 1,mem_mode + + rtnmark1 mark_sco_flag + + //load sniff parameters + fetch 2, mem_acl_dsniff + store 2,mem_dsniff + fetch 2,mem_acl_tsniff + store 2,mem_tsniff + fetch 1, mem_acl_attempt + store 1, mem_sniff_attempt + fetch 1, mem_acl_timeout + store 1, mem_sniff_timeout + branch sniff_init + + +send_lmp_not_accepted: + force 3,pdata + call msg_send_lmp + fetch 1,mem_lmi_opcode + beq LMP_AU_RAND,send_not_accept_aurand + istore 1,contw + fetch 1,mem_lmo_reason + istore 1,contw + branch send_lmp_follow + +send_not_accept_aurand: + istore 1,contw + fetch 1,mem_lmo_reason + istore 1,contw + arg mem_sres_tid,temp + branch special_tid_store + +send_remove_esco_link: + rtn + +send_lmpext_accepted: + force 4,queue + call send_lmpext + setarg LMP_ESCAPE + istore 1,contw + fetch 1,mem_lmi_opcode + icopy rega + set0 7,pdata + istore 1,contw + call send_lmp_follow + copy rega,pdata + beq LMP_EXT_ESCO_LINK_REQ,send_lmpext_accept_esco_link + beq LMP_EXT_REMOVE_ESCO_REQ,send_remove_esco_link + rtn + +send_lmpext_not_accepted: + force 5,queue + call send_lmpext + setarg LMP_ESCAPE + istore 1,contw + fetch 1,mem_lmi_opcode + set0 7,pdata + istore 1,contw + fetch 1,mem_lmo_reason + istore 1,contw + branch send_lmp_follow + + +send_lmp_accepted_inrand: + call clear_linkkey + call tid_check + rtn true + branch lmp_generate_key + +send_lmp_accepted_enc_mode: + fetch 1,mem_op + bbit1 op_start_enc,send_lmp_accepted_enc_start + rtnbit0 op_stop_enc + jam LMP_STOP_ENCRYPTION_REQ,mem_lmo_opcode2 + set0 op_stop_enc,pdata + call tid_reply + branch send_lmp_accepted_enc_exit +send_lmp_accepted_enc_start: + jam LMP_ENCRYPTION_KEY_SIZE_REQ,mem_lmo_opcode2 + set0 op_start_enc,pdata +send_lmp_accepted_enc_exit: + store 1,mem_op + rtn + +send_lmp_accepted_enc_key: + call check_localsm + branch lmp_start_encryption,true + rtn + +send_lmp_accepted_connection: + //jam LMP_SETUP_COMPLETE,mem_lmo_opcode2 + fetch 1,mem_lmp_conn_state + set1 RECEIVED_CONN_REQ,pdata + store 1,mem_lmp_conn_state + jam BT_EVT_BB_CONNECTED,mem_fifo_temp + branch ui_ipc_send_event + +send_lmp_accept_dhkey_check: + rtn +/******** LMP reply messages **********/ +/****** TID always set to remote *******/ + +send_lmpext_features_res: + force 12,queue + call send_lmpext + setarg 0x01 + istore 1,contw + fetch 2,mem_lmpext_ssp_enable + istore 2,contw + setarg 0 + istore 3,contw + setarg 0x00 + istore 4,contw + branch send_lmp_reply +send_lmpext_io_cap_res: + force 5,queue + call send_lmpext + fetch 3,mem_sp_iocap_local + istore 3,contw + call send_lmp_reply + jam FLAG_PAIRING_STATE_PAIRING,mem_flag_pairing_state + fetch 1,mem_sp_iocap_local + beq DISPLAY_YESNO,responder_iocap_display_yesno + beq KEYBOARD_ONLY,responder_iocap_keyboard_only + beq NO_INPUT_NO_OUTPUT,responder_iocap_no_input_no_output + rtn + +responder_iocap_keyboard_only: + fetch 1,mem_sp_iocap_remote + beq DISPLAY_ONLY,responder_iocap_keyboard_only_initiator_iocap_display_only + beq DISPLAY_YESNO,responder_iocap_keyboard_only_initiator_iocap_display_yesno + beq KEYBOARD_ONLY,responder_iocap_keyboard_only_initiator_iocap_keyboard_only + beq NO_INPUT_NO_OUTPUT,responder_iocap_keyboard_only_initiator_iocap_no_input_no_output + rtn + +responder_iocap_display_yesno: + fetch 1,mem_sp_iocap_remote + beq DISPLAY_ONLY,responder_iocap_display_yesno_initiator_iocap_display_only + beq DISPLAY_YESNO,responder_iocap_display_yesno_initiator_iocap_display_yesno + beq KEYBOARD_ONLY,responder_iocap_display_yesno_initiator_iocap_keyboard_only + beq NO_INPUT_NO_OUTPUT,responder_iocap_display_yesno_initiator_iocap_no_input_no_output + rtn + + +responder_iocap_no_input_no_output: + fetch 1,mem_sp_iocap_remote + beq DISPLAY_ONLY,responder_iocap_no_input_no_output_initiator_iocap_display_only + beq DISPLAY_YESNO,responder_iocap_no_input_no_output_initiator_iocap_display_yesno + beq KEYBOARD_ONLY,responder_iocap_no_input_no_output_initiator_iocap_keyboard_only + beq NO_INPUT_NO_OUTPUT,responder_iocap_no_input_no_output_initiator_iocap_no_input_no_output + rtn + +responder_iocap_keyboard_only_initiator_iocap_no_input_no_output: +responder_iocap_display_yesno_initiator_iocap_no_input_no_output: +responder_iocap_display_yesno_initiator_iocap_display_only: +responder_iocap_no_input_no_output_initiator_iocap_display_only: +responder_iocap_no_input_no_output_initiator_iocap_display_yesno: +responder_iocap_no_input_no_output_initiator_iocap_keyboard_only: +responder_iocap_no_input_no_output_initiator_iocap_no_input_no_output: +set_ssp_mode_justwork: + jam SSP_MODE_JUST_WORK_FLAG,mem_ssp_mode_flag + fetch 1,mem_spp_reject_justwork_flag + beq REJECT_JUSTWORK,app_bt_disconnect + rtn + +responder_iocap_display_yesno_initiator_iocap_display_yesno: +set_ssp_mode_numeric_comparison: + jam SSP_MODE_SSP_PIN_FLAG,mem_ssp_mode_flag + rtn + +responder_iocap_keyboard_only_initiator_iocap_display_yesno: +responder_iocap_keyboard_only_initiator_iocap_keyboard_only: +responder_iocap_keyboard_only_initiator_iocap_display_only: +responder_iocap_display_yesno_initiator_iocap_keyboard_only: +set_ssp_mode_passkey: + jam SSP_MODE_PASSKEY_ENTRY_FLAG,mem_ssp_mode_flag + rtn + +classic_bt_set_reject_justwork_flag: + arg FLAG_SSP_REJECT_JUSTWORK,queue + branch classic_bluetooth_set_flag + +classic_bt_clr_reject_justwork_flag: + arg FLAG_SSP_REJECT_JUSTWORK,queue + branch classic_bluetooth_clr_flag + +classic_bluetooth_set_flag: + fetch 1,mem_spp_reject_justwork_flag + qset1 pdata + store 1,mem_spp_reject_justwork_flag + rtn + +classic_bluetooth_clr_flag: + fetch 1,mem_spp_reject_justwork_flag + qset0 pdata + store 1,mem_spp_reject_justwork_flag + rtn + +send_lmp_io_cap_req: + force 5,queue + call send_lmpext + fetch 3,mem_sp_iocap_local + istore 3,contw + branch send_lmp_request + + +send_lmpext_sniff_subrating_req: + rtn + +send_lmpext_sniff_subrating_res: + force 9,queue + call send_lmpext + fetch 1,mem_subsniff_rate + istore 1,contw + fetch 2,mem_subsniff_tcmax + istore 2,contw + fetch 4,mem_subsniff_instant + istore 4,contw + branch send_lmp_reply + +send_lmp_name_res: + force 17,pdata + call msg_send_lmp + fetch 1,mem_lmi_opcode /* loading name offset */ + copy pdata,temp + beq 0x00,send_lmp_name_res_offset_ok + beq 0x0e,send_lmp_name_res_offset_ok + beq 0x1c,send_lmp_name_res_offset_ok + rtn +send_lmp_name_res_offset_ok: + istore 1,contw /* writing name offset */ + fetch 1,mem_local_name_length + istore 1,contw /* writing name length */ + copy pdata,loopcnt + setarg mem_local_name + iadd temp,contr /* setting read location */ + call memcpy + branch send_lmp_reply + + +send_lmp_timing_accuracy_res: + force 3,pdata + call msg_send_lmp + setarg 0x0114 + istore 2,contw + branch send_lmp_reply + +send_lmp_clkoffset_res: + // dopod s505 must wait for this res + force 3,pdata + call msg_send_lmp + fetch 4,mem_clke_bt + isub clkn_bt,pdata + branch send_lmp_clkoffset_res_master,master + sub pdata,0,pdata /* our role is slave */ +send_lmp_clkoffset_res_master: + // bit 16-2 of clkslave-clkmaster + rshift2 pdata,pdata + set0 15,pdata + istore 2,contw + branch send_lmp_reply + +send_lmp_version_res: + force 6,pdata + call msg_send_lmp + fetch 5,mem_lmp_version + istore 5,contw + branch send_lmp_reply + +send_lmp_features_res: + force 9,pdata + call msg_send_lmp + fetch 8,mem_features + istore 8,contw + branch send_lmp_reply + + +/******** LMP request messages **********/ +/****** TID always set to local initiated *******/ + + + +send_lmpext_features_req: + force 12,queue + call send_lmpext + setarg 0x01 + istore 1,contw + fetch 2,mem_lmpext_ssp_enable + istore 2,contw + setarg 0 + istore 3,contw + setarg 0x00 + istore 4,contw + branch send_lmp_request + +send_lmpext_packet_type_table_req: + force 3,queue + call send_lmpext + fetch 1,mem_ptt + istore 1,contw + disable user + call send_lmp_request + nrtn user + nrtn master + fetch 1,mem_afh_cfg + rtnbit0 AFH_CFG_ON + call afh_init + branch afh_open_all_channels + +//default:featrue is enable,extfeature is disable +ssp_enable: + fetch 1,mem_features+6 + set1 param_featrue_ssp,pdata + store 1,mem_features+6 + setarg param_lmpext_ssp_enable + store 2,mem_lmpext_ssp_enable + rtn + +ssp_disable: + fetch 1,mem_features+6 + set0 param_featrue_ssp,pdata + store 1,mem_features+6 + setarg 0 + store 2,mem_lmpext_ssp_enable + rtn + +afh_init: + jam 0x3,mem_afh_cfg + setarg 0 + store 4,mem_afh_timer + arg mem_afh_map_lo,contw + call afh_reset_map + arg mem_afh_map_new,contw + call afh_reset_map + arg mem_afh_classify_channel_map,contw + call afh_reset_map + branch afh_clear_error_counter +afh_open_all_channels: + arg mem_afh_map_new,contw + call afh_reset_map + call afh_clear_error_counter + branch afh_set_send_flag + + +afh_open_classify_map: + fetch 5,mem_afh_classify_channel_map + store 5,mem_afh_map_new + ifetch 5,contr + istore 5,contw + call afh_clear_error_counter + branch afh_set_send_flag + +afh_reset_map: + setarg 0xffffff + istore 3,contw + istore 3,contw + istore 3,contw + setarg 0x7f + istore 1,contw + rtn +afh_clear_error_counter: + setarg 0 + store 2,mem_afh_error_total + rtn +afh_set_send_flag: + fetch 1,mem_afh_cfg + set1 send_lmp_set_afh,pdata + store 1,mem_afh_cfg + rtn +send_set_afh: + nrtn master + force 16,pdata + call msg_send_lmp + deposit clkn_bt + arg 476,temp + iadd temp,pdata + rshift pdata,pdata + increase 1,pdata + set0 0,pdata + istore 4,contw + copy pdata,temp + setarg 1 + istore 1,contw + fetch 5,mem_afh_map_new + istore 5,contw + ifetch 5,contr + istore 5,contw + lshift temp,temp + storet 4,mem_afh_instant + call send_lmp_request + fetch 1,mem_mode + set1 afh_change,pdata + store 1,mem_mode + jam 1,mem_afh_new_mod + fetch 4,mem_afh_instant + arg TIMER_ONE_MINUTE,temp //set ahf_reset_timer + iadd temp,pdata + store 4,mem_afh_timer + fetch 1,mem_afh_cfg + rtnbit1 AFH_CFG_MASTER_SENT_REQ + jam LMP_EXT_CHN_CLASSIFICATION_REQ,mem_lmo_opcode2 + rtn + + +send_lmpext_pause_encryption_req: + force 2,queue + call send_lmpext + nbranch send_lmp_reply,master + // assume slave will not send pause req firstly??? + branch send_lmp_request + + + +send_lmp_detach: + force 2,pdata + call msg_send_lmp + fetch 1,mem_disconn_reason_send + istore 1,contw + call send_lmp_request +prepare_disconnect: + fetch 1,mem_op + set1 op_disconn,pdata + store 1,mem_op + jam 50,mem_conn_timer + rtn + +send_lmp_no_payload: + force 1,pdata + call msg_send_lmp + branch send_lmp_request + +send_lmp_host_connection_req: + fetch 1,mem_lmp_conn_state + set1 SENT_CONN_REQ,pdata + store 1,mem_lmp_conn_state + call send_lmp_no_payload + jam BT_EVT_RECONN_STARTED,mem_fifo_temp + branch ui_ipc_send_event + +send_lmp_nopayload_reply: + force 1,pdata + call msg_send_lmp + branch send_lmp_reply + + +send_lmp_sco_link_req: + branch send_lmp_sco_link_master,master + jam 0x00,mem_sco_handle + fetch 1,mem_mode + set1 sco_req_by_slave,pdata + store 1,mem_mode +send_lmp_sco_link_master: + jam sco_type_hv3,mem_sco_tx_packet_type + jam sco_type_hv3,mem_sco_rx_packet_type + setarg 30 + store 2,mem_sco_tx_packet_len + store 2,mem_sco_rx_packet_len + jam 12, mem_sco_tsniff + jam 0,mem_sco_dsniff + force 7,pdata + call msg_send_lmp + fetch 1,mem_sco_handle + istore 1,contw + setarg 0x00 /*timing ctrl flags*/ + istore 1,contw + rshift pdata,pdata + fetch 1,mem_sco_dsniff /*Dsco*/ + istore 1,contw + + fetch 1,mem_sco_tsniff /*Tsco*/ + rshift pdata,pdata + istore 1,contw + + setarg sco_type_hv3 /*HV3*/ + istore 1,contw + force AIR_MODE_CVSD,pdata + istore 1,contw + branch send_lmp_reply,master + branch send_lmp_tid + +send_lmp_remove_sco_link_req: + /* default to TID_NORM_SEND */ + force 3,pdata + call msg_send_lmp + fetch 1,mem_sco_handle + istore 1,contw + force OTHER_END_TERMINATED,pdata + istore 1,contw + branch send_lmp_request + + +send_lmp_encryption_mode_req: + force 2,pdata + call msg_send_lmp + fetch 1,mem_state_map + isolate0 smap_encryption,pdata + setflag true,0,pdata + and_into 1,pdata + istore 1,contw + branch send_lmp_request + + +send_lmp_superto: + force 3,pdata + call msg_send_lmp + fetch 2,mem_supervision_to + istore 2,contw + branch send_lmp_request + +send_lmp_name_req: + jam 250,mem_conn_timer + force 2,pdata + call msg_send_lmp + fetch 1,mem_name_offset + istore 1,contw + branch send_lmp_request + +send_lmp_test_control: + force 10,pdata + call msg_send_lmp + arg mem_temp_payload,contr + force 9,loopcnt +send_lmp_test_control_loop: + ifetch 1,contr + xor_into 0x55,pdata + istore 1,contw + loop send_lmp_test_control_loop + branch send_lmp_request + +send_lmp_quality_of_service_req: + branch send_lmp_request +send_lmp_unit_key: + branch send_lmp_request + +send_lmp_slot_offset: + rtn master + call calc_slot_offset + force 9,pdata + call msg_send_lmp + fetch 2,mem_slot_offset + istore 2,contw + fetch 3,mem_lap + istore 3,contw + fetch 1,mem_uap + istore 1,contw + fetch 2,mem_nap + istore 2,contw + bmark0 mark_switch_initiated,send_lmp_slot_offset_reply + set0 mark_switch_initiated,mark + call send_lmp_request + jam LMP_SWITCH_REQ,mem_lmo_opcode2 + rtn +send_lmp_slot_offset_reply: + call send_lmp_reply + jam LMP_ACCEPTED,mem_lmo_opcode2 + jam LMP_SWITCH_REQ,mem_lmi_opcode2 + rtn + +send_lmp_switch_req: + arg 0x200,temp + branch switch_on_native,master + deposit clke_bt + branch switch_slack +switch_on_native: + deposit clkn_bt +switch_slack: + deposit bt_clk + iadd temp,pdata + and_into 0x1fc,pdata + store 4,mem_sniff_anchor + force 5,pdata + call msg_send_lmp + fetch 4,mem_sniff_anchor /* reused as switch instant */ + rshift pdata,pdata + istore 4,contw + branch send_lmp_request + +send_lmp_sniff_req: + force 10,pdata + call msg_send_lmp + arg mem_sniff_payload,contr + ifetch 9,contr + istore 9,contw + branch send_lmp_request + + +send_lmp_timing_accuracy_req: +/* default to TID_NORM_SEND */ + force 3,pdata + call msg_send_lmp + setarg 0x0114 + istore 2,contw + branch send_lmp_request + +send_lmp_unsniff_req: +//--------------------need to completa + force 1,pdata + call msg_send_lmp + //fetch 1,mem_unsniff_pending + //nbranch send_msg_done,blank + //jam 1,mem_unsniff_pending + //fetch 2,mem_sniff_attempt + //fetch 2,mem_nsniff_attempt + //lshift3 pdata,pdata + //lshift pdata,pdata + //store 1,mem_unsniff_cnt + branch send_lmp_request + + +send_lmp_max_slot: + force 2,pdata + call msg_send_lmp + fetch 1,mem_max_slot + istore 1,contw + branch send_lmp_request + + +send_lmp_max_slot_req: + force 2,pdata + call msg_send_lmp + setarg 0x05 /*5 slot*/ + istore 1,contw + branch send_lmp_request + +send_lmp_setup_complete: + fetch 1,mem_state + set1 state_conn_comp,pdata + store 1,mem_state + copy clkn_bt,pdata + store 4,mem_aurand_send_delay_time + fetch 1,mem_lmp_conn_state + bbit1 SENT_SETUP_COMPLETE,send_lmp_setup_complete_has_sent + set1 SENT_SETUP_COMPLETE,pdata + store 1,mem_lmp_conn_state + jam BT_EVT_SETUP_COMPLETE,mem_fifo_temp + call ui_ipc_send_event + force 1,pdata + call msg_send_lmp + branch send_lmp_request +send_lmp_setup_complete_has_sent: + jam 0,mem_lmp_to_send + rtn + +send_lmp_version_req: + force 6,pdata + call msg_send_lmp + fetch 5,mem_lmp_version + istore 5,contw + branch send_lmp_request + +send_lmp_features_req: + force 9,pdata + call msg_send_lmp + fetch 8,mem_features + istore 8,contw + branch send_lmp_request + +sp_master_send_io_cap_get: + fetch 1,mem_device_option + beq dvc_op_hci,sp_master_send_io_cap_get_hci + jam SP_FLAG_COMMIT,mem_master_sp_flag + fetch 1,mem_sp_local_key_invalid + rtnne SP_KEY_VALID +sp_master_send_io_cap_get_hci: + jam SP_MASTER_STAT_START_DONE,mem_master_sp_state + rtn + +sp_master_send_io_cap_send: + call tid_initiate + jam LMP_IO_CAP_REQ,mem_lmo_opcode2 + jam SP_STAT_KEY_SEND,mem_master_sp_state + rtn + + +sp_master_send_LMP_ENCAPSULATED_HEADER: + call tid_initiate + jam LMP_ENCAPSULATED_HEADER,mem_lmo_opcode2 + jam SP_STAT_RANDOM_SEND,mem_master_sp_state + rtn + +sp_master_commitment_compare: + arg mem_sp_calc_result_high,rega + arg mem_sp_confirm_remote,regb + arg 16,loopcnt + call string_compare + branch sp_master_commitment_compare_success,zero + jam SP_STAT_NULL,mem_master_sp_state +ifdef SIMPLE_PAIRING + call master_clear_mem_master_sp_flag +endif + jam PDU_NOT_ALLOWED,mem_lmo_reason2 + jam LMP_SIMPLE_PAIRING_NUMBER,mem_lmi_opcode2 + branch reject_lmp_packet +sp_master_commitment_compare_success: + jam SP_STAT_CONFIRM_CALC,mem_master_sp_state +ifdef SIMPLE_PAIRING + call master_set_mem_master_sp_flag +endif + jam LMP_SIMPLE_PAIRING_NUMBER,mem_lmi_opcode2 + branch accept_lmp_msg + + + +sp_master_send_lmp_simple_pairing_number: + jam LMP_SIMPLE_PAIRING_NUMBER,mem_lmo_opcode2 + rtn + + + +sp_send_lmp_encapsulated_header: + // calculate the private & public key here + //jam LMP_ENCAPSULATED_HEADER,mem_lmp_to_send + jam LMP_ENCAPSULATED_HEADER,mem_lmo_opcode2 + //jam TID_PAIRING,mem_lmp_tid + rtn + //fetch 1,mem_tid_table + //set1 TID_PAIRING,pdata + //store 1,mem_tid_table + + +send_lmp_encapsulated_header: + jam 0,mem_sp_local_key_send_count + force 4,pdata + call msg_send_lmp + force ENCAPSULATED_MAJOR_TYPE_P192,pdata + istore 1,contw + force ENCAPSULATED_MINOR_TYPE_P192,pdata + istore 1,contw + force ENCAPSULATED_LEN_P192,pdata + istore 1,contw + call check_localsm + branch send_lmp_request,true + branch send_lmp_reply + +send_lmp_encapsulated_payload: + //jam TID_PAIRING,mem_lmp_tid + force 17,pdata + call msg_send_lmp + fetch 1,mem_sp_local_key_send_count + arg mem_sp_pubkey_local,contr + iadd contr,contr + ifetch 8,contr + istore 8,contw + ifetch 8,contr + istore 8,contw + fetch 1,mem_sp_local_key_send_count + increase 16,pdata + store 1,mem_sp_local_key_send_count + call check_localsm + branch send_lmp_request,true + branch send_lmp_reply + //branch send_lmp_request + +sp_send_lmp_simple_pairing_comfirm: + jam SP_STAT_RANDOM_RECV,mem_sp_state + jam LMP_SIMPLE_PAIRING_CONFIRM,mem_lmo_opcode2 + rtn +send_lmp_simple_pairing_comfirm: + //jam SP_STAT_RANDOM_RECV,mem_sp_state + //jam TID_PAIRING,mem_lmp_tid + force 17,pdata + call msg_send_lmp + arg mem_sp_calc_result_high,contr + ifetch 8,contr + istore 8,contw + ifetch 8,contr + istore 8,contw + branch send_lmp_reply + +sp_send_lmp_simple_pairing_number: + call lmo_fifo_process + //if lmo_fifo(0,1,3) is full,we should add code for stop jam NEW LMP to mem_lmo_opcode2 + jam LMP_SIMPLE_PAIRING_NUMBER,mem_lmo_opcode2 + rtn + +send_lmp_simple_pairing_number: + //jam TID_PAIRING,mem_lmp_tid + call check_localsm +ifdef SIMPLE_PAIRING + call sp_local_random_key_generator,true +endif + force 17,pdata + call msg_send_lmp + arg mem_sp_random_local,contr + ifetch 8,contr + istore 8,contw + ifetch 8,contr + istore 8,contw + call check_localsm + nbranch send_lmp_reply,true + branch send_lmp_request,true + +master_sp_sm_end: + //jam DEFAULT_STATEMACHINE,mem_sp_localsm + jam SP_STAT_DONE,mem_master_sp_state +sp_aurand_send: + call tid_initiate + jam LMP_AU_RAND,mem_lmo_opcode2 + call check_localsm_master +ifdef SIMPLE_PAIRING + branch sp_master_key_prarm_push,true + branch sp_link_key_prarm_push +endif +master_sp_send_lmp_dhkey_check: + call tid_reply +sp_send_lmp_dhkey_check: + jam LMP_DHKEY_CHECK,mem_lmo_opcode2 + rtn +send_lmp_dhkey_check: + //jam TID_PAIRING,mem_lmp_tid + force 17,pdata + call msg_send_lmp + arg mem_sp_calc_result_high,contr + ifetch 8,contr + istore 8,contw + ifetch 8,contr + istore 8,contw + call check_localsm + nbranch send_lmp_reply,true + branch send_lmp_request,true + +send_lmp_enc_key_size_mask_res: + force 3,pdata + call msg_send_lmp + setarg 0xfffe //enc key size mask + istore 2,contw + branch send_lmp_reply + +send_lmp_auto_rate: + branch send_lmp_request +send_lmp_clkoffset_req: + branch send_lmp_request +send_lmp_quality_of_service: + branch send_lmp_request +send_lmp_test_activate: + branch send_lmp_request + + +send_incr_power_req: + force 2,pdata + call msg_send_lmp + arg 0,pdata + istore 1,contw + branch send_lmp_request + +/******** LMP request/reply messages **********/ +/****** TID transaction specific *******/ + +send_lmp_comb_key: + call generate_random_number + arg mem_lap,rega + call generate_linkkey + force 17,pdata + call msg_send_lmp + arg mem_kinit,rega + arg mem_random_number,regb + call xor16 + nbranch send_lmp_follow,master + branch send_lmp_tid + +send_lmp_inrand: + call generate_random_number + arg mem_plap,rega + call generate_kinit +send_lmp_rand: /* used by in_rand,au_rand,start_encrypt */ + force 17,pdata + call msg_send_lmp + arg mem_random_number,contr + call memcpy16 + branch send_lmp_tid + +send_lmp_aurand: + fetch 1,mem_pairing_auth + branch send_lmp_aurand_notpairing,blank + call check_localsm + call tid_initiate,true + ncall tid_reply,true + branch send_lmp_aurand_common +send_lmp_aurand_notpairing: + call tid_initiate +send_lmp_aurand_common: + call generate_random_number + branch send_lmp_rand + +send_lmp_sres: + arg mem_lap,rega + call function_e1 + force 5,pdata + call msg_send_lmp + fetch 4,mem_input_store + istore 4,contw + arg mem_sres_tid,temp + call special_tid_store + call copy_aco + call check_localsm + branch send_lmp_sres_master,true + jam DONE_ENCRYP,mem_wait_encryption + fetch 1,mem_pairing_auth + rtn blank + jam LMP_AU_RAND,mem_lmo_opcode2 +send_lmp_sres_master: + fetch 1,mem_link_key_exists + rtn blank +send_lmp_sres_startenc: + call check_localsm + nbranch send_lmp_sres_startenc_slave,true + jam LMP_ENCRYPTION_MODE_REQ, mem_lmo_opcode2 + rtn +send_lmp_sres_startenc_slave: + rtnmark0 mark_slave_in_rand_accepted + set0 mark_slave_in_rand_accepted,mark + jam LMP_ENCRYPTION_MODE_REQ, mem_lmo_opcode2 + rtn + + + +send_lmp_start_encryption: + call generate_random_number + call function_e3 + force 17,pdata + call msg_send_lmp + arg mem_random_number,contr + call memcpy16 + branch send_lmp_tid + +send_lmp_stop_encryption_req: + force 1,pdata + call msg_send_lmp + branch send_lmp_tid + +send_lmp_encryption_key_size_req: + force 2,pdata + call msg_send_lmp + force 16,pdata + istore 1,contw + store 1,mem_key_size + branch send_lmp_tid + +msg_send_lmp: +/* FLOW is set high and LMP is indicated */ + lshift3 pdata,pdata + or_into 0x07,pdata + store 1,mem_lmo_header_length + arg 17,loopcnt + arg mem_lmo_payload,contw + call clear_mem + arg mem_lmo_payload,contw + rtn + +send_lmpext: + and pdata,0x7f,rega + jam LMP_ESCAPE,mem_lmp_to_send + deposit queue + call msg_send_lmp + istorer rega,1,contw + rtn + +send_lmp_follow: + fetch 1,mem_lmp_to_send + lshift pdata,pdata + fetcht 1,mem_state_map + isolate1 smap_lmptid,temp + setflag true,0,pdata + branch send_lmp_exit + + +send_lmp_tid: + fetcht 1,mem_state_map + and_into 1,temp + branch send_lmp_end + +send_lmp_reply: + force 0,temp + branch send_lmp_end + +send_lmp_request: + force 1,temp +send_lmp_end: + fetch 1,mem_lmp_to_send + lshift pdata,pdata + setflag master,0,pdata + ixor temp,pdata +send_lmp_exit: + store 1,mem_lmo_header_opcode + jam 0,mem_lmp_to_send + call lmo_fifo_process_lmo0empty + enable user + rtn + +lmo_fifo_process: + fetch 1,mem_lmp_to_send + branch lmo_fifo_process_lmo0empty,blank + fetch 1,mem_lmo_opcode1 + nrtn blank + branch lmo_fifo_process_lmo2to1 +lmo_fifo_process_lmo0empty: + fetch 1,mem_lmo_opcode1 + branch lmo_fifo_process_lmo1_empty,blank + fetch 3,mem_lmo_opcode1 + store 3,mem_lmp_to_send//1=>0 + fetcht 1,mem_lmo_tid1 + fetch 1,mem_state_map + set0 smap_lmptid,pdata + ior temp,pdata + store 1,mem_state_map + jam 0,mem_lmo_opcode1 +lmo_fifo_process_lmo2to1: + fetch 1,mem_lmo_opcode2 + rtn blank + fetch 4,mem_lmo_opcode2 + store 4,mem_lmo_opcode1//2=>1 + jam 0,mem_lmo_opcode2 + rtn +lmo_fifo_process_lmo1_empty: + fetch 1,mem_lmo_opcode2 + rtn blank + fetch 3,mem_lmo_opcode2 + store 3,mem_lmp_to_send//2=>0 + fetcht 1,mem_lmo_tid2 + fetch 1,mem_state_map + set0 smap_lmptid,pdata + ior temp,pdata + store 1,mem_state_map + jam 0,mem_lmo_opcode2 + rtn + +//input:temp +special_tid_store: + fetchr regc,1,mem_state_map + ifetch 1,temp + call pop_tid_follow + call send_lmp_follow + storer regc,1,mem_state_map + rtn + +tid_reply: + fetcht 1,mem_state_map + set0 smap_lmptidinit,temp + storet 1,mem_state_map + rtn + +tid_initiate: + fetcht 1,mem_state_map + set1 smap_lmptidinit,temp + storet 1,mem_state_map + rtn + + /* true if transaction from remote */ +tid_check: + nsetflag master,smap_lmptid,pdata //it is ok + fetcht 1,mem_state_map + ixor temp,pdata + isolate1 smap_lmptid,pdata + rtn + + /* set to remote */ +tid_set_reply: + fetch 1,mem_state_map + setflag master,smap_lmptid,pdata //it is ok + store 1,mem_state_map + rtn + + /*rtn true when we lead lmp*/ +check_localsm: + fetch 1,mem_sp_localsm + compare LOCAL_STATEMACHINE,pdata,0x7f + rtn +setlocalsm_master: + fetch 1,mem_sp_localsm + set1 7,pdata + store 1,mem_sp_localsm + rtn +setlocalsm_slave: + fetch 1,mem_sp_localsm + set0 7,pdata + store 1,mem_sp_localsm + rtn +check_localsm_master: + fetch 1,mem_sp_localsm + isolate1 7,pdata + store 1,mem_sp_localsm + rtn + +generate_random_number: + /* generating a 16 byte random number,storing in ape_random_number */ + arg mem_random_number,contw +generate_random: + force 16,loopcnt +generate_random_another: +generate_random_loop: + random pdata + istore 1,contw + loop generate_random_another + rtn + +generate_linkkey: + call function_e21 + arg mem_link_key,rega + arg mem_input_store,regb + ifetch 8,rega /* check if already got comb key */ + fetcht 1,mem_state + nsetflag blank,state_combkey,temp + storet 1,mem_state + copy rega,contw + call xor16 + branch generate_linkkey_continue + +/*********************************/ +/*********lmp send*************/ +/********************************/ + +process_conn_sm: + //nrtn master + fetch 1,mem_lmo_opcode2 + branch process_conn_sm_continue,blank + call lmo_fifo_process + fetch 1,mem_lmo_opcode2 + nrtn blank +process_conn_sm_continue: + bpatchx patch2e_6,mem_patch2e + fetch 1,mem_reconn_lmp_sm + rtn blank + /* state machine begins in standby */ + //beq CONN_SM_STANDBY, host_create_conn_begin + //beq CONN_SM_WAIT_PAGE, host_create_conn_wait_page + beq CONN_SM_SEND_FEATURES, host_create_conn_send_features + beq CONN_SM_WAIT_FEATURES_RES, host_create_conn_waiting + beq CONN_SM_SEND_FEATURES_EXT,host_creat_conn_send_feat_ext + beq CONN_SM_WAIT_FEATURES_EXT,host_create_conn_waiting + beq CONN_SM_SEND_CONN_REQ, host_create_conn_send_conn_req + beq CONN_SM_WAIT_CONN_ACCEPT, host_create_conn_wait_accept + beq CONN_SM_SEND_SWITCH,host_create_conn_switch + beq CONN_SM_WAIT_SWITCH_AFTER_HOST_CONNECTION, host_creat_after_host_conn + beq CONN_SM_WAIT_SWITCH,host_create_conn_wait_switch + beq CONN_SM_WAIT_SEND_AUTH,host_create_conn_wait_send_auth + beq CONN_SM_SEND_AURAND,host_auth_remote_dev + rtneq CONN_SM_AUTH_WAIT + beq CONN_SM_ENCRYPT, host_create_conn_encrypt + beq CONN_SM_ENCRYPT_WAIT, host_create_conn_encrypt_wait + beq CONN_SM_ENCRYPT_WAIT_CLEAR, host_create_conn_encrypt_wait_clear + beq CONN_SM_SEND_SETUP_COMPLETE, host_create_conn_send_setup_complete + beq CONN_SM_WAIT_SETUP_COMPLETE, host_create_conn_wait_setup_complete + branch assert + /* sending error message to host */ + rtn + +host_conn_judge_encrypt: + fetch 1,mem_connection_options + rtnbit0 CONNECTION_ENCRYPT + jam CONN_SM_ENCRYPT_WAIT,mem_reconn_lmp_sm + rtn + +host_creat_conn_send_feat_ext: + jam CONN_SM_WAIT_FEATURES_EXT,mem_reconn_lmp_sm + jam LMP_EXT_FEATURES_REQ,mem_lmo_opcode2 + rtn + +host_creat_conn_send_auth: + jam CONN_SM_SEND_AURAND,mem_reconn_lmp_sm + rtn + +host_creat_after_host_conn: + jam CONN_SM_WAIT_SWITCH,mem_reconn_lmp_sm + rtn + +host_auth_remote_dev: + fetch 1,mem_connection_options + bbit0 CONNECTION_AUTH,host_sm_done + jam CONN_SM_AUTH_WAIT,mem_reconn_lmp_sm + fetch 1,mem_op + rtnbit1 op_auth_req + jam LMP_AU_RAND,mem_lmo_opcode2 + rtn + +host_sm_done: + jam CONN_SM_STANDBY,mem_reconn_lmp_sm + rtn + +host_create_conn_send_features: + jam CONN_SM_WAIT_FEATURES_RES,mem_reconn_lmp_sm + jam LMP_FEATURES_REQ,mem_lmo_opcode2 + rtn + +host_create_conn_send_conn_req: + jam CONN_SM_WAIT_CONN_ACCEPT,mem_reconn_lmp_sm + set0 mark_reconn_recieve_switch,mark + jam LMP_HOST_CONNECTION_REQ,mem_lmo_opcode2 + branch init_lmp_reinit +host_create_conn_wait_accept: + nbranch host_sm_done,master + fetch 1,mem_connection_options + bbit0 CONNECTION_SWITCH,host_creat_conn_send_auth + jam CONN_SM_SEND_SWITCH,mem_reconn_lmp_sm + rtn + + +host_create_conn_waiting: + rtn + + + +host_create_conn_switch: + fetch 1,mem_lmp_conn_state + rtnbit0 SENT_SETUP_COMPLETE + rtnbit0 RECEIVED_SETUP_COMPLETE + nbranch host_create_conn_wait_switch_end,master + fetch 1,mem_switch_flag + rtneq SWITCH_FLAG_ACCEPT + fetch 1,mem_connection_options + set0 CONNECTION_SWITCH,pdata + store 1,mem_connection_options + jam LMP_SWITCH_REQ,mem_lmo_opcode2 + jam CONN_SM_WAIT_SWITCH_AFTER_HOST_CONNECTION,mem_reconn_lmp_sm + rtn + +host_create_conn_wait_switch: + rtn master +host_create_conn_wait_switch_end: + copy clkn_bt,pdata + store 4,mem_wait_auth_clk + jam CONN_SM_WAIT_SEND_AUTH,mem_reconn_lmp_sm + rtn + +host_create_conn_wait_send_auth: + copy clkn_bt,pdata + fetcht 4,mem_wait_auth_clk + isub temp,pdata + sub pdata,100,null + rtn positive + branch host_creat_conn_send_auth + +host_create_conn_send_setup_complete: + jam CONN_SM_WAIT_SETUP_COMPLETE,mem_reconn_lmp_sm + jam LMP_SETUP_COMPLETE,mem_lmo_opcode2 + rtn + +host_create_conn_wait_setup_complete: + fetch 1,mem_lmp_conn_state + rtnbit0 RECEIVED_SETUP_COMPLETE + jam CONN_SM_STANDBY,mem_reconn_lmp_sm + rtn + +host_create_conn_encrypt: + fetch 1,mem_connection_options + bbit1 CONNECTION_ENCRYPT,host_create_conn_encrypt_start + rtn + +host_create_conn_encrypt_start: + fetch 1,mem_connection_options + set0 CONNECTION_ENCRYPT,pdata + store 1,mem_connection_options + jam LMP_ENCRYPTION_MODE_REQ,mem_lmo_opcode2 + rtn + +host_create_conn_encrypt_wait: + fetch 1, mem_wait_encryption + rtn blank + jam CONN_SM_STANDBY,mem_reconn_lmp_sm + branch host_create_conn_encrypt_start + +host_create_conn_encrypt_wait_clear: + jam CONN_SM_SEND_SETUP_COMPLETE,mem_reconn_lmp_sm + rtn + +host_auth: + fetch 1,mem_op + bbit1 op_inrand_req,remote_auth + call tid_initiate + jam LMP_IN_RAND,mem_lmo_opcode2 + branch cmd_exit +remote_auth: + fetch 1,mem_op + set0 op_inrand_req,pdata + store 1,mem_op + call lmp_accept_inrand + call tid_set_reply + branch cmd_exit + +pincode_reinit: + setarg 4 + store 1,mem_pin_length + setarg 0x3030 + istore 2,contw + istore 2,contw + rtn + + Index: tag/Soft/Librarier/bt_rom/program/ota.prog =================================================================== --- /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/ota.prog (nonexistent) +++ /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/ota.prog (working copy) @@ -0,0 +1,368 @@ + +ota_init: + setarg 0 + store 2,mem_ota_write_index + store 2,mem_ota_write_length + setarg OTA_DATA_ADDR + store 3,mem_ota_write_data_addr + jam 0,mem_ota_return_result + rtn + +ota_process: + fetch 1,mem_ota_write_handle + fetcht 2,mem_le_att_handle + isub temp,null + nrtn zero + fetch 2,mem_le_payload_ptr + add pdata,7,contr + ifetch 1,contr + rtnne OTA_COMMAND + ifetch 1,contr + copy contr,rega + store 1,mem_ota_cmd + beq OTA_PORTOCOL_VERSION_REQUEST,ota_process_version_request + beq OTA_BUCK_SIZE_REQUEST ,ota_process_buck_size_request + beq OTA_WORK_MODE_REQUEST, ota_process_work_mode_request + beq OTA_SWITCH_WORK_MODE_REQUEST, ota_process_switch_work_mode + beq OTA_FLASH_CHECKSUM_REQUEST ,ota_process_flash_checksum + beq OTA_START_REQUEST ,ota_process_start_request + beq OTA_DATA_WRITE_CMD, ota_process_write_cmd + beq OTA_DATA_WRITE_REQUEST ,ota_process_write_rsp + beq OTA_END_REQUEST ,ota_process_end_request + branch assert + +ota_process_version_request: + arg 5,rega + call ota_tx_notify_success + fetch 2,mem_ota_version + istore 2,contw + rtn + +ota_process_buck_size_request: + arg 7,rega + call ota_tx_notify_success + fetch 2,mem_ota_buck_size + istore 2,contw + fetch 2,mem_ota_packet_max_len + istore 2,contw + rtn + +ota_process_work_mode_request: + call ota_check_work_mode + ncall ota_tx_result_error,zero + arg 4,rega + call ota_tx_notify_common + fetch 1,mem_ota_work_mode + istore 1,contw + rtn + +ota_check_work_mode: + fetch 3,mem_storage_start_addr + arg OTA_CODE_START_ADDR,temp + isub temp,null + branch ota_set_work_mode_ota,zero + arg NORMAL_CODE_START_ADDR,temp + isub temp,null + branch ota_set_work_mode_normal,zero + rtn + +ota_set_work_mode_ota: + jam OTA_WORK_MODE_OTA,mem_ota_work_mode + rtn + +ota_set_work_mode_normal: + jam OTA_WORK_MODE_NORMAL,mem_ota_work_mode + rtn + +ota_process_switch_work_mode: + ifetch 1,contr + beq OTA_WORK_MODE_NORMAL,ota_process_switch_work_mode_normal + beq OTA_WORK_MODE_OTA,ota_process_switch_work_mode_ota + branch ota_tx_workmode_error + +ota_process_switch_work_mode_normal: + call ota_process_switch_work_mod_success + call ota_write_flash_start_addr_normal + branch ota_reset + +ota_process_switch_work_mode_ota: + call ota_process_switch_work_mod_success + call ota_write_flash_start_addr_ota + branch ota_reset + +ota_process_switch_work_mod_success: + arg 3,rega + branch ota_tx_notify_success + +ota_process_flash_checksum_rsp: + call ota_process_flash_checksum + arg 7,rega + call ota_tx_notify_success + fetch 4,mem_regc + istore 4,contw + rtn + +ota_process_flash_checksum: + ifetch 4,contr + store 3,mem_flash_address + ifetch 4,contr + store 4,mem_regc + ifetch 4,contr + store 4,mem_timeup + setarg OTA_DATA_ADDR + store 2,mem_flash_data_address + setarg 0 + store 4,mem_sum_temp + bpatchx patch2e_7,mem_patch2e +ota_flash_read_loop: + fetch 4,mem_regc + arg 0x1000,temp + isub temp,null + call ota_read_page,positive + store 2,mem_flash_trans_length + call qspi_read + + fetchr loopcnt, 2,mem_flash_trans_length + fetcht 4,mem_sum_temp + fetch 2,mem_flash_data_address + copy pdata,contr + call ota_sum_loop + storet 4,mem_sum_temp + + arg 0x1000,pdata + fetcht 3,mem_flash_address + iadd temp,temp + storet 3,mem_flash_address + fetch 4,mem_regc + arg 0x1000,temp + isub temp,pdata + store 4,mem_regc + branch ota_flash_read_loop_end,zero + branch ota_flash_read_loop,positive +ota_flash_read_loop_end: + fetch 4,mem_sum_temp + fetcht 4,mem_timeup + isub temp,null + branch ota_process_flash_checksum_success,zero + jam OTA_RESULT_ERROR,mem_ota_return_result + rtn +ota_process_flash_checksum_success: + jam OTA_RESULT_SUCCESS,mem_ota_return_result + rtn + + + +ota_sum_loop: + ifetch 1,contr + iadd temp,temp + loop ota_sum_loop + rtn + +ota_read_page: + arg 0x1000,pdata + rtn + + +ota_process_start_request: + ifetch 1,contr + store 1,mem_ota_update_flash_mode + beq OTA_UPDATE_FLASH_NORMAL,ota_process_start_update_normal + beq OTA_UPDATE_FLASH_OTA,ota_process_start_update_ota + beq OTA_UPDATE_FLASH_PCM,ota_process_start_update_pcm + branch ota_tx_flashmode_not_support + +ota_process_start_req_success: + arg 4,rega + call ota_tx_notify_success + fetch 1,mem_ota_update_flash_mode + istore 1,contw + rtn + +ota_process_start_update_normal: + call ota_process_start_req_success + call ota_init + setarg NORMAL_CODE_START_ADDR + store 3,mem_ota_write_flash_addr + rtn + +ota_process_start_update_ota: + call ota_process_start_req_success + call ota_init + setarg OTA_CODE_START_ADDR + store 3,mem_ota_write_flash_addr + rtn + +ota_process_start_update_pcm: + call ota_process_start_req_success + call ota_init + setarg VP_FLASH_START_ADDR + store 3,mem_ota_write_flash_addr + rtn + +ota_process_write_cmd: + copy contr,rega + fetch 1,mem_ota_return_result + nrtn blank + ifetch 2,rega + increase 2,rega + fetcht 2,mem_ota_write_index + store 2,mem_ota_write_index + isub temp,pdata + bne 1,ota_tx_write_index_error + ifetch 2,rega + increase 2,rega + copy pdata,loopcnt + fetcht 2,mem_ota_write_length + iadd temp,pdata + store 2,mem_ota_write_length + fetcht 2,mem_ota_buck_size + isub temp,null + branch ota_tx_buck_size_error,positive + fetch 3,mem_ota_write_data_addr + copy pdata,contw + copy rega,contr + call memcpy + copy contw,pdata + store 3,mem_ota_write_data_addr + rtn + +ota_process_write_rsp: + call ota_process_write_request + arg 3,rega + branch ota_tx_notify_common + +ota_process_write_request: + copy contr,rega + fetch 1,mem_ota_return_result + nrtn blank + ifetch 2,rega + increase 2,rega + fetcht 2,mem_ota_write_index + store 2,mem_ota_write_index + isub temp,pdata + bne 1,ota_tx_write_index_error + ifetch 2,rega + increase 2,rega + copy pdata,loopcnt + fetcht 2,mem_ota_write_length + iadd temp,pdata + store 2,mem_ota_write_length + fetcht 2,mem_ota_buck_size + isub temp,null + nbranch ota_tx_buck_size_error,zero + fetch 3,mem_ota_write_data_addr + copy pdata,contw + copy rega,contr + call memcpy +ota_send_write_rsp_success: + jam OTA_RESULT_SUCCESS,mem_ota_return_result + setarg OTA_DATA_ADDR + store 2,mem_flash_data_address + fetch 2,mem_ota_buck_size + store 2,mem_flash_trans_length + fetch 3,mem_ota_write_flash_addr + store 3,mem_flash_address + branch qspi_write + +ota_process_end_request: + ifetch 1,contr + fetcht 1,mem_ota_update_flash_mode + isub temp,null + nbranch ota_tx_flashmode_not_support,zero + beq OTA_UPDATE_FLASH_NORMAL,ota_process_end_request_normal + beq OTA_UPDATE_FLASH_OTA,ota_process_end_request_ota + beq OTA_UPDATE_FLASH_PCM,ota_process_end_request_pcm + branch ota_tx_flashmode_not_support + +ota_process_end_request_normal: + call ota_process_end_request_success + call ota_write_flash_start_addr_normal + branch ota_reset + +ota_process_end_request_ota: + call ota_process_end_request_success + call ota_write_flash_start_addr_ota + branch ota_reset + +ota_process_end_request_pcm: +ota_process_end_request_success: + arg 4,rega + call ota_tx_notify_success + fetch 1,mem_ota_update_flash_mode + istore 1,contw + rtn + +ota_write_flash_start_addr_ota: + setarg OTA_CODE_START_ADDR+3 +ota_write_flash_start_addr: + store 3,mem_temp_block0 + fetch 2,mem_temp_block0+1 + byteswap pdata,pdata + fetcht 1,mem_temp_block0 + storet 1,mem_temp_block0+2 + store 2,mem_temp_block0 + setarg mem_temp_block0 + store 2,mem_flash_data_address + setarg 3 + store 2,mem_flash_trans_length + setarg 0 + store 3,mem_flash_address + branch qspi_write + +ota_write_flash_start_addr_normal: + setarg NORMAL_CODE_START_ADDR+3 + branch ota_write_flash_start_addr + + +ota_tx_buck_size_error: + jam OTA_RESULT_BUCK_SIZE_ERROR,mem_ota_return_result + rtn + +ota_tx_write_index_error: + jam OTA_RESULT_INDEX_ERROR,mem_ota_return_result + rtn + +ota_tx_write_length_error: + jam OTA_RESULT_LENGTH_ERROR,mem_ota_return_result + rtn + +ota_tx_result_error: + jam OTA_RESULT_ERROR,mem_ota_return_result + rtn + +ota_tx_workmode_error: + arg 3,rega + jam OTA_RESULT_WORKMODE_ERROR,mem_ota_return_result + branch ota_tx_notify_common + +ota_tx_workmode_not_support: + jam OTA_RESULT_WORKMODE_NOT_SUPPORT,mem_ota_return_result + rtn + +ota_tx_flashmode_not_support: + arg 4,rega + jam OTA_RESULT_FLASHMODE_NOT_SUPPORT,mem_ota_return_result + call ota_tx_notify_common + fetch 1,mem_ota_update_flash_mode + istore 1,contw + rtn + +ota_tx_notify_success: + jam OTA_RESULT_SUCCESS,mem_ota_return_result +//input rega:length +ota_tx_notify_common: + bpatchx patch2f_0,mem_patch2f + fetchr temp,1,mem_ota_notify_handle + call le_att_malloc_tx_notify + setarg OTA_EVENT + istore 1,contw + fetch 1,mem_ota_return_result + istore 1,contw + fetch 1,mem_ota_cmd + istore 1,contw + rtn + +ota_reset: + bpatchx patch2f_1,mem_patch2f + rtn + Index: tag/Soft/Librarier/bt_rom/program/peripherals.prog =================================================================== --- /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/peripherals.prog (nonexistent) +++ /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/peripherals.prog (working copy) @@ -0,0 +1,2073 @@ + +/* ===================== two wire SPI gpio ======================= */ + +twspi_reset: + rtn +twspi_write: + branch spid_write_reg + +twspi_read: + branch spid_read_reg + + + +/* ===================== code loading ======================= */ + +read_enc: + nbranch read_unenc,user + force 0,aes_ctrl + branch read_function + +read_unenc: + force aes_zero,aes_ctrl + +read_function: + copy temp,null + branch read_fuction_zero,zero + copy regc,pc +read_fuction_zero: + isolate0 0,null + branch set_ucode_status + +// return temp = block length +get_block_header: + force 4,temp +get_block_header0: + arg mem_ucode_buf,rega + call read_unenc + arg 0x55aa,rega + fetch 2,mem_ucode_buf + ifetcht 2,contr + isub rega,null + rtn + +// return temp = block length +get_block_header_efuse: + force 2,temp +get_block_header0_efuse: + arg mem_ucode_buf,rega + iadd temp,regb + call read_unenc + arg 0x55,rega + fetch 1,mem_ucode_buf + ifetcht 1,contr + isub rega,null + rtn + +read_first_eep_block: + arg 2,temp + arg mem_ucode_buf,rega + call read_unenc + fetch 2,mem_ucode_buf + store 2,mem_eep_addr_hi + byteswap pdata,pdata + increase -2,pdata + store 3,mem_start_addr_temp + call get_iv,user + rtn + +read_first_flash_block: + arg 3,temp + arg mem_spid_rbuf,rega + call read_unenc + fetch 3,mem_spid_rbuf + store 3,mem_addr_hi + fetcht 2,mem_addr_hi+1 + byteswap temp,pdata + fetcht 1,mem_addr_hi + lshift16 temp,temp + iadd temp,pdata + increase -3,pdata + store 3,mem_start_addr_temp + call get_iv,user + rtn + +update_start_addr: + fetch 3,mem_start_addr_temp + store 3,mem_storage_start_addr + rtn + +get_iv: + arg 16,temp + arg mem_ucode_keybuf,rega + call read_unenc + arg mem_ucode_keybuf,contr + arg 16,loopcnt + call aes_load_data + call do_aes_ecb /* generate first IV */ + branch aes_clear_data // for ofb mode, xor data is blank + +load_storage: + disable match + call get_block_header + nrtn zero + enable match + jam 0x80, core_ucode_ctrl + jam 0,core_ucode_hi + jam 0,core_ucode_low + arg core_ucode_data,rega + call read_enc + jam 0x0, core_ucode_ctrl +load_storage_loop: + arg 6,temp + call get_block_header0 + nrtn zero + ifetchr rega,2,contr + call read_unenc + branch load_storage_loop + +load_storage_efuse: + disable match + call get_block_header_efuse + nrtn zero + enable match + jam 0x80,core_ucode_ctrl + jam 0,core_ucode_hi + jam 0,core_ucode_low + arg core_ucode_data,rega + copy regb,pdata + iadd temp,regb + call efuse_read_code + jam 0x0, core_ucode_ctrl +load_storage_efuse_loop: + arg 4,temp + copy regb,pdata + iadd temp,regb + call get_block_header0_efuse + nrtn zero + ifetchr rega,2,contr + copy regb,pdata + iadd temp,regb + call read_unenc + branch load_storage_efuse_loop + + /* only load memory data from eeprom */ +reload_eeprom: + call clean_mem + setarg 0x1000 + store 2,mem_eep_addr_hi + arg iicd_read_eep,regc + arg 2,loopcnt +reload_eeprom_loop: + call get_block_header + nrtn zero + fetch 2,mem_eep_addr_hi + byteswap pdata,pdata + iadd temp,pdata + byteswap pdata,pdata + store 2,mem_eep_addr_hi + loop reload_eeprom_loop + branch load_storage_loop + +loadcode: + jam 0x25,core_clkoff // disable debug uart + call clean_mem +ifndef SIM +// call clean_mem +endif +loadcode_lpm: + disable user + //branch loadcode_spi + call qspi_gpio_defualt_set0 + setarg EFUSE_UCODE_FLAG + arg mem_ucode_flag,rega + arg 2,temp + call efuse_read_data + fetch 2,mem_ucode_flag + bbit0 UFLAG_AES, loadcode_efuse + setarg EFUSE_UCODE_AESKEY + arg mem_ucode_keybuf,rega + arg 16,temp + call efuse_read_data + jam lock_efuse,core_misc_ctrl // disable further read/write of key + arg mem_ucode_keybuf,contr + call load_key128 + enable user // set user for aes + +loadcode_efuse: + fetch 2,mem_ucode_flag + byteswap pdata,pdata + arg 0x7ff,temp + iand temp,pdata + branch loadcode_spi, zero + copy pdata,regb + arg efuse_read_data,regc + call load_storage_efuse +loadcode_spi: + fetch 1,mem_ucode_flag + bbit1 UFLAG_SKIP_FLASH, loadcode_iic + setarg EFUSE_UCODE_QSPI_SET + arg mem_qspi_gpio_ncs,rega + arg 6,temp + call efuse_read_data + call qspi_init_set + call qspi_gpio_init + nop 200 // some flash will fail if no delay here + call qspi_release_powerdown_flash + nop 100 + arg qspi_read_for_loadcode,regc + call read_first_flash_block + call load_storage + ncall qspi_gpio_clear,match + call update_start_addr,match + call qspi_gpio_defualt_set0,match + nbranch loadcode_spi_not_match,match + fetch 1,mem_ucode_status + bbit0 0,loadcode_spi + branch loadcode_iic + +loadcode_spi_not_match: + fetch 1,mem_qspi_defualt + bne 0,loadcode_spi + +loadcode_iic: + nbranch loadcode_noenc,user + force 0,aes_ctrl + jam set_tea_key,core_misc_ctrl +loadcode_noenc: + fetch 1,mem_ucode_flag + bbit1 UFLAG_SKIP_EEP,loadcode_hci + setarg EFUSE_UCODE_IIC_SET + arg mem_iic_sda_pin ,rega + arg 2,temp + call efuse_read_data + call iicd_init_pin + call clear_eeprom_size_2k + call loadcode_iic_by_eeprom + ncall iicd_init_pin_clear,match + call update_start_addr,match + nbranch loadcode_iic_eeprom_2k,match + fetch 1,mem_ucode_status + bbit0 0,loadcode_iic + branch loadcode_hci + +loadcode_iic_eeprom_2k: + call iicd_init_pin_defualt + call set_eeprom_size_2k + call loadcode_iic_by_eeprom + ncall iicd_init_pin_clear,match + call update_start_addr,match + nbranch loadcode_hci,match + fetch 1,mem_ucode_status + bbit0 0,loadcode_iic +loadcode_hci: + force regidx_key,regext_index + call aes_clear + setarg 0 + store 8,mem_ucode_keybuf + store 8,mem_ucode_keybuf+8 + jam 0x21,core_clkoff // enable debug uart + fetch 1,mem_ucode_flag + rtnbit0 UFLAG_SKIP_HCI + call hci_init +loadcode_hci_loop: + branch loadcode_hci_loop + + +loadcode_iic_by_eeprom: + setarg 0x0 + store 2,mem_addr_mi + arg iicd_read_eep,regc + call iicd_init_20clk + call read_first_eep_block + branch load_storage + +/* true flag is set into status */ +set_ucode_status: + fetch 1,mem_ucode_status + lshift pdata,pdata + setflag true,0,pdata + isolate0 15,rega + rtn true + store 1,mem_ucode_status + rtn + + /* queue is bit position of hw done status */ +decrypt_code: + isolate1 7,aes_ctrl + rtn true +decrypt_code_loop: + fetch 1,core_dma_status + qisolate1 pdata + rtn true + fetch 1,core_misc_status + bbit0 1,decrypt_code_loop + call do_aes_cbc + branch decrypt_code_loop + + /* change 0x8000 to 0x10000 */ +translate_mram: + rtnbit0 15 + set0 15,pdata + set1 16,pdata + rtn + + + /* loopcnt is ucode instruction count, pdata is buffer ptr */ +save_ucode: + copy loopcnt,temp + storet 2,mem_patch_len + jam 0x80, core_ucode_ctrl + jam 0,core_ucode_hi + jam 0,core_ucode_low + store 2,mem_patch_ptr + call translate_mram + iforce contw + lshift2 loopcnt,loopcnt +save_ucode_loop: + fetch 1,core_ucode_data + istore 1,contw + loop save_ucode_loop + jam 0x0, core_ucode_ctrl + rtn + +load_ucode: + fetch 2,mem_patch_ptr + rtn blank + jam 0x80, core_ucode_ctrl + jam 0,core_ucode_hi + jam 0,core_ucode_low + fetcht 2,mem_patch_len + lshift2 temp,loopcnt + call translate_mram + iforce contr +load_ucode_loop: + ifetch 1,contr + store 1,core_ucode_data + loop load_ucode_loop + jam 0x0, core_ucode_ctrl + rtn + +load_ucode_efuse: + fetch 2,mem_patch_ptr + rtn blank + jam 0x80, core_ucode_ctrl + jam 0,core_ucode_hi + jam 0,core_ucode_low + fetcht 2,mem_patch_len + lshift2 temp,loopcnt + iforce contr +load_ucode_efuse_loop: + ifetch 1,contr + store 1,core_ucode_data + loop load_ucode_efuse_loop + jam 0x0, core_ucode_ctrl + rtn +/* ===================== SPI dma ======================= */ + +spid_init: + jam 0x75,core_spid_ctrl // A7530 should at least 34, or write fail + jam 10,core_spid_delay // 4us delay + setarg mem_spid_tbuf + store 2,core_spid_txaddr + setarg mem_spid_rbuf + store 2,core_spid_rxaddr + fetch 1,mem_spid_sclkpin + arg gpcfg_spid_sck,temp + call gpio_config_function + fetch 1,mem_spid_sdiopin + arg gpcfg_spid_sdio,temp + branch gpio_config_function + +spid_reset: + fetch 1,core_spid_ctrl + set1 7,pdata + store 1,core_spid_ctrl + set0 7,pdata + store 1,core_spid_ctrl + rtn + + +/* pdata 6:0 is reg address, 15:8 is data to write */ +spid_write_reg: + set1 7,pdata + store 2,mem_spid_tbuf + bpatchx patch2f_5,mem_patch2f + jam 2,core_spid_txlen + jam 0,core_spid_rxlen + jam spid_start,core_dma_start + branch wait_spid_done + +/* pdata 6:0 is reg address */ +spid_read_reg: + force 1,temp +/* pdata 6:0 is burst reg address, temp is bytes to read */ +spid_read_regs: +// nop 100 + store 1,mem_spid_tbuf + bpatchx patch2f_6,mem_patch2f + jam 1,core_spid_txlen + storet 2,core_spid_rxlen + jam spid_start,core_dma_start + call wait_spid_done + fetch 1,mem_spid_rbuf + rtn + +wait_spid_done: + fetch 1,core_dma_status + bbit0 spid_done,wait_spid_done + rtn + +/* ===================== QSPI dma ======================= */ + +qspi_init_set: + setarg 0x0 + store 3,mem_addr_hi + jam 8,core_qspi_delay + jam 1,core_qspi_ctrl + rtn + +qspi_gpio_init: + call qspi_check_gpio_init + branch qspi_gpio_init_defualt,zero + call qspi_gpio_defualt_set0 + branch qspi_gpio_set + +qspi_check_gpio_init: + fetch 3,mem_qspi_gpio_ncs + fetcht 3,mem_qspi_gpio_ncs+3 + isub temp,null + rtn + +qspi_gpio_init_defualt: + fetch 1,mem_qspi_defualt + beq 0,qspi_gpio_init_defualt1 + beq 1,qspi_gpio_init_defualt2 + beq 2,qspi_gpio_init_defualt3 + beq 3,qspi_gpio_defualt_set0 +// branch qspi_gpio_init_defualt1 +qspi_gpio_defualt_set0: + jam 0,mem_qspi_defualt + rtn + +qspi_gpio_init_defualt1: + jam QSPI_NCS_DEFAULT1_PIN,mem_qspi_gpio_ncs + jam QSPI_SCK_DEFAULT1_PIN,mem_qspi_gpio_sck + jam QSPI_IO0_DEFAULT1_PIN,mem_qspi_gpio_io0 + jam QSPI_IO1_DEFAULT1_PIN,mem_qspi_gpio_io1 + jam QSPI_IO2_DEFAULT1_PIN,mem_qspi_gpio_io2 + jam QSPI_IO3_DEFAULT1_PIN,mem_qspi_gpio_io3 + jam 1,mem_qspi_defualt + branch qspi_gpio_set + +qspi_gpio_init_defualt2: + jam QSPI_NCS_DEFAULT2_PIN,mem_qspi_gpio_ncs + jam QSPI_SCK_DEFAULT2_PIN,mem_qspi_gpio_sck + jam QSPI_IO0_DEFAULT2_PIN,mem_qspi_gpio_io0 + jam QSPI_IO1_DEFAULT2_PIN,mem_qspi_gpio_io1 + jam QSPI_IO2_DEFAULT2_PIN,mem_qspi_gpio_io2 + jam QSPI_IO3_DEFAULT2_PIN,mem_qspi_gpio_io3 + jam 2,mem_qspi_defualt + branch qspi_gpio_set + +qspi_gpio_init_defualt3: + jam QSPI_NCS_DEFAULT3_PIN,mem_qspi_gpio_ncs + jam QSPI_SCK_DEFAULT3_PIN,mem_qspi_gpio_sck + jam QSPI_IO0_DEFAULT3_PIN,mem_qspi_gpio_io0 + jam QSPI_IO1_DEFAULT3_PIN,mem_qspi_gpio_io1 + jam QSPI_IO2_DEFAULT3_PIN,mem_qspi_gpio_io2 + jam QSPI_IO3_DEFAULT3_PIN,mem_qspi_gpio_io3 + call qspi_gpio_defualt_set0 + branch qspi_gpio_set + +qspi_gpio_set: + arg gpcfg_qspi_ncs,temp + fetch 1,mem_qspi_gpio_ncs + call gpio_config_function + arg gpcfg_qspi_sck,temp + fetch 1,mem_qspi_gpio_sck + call gpio_config_function + arg gpcfg_qspi_io0,temp + fetch 1,mem_qspi_gpio_io0 + call gpio_config_function + arg gpcfg_qspi_io1,temp + fetch 1,mem_qspi_gpio_io1 + call gpio_config_function + arg gpcfg_qspi_io2,temp + fetch 1,mem_qspi_gpio_io2 + call gpio_config_function + arg gpcfg_qspi_io3,temp + fetch 1,mem_qspi_gpio_io3 + branch gpio_config_function + +qspi_gpio_clear: + arg 0,temp + fetch 1,mem_qspi_gpio_ncs + call gpio_config_function + fetch 1,mem_qspi_gpio_sck + call gpio_config_function + fetch 1,mem_qspi_gpio_io0 + call gpio_config_function + fetch 1,mem_qspi_gpio_io1 + call gpio_config_function + fetch 1,mem_qspi_gpio_io2 + call gpio_config_function + fetch 1,mem_qspi_gpio_io3 + branch gpio_config_function + +qspi_unlock_flash: + setarg 0 + store 2,core_qspi_rxlen + setarg 1 + store 2,core_qspi_txlen + setarg mem_qspi_tbuf + store 2,core_qspi_txaddr + jam 6,mem_qspi_tbuf + jam qspi_start,core_dma_start + branch wait_qspi_done + + /* pdata is flash address, rega pointers to txdata(4 ahead bytes should be left), temp is length */ +qspi_write_flash: + increase 4,temp + storet 2,core_qspi_txlen + increase -4,rega + arg 2,temp + istoret 1,rega + rshift16 pdata,temp + istoret 1,contw + rshift8 pdata,temp + istoret 1,contw + istore 1,contw + storer rega,2,core_qspi_txaddr + setarg 0 + store 2,core_qspi_rxlen + jam qspi_start,core_dma_start + branch wait_qspi_done + + +/* temp is length, rega pointers to buf */ +qspi_read_for_loadcode: + jam 0x3b,mem_qspi_tbuf + setarg 4 + store 2,core_qspi_txlen +qspi_read_flash_raw: + storet 2,core_qspi_rxlen + setarg mem_qspi_tbuf + store 2,core_qspi_txaddr + storer rega,2,core_qspi_rxaddr + fetch 1,core_qspi_ctrl + isolate0 15,rega + setflag true,2,pdata + store 1,core_qspi_ctrl + jam qspi_start,core_dma_start + isolate1 7,aes_ctrl + branch qspi_no_decryption,true +qspi_read_flash_wait: + fetch 1,core_dma_status + bbit1 qspi_rw,qspi_read_flash_wait // waiting for qspi write + arg qspi_done,queue + rshift4 temp,loopcnt +qspi_decryption_loop: + force aes_cbc | aes_load,aes_ctrl + force aes_cbc,aes_ctrl + call wait_aes + loop qspi_decryption_loop +qspi_no_decryption: + call wait_qspi_done + isolate1 qspi_crcok,pdata + call set_ucode_status + fetch 1,mem_addr_hi + lshift16 pdata,regb + fetch 2,mem_addr_mi + byteswap pdata,pdata + ior regb,pdata + iadd temp,pdata + store 1,mem_addr_lo + rshift8 pdata,pdata + store 1,mem_addr_mi + rshift8 pdata,pdata + store 1,mem_addr_hi + rtn + +wait_qspi_done: + fetch 1,core_dma_status + bbit0 qspi_done,wait_qspi_done + rtn + +qspi_release_powerdown_flash: + fetch 1,core_qspi_ctrl + copy pdata,regb + fetch 1,core_qspi_delay + copy pdata,regc + jam 0x04,core_qspi_ctrl + jam 0,core_qspi_delay + + setarg 0 + store 2,core_qspi_rxlen + setarg 1 + store 2,core_qspi_txlen + setarg mem_qspi_tbuf + store 2,core_qspi_txaddr + jam 0xab,mem_qspi_tbuf + jam qspi_start,core_dma_start + call wait_qspi_done + + copy regb,pdata + store 1,core_qspi_ctrl + copy regc,pdata + store 1,core_qspi_delay + rtn + +qspi_powerdown_flash: + call check_m0_qspi_lock_and_pause + jam 0x04,core_qspi_ctrl + jam 0,core_qspi_delay + setarg 0 + store 2,core_qspi_rxlen + setarg 1 + store 2,core_qspi_txlen + setarg mem_qspi_tbuf + store 2,core_qspi_txaddr + jam 0xb9,mem_qspi_tbuf + jam qspi_start,core_dma_start + call wait_qspi_done + branch check_m0_qspi_continue + + +qspi_mmode: + fetch 1,core_qspi_ctrl + set1 6,pdata + store 1,core_qspi_ctrl + rtn + +qspi_nmode: + fetch 1,core_qspi_ctrl + set0 6,pdata + store 1,core_qspi_ctrl + rtn + +//mem_flash_address:flash address +//mem_flash_data_address:memory source +//mem_flash_trans_length:read length +mqspi_read: + bpatchx patch2f_7,mem_patch2f + call check_m0_qspi_lock_and_pause + call qspi_mmode + fetch 1,core_qspi_ctrl + copy pdata,regb + fetch 1,core_qspi_delay + copy pdata,regc + + setarg 0x05 + ior regb,pdata + store 1,core_qspi_ctrl + jam 0x08,core_qspi_delay + fetch 2,mem_flash_data_address + store 2,core_qspi_rxaddr + fetch 2,mem_flash_trans_length + store 2,core_qspi_rxlen + setarg 4 + store 2,core_qspi_txlen + fetch 2,mem_mram_qspi_tx_addr + store 2,core_qspi_txaddr + fetcht 2,mem_mram_qspi_tx_addr + setarg 0x10000 + iadd temp,contw + setarg 0x3b + istore 1,contw + fetch 3,mem_flash_address + rshift16 pdata,temp + istoret 1,contw + rshift8 pdata,temp + istoret 1,contw + istore 1,contw + jam qspi_start,core_dma_start + call wait_qspi_done + copy regb,pdata + store 1,core_qspi_ctrl + copy regc,pdata + store 1,core_qspi_delay + branch check_m0_qspi_continue + +//mem_flash_address:flash address +//mem_flash_data_address:memory source +//mem_flash_trans_length:read length +qspi_read: + bpatchx patch30_0,mem_patch30 + call check_m0_qspi_lock_and_pause + call qspi_nmode + fetch 1,core_qspi_ctrl + copy pdata,regb + fetch 1,core_qspi_delay + copy pdata,regc + + setarg 0x05 + ior regb,pdata + store 1,core_qspi_ctrl + jam 0x08,core_qspi_delay + fetch 2,mem_flash_data_address + store 2,core_qspi_rxaddr + fetch 2,mem_flash_trans_length + store 2,core_qspi_rxlen + setarg 4 + store 2,core_qspi_txlen + setarg mem_qspi_tbuf + store 2,core_qspi_txaddr + setarg 0x3b + store 1,mem_qspi_tbuf + fetch 3,mem_flash_address + rshift16 pdata,temp + istoret 1,contw + rshift8 pdata,temp + istoret 1,contw + istore 1,contw + jam qspi_start,core_dma_start + call wait_qspi_done + copy regb,pdata + store 1,core_qspi_ctrl + copy regc,pdata + store 1,core_qspi_delay + branch check_m0_qspi_continue + +//mem_flash_address:flash address +//mem_flash_data_address:memory source +//mem_flash_trans_length:write length +qspi_write: + bpatchx patch30_1,mem_patch30 + call check_m0_qspi_lock_and_pause + fetch 1,core_qspi_ctrl + copy pdata,regb + fetch 1,core_qspi_delay + copy pdata,regc + jam 0x04,core_qspi_ctrl + jam 0,core_qspi_delay + call qspi_unlock_flash + fetch 3,mem_flash_address + copy pdata,rega + call qspi_sector_earse_flash + call qspi_wait_write_flash + +qspi_write_loop: + call qspi_unlock_flash + fetcht 2,mem_flash_trans_length + arg 0x100,pdata + isub temp,null + ncall qspi_write_page,positive + + fetch 2,mem_flash_data_address + copy pdata,rega + fetch 3,mem_flash_address + call qspi_write_flash + call qspi_wait_write_flash + + fetcht 2,mem_flash_data_address + arg 0x100,pdata + iadd temp,temp + storet 2,mem_flash_data_address + fetcht 3,mem_flash_address + iadd temp,temp + storet 3,mem_flash_address + fetch 2,mem_flash_trans_length + arg 0x100,temp + isub temp,pdata + store 2,mem_flash_trans_length + branch qspi_write_end,zero + branch qspi_write_loop,positive +qspi_write_end: + copy regb,pdata + store 1,core_qspi_ctrl + copy regc,pdata + store 1,core_qspi_delay + branch check_m0_qspi_continue + +qspi_write_page: + arg 0x100,temp + rtn + +// 0~fff +/* rega is flash address, */ +qspi_sector_earse_flash: + bpatchx patch30_2,mem_patch30 + call check_m0_qspi_lock_and_pause + setarg 0 + store 2,core_qspi_rxlen + setarg 4 + store 2,core_qspi_txlen + setarg mem_qspi_tbuf + store 2,core_qspi_txaddr + setarg 0x20 + store 1,mem_qspi_tbuf + rshift16 rega,temp + istoret 1,contw + rshift8 rega,temp + istoret 1,contw + copy rega,pdata + istore 1,contw + jam qspi_start,core_dma_start + call wait_qspi_done + branch check_m0_qspi_continue + +qspi_wait_write_flash: + bpatchx patch30_3,mem_patch30 + call check_m0_qspi_lock_and_pause + jam 0,mem_temp + arg mem_temp,pdata + store 2,core_qspi_rxaddr + setarg 1 + store 2,core_qspi_rxlen + setarg 1 + store 2,core_qspi_txlen + setarg mem_qspi_tbuf + store 2,core_qspi_txaddr + jam 0x05,mem_qspi_tbuf + jam qspi_start,core_dma_start + call wait_qspi_done + fetch 1,mem_temp + bbit1 0,qspi_wait_write_flash + branch check_m0_qspi_continue + +/* ===================== I2C dma ======================= */ + + +/* scl high time: scl_high + 2 clks, scl low time:scl_low + 6 clks +data setup time: data_setup + 2 clks, data hold time: scl_low-setup-hold+4 clks */ +iicd_init_20clk: + jam 5,core_iicd_scl_low + jam 7,core_iicd_scl_high + jam 7,core_iicd_start_setup + jam 7,core_iicd_start_hold + jam 7,core_iicd_stop_setup + jam 5,core_iicd_data_setup + rtn + +iicd_init_30clk: + jam 10,core_iicd_scl_low + jam 12,core_iicd_scl_high + jam 12,core_iicd_start_setup + jam 12,core_iicd_start_hold + jam 12,core_iicd_stop_setup + jam 10,core_iicd_data_setup + rtn + +iicd_init_pin_defualt: + jam IIC_SDA_DEFAULT_PIN,mem_iic_sda_pin + jam IIC_SCL_DEFAULT_PIN,mem_iic_scl_pin + rtn + +iicd_init_pin: + fetch 1,mem_iic_sda_pin + fetcht 1,mem_iic_scl_pin + isub temp,null + call iicd_init_pin_defualt,zero + + arg gpcfg_iic_sda ,temp + fetch 1,mem_iic_sda_pin + call gpio_config_function + arg gpcfg_iic_scl ,temp + fetch 1,mem_iic_scl_pin + branch gpio_config_function + +iicd_init_pin_clear: + arg 0,temp + fetch 1,mem_iic_sda_pin + call gpio_config_function + fetch 1,mem_iic_scl_pin + branch gpio_config_function + +wait_iicd_done: + fetch 1,core_dma_status + bbit0 iicd_done,wait_iicd_done + rtn + + /* pdata is iic addr, rega points to buf, temp is length */ +iicd_read_data: + store 1,mem_iicd_tbuf + setarg mem_iicd_tbuf + store 2,core_iicd_txaddr + setarg 1 + store 2,core_iicd_txlen + storet 2,core_iicd_rxlen + storer rega,2,core_iicd_rxaddr + jam 1,core_iicd_ctrl + jam iicd_start,core_dma_start + branch wait_iicd_done + + +set_eeprom_size_2k: + set1 mark_eeprom_size,mark + jam 0x08,mem_eeprom_block_size + rtn + +clear_eeprom_size_2k: + set0 mark_eeprom_size,mark + jam 0x20,mem_eeprom_block_size + rtn + + +iicd_read_eep_data_size_2k: + fetch 1,mem_ef_base + iadd regb,pdata + store 1,mem_addr_mi + branch iicd_read_eep_size_2k + +iicd_read_eep_size_2k_loadcode: + fetch 2,mem_addr_mi + byteswap pdata,pdata + store 1,mem_addr_mi + +//length:temp +//mem ptr:rega +//eeprom addr:pdata +iicd_read_eep_size_2k: + setarg 3 + store 2,core_iicd_txlen + jam 0xa0,mem_iicd_tbuf + jam 0xa1,mem_iicd_tbuf+2 + branch iicd_read_eep_common + + +//length:temp +//mem ptr:rega +//eeprom addr offset:regb +iicd_read_eep_data: + bpatchx patch30_4,mem_patch30 + bmark1 mark_eeprom_size,iicd_read_eep_data_size_2k + fetch 2,mem_ef_base + iadd regb,pdata + byteswap pdata,pdata + store 2,mem_eep_addr_hi + +/* rega pointers to buf, temp is length */ +iicd_read_eep: + bpatchx patch30_5,mem_patch30 + bmark1 mark_eeprom_size,iicd_read_eep_size_2k_loadcode + setarg 4 + store 2,core_iicd_txlen + jam 0xa0,mem_iicd_tbuf + jam 0xa1,mem_iicd_tbuf+3 +iicd_read_eep_common: + setarg mem_iicd_tbuf + store 2,core_iicd_txaddr + storet 2,core_iicd_rxlen + storer rega,2,core_iicd_rxaddr + setarg 2 + isolate0 15,rega + setflag true,0,pdata + store 1,core_iicd_ctrl + jam iicd_start,core_dma_start + arg iicd_done,queue + call decrypt_code + call wait_iicd_done + isolate1 iicd_crcok,pdata + call set_ucode_status + bmark1 mark_eeprom_size,iicd_read_eep_load_code_size_2k + fetch 2,mem_eep_addr_hi + byteswap pdata,pdata + iadd temp,pdata + byteswap pdata,pdata + store 2,mem_eep_addr_hi + rtn + +iicd_read_eep_load_code_size_2k: + fetch 1,mem_addr_mi + iadd temp,pdata + byteswap pdata,pdata + store 2,mem_addr_mi + rtn + +//length:temp +//mem ptr:rega +//eeprom addr offset:regb +iicd_write_eep_data: + bpatchx patch30_6,mem_patch30 + fetch 2,mem_ef_base + iadd regb,pdata + +//cuur ptr:pdata length:temp buf:rega + store 2,mem_pdatatemp //curr ptr + storet 2,mem_temp //len + storer rega,2,mem_contr +iicd_write_eep_loop: + call iicd_eep_transparency + + fetcht 2,mem_regb + fetchr rega,2,mem_contr + fetch 2,mem_pdatatemp + + call iicd_write_eep + + fetch 2,mem_regb + fetcht 2,mem_contr + iadd temp,temp + storet 2,mem_contr + fetcht 2,mem_pdatatemp + iadd temp,temp + storet 2,mem_pdatatemp + fetch 2,mem_temp + nbranch iicd_write_eep_loop,blank + rtn + +//in: +//1.size 2.len 3.src 4.des +//mem_regc page's area +//mem_pdatatemp curr ptr +//mem_temp all len +//mem_regb curr len +iicd_eep_transparency: + fetch 2,mem_eeprom_block_size + increase -1,pdata + fetcht 2,mem_pdatatemp + ior temp,pdata + increase 1,pdata + store 3,mem_regc + + fetch 2,mem_temp + iadd temp,pdata + + fetcht 3,mem_regc + isub temp,pdata + nbranch iicd_eep_deal_short_packet,positive + store 2,mem_temp + fetch 3,mem_regc + fetcht 2,mem_pdatatemp + isub temp,pdata + store 2,mem_regb + rtn +iicd_eep_deal_short_packet: + fetch 2,mem_temp + store 2,mem_regb + setarg 0 + store 2,mem_temp + rtn + +/* pdata is eeprom address, rega pointers to txdata(2 ahead bytes should be left), temp is length */ +iicd_write_eep_size_2k: + increase 2,temp + storet 2,core_iicd_txlen + increase -2,rega + ifetcht 3,rega + copy temp,regb + arg 0xa0,temp + istoret 1,rega + istore 1,contw + branch iicd_write_eep_common + +/* pdata is eeprom address, rega pointers to txdata(3 ahead bytes should be left), temp is length */ +iicd_write_eep: + copy pdata,regb + bpatchx patch30_7,mem_patch30 + bmark1 mark_eeprom_size,iicd_write_eep_size_2k + copy regb,pdata + increase 3,temp + storet 2,core_iicd_txlen + increase -3,rega + ifetcht 3,rega + copy temp,regb + arg 0xa0,temp + istoret 1,rega + byteswap pdata,pdata + istore 2,contw +iicd_write_eep_common: + storer rega,2,core_iicd_txaddr + setarg 0 + store 2,core_iicd_rxlen + jam 1,core_iicd_ctrl + jam iicd_start,core_dma_start + call wait_iicd_done + istorer regb,3,rega + +iic_check_eeprom_standby: + jam 0,mem_iicd_tbuf+3 +iic_check_eeprom_standby_wait: + setarg 1 + store 2,core_iicd_txlen + jam 0xa0,mem_iicd_tbuf + setarg mem_iicd_tbuf + store 2,core_iicd_txaddr + setarg 0 + store 2,core_iicd_rxlen + store 2,core_iicd_rxaddr + setarg 3 + store 1,core_iicd_ctrl + jam iicd_start,core_dma_start + call wait_iicd_done + fetch 1,core_perf_status + rtnbit0 iicd_ack + nop 1500 + fetch 1,mem_iicd_tbuf+3 + increase 1,pdata + store 1,mem_iicd_tbuf+3 + sub pdata,40,null + nrtn positive//polling timeout 6ms + branch iic_check_eeprom_standby_wait + +/* ===================== efuse ======================= */ +//pdata: efuse address, rega :points to data, temp : count +efuse_read_data: + copy temp,loopcnt + copy pdata,temp + lshift3 temp,temp + arg CLOCK_OFF_EFUSE,queue + call mram_clkon +efuse_read_loop: + jam 0x32,core_efuse_ctrl + storet 2,core_efuse_addr + increase 8,temp + jam 0X33,core_efuse_ctrl + fetch 1,core_efuse_rdata + istore 1,rega + increase 1,rega + loop efuse_read_loop + jam 0x32,core_efuse_ctrl + jam 0x30,core_efuse_ctrl + arg CLOCK_OFF_EFUSE,queue + branch mram_clkoff + +//temp = efuse address, rega pointers data, loopcnt is count +efuse_program: + arg CLOCK_OFF_EFUSE,queue + call mram_clkon + jam 0x80,core_efuse_ctrl + call efuse_program_enable + copy rega,contr +efuse_program_loop: + ifetch 1,contr + arg 8,regb +efuse_program_bit_loop: + and pdata,1,null + ncall efuse_program_bit,zero + rshift pdata,pdata + increase 64,temp + increase -1,regb + nbranch efuse_program_bit_loop,zero + setarg -511 + iadd temp,temp + loop efuse_program_loop + jam 0xb4,core_efuse_ctrl + jam 0x80,core_efuse_ctrl + jam 0x30,core_efuse_ctrl + call efuse_program_disable + arg CLOCK_OFF_EFUSE,queue + branch mram_clkoff + +efuse_program_enable: + jam 1,core_lpm_reg +efuse_program_enable2: + nop 2 + jam 0x40,core_lpm_wr + nop 800 + rtn + +efuse_program_disable: + jam 0,core_lpm_reg + branch efuse_program_enable2 + +efuse_program_bit: + jam 0xb4,core_efuse_ctrl + nop 10 + storet 2,core_efuse_addr + jam 0xb5,core_efuse_ctrl + nop 90 + rtn + +//pdata: efuse address, rega :points to data, temp : count +efuse_read_code: + copy temp,loopcnt + copy pdata,temp + lshift3 temp,temp + arg CLOCK_OFF_EFUSE,queue + call mram_clkon +efuse_read_code_loop: + jam 0x32,core_efuse_ctrl + storet 2,core_efuse_addr + increase 8,temp + jam 0X33,core_efuse_ctrl + fetch 1,core_efuse_rdata + istore 1,rega + loop efuse_read_code_loop + jam 0x32,core_efuse_ctrl + jam 0x30,core_efuse_ctrl + arg CLOCK_OFF_EFUSE,queue + branch mram_clkoff + +/* ===================== uart ======================= */ +uartd_rx_cnt_got_first_byte: + jam 1,mem_uartd_rxitems_got_data + force uart_rx_timer,queue + fetch 2,mem_uartd_rx_timeout + branch timer_init +uartd_rx_cnt_with_threshold: + fetch 2,core_uart_rx_items + rtn blank + fetcht 1,mem_uartd_rxitems_threshold + isub temp,null + branch uartd_rx_cnt_rtn_value,positive + fetch 1,mem_uartd_rxitems_got_data + branch uartd_rx_cnt_got_first_byte,blank + arg uart_rx_timer,queue + call timer_check + branch uartd_rx_cnt_rtn_value,blank + setarg 0 + rtn +uartd_rx_cnt_rtn_value: + force uart_rx_timer,queue + call timer_stop + jam 0,mem_uartd_rxitems_got_data + fetch 2,core_uart_rx_items + rtn + + + /* temp=bytes to send */ +uartd_prepare_tx: + fetchr contus,2,core_uart_tx_saddr + fetchr contue,2,core_uart_tx_eaddr + fetchr contu,2,core_uart_tx_wptr + rtn + +uartd_send: + storer contu,2,core_uart_tx_wptr + rtn + +uartd_prepare_rx: + fetch 2,core_uart_rx_items + rtn blank + iforce loopcnt + fetchr contus,2,core_uart_rx_saddr + fetchr contue,2,core_uart_rx_eaddr + fetchr contu,2,core_uart_rx_rptr + rtn + + //len in temp +uartd_rxdone_by_len: + fetch 2,core_uart_rx_rptr + iadd temp,pdata + copy pdata,contu +uartd_rxdone: + storer contu,2,core_uart_rx_rptr + rtn + +uart_set_baud_by_mem: + fetch uart_baud_len,mem_baud + store uart_baud_len,core_uart_baud + rtn + +uart_copy_tx_bytes: + deposit loopcnt + rtn blank +uart_copy_tx_bytes_loop: + ifetch 1,contr + istore 1,contu + loop uart_copy_tx_bytes_loop + rtn + + +wait_uarttx: + fetch 2,core_uart_tx_items + nbranch wait_uarttx,blank + rtn + +//input:contr loopcnt +send_mem_to_uart: + copy contr,rega + call uartd_prepare_tx + copy rega,contr +send_mem_to_uart0: + call uart_copy_tx_bytes + call uartd_send + branch wait_uarttx + + + +/* =============== GPIO CONTROL ================= */ + + + //temp [4:0]=GPIO number, 0-31, +gpio_set_wake_by_current_state: + set1 gpio_active_bit,temp + call gpio_get_bit + nsetflag true,gpio_active_bit,temp + + //temp [4:0]=GPIO number, 0-31, [7]=0, low active +gpio_set_wake: + isolate1 5,temp + rtn true // doesnt support gpio32+ + isolate0 gpio_active_bit,temp + and temp,0x1f,queue + fetch 4,mem_gpio_wakeup_low + qsetflag true,pdata + store 4,mem_gpio_wakeup_low + fetch 4,mem_gpio_wakeup_high + nqsetflag true,pdata + store 4,mem_gpio_wakeup_high + rtn + + //temp [4:0]=GPIO number, 0-31, [7]=0, low active +gpio_clr_wake: + isolate1 5,temp + rtn true // doesnt support gpio32+ + isolate0 gpio_active_bit,temp + and temp,0x1f,queue + fetch 4,mem_gpio_wakeup_low + qset0 pdata + store 4,mem_gpio_wakeup_low + fetch 4,mem_gpio_wakeup_high + qset0 pdata + store 4,mem_gpio_wakeup_high + rtn + + +gpio_config_input_nowake: + call gpio_clr_wake + branch gpio_config_input_without_wake + + //temp [4:0]=GPIO number, 0-31, [7]=0, low active +gpio_config_input: + ncall gpio_set_wake,wake + +gpio_config_input_without_wake: + call gpio_addr + setarg 0 + isolate1 gpio_active_bit,temp + nsetflag true,6,pdata + setflag true,7,pdata + branch gpio_write + + /* temp is gpio number, return true if gpio active */ +gpio_get_bit: + arg core_gpio_in,contw + and temp,0x07,queue + rshift3 temp,pdata + and_into 7,pdata + iadd contw,contw + ifetch 1,contw + isolate1 gpio_active_bit,temp + branch gpio_get_bit_reverse,true + qisolate0 pdata + rtn +gpio_get_bit_reverse: + qisolate1 pdata + rtn + + //temp [5:0]=GPIO number, 0-39, [7]=0, low active. set gpio to inactive state +gpio_out_inactive: + isolate1 7,null + branch gpio_out_flag + +gpio_out_active: + isolate0 7,null + + /* temp is gpio number, [7]=1,set out equa true flag if gpio active */ +gpio_out_flag: + setarg 0 + nsetflag true,gpio_active_bit,pdata + ixor temp,temp + + /* temp is gpio number,0-31, [7]=out bit value */ +gpio_out: + call gpio_addr + setarg 0x3f + isolate1 gpio_active_bit,temp + setflag true,0,pdata + branch gpio_write + + // check output status +gpio_check_active: + call gpio_addr + ifetch 1,contw + bbit1 0,gpio_check_active_high + isolate0 gpio_active_bit,temp + rtn +gpio_check_active_high: + isolate0 gpio_active_bit,temp + rtn + +gpio_set_analog: + call gpio_addr + setarg gpcfg_no_ie +gpio_write: + istore 1,contw + rtn + + /* set all unused gpio to pull down mode to save power */ +gpio_pd_idle: + arg core_gpio_conf,contr + arg 40,loopcnt +gpio_pd_idle_loop: + ifetch 1,contr + nbranch gpio_pd_idle_configured,blank + setarg 0x80 + add contr,-1,contw + istore 1,contw +gpio_pd_idle_configured: + loop gpio_pd_idle_loop + rtn + +gpio_addr: + and temp,0x3f,pdata + arg core_gpio_conf,contw + iadd contw,contw + rtn + +gpio_config_param: + and pdata,0xff,temp + rshift8 pdata,pdata + branch gpio_config_function_int + + // pdata: gpio number bit7=1, temp: function type +gpio_config_function: + rtnbit0 gpio_active_bit +gpio_config_function_int: + and_into 0x3f,pdata + arg core_gpio_conf,contw + iadd contw,contw + istoret 1,contw + rtn + +//temp:gpio num +gpio_get_config: + and_into 0x3f,temp + setarg core_gpio_conf + iadd temp,contr + ifetch 1,contr + rtn + +gpio_config_uart: + fetch 1,mem_uart_txpin + arg gpcfg_uart_txd,temp + call gpio_config_function + fetch 1,mem_uart_rxpin + arg gpcfg_uart_rxd,temp + call gpio_config_function + fetch 1,mem_uart_rtspin + arg gpcfg_uart_rts,temp + call gpio_config_function + fetch 1,mem_uart_ctspin + arg gpcfg_uart_cts,temp + branch gpio_config_function + +gpio_config_uartb: + fetch 1,mem_uartb_txpin + arg gpcfg_uartb_txd,temp + call gpio_config_function + fetch 1,mem_uartb_rxpin + arg gpcfg_uartb_rxd,temp + call gpio_config_function + fetch 1,mem_uartb_rtspin + arg gpcfg_uartb_rts,temp + call gpio_config_function + fetch 1,mem_uartb_ctspin + arg gpcfg_uartb_cts,temp + branch gpio_config_function + +/* ===================== PWM ======================= */ + +set_pwm_blink: + lshift8 pdata,pdata + lshift4 pdata,pdata + store 2,core_pwm0_ncnt + store 2,core_pwm0_pcnt + rtn + +set_pwm_steadyon: + setarg 0 + store 2,core_pwm0_ncnt + setarg 1 + store 2,core_pwm0_pcnt + rtn + +set_pwm_off: + setarg 0 + store 2,core_pwm0_ncnt + store 2,core_pwm0_pcnt + rtn + + +/* ===================== XIP CONTROL ======================= */ + +enable_xip: + fetch 2,core_clkoff + set0 CLOCK_OFF_MRAM,pdata + set0 CLOCK_OFF_CM0,pdata + store 2,core_clkoff + fetch 3,mem_xip_flash_offset + rtn blank + fetcht 3,mem_storage_start_addr + iadd temp,pdata + store 3,core_flash_offset + setarg 2 +// nsetflag wake,0,pdata // init cache only at power up + set1 0,pdata +enable_xip_patch: + store 1,core_misc_ctrl + fetch 1,mem_xip_flash_read_cmd + store 1,core_flash_read_cmd + fetch 1,mem_ucode_flag + bbit0 7,enable_xip_cont + until null,lpo_edge + until null,lpo_edge +enable_xip_cont: + fetch 2,mem_xip_option + store 2,core_qspi_ctrl + rtn + +xip_status: + nop 800 + fetch 1,8 + rtn + +reset_xip1: + arg 10,loopcnt + call xip_status + rtneq 0x23 + jam 2,core_misc_ctrl + loop reset_xip1 + 1 + rtn + +reset_xip2: + arg 10,loopcnt + call xip_status + rtneq 0x23 + jam 2,core_reset + jam 2,core_misc_ctrl + loop reset_xip1 + 1 + rtn + + +read_m0_dhcsr: + setarg 0xedf2 + call read_scs + fetch 4,core_scs_rdata + rtn + +check_m0_qspi_lock_and_pause: + bpatchx patch31_0,mem_patch31 + call wait_m0_lock_qspi + fetch 1,mem_m0_pause_state + beq M0_STATE_NORMAL,m0_pause + rtn + +check_m0_qspi_continue: + bpatchx patch31_1,mem_patch31 + fetch 1,mem_m0_pause_state + rtnne M0_STATE_PAUSE + branch m0_continue + +wait_m0_lock_qspi: + fetch 1,mem_m0_lock_qspi + rtn blank + nop 10 + branch wait_m0_lock_qspi + +m0_continue: + fetch 3,core_flash_offset + rtn blank + jam M0_STATE_NORMAL,mem_m0_pause_state + jam 1,core_scs_wdata + branch m0_set_dhcsr + + +m0_pause: + fetch 3,core_flash_offset + rtn blank + call m0_pause_write_scs + jam M0_STATE_PAUSE,mem_m0_pause_state +m0_pause_delay: + nop 160 + rtn + +m0_pause_write_scs: + jam 3,core_scs_wdata +m0_set_dhcsr: + setarg 0xa05f00 + store 3,core_scs_wdata + 1 + setarg 0xedf2 + + // pdata:register address +write_scs: + or pdata,1,rega +write_scs_loop: + storer rega, 2,core_scs_addr + nop 2 + call bt_wake_up_m0_light_sleep +wait_scs: + fetch 1,core_misc_status + rtnbit1 3 + branch write_scs_loop + +read_scs: + copy pdata,rega + branch write_scs_loop + + +/* ===================== XIP CONTROL END ======================= */ + +load_le_ltk: + call nv_ng_load_nvram + call nv_get_last_record_ptr + ifetch 6,regc + store 6,mem_le_plap + store 6,mem_hci_plap + rtn blank + arg 16,loopcnt + arg mem_le_ltk,contw + call memcpy + jam 1,mem_ltk_exists + rtn +//lpm_test: + //call reset_xip1 + //beq 0x23,hold_cont + //call reset_xip2 + //beq 0x23,hold_cont + //call reset_xip1 + //beq 0x23,hold_cont + //branch assert + + + + +/* ===================== soft dma ======================= */ +//cfg[31] = int_en ;//interrupt enable,default=1 +//cfg[30] = word_mode ;//word or byte mode select,default=0, byte mode +//cfg[29:28] = task_format[1:0] ;//task format selection,default=0,normal copy mode +//cfg[24:20] = trigger_idx[4:0] ;//trigger task index,default=0x1f,not trigger +//cfg[19:16] = addr_inc_mode[3:0] ;//[3]:source address increament enable;[2]:destination address increament enable;bit[1:0] is for fifo mode +//cfg[15:0] = num_bytes[15:0] ;// + +/* +soft dma work time + +from 0x2000 to 0x18000 +length: 0x686 +begin: bt:0x1cf09, rt:0x4d3 +end: bt:0x1cf0c, rt:0x568 +duration: rt:0x2c87=11399/12=949us + +from 0x1a000 to 0x18000 +length: 0x686 +begin: bt:0x27532, rt:0xe83 +end: bt:0x27533, rt:0x733 +duration: rt:0x756=1878/12=156us +*/ + +soft_dma_table_init: + fetch 1,mem_param_soft_dma_enable + rtn blank + // init the table unit + fetch 3,mem_param_soft_dma_table_start_addr + add pdata,SOFT_DMA_TABLE_START_OFFSET,pdata + arg RAM_HEADER_OFFSET_MRAM,rega + lshift16 rega,rega + ior rega,pdata + + arg SOFT_DMA_TABLE_TOTAL_COUNT,loopcnt + fetcht 3,mem_param_soft_dma_table_start_addr + copy temp,contw + +soft_dma_table_init_loop: + istore 4,contw + add pdata,SOFT_DMA_TABLE_UNIT_SIZE,pdata + loop soft_dma_table_init_loop + + rtn + +// input: mem_soft_dma_src_addr, mem_soft_dma_dst_addr, temp(length), rega(table index) +soft_dma_table_unit_set: + fetch 1,mem_param_soft_dma_enable + rtn blank + // Step1: find the table index + call soft_dma_get_table_unit_addr + copy pdata,contw + + // Step2: Store length + istoret 2,contw + + // Step3: Store soft dma param + arg SOFT_DMA_DEFAULT_CONFIG_HIGH_BIT,temp + istoret 2,contw + + // Step4: Store soft dma src addr + fetch 4,mem_soft_dma_src_addr + istore 4,contw + + // Step5: Store soft dma dst addr + fetch 4,mem_soft_dma_dst_addr + istore 4,contw + + rtn + +// input rega +// output pdata +soft_dma_get_table_unit_addr: + // init the table unit + fetch 3,mem_param_soft_dma_table_start_addr + add pdata,SOFT_DMA_TABLE_START_OFFSET,pdata + mul32 rega,SOFT_DMA_TABLE_UNIT_SIZE,rega + iadd rega,pdata + rtn + + +// input: temp(bit map enable work task) +soft_dma_add_task: + fetch 1,mem_param_soft_dma_enable + rtn blank + // Step1: set flag + storet 1,core_dma_task_val + + fetch 1,mem_param_soft_dma_table_start_addr + store 1,core_dma_table_addr_l + + fetch 1,mem_param_soft_dma_table_start_addr+1 + store 1,core_dma_table_addr_h + + setarg 0x35 + store 1,core_dma_ctrl + + setarg 0x31 + store 1,core_dma_ctrl + + rtn + +soft_dma_check_work_ready: + fetch 1,core_dma_task_status + rtn + + + +// input temp +// output pdata +get_full_mram_addr: + arg RAM_HEADER_OFFSET_MRAM,pdata + lshift16 pdata,pdata + ior temp,pdata + rtn + +get_full_sram_addr: + arg RAM_HEADER_OFFSET_SRAM,pdata + lshift16 pdata,pdata + ior temp,pdata + rtn + +//////////////////////////////////////////////////////////// ZCODE ////////////////////////////////////////// +// mem_zcode_temp_param0 ---- zocde number(0~1f) +zcode_entrance: + fetcht 1,mem_zcode_temp_param0 // zcode number @ high 4bit + rshift4 temp,temp + fetch 1,mem_zcode_current_number + isub temp,null + branch zcode_run,zero // if this zcode is already loaded, do not load again + storet 1,mem_zcode_current_number + increase 1,temp + setarg ZCODE_BUFF_SIZE + imul32 temp,temp + fetch 3,mem_xip_flash_offset + isub temp,pdata + fetcht 3,mem_storage_start_addr + iadd temp,pdata + increase -4,pdata + store 3,mem_flash_address + setarg ZCODE_BUFF_SIZE + store 2,mem_flash_trans_length + setarg mem_zcode_buff + store 2,mem_flash_data_address + fetch 1,core_qspi_ctrl + store 1,mem_pdatatemp + call qspi_read + fetch 1,mem_pdatatemp + store 1,core_qspi_ctrl + + setarg mem_zcode_buff + store 2,mem_patch_ptr + jam ZCODE_CODE_SIZE,mem_patch_len + call load_ucode + setarg 0 + store 4,mem_patch_ptr +zcode_run: + fetch 1,mem_zcode_temp_param0 + branch ZCODE_ENTER_ADDRESS + +//////////////////////////////////////////////////////////// ZCODE END ////////////////////////////////////////// + +//////////////////////////////////////////////////////////// SARADC END ////////////////////////////////////////// + +//input temp:adc channel +saradc_check_gpio: + or temp,0x30,temp + fetch 1,rf_adc_ch + ior temp,pdata + store 1,rf_adc_ch + jam 0x8f,rf_adc_mode + branch saradc_enable + +saradc_check_vinlpm: + jam 0xbf,rf_adc_mode + branch saradc_enable + +saradc_check_hvin: + jam 0xaf,rf_adc_mode +saradc_enable: + fetch 1,core_sbc_ctrl + set1 7,pdata + store 1,core_sbc_ctrl + fetch 1,rfen_adc + or_into 0x7c,pdata + store 1,rfen_adc + jam 0xaa,rf_adc_gc + rtn + +saradc_disable_sum: + fetch 1,core_sbc_ctrl + set0 7,pdata + store 1,core_sbc_ctrl + rtn + +saradc_diable: + fetch 1,rfen_adc + and pdata,0x83,pdata + store 1,rfen_adc + rtn + +//output temp : adcdata +saradc_read_hvin_timer: + arg mem_bat_read_timer,regc + call timer_single_step + nrtn user +saradc_enable_hvin: + copy clkn_bt,pdata + store 1,mem_saradc_check_clk + jam 1,mem_saradc_flag + rtn + +saradc_read_hvin_wait: + fetch 1,mem_saradc_flag + rtn blank + copy clkn_bt,pdata + and pdata,0xff,pdata + fetcht 1,mem_saradc_check_clk + isub temp,rega + branch saradc_read_hvin_wait_check_clk,positive + sub rega,0,rega +saradc_read_hvin_wait_check_clk: + sub rega,2,null + nbranch saradc_read_hvin_start_timer,positive + rtn + +saradc_read_hvin_start_timer: + jam 10,mem_bat_read_timer + jam 0,mem_saradc_flag + fetcht 2,core_sumdata + branch saradc_diable + + +//////////////////////////////////////////////////////////// SARADC END ////////////////////////////////////////// + +/* ===================== sco m0 transmit/receive ======================= */ +m0_sco_data_buffer_init: + fetch 1,mem_param_sco_use_cm0 + rtn blank + fetch 3,mem_param_m0_respin_sco_buffer_start_addr + copy pdata,contw + arg M0_SCO_RX_BUFFER_TOTAL_SIZE,loopcnt + call clear_mem + + fetch 3,mem_param_m0_respin_sco_buffer_start_addr + add pdata,M0_SCO_TX_BUFFER_START_OFFSET,contw + arg M0_SCO_TX_BUFFER_TOTAL_SIZE,loopcnt + call clear_mem + rtn + + + + + + + + + + + + + + + + + + + + + + + + + +m0_sco_tx_data_pop: + call m0_sco_tx_check_have_packet + branch m0_sco_tx_data_pop_0x55,zero + fetch 3,mem_param_m0_respin_sco_buffer_start_addr + add pdata,M0_SCO_TX_BUFFER_START_OFFSET,contr + // rptr + ifetcht 1,contr + // current contr ptr is point to data offset + copy temp,rega + call m0_sco_tx_data_get_fifo_unit_addr + + copy pdata,contr + + + arg mem_sco_outdata,contw + arg 60,loopcnt + call memcpy_fast + + // increase rptr + fetch 3,mem_param_m0_respin_sco_buffer_start_addr + add pdata,M0_SCO_TX_BUFFER_START_OFFSET,pdata + // rptr + ifetcht 1,pdata + increase 1,temp + call m0_sco_tx_update_rptr_loopback + istoret 1,pdata + rtn + +m0_sco_tx_data_pop_0x55: + branch pop_cvsd_0x55 + +// output: pdata +m0_sco_tx_check_have_packet: + fetch 3,mem_param_m0_respin_sco_buffer_start_addr + add pdata,M0_SCO_TX_BUFFER_START_OFFSET,contr + // rptr + ifetcht 1,contr + // wptr + ifetch 1,contr + isub temp,pdata + rtn + +// input rega +// output pdata +m0_sco_tx_data_get_fifo_unit_addr: + // init the table unit + fetch 3,mem_param_m0_respin_sco_buffer_start_addr + add pdata,M0_SCO_TX_BUFFER_START_OFFSET,pdata + add pdata,M0_SCO_TX_DATA_FIFO_START_OFFSET,pdata + mul32 rega,M0_SCO_TX_DATA_UNIT_SIZE,rega + iadd rega,pdata + rtn + +// input: temp +m0_sco_tx_update_rptr_loopback: + sub temp,M0_SCO_TX_BUFFER_SIZE,null + nrtn zero + arg 0,temp + rtn + +// ======================== rx ========================= +m0_sco_rx_data_push: + // do not check, wptr ptr will always work + //call m0_sco_rx_reserve_buffer_size + //rtn blank + fetch 3,mem_param_m0_respin_sco_buffer_start_addr + add pdata,M0_SCO_RX_WPTR_OFFSET,contr + // wptr + ifetcht 1,contr + // current contr ptr is point to data offset + copy temp,rega + call m0_sco_rx_data_get_fifo_unit_addr + + copy pdata,contw + + fetch 1,mem_sco_flag + istore 1,contw + arg mem_sco_indata,contr + arg 60,loopcnt + call memcpy_fast + + // increase wptr + fetch 3,mem_param_m0_respin_sco_buffer_start_addr + add pdata,M0_SCO_RX_WPTR_OFFSET,pdata + // wptr + ifetcht 1,pdata + increase 1,temp + call m0_sco_rx_update_wptr_loopback + istoret 1,pdata + rtn + +// input: temp +m0_sco_rx_update_wptr_loopback: + sub temp,M0_SCO_RX_BUFFER_SIZE,null + nrtn zero + arg 0,temp + rtn + +// input rega +// output pdata +m0_sco_rx_data_get_fifo_unit_addr: + // init the table unit + fetch 3,mem_param_m0_respin_sco_buffer_start_addr + add pdata,M0_SCO_RX_DATA_FIFO_START_OFFSET,pdata + mul32 rega,M0_SCO_RX_DATA_UNIT_SIZE,rega + iadd rega,pdata + rtn + + +// output: pdata +m0_sco_rx_reserve_buffer_size: + call m0_sco_rx_use_buffer_size + sub pdata,M0_SCO_RX_BUFFER_SIZE,pdata + rtn + +// output: pdata +m0_sco_rx_use_buffer_size: + fetch 3,mem_param_m0_respin_sco_buffer_start_addr + copy pdata,contr + // rptr + ifetcht 1,contr + // wptr + ifetch 1,contr + isub temp,pdata + rtn positive + add pdata,M0_SCO_RX_BUFFER_SIZE,pdata + rtn + + + +/* ===================== wdt ======================= */ +// 0x8004 set dsp watch dog counter[19:12], the work clk is 32K, then the one tick is 125ms +// is the decrease one, max bit is bit19. +// near 15s +wdt_kick_watchdog_max: + jam 0x00,0x8004 + rtn + +wdt_kick_watchdog_100ms: + jam 0x7f,0x8004 + rtn + +wdt_kick_watchdog_500ms: + jam 0x7b,0x8004 + rtn + +wdt_kick_watchdog_1_5s: + jam 0x75,0x8004 + rtn + +wdt_set_watchdog_mode_interrupt: + fetch 1,core_sysctrl + set1 1,pdata + store 1,core_sysctrl + rtn + +wdt_set_watchdog_mode_reset: + fetch 1,core_sysctrl + set0 1,pdata + store 1,core_sysctrl + rtn + +wdt_disable_watchdog: + fetch 1,core_config + set0 4,pdata + store 1,core_config + rtn + +wdt_enable_watchdog: + fetch 1,core_config + set1 4,pdata + store 1,core_config + rtn + +wdt_init_reset_with_start: + call wdt_set_watchdog_mode_reset + branch wdt_enable_watchdog + +wdt_init_interrupt_with_start: + call wdt_set_watchdog_mode_interrupt + branch wdt_enable_watchdog + Index: tag/Soft/Librarier/bt_rom/program/rfcomm.prog =================================================================== --- /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/rfcomm.prog (nonexistent) +++ /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/rfcomm.prog (working copy) @@ -0,0 +1,646 @@ + +ifdef COMPILE_RFCOMM +rfc_init: + rtn wake +rfc_reinit: + bpatchx patch31_2,mem_patch31 + setarg 0 + store 2,mem_rfc_server_state + store 1,mem_remote_spp_channel + store 1,mem_pn_dlci + jam 0x50,mem_credit_given + rtn + +l2cap_rfc_process: + bpatchx patch31_3,mem_patch31 + fetch 2,mem_l2cap_payload_ptr + copy pdata,contr + ifetch 1,contr + store 1,mem_rfc_adss + rshift3 pdata,pdata + store 1,mem_rfc_current_channel + ifetch 1,contr + store 1,mem_rfc_frame_type + call rfc_get_frame_len + storet 2,mem_rfc_paylead_length + copy contr,pdata + store 2,mem_rfc_paylead_ptr + fetch 1,mem_rfc_current_channel + beq 0,rfc_parse_signal_packet + branch rfc_parse_server_packet + +rfc_parse_signal_sabm: + fetcht 1,mem_rfc_current_channel //address + jam 0xd7,mem_current_fcs //FCS + call rfc_send_ua + fetch 2,mem_rfc_server_state + set1 RFC_SIGNAL_SABM,pdata + set1 RFC_SIGNAL_UA,pdata + store 2,mem_rfc_server_state + jam 0,mem_rfcomm_initiator + branch rfcomm_rx_process_end +rfc_parse_signal_ua: + fetch 2,mem_rfc_server_state + set1 RFC_SIGNAL_UA,pdata + store 2,mem_rfc_server_state + branch rfcomm_rx_process_end + +rfc_parse_signal_packet: + bpatchx patch31_4,mem_patch31 + fetch 1,mem_rfc_frame_type + beq RFCOMM_FRAME_TYPE_SABM,rfc_parse_signal_sabm + beq RFCOMM_FRAME_TYPE_UA,rfc_parse_signal_ua + beq RFCOMM_FRAME_TYPE_UIH,rfc_parse_signal_uih + rtneq RFCOMM_FRAME_TYPE_DISCONN + branch assert + + +rfc_parse_signal_uih: + fetch 2,mem_rfc_paylead_ptr + copy pdata,contr + call rfc_get_uih_head_struct + fetch 1,mem_uih_cmd_type + beq UIH_PARAM_NEG_CMD,rfc_parse_signal_cmd_pn + beq UIH_PARAM_NEG_RES,rfc_parse_signal_res_pn + beq UIH_MODEM_STATUS_CMD,rfc_parse_signal_cmd_ms + beq UIH_MODEM_STATUS_RES,rfc_parse_signal_res_ms + branch rfcomm_rx_process_end + +rfc_parse_signal_cmd_pn: + call rfc_get_sigal_pn_param + fetch 2,mem_rfc_server_state + set1 RFC_SIGNAL_PN_CMD,pdata + set1 RFC_SIGNAL_PN_RES,pdata + store 2,mem_rfc_server_state + call rfc_send_signal_res_pn + branch rfcomm_rx_process_end +rfc_parse_signal_res_pn: + fetch 2,mem_rfc_server_state + set1 RFC_SIGNAL_PN_RES,pdata + store 2,mem_rfc_server_state + call rfc_get_sigal_pn_param + branch rfcomm_rx_process_end +rfc_get_sigal_pn_param: + fetch 2,mem_rfc_payload_ptr + copy pdata,contr + ifetch 1,contr + store 1,mem_pn_dlci + ifetch 1,contr + store 1,mem_pn_credit_flow_type_info + ifetch 1,contr + store 1,mem_pn_priority + ifetch 1,contr + store 1,mem_pn_acknowledg_timer + ifetch 2,contr + store 2,mem_pn_max_frame_size + ifetch 1,contr + store 1,mem_pn_max_retrans + ifetch 1,contr + store 2,mem_remote_credits + rtn + +rfc_get_signal_ms_param: + fetch 2,mem_rfc_payload_ptr + copy pdata,contr + ifetch 1,contr + rshift3 pdata,pdata + store 1,mem_ms_channel + ifetch 1,contr + store 1,mem_ms_param + rtn + + +rfc_get_uih_head_struct: + ifetch 1,contr + rshift pdata,pdata + store 1,mem_uih_cmd_type + call rfc_get_frame_len + storet 2,mem_uih_length + copy contr,pdata + store 2,mem_rfc_payload_ptr + rtn + +rfc_get_frame_len: + ifetch 1,contr + copy pdata,temp + rshift temp,temp + rtnbit1 0 + ifetch 1,contr + lshift3 pdata,pdata + lshift4 pdata,pdata + iadd temp,temp + rtn + +rfc_parse_signal_cmd_ms: + call rfc_get_signal_ms_param + fetch 2,mem_rfc_server_state + set1 RFC_SIGNAL_RECV_MS_CMD,pdata + set1 RFC_SIGNAL_SEND_MS_RES,pdata + store 2,mem_rfc_server_state + call rfc_send_modem_status_res + branch rfcomm_rx_process_end + +rfc_parse_signal_res_ms: + call rfc_get_signal_ms_param + fetch 2,mem_rfc_server_state + set1 RFC_SIGNAL_RECV_MS_RES,pdata + store 2,mem_rfc_server_state + branch rfcomm_rx_process_end + +rfc_parse_server_packet: + bpatchx patch31_5,mem_patch31 + fetch 1,mem_rfc_frame_type + beq RFCOMM_FRAME_TYPE_UA,rfc_parse_server_ua + beq RFCOMM_FRAME_TYPE_SABM,rfc_parse_server_sabm + beq RFCOMM_FRAME_TYPE_DISCONN,rfc_parse_sverver_disconnect +rfc_parse_sever_uih: + beq RFCOMM_FRAME_TYPE_UIH,rfc_parse_server_uih + beq RFCOMM_FRAME_TYPE_UIH_CREDITS,rfc_parse_server_uih_credits + rtn + +rfc_parse_server_ua: + fetch 1,mem_major_uppersm + beq UP_MAJOR_SM_DISCONNECT_SERVER,rfc_parse_server_ua_disc + fetch 1,mem_rfc_current_channel + store 1,mem_profile_channel + fetch 2,mem_rfc_server_state + set1 RFC_SERVER_UA,pdata + store 2,mem_rfc_server_state + branch rfcomm_rx_process_end +rfc_parse_server_ua_disc: + setarg 0 + store 2,mem_rfc_server_state + branch rfcomm_rx_process_end + +rfc_parse_server_sabm: + fetch 1,mem_rfc_current_channel + store 1,mem_profile_channel + fetch 2,mem_rfc_server_state + set1 RFC_SERVER_UA,pdata + set1 RFC_SERVER_SABM,pdata + store 2,mem_rfc_server_state + fetch 1,mem_rfc_adss + call rfcomm_calculate_FCS_ua + store 1,mem_current_fcs + call rfc_send_ua + fetch 1,mem_rfc_adss + rshift2 pdata,pdata + store 1,mem_pn_dlci + lshift2 pdata,pdata + set0 RFCOMM_ADDRESS_CR,pdata + set1 RFCOMM_ADDRESS_EXT_LEN,pdata + arg mem_HIUfcs_spp,temp // mem_HIUfcs_HF_WCredits in regB++ + storet 2,mem_contw_temp + call rfcomm_save_FCS_uih + branch rfcomm_rx_process_end + +rfc_parse_server_uih_credits: + fetch 2,mem_rfc_paylead_ptr + copy pdata,contr + increase 1,pdata + store 2,mem_rfc_paylead_ptr + ifetch 1,contr //remote credits + fetcht 2,mem_remote_credits + iadd temp,pdata + store 2,mem_remote_credits +rfc_parse_server_uih: + call rfcomm_increase_credit_given + fetch 1,mem_ui_profile_supported + bbit0 support_HF_HS,parse_uih_spp_uih_cont0 + call rfc_send_uih_credit + fetch 2,mem_rfc_paylead_ptr + store 2,mem_at_payload_ptr + fetchr queue,1, mem_rfc_paylead_length + branch HFP_process_rfcomm_packet +parse_uih_spp_uih_cont0: + call rfc_get_rfcomm_snd_adss + call rfc_send_uih_without_payload + //call spp_process_rx_data + branch rfcomm_rx_process_end + +rfc_send_uih_credit: + fetch 1,mem_credit_given + sub pdata,40,null + rtn positive + call rfc_get_rfcomm_snd_adss + branch rfc_send_uih_without_payload + + +rfc_parse_sverver_disconnect: + call rfc_reinit + fetch 1,mem_rfc_adss + call rfcomm_calculate_FCS_ua + store 1,mem_current_fcs + call rfc_send_ua + branch rfcomm_rx_process_end + +rfcomm_rx_process_end: + rtn + +rfc_prepare_send_signal_ms: + bpatchx patch31_6,mem_patch31 + fetch 2,mem_rfc_server_state + rtnbit1 RFC_SIGNAL_SEND_MS_CMD + rtnbit0 RFC_SIGNAL_PN_CMD + rtnbit0 RFC_SIGNAL_PN_RES + rtnbit0 RFC_SERVER_SABM + rtnbit0 RFC_SERVER_UA + rtnbit0 RFC_SIGNAL_SABM + rtnbit0 RFC_SIGNAL_UA + + set1 RFC_SIGNAL_SEND_MS_CMD,pdata + store 2,mem_rfc_server_state +rfc_send_signal_ms_cmd: + fetchr regd,2,mem_rfc_l2capch_ptr + arg 8,rega + call l2cap_malloc_server_channel + fetcht 1, mem_profile_channel + lshift3 temp,temp + or_into 0x03,temp + arg 0xaa,rega +rfc_org_signal_ms: + fetch 1,mem_rfcomm_initiator + lshift pdata,pdata + set1 0,pdata + istore 1,contw + setarg 0x09ef + istore 2,contw + setarg 0x05e3 + istore 2,contw + copy temp,pdata + istore 1,contw + setarg 0x8d + istore 1,contw + call rfcomm_calculate_FCS_dlci0 + istore 1,contw + rtn + + +rfc_send_ua: + arg 4,rega + call l2cap_malloc_server_channel + fetch 1,mem_rfc_adss + istore 1,contw //address + setarg 0x0173 + istore 2,contw + fetch 1,mem_current_fcs + istore 1,contw + rtn + +rfc_send_signal_res_pn: + arg 0xe,rega + call l2cap_malloc_server_channel + fetch 1,mem_rfcomm_initiator + lshift pdata,pdata + set1 0,pdata //ext len + istore 1,contw //DLCI0 address + setarg 0x15ef + istore 2,contw + setarg 0x1181 + istore 2,contw + fetch 1,mem_pn_dlci + istore 1,contw //DLCI + setarg 0x0000e0 + istore 3,contw + setarg RFCOMM_MAX_FRAME_SIZE //max frame size + istore 2,contw + setarg 0x00 //max retrans + istore 1,contw + setarg 0x07 + istore 1,contw // init credits + call rfcomm_calculate_FCS_dlci0 + istore 1,contw + rtn + + +rfc_send_modem_status_res: + arg 8,rega + call l2cap_malloc_server_channel + fetch 1,mem_rfcomm_initiator + lshift pdata,pdata + set1 0,pdata //ext len + istore 1,contw //DLCI0 address + setarg 0x09ef + istore 2,contw + setarg 0x05e1 + istore 2,contw + fetcht 1,mem_pn_dlci + lshift2 temp,temp + or_into 3,temp + istoret 1,contw + setarg 0x8d + istore 1,contw + call rfcomm_calculate_FCS_dlci0 + istore 1,contw + rtn + +rfc_send_uih_without_payload: + fetch 1,mem_credit_given + rtn blank + call l2cap_malloc_is_fifo_full + nrtn blank + arg 0x5,rega + call l2cap_malloc_server_channel + fetch 1,mem_rfcomm_send_adss + istore 1,contw + setarg 0x01ff + istore 2,contw + fetch 1,mem_credit_given + istore 1,contw + fetch 1,mem_HIUfcs_SPP_WCredits + istore 1,contw + jam 0,mem_credit_given + rtn + +rfcomm_increase_credit_given: + fetch 2,mem_rfc_paylead_length + rtn blank + fetch 1,mem_credit_given + increase 1,pdata + store 1,mem_credit_given + rtn + + + +rfc_tx_write_length: + fetch 2,mem_current_packet_length + sub pdata,0x7f,null + nbranch rfc_tx_write_long_packet,positive + lshift pdata,pdata + set1 0,pdata + istore 1,contw + rtn +rfc_tx_write_long_packet: + fetch 2,mem_current_packet_length + rshift3 pdata,pdata + rshift4 pdata,temp + and_into 0x7f,pdata + lshift pdata,pdata + set0 0,pdata + istore 1,contw + istoret 1,contw + rtn +rfc_tx_write_given_credit: + fetch 1,mem_credit_given + rtn blank + istore 1,contw + rtn + +rfc_send_signal_cmd_pn: + bpatchx patch31_7,mem_patch31 + //jam 3,mem_profile_channel + fetcht 1,mem_profile_channel + call channel_to_dlci + storet 1,mem_pn_dlci + arg 14,rega + call l2cap_malloc_server_channel + fetch 1,mem_rfcomm_initiator + lshift pdata,pdata + set1 0,pdata //ext len + istore 1,contw //DLCI0 address + setarg 0x15ef + istore 2,contw + setarg 0x1183 + istore 2,contw + fetch 1,mem_pn_dlci + istore 1,contw + setarg 0x0000f0 + istore 3,contw + setarg RFCOMM_MAX_FRAME_SIZE + istore 2,contw + setarg 0 + istore 1,contw + setarg 0x07 + istore 1,contw + call rfcomm_calculate_FCS_dlci0 + istore 1,contw + jam 0x10,mem_credit_given + rtn + +rfc_send_signal_sabm: + jam 3,mem_rfc_adss + jam 0x1c,mem_current_fcs + call rfc_send_sabm + jam 1,mem_rfcomm_initiator + rtn + +rfc_send_server_sabm: + fetcht 1,mem_pn_dlci + call rfc_dlci_to_address_cmd + call rfcomm_calculate_FCS_sabm //sabm fcs use once only,not need to save + store 1,mem_current_fcs + fetcht 1,mem_pn_dlci + call rfc_dlci_to_address_cmd + storet 1,mem_rfc_adss +rfc_send_sabm: + arg 4,rega + call l2cap_malloc_server_channel + fetch 1,mem_rfc_adss + istore 1,contw //address + setarg 0x013f + istore 2,contw + fetch 1,mem_current_fcs + istore 1,contw + rtn + +rfc_send_server_disc: + fetcht 1,mem_pn_dlci + call rfc_dlci_to_address_cmd + call rfcomm_calculate_FCS_disc //sabm fcs use once only,not need to save + store 1,mem_current_fcs + fetcht 1,mem_pn_dlci + call rfc_dlci_to_address_cmd + storet 1,mem_rfc_adss + branch rfc_send_disc +rfc_send_signal_disc: + jam 3,mem_rfc_adss + jam 0xfd,mem_current_fcs + jam 0,mem_rfcomm_initiator +rfc_send_disc: + arg 4,rega + call l2cap_malloc_server_channel + fetch 1,mem_rfc_adss + istore 1,contw //address + setarg 0x0153 + istore 2,contw + fetch 1,mem_current_fcs + istore 1,contw + rtn + + +/*rfcomm_calculate_FCS_sabm*/ +/*input: address in temp*/ +/*output: FCS in pdata */ +rfcomm_calculate_FCS_disc: + copy temp,pdata + reverse pdata,pdata + store 1,memFCStemp3 + force INI_TX_DISC,pdata + reverse pdata,pdata + store 1,memFCStemp2 + force 0x01,pdata + reverse pdata,pdata + store 1,memFCStemp1 + call caculate_fcs + copy temp,pdata + rtn + +rfcomm_calculate_FCS_sabm: + copy temp,pdata + reverse pdata,pdata //address + store 1,memFCStemp3 + force INI_TX_SABM,pdata + reverse pdata,pdata + store 1,memFCStemp2 + force 0x01,pdata + reverse pdata,pdata + store 1,memFCStemp1 + call caculate_fcs + copy temp,pdata + rtn +rfcomm_calculate_FCS_ua: + reverse pdata,pdata //address + store 1,memFCStemp3 + force RSP_TX_UA, pdata + reverse pdata, pdata + store 1, memFCStemp2 + force 0x01, pdata + reverse pdata, pdata + store 1, memFCStemp1 + branch caculate_fcs + /* FCS return from temp */ +rfcomm_calculate_FCS_dlci0: + fetch 1,mem_rfcomm_initiator + branch rfcomm_calculate_FCS_dlci0_res,blank + setarg 0x70 //FCS of initiator + rtn +rfcomm_calculate_FCS_dlci0_res: + setarg 0xaa//FCS of responder + rtn + +rfcomm_save_FCS_uih: + reverse pdata, pdata //address + store 1,memFCStemp3 /* contw distroided */ + force RSP_RX_UIH,pdata + call caculate_UIHdata_fcs + fetcht 2,mem_contw_temp + copy temp,contw + istore 1,contw /* save FCS for later use */ + copy contw,temp + storet 2,mem_contw_temp + force RSP_RX_UIH_WDATA,pdata /* P/F =1 + RSP_RX_UIH */ + call caculate_UIHdata_fcs + fetcht 2,mem_contw_temp + copy temp,contw + istore 1,contw /* save FCS for later use */ + rtn +/**********************************************************************/ +/* This subroutine caculates the FCS for UIH data */ +/* Input: */ +/* the address byte at memFCStemp3(bit reversed), control byte */ +/* at pdata (not bit reversed) */ +/* Output: */ +/* pdata: the FCS */ +/**********************************************************************/ +caculate_UIHdata_fcs: + reverse pdata,pdata + store 1,memFCStemp2 + fetch 2, memFCStemp2 + lshift8 pdata,pdata + store 3,mem_mod2div_temp + arg 0x107,regA + arg 0xf,regB + call mod2div + xor_into 0xd7, pdata + invert pdata,pdata + reverse pdata,pdata + rtn + +/**********************************************************************/ +/* This subroutine caculates the FCS */ +/* Input: */ +/* the address byte at memFCStemp3, control byte at memFCStemp2*/ +/* lenght at memFCStemp1 (all above data are bit reversed) */ +/* Output: */ +/* temp: the FCS */ +/**********************************************************************/ +caculate_fcs: + fetch 3, memFCStemp1 /* load 3 bytes start at memFCStemp1 */ + store 3,mem_mod2div_temp + arg 0x107,regA + arg 0xf,regB //24bit(memFCStemp1+..+memFCStemp3) - 9bit(regA) = 15bit + call mod2div + lshift8 pdata,pdata + arg 0x7, regB //16bit(lshift8 pdata,pdata ) - 9bit(regA) = 7bit + call mod2div + xor_into 0x2b, pdata //0x3d + invert pdata, pdata + reverse pdata, pdata /* FCS at pdata */ + copy pdata, temp + rtn + +mod2div: + arg 0,regC + copy regB,loopcnt + call right_shift_n // right shift pdata (regB)bit + icopy temp +mod2div_loop: + //jam 1,0x1fff +//mod2div_loop1: + //fetch 1,0x1fff + //nbranch mod2div_loop1,blank + copy temp,pdata + lshift regC,regC//quotient + bbit0 8, mod2div_not_enough_reduction//the high bit of 0x107 + ixor regA,temp// temp----remainer + increase 1,regC// quotient +mod2div_not_enough_reduction: //Minuend smaller than Subtrahend + lshift temp,temp + fetch 3,mem_mod2div_temp + increase -1,regB + compare 0xff,regB,0xff + branch mod2div_end,true + copy regB,loopcnt + call right_shift_n // right shift pdata (regB)bit + isolate1 0,pdata + setflag true,0,temp //move a new bit from Dividend(queue) into Minuend(pdata) + branch mod2div_loop +mod2div_end: + //output:remainer in pdata + rshift temp,pdata + rtn + +rfc_get_rfcomm_snd_adss: + fetcht 1,mem_pn_dlci +rfc_dlci_to_address_cmd: + //input DLCI from temp + lshift2 temp,temp + set1 RFCOMM_ADDRESS_EXT_LEN,temp + fetch 1,mem_rfcomm_initiator + ncall set_CR_bit,blank + storet 1,mem_rfcomm_send_adss + rtn + +dlci_to_address_res: + //input DLCI from temp + lshift2 temp,temp + set1 RFCOMM_ADDRESS_EXT_LEN,temp + fetch 1,mem_rfcomm_initiator + call set_CR_bit,blank + rtn +channel_to_dlci: + //input channel from temp + lshift temp,temp + fetch 1,mem_rfcomm_initiator + setflag blank,0,temp //direction in dlci + //output dlci to temp + rtn + +set_CR_bit: + or_into 0x02,temp + rtn + + +else + +endif Index: tag/Soft/Librarier/bt_rom/program/scheduler.prog =================================================================== --- /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/scheduler.prog (nonexistent) +++ /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/scheduler.prog (working copy) @@ -0,0 +1,86 @@ +scheduler_process: + bpatchx patch32_0,mem_patch32 + call check_51cmd + call app_process_bb_event + call app_process_bt + call process_conn_sm + call HFP_HSP_process +ifdef SIMPLE_PAIRING + call sp_calc_sequence + call simple_pairing_sequence + call master_simple_paring_sequence +endif + call l2cap_malloc_is_fifo_empty + nrtn blank + call upper_sm_single_step +///l2cap_signal_channel + bpatchx patch32_1,mem_patch32 + call l2cap_prepare_send_config_req + call l2cap_prepare_send_connect_res_succ +//l2cap server channel + call l2cap_malloc_is_fifo_nearly_full + nrtn blank + call rfc_prepare_send_signal_ms + call l2cap_malloc_is_fifo_nearly_full + nrtn blank + + bmark0 mark_sco_flag,handle_avrcp + branch handle_avrcp, master + fetch 1,mem_current_sniff_attempt + fetcht 1, mem_sniff_attempt + isub temp,null + rtn zero +handle_avrcp: + call avctp_send_avr_vd_get_cap + call l2cap_check_empty_channel_info + branch l2cap_trigger_nochannel_waicthdog,user + branch l2cap_clear_nochannel_watchdog + +scheduler_tx_l2cap_pkt: + bpatchx patch32_2,mem_patch32 + call l2cap_malloc_is_fifo_empty + rtn blank //empty + fetch 1,mem_op + rtnbit1 op_txl2cap + call l2cap_malloc_fifo_out + store 2,mem_txptr + copy pdata,contr + ifetch 2,contr + increase 4,pdata + store 2,mem_tx_len + jam 6,mem_tx_lch//start pkt + fetch 2,mem_l2cap_tx_multi_offset + branch scheduler_tx_l2cap_start_pkt,blank + fetch 1,mem_op + rtnbit0 op_pkt_comp + set0 op_pkt_comp,pdata + store 1,mem_op + jam 5,mem_tx_lch//continue pkt + fetcht 2,mem_l2cap_tx_multi_offset + fetch 2,mem_txptr + iadd temp,pdata + store 2,mem_txptr + fetch 2,mem_tx_len + isub temp,pdata + store 2,mem_tx_len +scheduler_tx_l2cap_start_pkt: + fetch 2,mem_tx_len + branch assert,blank + arg l2cap_max_pkt_len,temp //max len of dh3 pkt + isub temp,pdata + nbranch scheduler_Tx_l2cap_last_pkt,positive + storet 2,mem_tx_len //l2cap_max_pkt_len + fetch 2,mem_l2cap_tx_multi_offset + iadd temp,pdata + store 2,mem_l2cap_tx_multi_offset + branch scheduler_Tx_l2cap_pkt_end +scheduler_Tx_l2cap_last_pkt: + setarg 0 + store 2,mem_l2cap_tx_multi_offset +scheduler_Tx_l2cap_pkt_end: + fetch 1,mem_op + set1 op_txl2cap,pdata + store 1,mem_op + rtn + + Index: tag/Soft/Librarier/bt_rom/program/sdp.prog =================================================================== --- /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/sdp.prog (nonexistent) +++ /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/sdp.prog (working copy) @@ -0,0 +1,1290 @@ +/**********************************************************************/ +/* Subroutine: sdp_process */ +/* Process Service Discovery Request */ +/* Called from L2CAP, check PDUID, branch to different req processings*/ +/* */ +/* Input: mem_L2CAP_Rx_payload */ +/* Output: mem_SDP_Tx_payload, mem_SDP_Tx_pkt_length */ +/* */ +/**********************************************************************/ +sdp_process: + bpatchx patch32_3,mem_patch32 + fetch 2,mem_l2cap_payload_ptr + iforce contr + ifetchr regb,1,contr /* PDUID */ + storer regb,1,mem_sdp_pduid + ifetch 2,contr + store 2,mem_sdp_transactionid /* save transaction id */ + ifetch 1,contr /* higher byte of parameter length */ + lshift8 pdata,timeup + ifetch 1,contr /* lower byte of parameter length */ + iadd timeup,timeup /* parameter length stored in "timeup" */ + copy contr,temp + arg 4,loopcnt + arg mem_sdp_handle_list,contw + call memset0 + copy temp,contr + bpatchx patch32_4,mem_patch32 + deposit regb /* PDUID */ + beq SDP_ERROR_RES,sdp_process_error_res + beq SDP_SEARCH_REQ,sdp_process_ss_req + beq SDP_SEARCH_RES,sdp_process_ss_res + beq SDP_ATTRIBUTE_REQ,sdp_process_sa_req + beq SDP_ATTRIBUTE_RES,sdp_process_sa_res + beq SDP_SEARCHATTRIB_REQ,sdp_process_ssa_req + beq SDP_SEARCHATTRIB_RES,sdp_process_ssa_res + branch sdp_insufficient_resource + +/**********************************************************************/ +/* ss_req */ +/* Processing Service Search Request */ +/* Call: ask_serviceclassid, empty_response */ +/* */ +/* Input: mem_L2CAP_Rx_payload pointer in contr */ +/* Output: mem_SDP_Tx_payload, mem_SDP_Tx_pkt_length */ +/* */ +/**********************************************************************/ +sdp_process_ss_req: + call ask_serviceclassid + compare 1,temp,0xff + branch ss_empty_rsp,true + compare 0xff,temp,0xff + branch sdp_invalid_request_syntax,true + + ifetch 2,contr /* max aservice record count */ + store 2,mem_sdp_record_maxcnt + increase -2,timeup + + increase -1,timeup /* continuation state 1 byte (0) */ + nbranch sdp_invalid_pdu_size,zero /* invalid pdu size */ + arg mem_sdp_uuid_search_ptr,timeup + ifetch 2,timeup + rtn blank + call search_all_uuid + call l2cap_get_sdp_tx_payload /* put the pointer to Tx buffer */ + force 3,pdata /* PDUID 3, Service Search Response */ + istore 1,contw + fetch 2,mem_sdp_transactionid /* write transaction id */ + istore 2,contw + lshift2 queue,pdata + add pdata,5,pdata + add pdata,5,regc + byteswap pdata,pdata + istore 2,contw /* write parLength */ + deposit queue + byteswap pdata,pdata + istore 2,contw /* write TotSrvRecCount */ + istore 2,contw /* write CurSrvRecCount */ + arg mem_sdp_handle_list,contr + copy queue,loopcnt + branch ss_req_blank,zero +ss_req_loop: + ifetch 4,contr + istore 4,contw + loop ss_req_loop +ss_req_blank: + force 0,pdata + istore 1,contw /* continuation state */ + deposit regc + store 2,mem_sdp_tx_pkt_length +// branch assert,blank + rtn + +/**********************************************************************/ +/* sa_req */ +/* Processing Service Attribute Request */ +/* Call: ask_attributeid, empty_response (if 3 stored attr. */ +/* not asked) or answer_attributelist */ +/* Input: mem_L2CAP_Rx_payload pointer in contr */ +/* Output: mem_SDP_Tx_payload, mem_SDP_Tx_pkt_length */ +/* */ +/**********************************************************************/ +sdp_process_sa_req: + ifetch 4,contr /* service record handle */ + store 4,mem_sdp_record_handle + increase -4,timeup + call sdp_store_maxbyte + store 2,mem_sdp_attribute_maxbyte + increase -2,timeup + call dataelementtype6 /* result: data size stored in rega */ + branch sdp_invalid_request_syntax,zero + compare 5,rega,0xff // length + //branch sa_req_all,true + branch sa_judge_wholerange,true +sa_isnot_wholerange: + arg mem_sdp_attrib_list,contw + force 0,queue + branch sa_req_loop +sa_judge_wholerange: + ifetch 1,contr + bne SDP_ATTRIBUTE_RANGE,sdp_invalid_request_syntax + ifetch 2,contr + nbranch sa_judge_wholerange_false1,blank + ifetch 1,contr + bne 0xff,sa_judge_wholerange_false2 + ifetch 1,contr + bne 0xff,sa_judge_wholerange_false3 //also exist potential bug because mem_sdp_attrib_list length is only 7f + branch sa_req_all +sa_judge_wholerange_false3: + increase -5,contr + branch sa_isnot_wholerange +sa_judge_wholerange_false2: + increase -4,contr + branch sa_isnot_wholerange +sa_judge_wholerange_false1: + increase -3,contr + branch sa_isnot_wholerange +sa_req_loop: + bpatchx patch32_5,mem_patch32 + ifetch 1,contr + beq SDP_ATTRIBUTE_ID, sa_req_one_id + beq SDP_ATTRIBUTE_RANGE, sa_req_range +sa_req_range: + ifetch 2, contr + istore 2, contw + increase 1,queue + byteswap pdata,regb + ifetch 2, contr + byteswap pdata,pdata +sa_req_range_id_increase: + increase 1, regb + isub regb, null + nbranch sa_req_range_id_finish,positive + copy pdata, regc + byteswap regb,pdata + istore 2, contw + increase 1,queue + copy regc, pdata + branch sa_req_range_id_increase +sa_req_range_id_finish: + increase -5,timeup + increase -5,rega + branch sa_req_check_next_id +sa_req_one_id: + ifetch 2,contr + istore 2,contw //save the attribute id in mem_sdp_attrib_list + increase 1,queue + increase -3,timeup + increase -3,rega +sa_req_check_next_id: + nbranch sdp_invalid_request_syntax,positive + nbranch sa_req_loop,zero //another attribute + increase -1,timeup + nbranch sdp_invalid_request_syntax,zero + + call l2cap_get_sdp_tx_payload + increase 10,contw + arg mem_sdp_attrib_list,rega +sa_req_handle_attributelist_next: + copy queue,pdata + branch sa_req_handle_attributelist_end,blank + ifetch 2,rega + branch sa_req_handle_attributelist_end,blank + iforce regb /* regb is the attribute ID */ + fetch 4,mem_sdp_record_handle + iforce temp + call search_handle_attrib + copy contr,pdata + branch sa_req_handle_attributelist_notfound,blank + increase -3,contr + ifetch 3,contr + istore 3,contw + call sdp_data_len + iforce loopcnt + call memcpy +sa_req_handle_attributelist_notfound: + increase 2,rega + increase -1, queue + branch sa_req_handle_attributelist_next + +sa_req_handle_attributelist_end: + arg SDP_ATTRIBUTE_RES,rega + call ssa_req_range_lastfreg_common + fetch 2,mem_sdp_tx_pkt_length + beq 11,sa_empty_rsp + branch ssa_req_range_attrbutes_length_no_continue + + +sdp_store_continue_common: + ifetch 1, contr + beq 0, sdp_store_continue_0byte + beq 1,sdp_store_continue_1byte + beq 2, sdp_store_continue_2byte +sdp_store_continue_0byte: + increase -1,timeup /* continuation state byte (0) */ + branch sdp_store_continue_end +sdp_store_continue_1byte: + ifetch 1, contr + increase -2,timeup /* continuation state byte (1) */ + branch sdp_store_continue_end +sdp_store_continue_2byte: + ifetch 2, contr + byteswap pdata,pdata + increase -3,timeup /* continuation state byte (2) */ +sdp_store_continue_end: + store 2, mem_sdp_continue_byte + rtn + +sa_req_all: + bpatchx patch32_6,mem_patch32 + increase -5,timeup + call sdp_store_continue_common + nbranch sdp_invalid_pdu_size,zero + fetcht 4,mem_sdp_record_handle + call search_handle + nbranch sdp_invalid_service_record_handle,zero + copy contr,rega + call l2cap_get_sdp_tx_payload + copy rega,contr + increase 3,contw//arg mem_SDP_Tx_payload+3,contw + copy contr,timeup //sdp start pointer + call sdp_get_data + copy pdata, rega //sdp total length + fetchr regb,2,mem_sdp_continue_byte + copy rega,pdata + isub regb,regb //total_length - continue_byte in regb + fetch 2, mem_sdp_attribute_maxbyte + isub regb, null + nbranch sa_req_all_fragment_sdp, positive + // the last fragment + disable user + fetch 2, mem_sdp_continue_byte + branch sa_req_all_fisrt_fragment,blank + iadd timeup, contr //set the read pointer + increase 3,regb //include the total length field, 3 bytes + copy regb, loopcnt + copy loopcnt, pdata + increase 3, pdata + byteswap pdata,pdata + istore 2, contw + copy loopcnt, pdata + byteswap pdata,pdata + istore 2, contw + branch sa_req_all_answer_attributelist_full_loop +sa_req_all_fisrt_fragment: + add rega,6,loopcnt + branch sa_req_all_parlength_continue_byte, user + byteswap loopcnt,pdata + branch sa_req_all_parlength_continue_byte_end +sa_req_all_parlength_continue_byte: + copy loopcnt, pdata + increase 2, pdata + byteswap pdata,pdata +sa_req_all_parlength_continue_byte_end: + istore 2,contw /* ParLength */ + increase -3,loopcnt + byteswap loopcnt,pdata + istore 2,contw /* AttrListByteCount */ + copy timeup,contr + branch sa_req_all_answer_attributelist_full_loop +sa_req_all_fragment_sdp: + enable user + fetchr rega,2,mem_sdp_attribute_maxbyte + copy rega,loopcnt + fetch 2, mem_sdp_continue_byte + branch sa_req_all_fisrt_fragment,blank + iadd timeup, contr + copy rega,pdata + increase 5,pdata + byteswap pdata,pdata + istore 2, contw + copy rega,pdata + byteswap pdata,pdata + istore 2, contw +sa_req_all_answer_attributelist_full_loop: + call memcpy + nbranch sa_req_all_last_frag_continue, user + force 2,pdata + istore 1,contw + copy contr, pdata + isub timeup, pdata + byteswap pdata,pdata + istore 2, contw // continuation length + branch sa_req_all_frag_end +sa_req_all_last_frag_continue: + force 0,pdata + istore 1,contw +sa_req_all_frag_end: + arg SDP_ATTRIBUTE_RES,rega + branch ssa_req_range_common + +/**********************************************************************/ +/* ssa_req */ +/* Processing Service Search Attribute Request */ +/* Call: ask_serviceclassid, ask_attributeid, empty_response */ +/* or answer_attributelist */ +/* Input: contr */ +/* Output: mem_SDP_Tx_payload, mem_SDP_Tx_pkt_length */ +/* */ +/**********************************************************************/ +sdp_process_ssa_req: + call ask_serviceclassid + compare 0xff,temp,0xff + branch sdp_invalid_request_syntax,true + call sdp_store_maxbyte + store 2,mem_sdp_attribute_maxbyte + increase -2,timeup + call dataelementtype6 + arg mem_sdp_attrib_list,contw + force 0,queue +ssa_req_loop: + bpatchx patch32_7,mem_patch32 + ifetch 1,contr + beq SDP_ATTRIBUTE_RANGE,ssa_req_range + ifetch 2,contr + istore 2,contw //save the attribute id in mem_sdp_attrib_list + increase 1,queue + increase -3,timeup + increase -3,rega + nbranch sdp_invalid_request_syntax,positive + nbranch ssa_req_loop,zero + increase -1,timeup + nbranch sdp_invalid_request_syntax,zero + call l2cap_get_sdp_tx_payload + increase 13,contw//arg mem_SDP_Tx_payload+13,contw + fetch 2,mem_sdp_uuid_search_ptr + iforce regc + arg mem_sdp_attrib_list,rega +ssa_req_attributelist_next: + bpatchx patch33_0,mem_patch33 + ifetch 2,rega + branch ssa_req_attributelist_end,blank + iforce regb /* regb is the attribute ID */ + call search_attrib + branch ssa_req_attributelist_notfound,blank + increase -3,contr + ifetch 3,contr + istore 3,contw + call sdp_data_len + iforce loopcnt + call memcpy +ssa_req_attributelist_notfound: + increase 2,rega + branch ssa_req_attributelist_next + +ssa_req_attributelist_end: + call ssa_req_range_lastfreg + fetch 2,mem_sdp_tx_pkt_length + beq 14,ssa_empty_rsp + call ssa_req_range_attrbutes_length_no_continue + branch ssa_req_range_attrbutes_length_no_continue + + +sdp_store_maxbyte: + ifetch 2,contr + byteswap pdata,pdata + increase -3,pdata + arg 200,temp + isub temp,null + nrtn positive + setarg 200 + rtn + + +ssa_req_range: + increase 4,contr + increase -5,timeup + increase -5,rega + nbranch sdp_invalid_request_syntax,zero + call sdp_store_continue_common + nbranch sdp_invalid_pdu_size,zero + arg mem_sdp_uuid_search_ptr,timeup + call search_all_uuid + deposit queue + branch ssa_empty_rsp,blank + store 1,mem_handle_humber + storer regb,2,mem_sdp_all_length + arg 0,queue + arg 0,rega + call l2cap_get_sdp_tx_payload + increase 10,contw +ssa_req_range_find_handle: + call ssa_req_range_get_length + nbranch assert,user + copy contr,timeup + copy pdata,regc + iadd rega,rega +// copy pdata,rega +// fetch 2,mem_sdp_all_length + fetch 2,mem_sdp_continue_byte + copy pdata,regb + branch ssa_req_range_first_freg,blank +ssa_req_range_later_freg_with_continue: + copy rega,pdata + isub regb,regb //total_length - continue_byte in rega + branch ssa_req_range_next_handle,zero + nbranch ssa_req_range_next_handle,positive + fetch 2, mem_sdp_attribute_maxbyte + isub regb, null + branch ssa_req_range_maxbyte_with_continue,zero + nbranch ssa_req_range_maxbyte_with_continue, positive + + // data length < =maxbyte +ssa_req_range_send_not_maxbyte: + copy regb,loopcnt + call ssa_req_range_maxbyte_with_continue_cpy + fetch 1,mem_handle_humber + increase 1,queue + isub queue,null + branch ssa_req_range_lastfreg,zero + branch ssa_req_range_freg_with_continue + +ssa_req_range_maxbyte_with_continue: + copy pdata,loopcnt + call ssa_req_range_maxbyte_with_continue_cpy + branch ssa_req_range_freg_with_continue + +ssa_req_range_maxbyte_with_continue_cpy: + increase -3,contw + copy loopcnt,temp + copy regc,pdata + isub regb,pdata + iadd timeup,contr + branch memcpy + +ssa_req_range_next_handle: + fetch 1,mem_handle_humber + increase 1,queue + isub queue,null + rtn zero // + branch ssa_req_range_find_handle + +ssa_req_range_get_length: + call disable_user + arg mem_sdp_handle_list,contr + lshift2 queue,pdata + iadd contr,contr + ifetcht 4, contr + call search_handle + nrtn zero + call sdp_data_len + branch enable_user + +ssa_req_range_first_freg: + fetch 2, mem_sdp_attribute_maxbyte + isub rega, null + nbranch ssa_req_range_firstfreg_maxbyte_with_continue,positive + copy rega,loopcnt + copy loopcnt,temp + copy timeup,contr + call memcpy + fetch 2,mem_sdp_all_length + isub rega,null + branch ssa_req_range_freg_no_continue,zero +ssa_req_range_firstfreg_not_maxbyte_with_continue: + call ssa_req_range_freg_with_continue + branch ssa_req_range_attrbutes_length + +ssa_req_range_freg_no_continue: + call ssa_req_range_lastfreg + branch ssa_req_range_attrbutes_length + +ssa_req_range_lastfreg: + arg SDP_SEARCHATTRIB_RES,rega //PUD ID +ssa_req_range_lastfreg_common: + force 0,pdata + istore 1,contw + call ssa_req_range_common + fetcht 2,mem_sdp_tx_pkt_length + increase -5,temp + byteswap temp,pdata + istore 2, contw + increase -3,temp + byteswap temp,pdata + istore 2, contw //attribute length + rtn + +ssa_req_range_firstfreg_maxbyte_with_continue: + copy pdata,loopcnt + copy loopcnt,temp + copy timeup,contr + call memcpy + call ssa_req_range_freg_with_continue +ssa_req_range_attrbutes_length: + setarg 0x36 + istore 1,contw + fetch 2,mem_sdp_all_length + byteswap pdata,pdata + istore 2, contw + rtn + +ssa_req_range_attrbutes_length_no_continue: + setarg 0x36 + istore 1,contw + increase -3,temp + byteswap temp,pdata + istore 2, contw + rtn + +ssa_req_range_freg_with_continue: + arg SDP_SEARCHATTRIB_RES,rega //PUD ID + setarg 2 + istore 1,contw + fetch 2,mem_sdp_continue_byte + iadd temp,temp + byteswap temp,pdata + istore 2,contw + call ssa_req_range_common + fetcht 2,mem_sdp_tx_pkt_length + increase -5,temp + byteswap temp,pdata + istore 2, contw + increase -5,temp + byteswap temp,pdata + istore 2, contw + rtn + +ssa_req_range_common: + fetch 2,mem_sdp_tx_payload_ptr + isub contw,pdata + sub pdata,0,pdata + store 2,mem_sdp_tx_pkt_length + call l2cap_get_sdp_tx_payload + copy rega,pdata //PUD ID + istore 1,contw + fetch 2,mem_sdp_transactionid + istore 2,contw + rtn + + + + +/**********************************************************************/ +/* ssa_res */ +/* Processing Service Search Attribute Response */ +/* Call: dataelementtype6, attribute_reading */ +/* Input: contr */ +/* Output: mem_sdp_record_handle,mem_sdp_search_failed */ +/* */ +/**********************************************************************/ +sdp_process_ssa_res: + rtn + +sdp_process_ss_res: + ifetch 2,contr + ifetch 2,contr + byteswap pdata,pdata + bne 1,assert + ifetch 4,contr + store 4,mem_sdp_record_handle + fetchr regc,2,mem_sdp_l2capch_ptr + add regc,offset_lc_state,regc + ifetch 1,regc + set1 L2CAP_CHANNEL_STATE_RECV_SEARCH_RES,pdata + istore 1,regc + + rtn + +sdp_process_sa_res: + fetchr regc,2,mem_sdp_l2capch_ptr + add regc,offset_lc_state,regc + ifetch 1,regc + set1 L2CAP_CHANNEL_STATE_RECV_ATTRIB_RES,pdata + istore 1,regc + + copy temp,contr + ifetch 2,contr + call search_rfcomm_cn + store 1,mem_profile_channel + rtn + +sdp_process_error_res: + rtn + +/**********************************************************************/ +/* Subroutine: attribute_reading */ +/* Reading each Data Element Sequence inside one Attribute List */ +/* Called from process_ssa_res */ +/* Call dataelementtype6 */ +/* Input: contr,timeup */ +/* Output: timeup,mem_sdp_LACAP_found,mem_sdp_RFCOMM_found */ +/* */ +/* */ +/**********************************************************************/ +attribute_reading: + call dataelementtype6 /* decode data element sequence */ + branch rdnortn,zero + force 0,regb /* regb to be used as 128 bit uuid flag */ + ifetch 1,contr + increase -1,rega + increase -1,timeup + compare 0x18,pdata,0xf8 /* 5 MSB: b00011, uuid */ + nbranch rduuid3,true + compare 0x04,pdata,0x07 /* 3 LSB: b100, 128 bits uuid */ + nbranch is032,true + force 1,regb /* mark it as 128 bit uuid */ +skp2bytes: + increase 2,contr /* skip 2 bytes */ + increase -2,rega + increase -2,timeup + branch rduuid1 /* add 126 bits */ +is032: + compare 0x02,pdata,0x07 /* 3 LSB: b010 32 bits uuid */ + nbranch is016,true + branch skp2bytes +is016: + compare 0x01,pdata,0x07 /* 3 LSB: b001 16 bit uuid */ + nbranch rduuid3,true +rduuid1: + ifetch 1,contr /* get higher order byte */ + increase -1,rega + increase -1,timeup + bne 0x01, rduuid2 + ifetch 1,contr /* get lower order byte */ + increase -1,rega + increase -1,timeup + bne 0x00, rduuid3 + jam 0xff,mem_sdp_LACAP_found /* set L2CAP found parameter */ + branch rduuid3 +rduuid2: + bne 0x00, rduuid3 + ifetch 1,contr /* get lower order byte */ + increase -1,rega + increase -1,timeup + bne 0x03, rduuid3 + copy regb,null + branch not16by,zero /* 128 bit uuid, skip 12 bytes */ + increase -12,contr + increase -12,timeup +not16by: + force 0xff,pdata + store 1,mem_sdp_RFCOMM_found /* set RFCOMM found parameter */ + ifetch 1,contr + increase -1,rega + increase -1,timeup + compare 0x08,pdata,0xf8 //b00001 + nbranch rduuid3,true + compare 0x00,pdata,0x07 + branch unsign1,true + compare 0x01,pdata,0x07 + branch unsign2,true + compare 0x02,pdata,0x07 + branch unsign4,true + compare 0x03,pdata,0x07 + branch unsign8,true + compare 0x04,pdata,0x07 + nbranch rduuid3,true + increase 8,contr + increase -8,rega + increase -8,timeup +unsign8: + increase 4,contr + increase -4,rega + increase -4,timeup +unsign4: + increase 2,contr + increase -2,rega + increase -2,timeup +unsign2: + increase 1,contr + increase -1,rega + increase -1,timeup +unsign1: + ifetch 1,contr + increase -1,rega + increase -1,timeup +rduuid3: + increase -1,timeup + increase -1,rega + branch rduuid3,positive /* if rega=0, done */ + increase 1,timeup /* return byte count */ + force 0x01,pdata + rtn +rdnortn: + force 0x00,pdata + rtn + +sdp_invalid_service_record_handle: + setarg 0x0200 + store 2,mem_sdp_error_code + branch sdp_error_response +sdp_invalid_pdu_size: + setarg 0x0400 + store 2,mem_sdp_error_code + branch sdp_error_response +sdp_insufficient_resource: + setarg 0x0600 + store 2,mem_sdp_error_code + branch sdp_error_response +sdp_invalid_request_syntax: + setarg 0x0300 + store 2,mem_sdp_error_code +sdp_error_response: + call l2cap_get_sdp_tx_payload + istore 1,contw + fetch 2,mem_sdp_transactionid + istore 2,contw + setarg 0x0200 + istore 2,contw + fetch 2,mem_sdp_error_code + istore 2,contw + jam 7,mem_sdp_tx_pkt_length + rtn + + +//store uuid in mem_sdp_uuid_search_ptr, +//return temp 0xff if wrong +ask_serviceclassid: + arg 0,regb + force 0,temp /* use "temp" to mark syntax error or to mark 128 bit uuid */ + arg mem_sdp_uuid_search_ptr,contw + call dataelementtype6 + branch asksrv_error,zero +classidloop: + increase 1,regb + ifetch 1,contr + increase -1,rega + increase -1,timeup + compare 0x18,pdata,0xf8 /* 5 MSB: b00011: uuid */ + nbranch asksrv_error,true + compare 0x04,pdata,0x07 /* 3 LSB: b100 128 bits uuid */ + nbranch cmp032,true + force 1,temp /* mark it as 128 bit uuid */ +skip2bytes: + ifetch 1,contr + increase -1,rega + increase -1,timeup + bne 0x00, frstbwrong + ifetch 1,contr + increase -1,rega + increase -1,timeup + beq 0x00, cmpuuid + branch scndbwrong +frstbwrong: + increase 1,contr + increase -1,rega + increase -1,timeup +scndbwrong: + increase 2,contr /* skip 2 bytes, first 2 bytes already wrong */ + increase -2,rega + increase -2,timeup + compare 0x00,temp,0xff /* 128 bits or 32 bits ? */ + branch loopornot,true + increase 12,contr /* skip 12 bytes, first 2 bytes already wrong */ + increase -12,rega + increase -12,timeup + branch loopornot +cmp032: + compare 0x02,pdata,0x07 /* 3 LSB: b010 32 bits uuid */ + nbranch cmp016,true + branch skip2bytes +cmp016: + compare 0x01,pdata,0x07 /* 3 LSB: b001 16 bit uuid */ + nbranch asksrv_error,true +cmpuuid: + increase -2,rega + increase -2,timeup + ifetch 2,contr /* higher order byte */ + sub regb,4,null + branch uuidsize,zero //max store uuids =3 + istore 2,contw +uuidsize: + compare 0x00,temp,0xff /* is this 128 bits uuid */ + branch loopornot,true + copy contr,temp + ifetch 1,contr + bne 0x00, wrong12b + ifetch 1,contr + bne 0x00, wrong12b + ifetch 1,contr + bne 0x10, wrong12b + ifetch 1,contr + bne 0x00, wrong12b + ifetch 1,contr + bne 0x80, wrong12b + ifetch 1,contr + bne 0x00, wrong12b + ifetch 1,contr + bne 0x00, wrong12b + ifetch 1,contr + bne 0x80, wrong12b + ifetch 1,contr + bne 0x5f, wrong12b + ifetch 1,contr + bne 0x9b, wrong12b + ifetch 1,contr + bne 0x34, wrong12b + ifetch 1,contr + beq 0xfb, chck12dn +wrong12b: + copy temp,contr +wrong12b1: + increase 12,contr /* skip 12 bytes */ + force 0x00,queue + force 0x00,temp + branch chck12dn + +chck12dn: + increase -12,timeup + increase -12,rega +loopornot: + compare 0x00,rega,0xff + nbranch classidloop,true + force 0,pdata + istore 2,contw /* end list with null */ + rtn +asksrv_error: + arg 0xff,temp + rtn + +/**********************************************************************/ +/* Subroutine: dataelementtype6 */ +/* Parse Data Element Sequence, obtain the data size */ +/* Input: SDP Rx Buf Pointer in contr, parameter count in timeup */ +/* Output: data length in rega, data pointer in contr */ +/* and parameter count in timeup, return with zero flag set: */ +/* syntax error */ +/**********************************************************************/ +dataelementtype6: + bpatchx patch33_1,mem_patch33 + ifetch 1,contr + increase -1,timeup + compare 0x30,pdata,0xf8 /* 5 MSB: b00110: type 6 */ + nbranch dsize_error,true + compare 0x07,pdata,0x07 /* 3 LSB: b111: 32 bits */ + branch dsize32,true + compare 0x06,pdata,0x07 /* 3 LSB: b110: 16 bits */ + branch dsize16,true + compare 0x05,pdata,0x07 /* 3 LSB: b101: 8 bits */ + nbranch dsize_error,true + ifetchr rega,1,contr /* data length in reg A */ + increase -1,timeup + branch dsize +dsize32: + increase 2,contr + increase -2,timeup +dsize16: + ifetch 2,contr + byteswap pdata,rega + increase -2,timeup +dsize: + force 0x01,pdata + rtn +dsize_error: + force 0x00,pdata + rtn + +/**********************************************************************/ +/* Subroutine: sa_empty_rsp */ +/* Send empty response */ +/* */ +/* Input: mem_sdp_pduid, mem_sdp_transactionid */ +/* Output: mem_SDP_Tx_payload, mem_SDP_Tx_pkt_length */ +/* */ +/**********************************************************************/ +ss_empty_rsp: + setarg SDP_SEARCH_RES + store 1, mem_sdp_pduid + branch empty_response +sa_empty_rsp: + setarg SDP_ATTRIBUTE_RES + store 1, mem_sdp_pduid + branch empty_response +ssa_empty_rsp: + setarg SDP_SEARCHATTRIB_RES + store 1, mem_sdp_pduid +empty_response: + call l2cap_get_sdp_tx_payload /* empty attribute list */ + fetchr regb,1,mem_sdp_pduid /* PDUID */ + istorer regb,1,contw + fetch 2,mem_sdp_transactionid /* copy back transaction id */ + istore 2,contw + setarg 0x0500 + istore 2, contw + compare SDP_ATTRIBUTE_RES,regb,0xff + branch fullsearch,true + compare SDP_SEARCHATTRIB_RES,regb,0xff + branch fullsearch,true + setarg 0x000000 + istore 5,contw + branch outempty + +fullsearch: /* pduid must be 5 or 7 */ + setarg 0x350200 + istore 5,contw +outempty: + jam 10,mem_sdp_tx_pkt_length + rtn + +//return length in pdata(whole element ,include header and data ), contr not change +sdp_data_len: + call store_contw + call store_contr + call sdp_get_data + call get_contw + call get_contr + copy temp,pdata + rtn + +//return data length in pdata, contr is data pionter,return length in temp(whole element ,include header and data ) +sdp_get_data: + ifetch 1,contr + and pdata,0x7,loopcnt + rshift3 pdata,pdata + bne 0,sdp_get_data_type_not0 +sdp_get_data_type0: + force 1,pdata + force 1,temp + rtn + +sdp_get_data_type_not0_sizeindex01234: + call left_shift_n + add pdata,1,temp //add header length + rtn +sdp_get_data_type_not0: + deposit loopcnt + sub pdata,4,null + branch sdp_get_data_type_not0_sizeindex01234,positive + beq 5,sdp_get_data_type_not0_sizeindex5 + beq 6,sdp_get_data_type_not0_sizeindex6 + beq 7,sdp_get_data_type_not0_sizeindex7 + rtn + +sdp_get_data_type_not0_sizeindex5: + ifetch 1,contr + add pdata,2,temp //add header length + rtn +sdp_get_data_type_not0_sizeindex6: + ifetch 2,contr + byteswap pdata,pdata + add pdata,3,temp //add header length + rtn +sdp_get_data_type_not0_sizeindex7: + ifetch 2,contr + byteswap pdata,pdata + ifetcht 2,contr + byteswap temp,temp + lshift16 temp,temp + iadd temp,pdata + add pdata,5,temp //add header length + rtn + +/* find with uuids +input uuids pionter in timeup +return handles in mem_sdp_handle_list; handles number in queue if found +return regb all length*/ +search_all_uuid: + bpatchx patch33_2,mem_patch33 + force 0,queue + arg 0,regb + arg mem_sdp_handle_list,contw +search_all_uuid_llop: + ifetch 2,timeup + rtn blank + call search_uuid + copy queue,pdata + rtneq SDP_MAX_HANDLE_NUMBER + increase 2,timeup + branch search_all_uuid_llop + +search_uuid: +// arg 0,regb + iforce regc +// force 0,queue + bpatchx patch33_3,mem_patch33 + fetch 2, mem_ui_uuid_table + iforce contr +search_uuid_next: + copy queue,pdata + rtneq SDP_MAX_HANDLE_NUMBER + disable user + ifetch 1,contr + rtn blank + iforce loopcnt +search_uuid_loop: + ifetch 2,contr + isub regc,null + nbranch search_uuid_not_found,zero + enable user // uuid match +search_uuid_not_found: + loop search_uuid_loop + ifetcht 4,contr // get handle + copy contr,rega + nbranch search_uuid_nomatch,user + arg mem_sdp_handle_list,contr + arg SDP_MAX_HANDLE_NUMBER,loopcnt +search_uuid_check_same_handle: + ifetch 4,contr + branch search_uuid_store_handle,blank + isub temp,null + branch search_uuid_nomatch,zero + loop search_uuid_check_same_handle + rtn +search_uuid_store_handle: + istoret 4,contw + increase 1,queue + copy rega,contr + call sdp_data_len + iadd regb,regb + iadd contr,contr + branch search_uuid_next +search_uuid_nomatch: + copy rega,contr + call sdp_get_data + iadd contr,contr // next paragraph + branch search_uuid_next + +/* temp is handle, +return zero if found +return data pointer in contr +*/ +search_handle: + bpatchx patch33_4,mem_patch33 + fetch 2,mem_ui_uuid_table + iforce contr +search_handle_loop: + ifetch 1,contr + branch disable_zero,blank + lshift pdata,pdata + iadd contr,contr + ifetch 4,contr + isub temp,null + rtn zero + deposit contw + store 2,mem_contw + storet 8,mem_temp + call sdp_get_data + iadd contr,contr + copy contr,pdata + fetcht 2,mem_contw + copy temp,contw + fetcht 8,mem_temp + copy pdata,contr + branch search_handle_loop + +/** +* input regb and regc.regb is the attribute ID and regc is UUID. +* set contr if find attribute or 0 if not +*/ +search_attrib: + bpatchx patch33_5,mem_patch33 + fetch 2,mem_ui_uuid_table + iforce contr +search_attrib_next: + ifetch 1,contr + branch search_attrib_end, blank + iforce loopcnt +search_attrib_loop: + ifetch 2,contr + isub regc,null /* regc is UUID, compare it */ + branch search_attrib_found_uuid,zero + loop search_attrib_loop + increase 4,contr + call sdp_get_data + iadd contr,contr /* next paragraph */ + branch search_attrib_next +search_attrib_found_uuid: + increase -1,loopcnt + lshift loopcnt,pdata + iadd contr,contr + increase 4,contr + call sdp_get_data + iadd contr,timeup /* attribute list end */ +search_attrib_loop_attribs: + increase 1,contr + ifetch 2,contr + isub regb,null + //force 0x1,pdata,zero +// setflag zero, 0,pdata +// copy timeup, timeup + branch setarg1,zero /* attribute found */ + call sdp_data_len + iadd contr,contr + deposit timeup + isub contr,null + branch search_attrib_end, zero /*attribute end, not found the attribute, return contr = 0*/ + branch search_attrib_loop_attribs +search_attrib_end: + force 0,contr + force 0,pdata + rtn + + +//search the attribute according the record handle +//record handle in temp, attribute in regb +//set the contr to zero if not found +search_handle_attrib: + bpatchx patch33_6,mem_patch33 + fetch 2,mem_ui_uuid_table + iforce contr +search_handle_attrib_next: + ifetch 1,contr + branch search_handle_attrib_end, blank + lshift pdata,pdata + iadd contr, contr + ifetch 4,contr + isub temp,null /* regc is UUID, compare it */ + branch search_handl_attrib_found_handle,zero + copy temp,timeup + call sdp_get_data + copy timeup,temp + iadd contr,contr /* next paragraph */ + branch search_handle_attrib_next +search_handl_attrib_found_handle: + call sdp_get_data + iadd contr,timeup /* attribute list end */ +search_handle_attrib_loop_attribs: + increase 1,contr + ifetch 2,contr + isub regb,null + rtn zero /* attribute found */ + call sdp_data_len + iadd contr,contr + deposit timeup + isub contr,null + branch search_handle_attrib_end, zero /*attribute end, not found the attribute, return contr = 0*/ + branch search_handle_attrib_loop_attribs +search_handle_attrib_end: + force 0,contr + rtn + + +//enable user if find rfcomm channel number, pdata is channel number +search_rfcomm_cn: + arg 0x0400,regb // attribute protocol edscriptor list + call search_handl_attrib_found_handle + arg 0x0300,regb // uuid rfcomm + call search_uuid_in_data + nrtn user + sub rega,3,null + branch disable_user,positive + ifetch 1,contr + bne 0x08,disable_user + ifetch 1,contr + rtn + + //input timeup is lenth + //input contr is data ptr + //return contr is end of uuid; enable user if found uuid +search_uuid_in_data: + bpatchx patch33_7,mem_patch33 + call sdp_get_data + copy pdata,rega +search_uuid_in_data_loop: + ifetch 1,contr + and pdata,0x7,loopcnt + rshift3 pdata,pdata + sub pdata,3,null + branch search_uuid_in_data_found_uuid,zero + copy loopcnt,pdata + beq 5,search_uuid_in_data_found_element_index5 + beq 6,search_uuid_in_data_found_element_index6 + beq 7,search_uuid_in_data_found_element_index7 + increase -1,contr + call sdp_get_data + iadd contr,contr + copy rega,pdata + isub temp,rega + branch disable_user,zero + branch search_uuid_in_data_loop + +search_uuid_in_data_found_element_index5: + increase -2,rega + increase 1,contr + branch search_uuid_in_data_loop +search_uuid_in_data_found_element_index6: + increase -3,rega + increase 2,contr + branch search_uuid_in_data_loop +search_uuid_in_data_found_element_index7: + increase -5,rega + increase 4,contr + branch search_uuid_in_data_loop + +search_uuid_in_data_found_uuid: + increase -1,rega + copy loopcnt,pdata + beq 1,search_uuid_in_data_type_uuid_16 + beq 2,search_uuid_in_data_type_uuid_32 + beq 4,search_uuid_in_data_type_uuid_128 + branch disable_user +search_uuid_in_data_type_uuid_128: + increase -12,rega +search_uuid_in_data_type_uuid_32: + ifetch 2,contr + increase -2,rega +search_uuid_in_data_type_uuid_16: + ifetch 2,contr + isub regb,null + branch enable_user,zero + increase -2,rega + branch disable_user,zero + branch search_uuid_in_data_loop + + +//rega:l2cap len ,mem_search_uuid:uuid to search +sdp_send_search_req: + call l2cap_malloc_sdp_req + setarg SDP_SEARCH_REQ + istore 1,contw + fetch 2,mem_sdp_transactionid_local + byteswap pdata,pdata + istore 2,contw + increase -5,rega + byteswap rega,rega + istorer rega,2,contw + setarg 0x0335 + istore 2,contw + setarg 0x19 + istore 1,contw + fetch 2,mem_search_uuid + istore 2,contw + setarg 0x0008 + istore 2,contw + setarg 0 + istore 1,contw + rtn + +//rega:l2cap len +sdp_send_attribute_req: + call l2cap_malloc_sdp_req + setarg SDP_ATTRIBUTE_REQ + istore 1,contw + fetch 2,mem_sdp_transactionid_local + byteswap pdata,pdata + istore 2,contw + increase -5,rega + byteswap rega,rega + istorer rega,2,contw + fetch 4,mem_sdp_record_handle + istore 4,contw + setarg 0x2c01 + istore 2,contw + setarg 0x0535 + istore 2,contw + setarg 0x0a + istore 1,contw + setarg 0 + istore 2,contw + setarg -1 + istore 2,contw + setarg 0 + istore 1,contw + rtn + +sdp_send_spp_request: + call l2cap_get_sdp_tx_payload + copy pdata,contw + setarg 6//Search Attr Req + istore 1,contw + setarg sdp_tid_spp + istore 2,contw + setarg 0x0f00 //length15 + istore 2,contw + setarg 0x1a0535 + istore 3,contw + setarg 0x0111 + lshift16 pdata,pdata //UUID + istore 4,contw + setarg 0x2600 //max return len + istore 2,contw + setarg 0x0335 + istore 2,contw + setarg 0x0009 + istore 2,contw + setarg 0x0004 + istore 2,contw + jam 0x14,mem_sdp_tx_pkt_length + rtn + + Index: tag/Soft/Librarier/bt_rom/program/security.prog =================================================================== --- /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/security.prog (nonexistent) +++ /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/security.prog (working copy) @@ -0,0 +1,1634 @@ + +ifdef SECURE_CONNECTION + +function_g2: + bpatchx patch34_0,mem_patch34 + jam 80,mem_AES_CMAC_data_length + arg memdat,contw + arg mem_le_srand,contr + call memcpy16 + arg mem_le_pubkey_local_x_256,contr + call memcpy32 + arg mem_le_pubkey_remote_x_256,contr + call memcpy32 + call inverse_memdat + arg mem_le_mrand,contr + call store_inverse_k + call function_AES_CMAC + + arg mem_AES_CMAC_temp,contw + call load_inverse_result + setarg 1000000 + copy pdata,rega + fetch 4,mem_AES_CMAC_temp + idiv rega + call wait_div_end + remainder pdata + store 4,mem_gkey + rtn + +function_f6_eb: + jam 65,mem_AES_CMAC_data_length + arg memdat,contw + call store_addr_common_a + call store_addr_common_b + fetch 3,mem_le_pres+1 + istore 3,contw +// arg mem_le_r,contr +// call memcpy16 + call get_r + + arg mem_le_mrand,contr + call memcpy16 + arg mem_le_srand,contr + call memcpy16 + call inverse_memdat + arg mem_le_mackey ,contr + arg mem_AES_CMAC_k,contw + call memcpy16 +// call p_store_inverse_k + branch function_AES_CMAC +// arg mem_AES_CMAC_temp,contw +// branch p_load_inverse_result + +get_r: + fetch 4,mem_le_tk + istore 4,contw + call memset0_4 + branch memset0_8 + +function_f6_ea: + jam 65,mem_AES_CMAC_data_length + arg memdat,contw + call store_addr_common_b + call store_addr_common_a + fetch 3,mem_le_preq+1 + istore 3,contw +// arg mem_le_r,contr +// call memcpy16 + call get_r + arg mem_le_srand,contr + call memcpy16 + arg mem_le_mrand,contr + call memcpy16 + call inverse_memdat + arg mem_le_mackey ,contr + arg mem_AES_CMAC_k,contw + call memcpy16 +// call p_store_inverse_k + call function_AES_CMAC + arg mem_AES_CMAC_temp,contw + branch load_inverse_result + +function_f5: + jam 32,mem_AES_CMAC_data_length + arg mem_le_dhkey_256 ,contr + arg memdat,contw + call memcpy32 + call inverse_memdat + arg mem_le_slat,contr + call store_inverse_k + call function_AES_CMAC + arg mem_AES_CMAC_k,contw + call store_aes_result + arg 1,temp + call function_f5_common + arg mem_le_ltk,contw + call load_inverse_result + arg 0,temp + call function_f5_common + arg mem_le_mackey,contw +// branch p_load_inverse_result + branch store_aes_result + + +function_f5_common: + bpatchx patch34_1,mem_patch34 + jam 53,mem_AES_CMAC_data_length + setarg 0x100 + store 2,memdat + call store_addr_common_b + call store_addr_common_a + arg mem_le_srand,contr + call memcpy16 + arg mem_le_mrand,contr + call memcpy16 +// fetch 4,mem_le_keyid 0x62746c65 + setarg 0x6c65 + istore 2,contw + setarg 0x6274 + istore 2,contw + istoret 1,contw //counter + call inverse_memdat + branch function_AES_CMAC + +store_addr_common_b: + fetch 6,mem_le_lap + istore 6,contw + fetch 1,mem_le_conn_own_addr_type + istore 1,contw + rtn + +store_addr_common_a: + fetch 6,mem_le_plap + istore 6,contw +// setarg 0x2dcfc1 +// istore 3,contw +// setarg 0xa71370 +// istore 3,contw + fetch 1,mem_le_conn_peer_addr_type + istore 1,contw + rtn + +function_f4_ca: + jam 65,mem_AES_CMAC_data_length + fetch 1,mem_passkey_1bit + store 1,memdat + arg mem_le_pubkey_local_x_256,contr + call memcpy32 + arg mem_le_pubkey_remote_x_256,contr + call memcpy32 + call inverse_memdat + arg mem_le_mrand,contr + call store_inverse_k + branch function_AES_CMAC + + +function_f4_cb: + jam 65,mem_AES_CMAC_data_length + fetch 1,mem_passkey_1bit + store 1,memdat + arg mem_le_pubkey_remote_x_256,contr + call memcpy32 + arg mem_le_pubkey_local_x_256,contr + call memcpy32 + call inverse_memdat + arg mem_le_srand,contr + call store_inverse_k + branch function_AES_CMAC + +function_AES_CMAC: + call function_AES_CMAC_Generate_Subkey +//call ice_break +// jam 65,mem_AES_CMAC_data_length +//call ice_break + fetch 1,mem_AES_CMAC_data_length + copy pdata,temp +function_ceil16: + increase 15,pdata + rshift4 pdata,pdata + copy pdata,regb + branch function_AES_CMAC_set_flag_0_balnk,blank + and temp,0x0f,pdata + nbranch function_AES_CMAC_set_flag_0,blank +// flag =1; + arg mem_AES_CMAC_k1,regc + arg memdat,pdata + increase -16,pdata +// iadd temp,pdata +// isub rega,rega + iadd temp,rega + arg mem_AES_CMAC_M_last,contw + arg 4,loopcnt + call xor_loop +//call ice_break +// arg mem_f4_k1,contr +// call load_key + branch function_AES_CMAC_aes + +function_AES_CMAC_set_flag_0_balnk: + arg 1,regb + arg 0,rega +// arg mem_f4_test_data,pdata + branch function_AES_CMAC_set_flag_0_common +//call ice_break + +function_AES_CMAC_set_flag_0: +// flag = 0; + and temp,0x0f,rega +function_AES_CMAC_set_flag_0_common: + arg memdat,pdata + iadd temp,pdata + isub rega,contr +//call ice_break + arg mem_AES_CMAC_temp,contw + call function_AES_CMAC_padding +//call ice_break + arg mem_AES_CMAC_k2,regc + arg mem_AES_CMAC_temp,rega + arg mem_AES_CMAC_M_last,contw + arg 4,loopcnt + call xor_loop + +// arg mem_f4_k2,contr +// call load_key + +// branch p_function_f4_aes +function_AES_CMAC_aes: +// arg mem_f4_k,contr +// call load_key +// arg mem_AES_CMAC_xor,contr +// call load_data128 + call aes_clear_data + call aes_init +// arg mem_f4_k,contr +// call load_key + arg memdat,contr +function_AES_CMAC_aes_loop: +//generate_mic_loop: + increase -1,regb + deposit regb + branch function_AES_CMAC_aes_loop_end,blank + call load_data128 + call do_aes_cbc + branch function_AES_CMAC_aes_loop +//generate_mic_end: +function_AES_CMAC_aes_loop_end: + arg mem_AES_CMAC_temp,contw + call store_aes_result + arg mem_AES_CMAC_M_last,contr + call load_data128 + call aes_init + arg mem_AES_CMAC_temp,contr + call load_data128 + branch do_aes_cbc + + + +load_inverse_result: +// arg mem_AES_CMAC_temp,contw + copy contw,rega + call store_aes_result +// arg mem_AES_CMAC_temp,rega + arg 16,loopcnt + branch inverse_data + +store_inverse_k: + arg mem_AES_CMAC_k,contw + call memcpy16 +inverse_k: + arg 16,loopcnt + arg mem_AES_CMAC_k,rega + branch inverse_data + +inverse_memdat: + fetch 1,mem_AES_CMAC_data_length + copy pdata,loopcnt + arg memdat,rega + branch inverse_data + +bn_lshift_0_inverse: + ifetch 1,regA + lshift pdata,pdata + isolate1 0,regC + setflag true,0,pdata + isolate1 8,pdata + setflag true,0,regC + istore 1,rega + increase -1,rega + loop bn_lshift_0_inverse + rtn + +function_AES_CMAC_k1_inverse: + arg mem_AES_CMAC_k1,regA +function_AES_CMAC_inverse_common: + increase 15,rega + force 16,loopcnt + force 0,regC + branch bn_lshift_0_inverse + +function_AES_CMAC_k2_inverse: + arg mem_AES_CMAC_k2,regA + branch function_AES_CMAC_inverse_common + + +function_AES_CMAC_Generate_Subkey: + arg mem_AES_CMAC_k,contr + call load_key128 +// arg mem_AES_CMAC_xor,contr +// call aes_load_xor + force regidx_xor,regext_index + call aes_clear + call aes_clear_data + + call do_aes_ecb + +// force 0x38,aes_ctrl +// force 0x0,aes_ctrl +// call wait_aes + arg mem_AES_CMAC_k1,contw + call store_aes_result +function_AES_CMAC_k1: + fetch 1,mem_AES_CMAC_k1 + isolate1 7,pdata + nbranch function_AES_CMAC_k1_0,true + call function_AES_CMAC_k1_inverse + +//p_function_f4_k1_xor: + arg mem_AES_CMAC_k1,regc +// arg mem_AES_CMAC_rb,rega + arg mem_AES_CMAC_k1,contw +// arg 3,loopcnt +// call xor_loop + call function_AES_CMAC_xor_rb + branch function_AES_CMAC_k2 +function_AES_CMAC_k1_0: + call function_AES_CMAC_k1_inverse +function_AES_CMAC_k2: +//call ice_break + arg mem_AES_CMAC_k1,contr + arg mem_AES_CMAC_k2,contw + call memcpy16 + fetch 1,mem_AES_CMAC_k2 + isolate1 7,pdata + nbranch function_AES_CMAC_k2_inverse,true + call function_AES_CMAC_k2_inverse +//p_function_f4_k2_xor: + arg mem_AES_CMAC_k2,regc +// arg mem_AES_CMAC_rb,rega + arg mem_AES_CMAC_k2,contw +// arg 3,loopcnt +// branch xor_loop + + +//rb:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 87 +function_AES_CMAC_xor_rb: + arg 3,loopcnt +function_AES_CMAC_xor_rb_loop: + arg 0,temp + call function_AES_CMAC_xor_loop_common + increase 4,regc + loop function_AES_CMAC_xor_rb_loop + arg 0x8700,temp + lshift16 temp,temp +function_AES_CMAC_xor_loop_common: + ifetch 4,regc + ixor temp,pdata + istore 4,contw + rtn + + + + +//input rega :length <16 contr,contw +function_AES_CMAC_padding: + bpatchx patch34_2,mem_patch34 + arg 16,loopcnt + arg 0,pdata +function_AES_CMAC_padding_loop: + isub rega,null + branch function_AES_CMAC_padding_beq_length,zero + branch function_AES_CMAC_padding_big_length,positive + ifetcht 1,contr + istoret 1,contw +function_AES_CMAC_padding_loop2: + increase 1,pdata + loop function_AES_CMAC_padding_loop + rtn +function_AES_CMAC_padding_beq_length: + arg 0x80,temp +function_AES_CMAC_padding_common: + istoret 1,contw + branch function_AES_CMAC_padding_loop2 + +function_AES_CMAC_padding_big_length: + arg 0,temp + branch function_AES_CMAC_padding_common + +endif + +generate_kinit: + call function_e22 + arg mem_input_store,contr + arg mem_kinit,contw /* Kinit is ready */ + branch memcpy16 + + +function_e21: /* rega pointers to bdaddr */ + disable user + call function_expand + arg mem_random_number,contr + arg mem_x,contw + force 15,loopcnt + call memcpy + ifetch 1,contr + xor_into 6,pdata + istore 1,contw + setarg mem_y + store 2,memp_ar_input + setarg mem_x + store 2,memp_ar_key + set1 mark_ar2,mark + branch function_ar + + + +function_e22: /* rega pointers to bdaddr */ + fetcht 1,mem_pin_length + force 16,regb /* total 16 bytes */ + add temp,6,regc /* regc is l' */ + sub regc,16,null + branch function_e22_pin_init,positive + force 16,regc +function_e22_pin_init: /* generate x from pin and bdaddr */ + arg mem_x,contw +function_e22_genx_pin: + arg mem_pin,contr + copy temp,loopcnt + disable user +function_e22_genx_loop: + ifetch 1,contr + istore 1,contw + increase -1,regb + branch function_e22_genx_end,zero + loop function_e22_genx_loop + branch function_e22_genx_pin,user + enable user + force 6,loopcnt + copy rega,contr + branch function_e22_genx_loop +function_e22_genx_end: + arg mem_random_number,contr + arg mem_y,contw + call memcpy16 + fetch 1,mem_y15 + ixor regc,pdata + store 1,mem_y15 /* inpy[15] = rand_num[15]^l'; */ + setarg mem_y + store 2,memp_ar_input + setarg mem_x + store 2,memp_ar_key + set1 mark_ar2,mark + branch function_ar + + + + +function_e1: /* rega pointers to bdaddr */ + disable user + call function_expand + branch function_hash + +function_e3: + arg mem_aco,rega + enable user + call function_expand + call function_hash + arg mem_input_store,contr + arg mem_kc,contw + branch memcpy16 + + /* costs 41769 clocks */ +function_hash: + setarg mem_random_number + store 2,memp_ar_input + setarg mem_link_key + store 2,memp_ar_key + set0 mark_ar2,mark + call function_ar + arg mem_input_store,rega + arg mem_random_number,regb + arg mem_x,contw + call xor16 + arg mem_x,rega + arg mem_y,regb + copy regb,contw + enable user + call add16 + call key_offset + setarg mem_y + store 2,memp_ar_input + setarg mem_x + store 2,memp_ar_key + set1 mark_ar2,mark + branch function_ar + + + /* totally costs 20700 clocks */ +function_ar: + jam 0,mem_ar_hround + fetch 2,memp_ar_key + iforce contr + arg mem_key_store,contw + call memcpy16 + fetch 2,memp_ar_input + iforce contr + arg mem_input_store,contw + call memcpy16 + +function_ar_loop: + call key_scheduling + disable user + bmark0 mark_ar2,function_ar_original + fetch 1,mem_ar_hround + bne 4,function_ar_original + fetchr regb,2,memp_ar_input + call xor_mod32_ar2 +function_ar_original: + call xor_mod32 + call el_boxes + fetch 1,mem_ar_hround + increase 1,pdata + store 1,mem_ar_hround + + call key_scheduling + enable user + call xor_mod32 + call pht + call permute + call pht + call permute + call pht + call permute + call pht + fetch 1,mem_ar_hround + increase 1,pdata + store 1,mem_ar_hround + bne 16,function_ar_loop + call key_scheduling + disable user + branch xor_mod32 + +/* input round number and temp key in mem_key_store, and output the next temp key in mem_key_store */ +/* round key is generated and store in mem_round_key */ +key_scheduling: + fetch 1,mem_ar_hround + arg mem_key_store,contr + branch key_sched_zero,blank + iforce regb /* regb is half round */ + force 17,loopcnt + copy contr,contw +key_rotateloop: + ifetch 1,contr + lshift3 pdata,temp + rshift2 pdata,pdata + rshift3 pdata,pdata + ior temp,pdata + istore 1,contw + loop key_rotateloop + setarg mem_key_store + iadd regb,contr + force 16,loopcnt + arg mem_round_key,contw +key_select_octet_loop: + ifetch 1,contr + istore 1,contw + compare mem_key_store_end,contr,0xff + nbranch key_select_octet_nwrap,true + increase -17,contr +key_select_octet_nwrap: + loop key_select_octet_loop + force 0,rega /* rega is index of octet within row */ + add regb,-1,regc /* this is the row index, half_round#1 is 0 */ + lshift2 regc,regc + lshift2 regc,regc + call enable_authrom + setarg mem_b_box + iadd regc,regc /* regc hold the starting address of the row */ + arg mem_round_key,contw + force 16,loopcnt +bias_round_key_loop: + ifetcht 1,regc + ifetch 1,contw + iadd temp,pdata + istore 1,contw + increase 1,regc + loop bias_round_key_loop + branch disable_authrom + +key_sched_zero: /* round 0, key1 */ + force 16,loopcnt + force 0,temp +create_byte_16_loop: + ifetch 1,contr + ixor temp,temp + loop create_byte_16_loop + deposit temp + istore 1,contr /* store the byte #16 */ + arg mem_key_store,contr + arg mem_round_key,contw + branch memcpy16 + +xor_mod32: /* xor on 0,3, add on 1,2. if user is set, invert. x in rega and y in regb, out in contw */ + arg mem_round_key,regb +xor_mod32_ar2: + force 16,loopcnt + arg mem_input_store,rega + copy rega,contw +xor_mod32_loop: + ifetcht 1,rega + ifetch 1,regb + ixor temp,alarm + and loopcnt,3,regc + nbranch xor_mod32_invert,user + xor_into 3,regc +xor_mod32_invert: + sub regc,1,regc + branch xor_even,positive + iadd temp,alarm +xor_even: + istorer alarm,1,contw + increase 1,rega + increase 1,regb + loop xor_mod32_loop + rtn + +el_boxes: + call enable_authrom + force 16,loopcnt + arg mem_input_store,rega +el_box_loop: + ifetch 1,rega + arg mem_e_box,contr + and loopcnt,3,regc + sub regc,1,null + branch e_boxes,positive + arg mem_l_box,contr +e_boxes: + iadd contr,contr + ifetch 1,contr + istore 1,rega + increase 1,rega + loop el_box_loop + branch disable_authrom + +pht: + force 8,loopcnt + arg mem_input_store,contr + copy contr,contw +pht_loop: + ifetchr rega,1,contr + ifetchr regb,1,contr + lshift rega,pdata + iadd regb,pdata + istore 1,contw + deposit rega + iadd regb,pdata + istore 1,contw + loop pht_loop + rtn + +/* 8 11 12 15 2 1 6 5 10 9 14 13 0 7 4 3 */ +permute: + setarg 0x8ae42c + iforce temp + force 7,loopcnt + call permute_exchange + setarg 0xd751b + iforce temp + force 5,loopcnt + call permute_exchange + fetchr rega,1,mem_input_store+15 + fetch 1,mem_input_store+3 + store 1,mem_input_store+15 + storer rega,1,mem_input_store+3 + rtn + +permute_exchange: + and temp,0xf,regb +permute_loop: + and temp,0xf,pdata + arg mem_input_store,contw + iadd contw,contw + ifetchr regc,1,contw + istorer rega,1,contw + copy regc,rega + rshift4 temp,temp + loop permute_loop + setarg mem_input_store + iadd regb,contw + istorer rega,1,contw + rtn + +add16: + enable user + branch xor_add16 + +xor16: + disable user +xor_add16: /* if user is set, do add, else do xor */ + force 16,loopcnt /* rega and regb pointers to src, contw is result */ +xoradd_loop: + ifetcht 1,rega + ifetch 1,regb + branch xoradd_add,user + ixor temp,pdata + branch xoradd_store +xoradd_add: + iadd temp,pdata +xoradd_store: + istore 1,contw + increase 1,rega + increase 1,regb + loop xoradd_loop + rtn + + +function_expand: /* rega pointers to bdaddr, or aco and user is set */ + arg mem_y,contw + ifetch 6,rega + istore 6,contw + branch expand_12,user + ifetch 6,rega + branch expand_cont +expand_12: + ifetch 6,contr +expand_cont: + istore 6,contw + ifetch 4,rega + istore 4,contw + rtn + +key_offset: + arg mem_link_key,contr + arg mem_x,contw + arg 0,temp + setarg 0x8395a7 + call concatenate_temp24 + setarg 0xb3c1df + call concatenate_temp24 + setarg 0xe5e9 + call concatenate_temp16 + copy temp,regab + disable user + call key_addxor + copy regab,temp + enable user + branch key_addxor + +key_addxor: + force 8,loopcnt +key_addxor_loop: + ifetch 1,contr + compare 1,loopcnt,1 + branch key_high,user + branch key_xor,true +key_add: + iadd temp,pdata + branch key_store +key_high: + branch key_add,true +key_xor: + ixor temp,pdata +key_store: + istore 1,contw + rshift8 temp,temp + loop key_addxor_loop + rtn + +copy_aco: + fetch 6,mem_input_store+4 + store 6,mem_aco + ifetch 6,contr + istore 6,contw + rtn + +concatenate_temp24: + lshift8 temp,temp +concatenate_temp16: + lshift16 temp,temp + ior temp,temp + rtn + +ifdef TESTING +test_security: + fetch 1,0xff + branch test_security,blank + + /* inrand */ + setarg 0x1BC683 + store 3,0x0 + setarg 0x122980 + istore 3,contw + setarg 0xD0DB17 + istore 3,contw + setarg 0x2B1D78 + istore 3,contw + setarg 0x2743A6 + istore 3,contw + setarg 0xD8 + istore 1,contw + + /* comb A */ + setarg 0xA6D0C9 + store 3,0x10 + setarg 0xA9E86C + istore 3,contw + setarg 0x9E89D5 + istore 3,contw + setarg 0xC61838 + istore 3,contw + setarg 0x6F0318 + istore 3,contw + setarg 0x9F + istore 1,contw + + /* comb B */ + setarg 0x7F6833 + store 3,0x20 + setarg 0xE62E1B + istore 3,contw + setarg 0x9F67FC + istore 3,contw + setarg 0x8D3712 + istore 3,contw + setarg 0x0B846C + istore 3,contw + setarg 0x4A + istore 1,contw + + /* auth rand A */ + setarg 0xFBB686 + store 3,0x30 + setarg 0x19FE7F + istore 3,contw + setarg 0x16A439 + istore 3,contw + setarg 0xF4F6A4 + istore 3,contw + setarg 0x10D61D + istore 3,contw + setarg 0xDE + istore 1,contw + + /* auth rand B */ + setarg 0x735B0C + store 3,0x40 + setarg 0xA7F06B + istore 3,contw + setarg 0x04625E + istore 3,contw + setarg 0x3463B0 + istore 3,contw + setarg 0xB8F17A + istore 3,contw + setarg 0x7C + istore 1,contw + + /* address A */ + setarg 0xf91330 + store 3,0xb0 + setarg 0x664c7d + istore 3,contw + + /* address B */ + setarg 0xdc7100 + store 3,0xb8 + setarg 0x2ea003 + istore 3,contw + + /* sres A */ + setarg 0x2EEE19 + store 3,0x50 + setarg 0x7E + istore 1,contw + + /* sres B */ + setarg 0x4231A4 + store 3,0x58 + setarg 0xD1 + istore 1,contw + + /* linkA */ + setarg 0xa6a026 + store 3,0x60 + setarg 0x2569d2 + istore 3,contw + setarg 0xab4a9d + istore 3,contw + setarg 0x5e87c0 + istore 3,contw + setarg 0x792aa9 + istore 3,contw + setarg 0x4b + istore 1,contw + + /* linkB */ + setarg 0xa1f07d + store 3,0x70 + setarg 0xec97a6 + istore 3,contw + setarg 0xae31eb + istore 3,contw + setarg 0x6fe3c4 + istore 3,contw + setarg 0xa1ae1a + istore 3,contw + setarg 0x3a + istore 1,contw + + /* linkkey */ + setarg 0x07505b + store 3,0x80 + setarg 0xc9fe74 + istore 3,contw + setarg 0x057b76 + istore 3,contw + setarg 0x316404 + istore 3,contw + setarg 0xd884b3 + istore 3,contw + setarg 0x71 + istore 1,contw + + /* K */ + setarg 0x0c333f + store 3,0x90 + setarg 0x41de70 + istore 3,contw + setarg 0x9b05a2 + istore 3,contw + setarg 0xb954a2 + istore 3,contw + setarg 0xb37516 + istore 3,contw + setarg 0x36 + istore 1,contw + + /* kinit */ + setarg 0x5ff91a + store 3,0xa0 + setarg 0x39b5a4 + istore 3,contw + setarg 0x258f2d + istore 3,contw + setarg 0x5d4a85 + istore 3,contw + setarg 0x656ad3 + istore 3,contw + setarg 0xab + istore 1,contw + + arg 0,contr + arg mem_random_number,contw + call memcpy16 + setarg 0x3131 + store 2,mem_pin + istore 2,contw + jam 4,mem_pin_length + arg 0xb8,rega + call function_e22 + arg mem_input_store,contr + arg mem_kinit,contw + call memcpy16 + arg 0x10,rega + arg mem_kinit,regb + arg mem_random_number,contw + call xor16 + arg 0xb0,rega + call function_e21 + arg 0x60,regb + call compare16 +error_lka: + nbranch error_lka,zero + arg mem_input_store,contr + arg mem_link_key,contw + call memcpy16 + arg 0x20,rega + arg mem_kinit,regb + arg mem_random_number,contw + call xor16 + arg 0xb8,rega + call function_e21 + arg 0x70,regb + call compare16 +error_lkb: + nbranch error_lkb,zero + arg mem_input_store,rega + arg mem_link_key,regb + arg mem_link_key,contw + call xor16 + arg 0x30,contr + arg mem_random_number,contw + call memcpy16 + arg 0xb8,rega + call function_e1 + arg 0x50,regb + force 4,loopcnt + call compare_key +error_sresa: + nbranch error_sresa,zero + arg 0x40,contr + arg mem_random_number,contw + call memcpy16 + arg 0xb0,rega + call function_e1 + arg 0x58,regb + force 4,loopcnt + call compare_key +error_sresb: + nbranch error_sresb,zero + branch loop1 + + arg 0,contr + arg mem_random_number,contw + call memcpy16 + force 12,loopcnt + call memcpy + arg 0x1c,contr + arg mem_link_key,contw + call memcpy16 + arg 0x10,rega + call function_e3 + branch loop1 + +compare16: + force 16,loopcnt +compare_key: + arg mem_input_store,rega +compare_loop: + ifetch 1,rega + ifetcht 1,regb + isub temp,null + nrtn zero + increase 1,rega + increase 1,regb + loop compare_loop + force 0,pdata + rtn + +endif + +loop1: + branch loop1 + +/* ==================== LE security ================= */ + +generate_stk: + call function_s1 + arg mem_le_ltk,contw + branch store_aes_result + + /* contr = rand pointer */ +authenticate_rconfirm: + arg mem_le_srand,contw + branch authenticate_mconfirm,master + arg mem_le_mrand,contw +authenticate_mconfirm: + copy contr,rega + call memcpy16 + call function_c1 + arg mem_le_rconfirm,contr + branch compare_res + +generate_confirm: + arg mem_le_mrand,rega + branch generate_mrand,master + arg mem_le_srand,rega +generate_mrand: + copy rega,contw + call generate_random + branch function_c1 + +generate_sk: + arg mem_le_skdm,contr + call load_data128 + arg mem_le_ltk,contr + call load_key128 + force aes_big_endian | aes_load,aes_ctrl + force 0,aes_ctrl // change result to little endian + call wait_aes + arg mem_le_sk,contw + branch store_aes_result + + /* temp=packet counter, rega = length or block counter*/ +first_block_counter: + force 0x49,pdata + branch first_block +first_block_data: + force 1,pdata +first_block: + force regidx_data,regext_index /* B0 */ + lshift8 temp,regext + ior regext,regext + increase 1,regext_index + rshift8 temp,regext + rshift16 regext,regext + fetch 2,mem_le_ivm + lshift16 pdata,pdata + ior regext,regext /* octet3&octet4 of counter and low 16 bit of IV */ + increase 1,regext_index + ifetch 4,contr /* IV2-IV5 */ + iforce regext + increase 1,regext_index + ifetch 2,contr /* IV6-IV7 */ + byteswap rega,regext + lshift16 regext,regext + ior regext,regext + increase 1,regext_index + rtn + + + /* temp=packet counter, regc pointers to header, return mic in regb */ +generate_mic: + add regc,1,contr + ifetchr rega,1,contr + call first_block_counter + call do_aes_ecb + + force regidx_data,regext_index /* B1 */ + ifetch 1,regc + and_into 0x3,pdata + lshift16 pdata,regext + set1 8,regext + call clear_hidata + call do_aes_cbc + + copy rega,loopcnt + add regc,2,contr + call padding_data +generate_mic_loop: + call aes_load_data + call do_aes_cbc + deposit loopcnt + branch generate_mic_end,blank + branch generate_mic_loop +generate_mic_end: + force regidx_result,regext_index + copy regext,regb + storer regb,4,mem_le_mic + rtn + +aes_crypt_data: + increase 1,rega + call first_block_data + call aes_init + copy regc,contr + call load_data128 + call do_aes_cfb + call store_enc_data + increase 16,regc + increase -16,regb + branch aes_crypt_data,positive + rtn + +le_encrypt: + arg mem_le_txheader,regc + fetcht 5,mem_le_pcnt_tx + call generate_mic + force 0,rega + call first_block_data + call aes_init + force regidx_data,regext_index + copy regb,regext + call do_aes_cfb + arg mem_le_txpayload,regc + fetch 1,mem_le_txlen + add pdata,-1,regb + iadd regc,contw + force regidx_result,regext_index + istorer regext,4,contw + force 0,rega /* rega is block counter */ + call aes_crypt_data + fetch 1,mem_le_txlen + increase 4,pdata + store 1,mem_le_txlen + fetcht 5,mem_le_pcnt_tx + increase 1,temp + storet 5,mem_le_pcnt_tx + rtn + +le_decrypt: + fetcht 5,mem_le_pcnt_rx + force 0,rega + call first_block_data + call aes_init + fetch 1,mem_le_rxbuf+1 + arg mem_le_rxbuf+2,regc + add pdata,-1,regb + increase -4,pdata /* mic will be discarded */ + store 1,mem_le_rxbuf+1 + iadd regc,contr + force regidx_data,regext_index + ifetchr regext,4,contr + call do_aes_cfb + force regidx_result,regext_index + storer regext,4,mem_le_peer_mic + force 0,rega /* rega is block counter */ + call aes_crypt_data + arg mem_le_rxbuf,regc + call generate_mic + fetch 4,mem_le_peer_mic + isub regb,pdata /* MIC ok? */ + nrtn blank + fetch 4,mem_le_last_mic /* reduntdant packet? */ + isub regb,pdata + rtn blank + storet 4,mem_le_last_mic + fetch 5,mem_le_pcnt_rx + increase 1,pdata + store 5,mem_le_pcnt_rx + force 0,pdata + rtn + +wait_aes: + nbranch wait_aes,aes_ready + rtn + + +do_aes_ecb256: + force aes_load | aes_256,aes_ctrl + force aes_256,aes_ctrl + branch wait_aes + +do_aes_ecb192: + force aes_load | aes_192,aes_ctrl + force aes_192,aes_ctrl + branch wait_aes + +do_aes_ecb: + force aes_load,aes_ctrl + force 0,aes_ctrl + branch wait_aes + + +do_aes_cbc: + force aes_load | aes_cbc,aes_ctrl + force 0,aes_ctrl + branch wait_aes + +do_aes_cfb: + force aes_load | aes_cfb,aes_ctrl + force aes_cfb,aes_ctrl + branch wait_aes + +do_aes_ecb_be: + force aes_big_endian | aes_load,aes_ctrl + force aes_big_endian,aes_ctrl + branch wait_aes + +do_aes_cbc_be: + force aes_big_endian | aes_load | aes_cbc,aes_ctrl + force aes_big_endian,aes_ctrl + branch wait_aes + + +aes_init: + force aes_initialize,aes_ctrl + force 0,aes_ctrl + rtn + +function_s1: + force regidx_data,regext_index + fetch 4,mem_le_mrand + iforce regext + increase 1,regext_index + ifetch 4,contr + iforce regext + increase 1,regext_index + fetch 4,mem_le_srand + iforce regext + increase 1,regext_index + ifetch 4,contr + iforce regext + increase 1,regext_index + call aes_clear + increase -4,regext_index + fetch 4,mem_le_tk + copy pdata,regext + branch do_aes_ecb_be + + /* rega pointers to random number */ +function_c1: + copy rega,contr + call load_data128 // load r + force aes_big_endian | aes_initialize,aes_ctrl + force 0,aes_ctrl + fetch 1,mem_le_conn_peer_addr_type + fetcht 1,mem_le_adv_own_addr_type + nbranch function_c1_irat,master + fetch 1,mem_le_conn_own_addr_type + fetcht 1,mem_le_conn_peer_addr_type +function_c1_irat: + store 1,mem_le_iat + storet 1,mem_le_rat + arg mem_le_iat,contr + call load_data128 // load p1 + call aes_clear + increase -4,regext_index + fetch 4,mem_le_tk + copy pdata,regext + force aes_big_endian | aes_cbc | aes_load,aes_ctrl + force aes_big_endian,aes_ctrl + fetch 6,mem_le_lap + fetcht 6,mem_le_plap + branch function_c1_master,master + fetch 6,mem_le_plap + fetcht 6,mem_le_lap +function_c1_master: + force regidx_data,regext_index + copy temp,regext + increase 1,regext_index + rshift32 temp,regext + lshift16 pdata,pdata + ior regext,regext + increase 1,regext_index + rshift32 pdata,regext + increase 1,regext_index + force 0,regext /* p2 = ia || ra */ + branch do_aes_cbc_be + + +padding_data: + compare 0,loopcnt,3 + rtn true + deposit contr + iadd loopcnt,contw + force 0,pdata +padding_loop: + istore 1,contw + increase 1,loopcnt + compare 0,loopcnt,3 + rtn true + branch padding_loop + +aes_load_data: + force regidx_data,regext_index +load_data_loop: + deposit loopcnt + branch load_data_padding,blank + ifetch 4,contr + increase -4,loopcnt +load_data_padding: + iforce regext + increase 1,regext_index + compare regidx_key,regext_index,0xf + rtn true + branch load_data_loop + +load_key256: + force 8,loopcnt + branch load_key +load_key192: + force 6,loopcnt + branch load_key +load_key128: + force 4,loopcnt +load_key: + force regidx_key,regext_index + branch load_regext_loop +load_data128: + force regidx_data,regext_index + force 4,loopcnt +load_regext_loop: +// ifetchr regext,4,contr + ifetch 4,contr + icopy regext + increase 1,regext_index + loop load_regext_loop + rtn + + +load_sk: + arg mem_le_sk,contr + branch load_key128 + +clear_hidata: + force 4,loopcnt + branch clear_data_rest + +aes_clear_data: + force regidx_data,regext_index +aes_clear: + force 4,loopcnt +clear_loop: + force 0,regext +clear_data_rest: + increase 1,regext_index + loop clear_loop + rtn + +store_aes_result: + force regidx_result,regext_index + force 4,loopcnt +send_aes_result_loop: + deposit regext + istore 4,contw + increase 1,regext_index + loop send_aes_result_loop + rtn + +store_enc_data: + force regidx_result,regext_index + copy regc,contw + add regb,1,loopcnt + sub loopcnt,15,null + branch store_enc_loop,positive + force 16,loopcnt +store_enc_loop: + deposit regext + sub loopcnt,3,null + branch store_enc_byte,positive + istore 4,contw + increase -4,loopcnt + rtn zero + increase 1,regext_index + branch store_enc_loop +store_enc_byte: + istore 1,contw + rshift8 pdata,pdata + loop store_enc_byte + rtn + + /* contr pointers to value to be compared */ +compare_res: + force regidx_result,regext_index + force 4,loopcnt +compare_res_loop: + ifetch 4,contr + isub regext,null + nrtn zero + increase 1,regext_index + loop compare_res_loop + force 0,null + rtn + +enable_authrom: + fetch 1,core_clkoff + set0 CLOCK_OFF_AUTH_ROM,pdata + store 1,core_clkoff + rtn + +disable_authrom: + fetch 1,core_clkoff + set1 CLOCK_OFF_AUTH_ROM,pdata + store 1,core_clkoff + rtn + +init_memp: + arg mem_p,contw + setsect 0,0x3ffff + setsect 1,0x3ffff + setsect 2,0x3ffff + setsect 3,0x3fbff + istore 9,contw + setsect 0,0x3ffff + setsect 1,0x3ffff + setsect 2,0x3ffff + setsect 3,0x3ffff + istore 9,contw + setsect 0,0x3ffff + setsect 1,0x3ffff + setsect 2,0x3cfff + setsect 3,0x3ffff + istore 9,contw + setsect 0,0x3ffff + setsect 1,0x3ffff + setsect 2,0x3ffef + setsect 3,0x3ffff + istore 9,contw + setsect 0,0x3ffff + setsect 1,0x3ffff + setsect 2,0x3ffff + setsect 3,0x3ffff + istore 9,contw + setsect 0,0x3ffff + setsect 1,0x26c7f + setsect 2,0x146b + setsect 3,0x37bb3 + istore 9,contw + setsect 0,0x1feb8 + setsect 1,0x10c12 + setsect 2,0x2b722 + setsect 3,0x29fa6 + istore 9,contw + setsect 0,0xe70f + setsect 1,0x16720 + setsect 2,0x519e + setsect 3,0x19084 + istore 9,contw + setsect 0,0x31012 + setsect 1,0x360bf + setsect 2,0x3f0af + setsect 3,0x3d3 + istore 9,contw + setsect 0,0x3a188 + setsect 1,0x3ad0 + setsect 2,0x3cbf2 + setsect 3,0x243d9 + istore 9,contw + setsect 0,0x2b030 + setsect 1,0x36a03 + setsect 2,0x11188 + setsect 3,0x1e520 + istore 9,contw + setsect 0,0x3a11e + setsect 1,0xfe5d + setsect 2,0xdd57 + setsect 3,0x1ac93 + istore 9,contw + setsect 0,0x11ed + setsect 1,0x218c4 + setsect 2,0x8da7 + setsect 3,0x257ff + istore 9,contw + setsect 0,0x3192b + setsect 1,0x34641 + setsect 2,0x1be0c + setsect 3,0x366ad + istore 9,contw + setsect 0,0x1f83 + setsect 1,0x15a23 + setsect 2,0x3f9b0 + setsect 3,0x3949 + istore 9,contw + setsect 0,0x13a51 + setsect 1,0x153fd + setsect 2,0x3372a + setsect 3,0xf1bb + istore 9,contw + setsect 0,0x3ae85 + setsect 1,0x1eed9 + setsect 2,0x9e66 + setsect 3,0x1a8 + istore 8,contw + rtn + +ifdef SECURE_CONNECTION + + +init_memp_256: + arg mem_p_256,contw + setsect 0,0x3ffff + setsect 1,0x3ffff + setsect 2,0x3ffff + setsect 3,0x3ffff + istore 9,contw + setsect 0,0x3ffff + setsect 1,0x3f + setsect 2,0x0 + setsect 3,0x0 + istore 9,contw + setsect 0,0x0 + setsect 1,0x0 + setsect 2,0x1000 + setsect 3,0x0 + istore 9,contw + setsect 0,0x3ff00 + setsect 1,0x3ffff + setsect 2,0x3ffcf + setsect 3,0x3ffff + istore 9,contw + setsect 0,0x3ffff + setsect 1,0x3ffff + setsect 2,0x3ffff + setsect 3,0x3ff + istore 9,contw + setsect 0,0x0 + setsect 1,0x0 + setsect 2,0x0 + setsect 3,0x0 + istore 9,contw + setsect 0,0x10000 + setsect 1,0x0 + setsect 2,0x3f000 + setsect 3,0x3ffff + istore 9,contw + setsect 0,0x296ff + setsect 1,0x22630 + setsect 2,0x3945d + setsect 3,0x3d284 + istore 9,contw + setsect 0,0x333a0 + setsect 1,0x4b7a + setsect 2,0x37d8 + setsect 3,0x3c9dc + istore 9,contw + setsect 0,0x3a440 + setsect 1,0x1b958 + setsect 2,0x38bce + setsect 3,0x1091f + istore 9,contw + setsect 0,0x2e12c + setsect 1,0x1f47c + setsect 2,0x356b1 + setsect 3,0x2fd47 + istore 9,contw + setsect 0,0x6837 + setsect 1,0x2ed90 + setsect 2,0x1ecec + setsect 3,0x1acc5 + istore 9,contw + setsect 0,0x23357 + setsect 1,0x18af3 + setsect 2,0xf9e1 + setsect 3,0x129f0 + istore 9,contw + setsect 0,0x2e7eb + setsect 1,0x3e6e3 + setsect 2,0x3e1a7 + setsect 3,0x10b8b + istore 9,contw + setsect 0,0x24fe3 + setsect 1,0x20ef + setsect 2,0x1b5a6 + setsect 3,0xdc2f + istore 9,contw + setsect 0,0x13860 + setsect 1,0x2bd69 + setsect 2,0x391a + setsect 3,0x1b222 + istore 9,contw + rtn +endif + Index: tag/Soft/Librarier/bt_rom/program/sim.prog =================================================================== --- /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/sim.prog (nonexistent) +++ /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/sim.prog (working copy) @@ -0,0 +1,711 @@ +//define EFUSE +ifdef EFUSE + jam 0x3f,core_gpio_conf+26 + fetch 1,core_lpm_latch + bbit0 5,efuse_noload + call loadcode_spi+2 +efuse_noload: + nop 1 +else +simstart: + branch patch_start + nop 1 +// branch soft_reset+1 +patch_start: +// call sim_qspi + force 8,radio_ctrl + force 0,radio_ctrl + jam 0x1,core_clkoff + jam 0xe0,0x8907 // set if_phase=7 for simulation environment + jam 0xe0,0x890a + jam 0x25,0x8912 + jam 0xff,rfen_ck +// jam 5,core_clksel + jam 61,core_gpio_conf + 24 + jam 60,core_gpio_conf + 23 +// call sim_dac +// call sim_cvsd +// branch sim_lpm_doze +// branch sim_lpm_hibernate + branch sim_lpm_sleep + fetch 1,core_revid +// bbit1 7,sim_main +// call sim_adcd + call enable_xip + branch sim_assert +// call sim_aes +// call sim_i2s +// call sim_uart +// call sim_pwm +// call sim_iic +// call sim_eep +// call sim_spi +// branch test_tx +// branch sim_le +// branch sim_250k +// branch sim_clk +// branch sim_c1 +// branch loop +// branch sim_main +sim_lpm_hibernate: + setarg 0 + set1 31,pdata + store 8,mem_gpio_wakeup_low + branch lpm_hibernate +sim_lpm_doze: + arg 0x39,temp + branch lpm_doze +sim_lpm_sleep: + jam 0x6c,core_clkoff+1 + arg 0x50,loopcnt + setarg 0x8020 + ncall save_ucode,wake + arg 33,temp + branch lpm_sleep + +sim_lpm_cal: + jam 0x40,core_bist_ctrl + jam ccnt_start,core_dma_start +sim_lpm_wait: + call lpo_calibration + fetch 3,mem_clks_per_lpo + branch sim_lpm_wait,blank + lshift8 pdata,pdata + store 3,mem_clks_per_lpo + rtn + +sim_assert: + branch sim_assert + +ifdef null + +sim_scs: + nop 300 + setarg 0x101c + call read_scs + fetch 4,core_scs_rdata + store 4,core_pwm0_pcnt + nop 300 + jam 3,core_scs_wdata + setarg 0xa05f00 + store 3,core_scs_wdata + 1 + setarg 0xedf2 + call write_scs + setarg 0xf + store 4,core_scs_wdata + setarg 0xedf4 + call write_scs + setarg 0xedf8 + call read_scs + fetch 4,core_scs_rdata + store 4,core_pwm0_pcnt + + branch sim_assert + setarg 3 + store 4,core_scs_wdata + setarg 0x2000 + call write_scs + setarg 0x1369 + store 3,core_scs_wdata + jam 0xc0,core_scs_wdata+3 + setarg 0x2008 + call write_scs + rtn + nop 300 + setarg 1 + store 4,core_scs_wdata + setarg 0x2020 + call write_scs + setarg 0x2020 + call read_scs + fetch 4,core_scs_rdata + setarg 0x2020 + call read_scs + fetch 4,core_scs_rdata + setarg 0x2020 + call read_scs + fetch 4,core_scs_rdata + nop 3 + setarg 0xd00 + store 2,core_scs_addr + call wait_scs + fetch 4,core_scs_rdata + store 4,core_pwm0_pcnt + setarg 0xd0c + store 2,core_scs_addr + call wait_scs + nop 200 + jam 5,core_scs_wdata + store 2,core_scs_addr + setarg 0xf + store 4,core_scs_wdata + setarg 0x8df4 + store 2,core_scs_addr + setarg 0xdf8 + store 2,core_scs_addr + call wait_scs + fetch 4,core_scs_rdata + store 4,core_pwm0_pcnt + setarg 0xa05f00 + store 3,core_scs_wdata + 1 + jam 1,core_scs_wdata + setarg 0x8df0 + store 2,core_scs_addr + rtn + +sim_main: + call init_param + setarg 0 + store 2,core_clkoff + setarg 0xff00 + store 2,core_lpm_reg+2 + jam lpmreg_sel_ctrl2,core_lpm_wr + fetch 1,core_revid + bbit1 7,sim_slave + jam dvc_op_hci,mem_device_option + fetch 6,mem_lap + store 6,mem_hci_plap + setarg 0xbdbdbd + store 3,mem_lap + istore 3,contw + jam hci_cmd_create_conn,mem_hci_cmd + force 0x10,pdata + add pdata,-2,clkn_bt + store 4,mem_page_clk + rshift clkn_bt,pdata + store 4,mem_last_clkn + jam 0,mem_scan_mode +sim_loop: + call idle_dispatch + fetch 1,mem_context + bbit0 state_inconn,sim_skip + set1 mark_tx_l2cap,mark + fetch 1,mem_context + coffset_state_map + set1 smap_edr,pdata + store 1,mem_context + coffset_state_map + fetch 1,mem_context + coffset_op + set1 op_txl2cap,pdata + store 1,mem_context + coffset_op + jam 0,mem_context + coffset_lmp_to_send + jam 0,mem_lmo_opcode2 + setarg 700 + store 2,mem_tx_len + setarg mem_tmp_buffer + store 2,mem_txptr + jam 6,mem_tx_lch + jam 1,mem_hci_conn_handle +sim_skip: + call connection_dispatch + branch sim_loop + +sim_slave: + jam 2,mem_scan_mode + call page_scan_dispatch + branch sim_loop + + +sim_iic: + setarg 3 + store 2,core_iicd_txlen + setarg 0x1f051e + store 3,mem_iicd_addr + setarg mem_iicd_addr + store 2,core_iicd_txaddr + setarg 1 + store 2,core_iicd_rxlen + jam 3,core_iicd_ctrl + jam iicd_start,core_dma_start + rtn + +s_loop: + branch s_loop + +sim_usb: + call usb_init +sim_usb_loop: + call usb_isr + branch sim_usb_loop + + +sim_uart: + jam 0,core_clkoff+1 + setarg 0x9a9998 + store 3,mem_uart_txpin + setarg 0x9d9c9b + istore 3,contw + setarg 0x9f9e + istore 2,contw + call gpio_config_uart + call gpio_config_uartb + setarg mem_h5rx_buf + store 2,core_uart_tx_saddr + store 2,core_uart_tx_wptr + increase 0x80,pdata + store 2,core_uart_tx_eaddr + store 2,core_uart_rx_saddr + store 2,core_uart_rx_rptr + increase 0x80,pdata + store 2,core_uart_rx_eaddr + + setarg mem_h5tx_buf + store 2,core_uartb_tx_saddr + store 2,core_uartb_tx_wptr + increase 0x80,pdata + store 2,core_uartb_tx_eaddr + store 2,core_uartb_rx_saddr + store 2,core_uartb_rx_rptr + increase 0x80,pdata + store 2,core_uartb_rx_eaddr + + jam 0x81,core_uart_ctrl + jam 0x81,core_uartb_ctrl + setarg 0x8030 + store 2,core_uart_baud + setarg 0x30 + store 2,core_uartb_baud + + fetch 1,1 + rtnbit1 7 + setarg 0x1357d9a + store 4,mem_h5rx_buf | 0x10000 + setarg 0x55aa69 + istore 3,contw + setarg 0xfedcb3 + istore 3,contw + deposit contw + store 2,core_uart_tx_wptr + rtn + +sim_qspi: + jam 0x16,core_qspi_ctrl + jam 0x64,core_qspi_delay + setarg 5 + store 2,core_qspi_txlen + setarg 0x30000 + store 4,mem_addr_hi + jam 0xeb,mem_qspi_tbuf + arg 5,temp + arg mem_h5rx_buf,rega + branch qspi_read_flash_raw + + jam 0x04,core_qspi_ctrl + jam 0x00,core_qspi_delay + setarg 3 + store 2,core_qspi_txlen + setarg 0x200001 + store 3,mem_qspi_tbuf + arg 0,temp + arg mem_h5rx_buf,rega + branch qspi_read_flash_raw + setarg 1 + store 2,core_qspi_txlen + jam 0x05,mem_qspi_tbuf + arg 1,temp + arg mem_h5rx_buf,rega + branch qspi_read_flash_raw + +sim_pwm: + setarg gpcfg_pwm_out0 + call gpio_config_param + setarg 0x200 | gpcfg_pwm_out1 + call gpio_config_param + jam 0,core_clkoff+1 + setarg 123 + store 2,core_pwm0_pcnt + setarg 133 + store 2,core_pwm0_ncnt + jam 0x25,core_pwm0_ctrl + setarg 100 + store 2,core_pwm1_pcnt + setarg 10 + store 2,core_pwm1_ncnt + jam 0x2d,core_pwm1_ctrl + nop 10000 + setarg 55 + store 2,core_pwm0_pcnt + setarg 33 + store 2,core_pwm0_ncnt + rtn + +sim_i2s: + setarg 0x2500 | gpcfg_i2s_dout + call gpio_config_param + setarg 0x2400 | gpcfg_i2s_din + call gpio_config_param + setarg 0x2700 | gpcfg_i2s_clkin + call gpio_config_param + setarg 0x2600 | gpcfg_i2s_lrckin + call gpio_config_param + jam 0,core_clkoff+1 + setarg 0x300 + store 2,core_i2s_rx_saddr + setarg 0x200 + store 2,core_i2s_tx_saddr + setarg 10 + store 2,core_i2s_len + setarg 0x12356a7 + store 4,0x200 + setarg 0xabcdef + istore 3,contw + setarg 0x3fedcba + store 4,0x10200 + setarg 0x987651 + istore 3,contw + jam 9,core_i2s_clkdiv + jam 0x83,core_i2s_ctrl + call sim_i2s_wait + jam 0x91,core_i2s_ctrl + call sim_i2s_wait + jam 0xa3,core_i2s_ctrl + call sim_i2s_wait + jam 0xb3,core_i2s_ctrl + call sim_i2s_wait + setarg 0x2700 | gpcfg_i2s_clkout + call gpio_config_param + setarg 0x2600 | gpcfg_i2s_lrckout + call gpio_config_param + jam 0xaf,core_i2s_ctrl + call sim_i2s_wait + jam 0xbf,core_i2s_ctrl + call sim_i2s_wait + jam 0x87,core_i2s_ctrl + call sim_i2s_wait + jam 0x95,core_i2s_ctrl + call sim_i2s_wait + rtn + +sim_i2s_wait: + fetch 1,core_i2s_rdptr + bne 9,sim_i2s_wait + jam 4,core_i2s_ctrl + nop 30 + rtn + +sim_sine: + setarg 00 + store 2,0x10200 + setarg 5690 + istore 2,contw + setarg 11209 + istore 2,contw + setarg 16386 + istore 2,contw + setarg 21065 + istore 2,contw + setarg 25104 + istore 2,contw + setarg 28380 + istore 2,contw + setarg 30794 + istore 2,contw + setarg 32271 + istore 2,contw + setarg 32767 + istore 2,contw + add contw,-2,contr + arg 10,loopcnt +sine_loop1: + ifetch 2,contr + istore 2,contw + increase -4,contr + loop sine_loop1 + arg 0x10200,contr + arg 20,loopcnt +sine_loop2: + ifetcht 2,contr + sub temp,0,temp + istoret 2,contw + loop sine_loop2 + arg 0x10200,contr + arg 0x10100,contw + arg 40,loopcnt +sine_loop3: + ifetch 2,contr + istore 4,contw + loop sine_loop3 + rtn + + +sim_dac: + jam 0,core_clkoff + call sim_sine + setarg 0x100 + store 2,core_dac_saddr + jam 50,core_dac_len + jam 0x41,core_dac_ctrl + rtn + +//ifdef NULL +sim_250k: + call init_250k + fetch 1,1 + bbit1 7,sim_250k_rx + call tx_radio_freq + call start_transmitter /* get ready for that id packet */ + nop 600 + enable encode_fec0 + set1 TXGFSK,radio_ctrl + force 0,pdata + inject mod,9 + setarg 0xaa + inject mod,8 + preload access + inject mod,32 + setarg 0x1da861 + inject mod,24 + setarg 0x94445b + inject mod,24 + setarg 0x1275f + inject mod,24 + branch loop +sim_250k_rx: + call rx_radio_freq + call start_receiver /* wait for that id packet from master */ + enable decode_fec0 + correlate null,never + parse demod,bucket,72 + branch loop + + + +sim_eep: + call iicd_init_12m + setarg 3 + store 2,core_iicd_txlen + setarg 0x1f051e + store 3,mem_iicd_addr + setarg mem_iicd_addr + store 2,core_iicd_txaddr + setarg 1 + store 2,core_iicd_rxlen + jam 3,core_iicd_ctrl + jam iicd_start,core_dma_start + call wait_iicd_done + nop 200 + setarg 0x18f7a3b + store 4,mem_iicd_addr + arg mem_iicd_addr,rega + arg 4,temp + setarg 0x1235 + call iicd_write_eep + nop 300 + arg mem_ucode_keybuf,rega + arg 1,temp + setarg 0x3512 + store 2,mem_addr_mi + call iicd_read_eep + arg 1,temp + setarg 0x3512 + store 2,mem_addr_mi + call iicd_read_eep + nop 200 + setarg 0xa1 + arg 3,temp + arg mem_ucode_keybuf,rega + branch iicd_read_data + +sim_clk: + add lpo_time,12,alarm + snooze +clock_loop: + nop 100 + jam 1,core_config + setflag user,0,pdata + random pdata + and_into 0x1f,pdata + store 1,core_clksel + nop 70 + jam 2,core_kick + nop 200 + branch clock_loop + jam 2,core_clksel + setarg 1500 + call sleep + jam 0x42,core_clksel + add lpo_time,200,alarm + snooze + branch 0x4000 + + + // result should be 0x1e1e3fef878988ead2a74dc5bef13b86 +sim_c1: + setarg 0xb4b5b6 + store 3,mem_le_lap + setarg 0xb1b2b3 + istore 3,contw + setarg 0xa4a5a6 + store 3,mem_le_plap + setarg 0xa1a2a3 + istore 3,contw + setarg 0x101 + store 4,mem_le_preq + setarg 0x70710 + istore 3,contw + setarg 0x302 + store 4,mem_le_pres + setarg 0x50008 + istore 3,contw + jam 1,mem_le_conn_peer_addr_type + arg regidx_key,regext_index + call aes_clear + + setarg 0x702EE0 + store 3,mem_le_rconfirm + setarg 0x274EC6 + istore 3,contw + setarg 0x0E6388 + istore 3,contw + setarg 0x56AD6F + istore 3,contw + setarg 0x83D521 + istore 3,contw + setarg 0x57 + istore 1,contw + arg mem_le_rconfirm,rega + call function_c1 + branch sim_assert + + // result should be 0x9a1fe1f0e8b0f49b5b4216ae796da062 +sim_s1: + setarg 0x667788 + store 3,mem_le_srand + setarg 0x334455 + istore 3,contw + setarg 0x1122 + istore 2,contw + setarg 0xeeff00 + store 3,mem_le_mrand + setarg 0xbbccdd + istore 3,contw + setarg 0x99aa + istore 2,contw + arg regidx_key,regext_index + call aes_clear + call function_s1 + branch sim_assert + + + // decrypt result is 0e1b1700636465666768696a6b6c6d6e6f707131323334353637383930 +sim_mic: + setsect 0,0x10213 + setsect 1,0x3f83c + setsect 2,0x3dced + setsect 3,0x1e6b2 + store 9,mem_le_skdm + setsect 0,0x25768 + setsect 1,0x10d51 + setsect 2,0x2132 + setsect 3,0x0 + istore 7,contw + setsect 0,0x301bf + setsect 1,0x3a77e + setsect 2,0x3cf34 + setsect 3,0x360da + store 9,mem_le_ltk + setsect 0,0x1f574 + setsect 1,0x2104e + setsect 2,0xc683 + setsect 3,0x1 + istore 7,contw + call generate_sk + call load_sk + setsect 0,0xab24 + setsect 1,0x3aeb7 + setsect 2,0x2fbab + setsect 3,0x37a + store 8,mem_le_ivm + setarg 1 + set1 39,pdata + store 5,mem_le_pcnt_tx + store 5,mem_le_pcnt_rx + setsect 0,0x21f0e + setsect 1,0x19c1e + setsect 2,0x1564d + setsect 3,0x1b488 + store 9,mem_le_rxbuf + setsect 0,0x36bf2 + setsect 1,0x2a0c5 + setsect 2,0x4069 + setsect 3,0x16414 + istore 9,contw + setsect 0,0x2d66b + setsect 1,0x253d5 + setsect 2,0x1b6b7 + setsect 3,0x39a71 + istore 9,contw + setsect 0,0x332ff + setsect 1,0x356bd + setsect 2,0x336 + istore 6,contw + call le_decrypt + fetch 9,mem_le_rxbuf + ifetch 9,contr + ifetch 9,contr + ifetch 9,contr + branch sim_assert + +//endif + +sim_adcd: + setarg mem_x + store 2,core_adcd_saddr + setarg mem_x+15 + store 2,core_adcd_eaddr + setarg 230 + store 2,core_adcd_delay + jam 0x78,rfen_adc + jam 0x05,core_adcd_dcoff + jam 0x80,core_adcd_ctrl + rtn + + // result is f3eed1bdb5d2a03c064b5a7e3db181f8 +sim_aes: + arg mem_x,contw + setsect 0,0x33d60 + setsect 1,0x1443a + setsect 2,0x31ca1 + setsect 3,0xaef9 + istore 9,contw + setsect 0,0xae73 + setsect 1,0x3617c + setsect 2,0x1777 + setsect 3,0xd47e + istore 9,contw + setsect 0,0x3072c + setsect 1,0x2184e + setsect 2,0x2dd70 + setsect 3,0x4260 + istore 9,contw + setsect 0,0x9a3 + setsect 1,0x137c5 + setsect 2,0x16bf + setsect 3,0x38afb + istore 9,contw + setsect 0,0x3402e + setsect 1,0x265a7 + setsect 2,0x3e3de + setsect 3,0x1cc45 + istore 9,contw + setarg 0x2a1793 + istore 3,contw + arg mem_x,contr + call load_key256 + call load_data128 + call do_aes_ecb256 + setsect 0,0x1eef3 + setsect 1,0x16f74 + setsect 2,0x20d2b + setsect 3,0x18f2 + store 9,mem_x + setsect 0,0x25a4b + setsect 1,0x4f5f + setsect 2,0x3881b + setsect 3,0x3 + istore 7,contw + arg mem_x,contr + call compare_res + rtn zero + branch sim_assert +endif +endif + Index: tag/Soft/Librarier/bt_rom/program/simple_pairing.prog =================================================================== --- /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/simple_pairing.prog (nonexistent) +++ /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/simple_pairing.prog (working copy) @@ -0,0 +1,2351 @@ + +publickey_init: + fetch 1,mem_ssp_enable + nbranch sp_initialize,blank + branch sp_initialize_256 + +publickey_calc: + fetch 1,mem_ssp_enable + rtn blank + fetch 1,mem_sp_local_key_invalid + rtnne SP_KEY_VALID + fetch 1,mem_le_secure_connect_enable + rtn blank + fetch 1,mem_le_sc_local_key_invalid + rtneq SP_KEY_VALID_256 + fetch 2,mem_ui_state_map + bbit1 UI_STATE_BT_CONNECTED,stop_publickey_calc_256 + fetch 1,mem_le_sc_calc + beq SP_CALC_STANDBY,sp_initialize_256 + rtn +stop_publickey_calc_256: + jam SP_CALC_STANDBY,mem_le_sc_calc + rtn + +ifdef SIMPLE_PAIRING + +sp_initialize: + fetch 1,mem_ssp_enable + branch ssp_disable, blank + call ssp_enable + call sp_clear_flags + branch sp_pubkey_calc + +sp_clear_flags: + setarg 0 + store 8,mem_sp_state_start + store 4,mem_sp_flag_start + store 7,mem_sp_iocap_remote + rtn + +sp_generate_local_key: + jam SP_FLAG_COMMIT,mem_sp_flag + branch sp_generate_local_key0 +sp_master_generate_local_key: + fetch 1,mem_sp_local_key_invalid + beq SP_KEY_VALID,sp_dhkey_calc + branch assert +sp_generate_local_key0: + fetch 1,mem_sp_local_key_invalid + beq SP_KEY_VALID,sp_start_send_pubkey + branch sp_pubkey_calc + +sp_start_send_pubkey: + call sp_dhkey_calc + fetch 1,mem_master_sp_state + nrtn blank + jam SP_STAT_KEY_SEND,mem_sp_state + rtn + + +sp_calc_check_publickey_256: + call sp_calc_b256 + arg mem_le_pubkey_remote_y_256,regA + arg mem_t7_256,contw + call bn_sqrmod_256 + arg mem_le_pubkey_remote_x_256,regA + arg mem_t2_256,contw + call bn_sqrmod_256 + arg mem_t2_256,regA + arg mem_le_pubkey_remote_x_256,regB + arg mem_t2_256,contw + call bn_mulmod_256 + arg mem_a_256,regA + arg mem_le_pubkey_remote_x_256,regB + arg mem_t3_256,contw + call bn_mulmod_256 + arg mem_t3_256,regA + arg mem_t2_256,regB + arg mem_t2_256,contw + call bn_addmod_256 + arg mem_t0_256,regA + arg mem_t2_256,regB + arg mem_t0_256,contw + call bn_addmod_256 + arg 32,loopcnt + arg mem_t7_256,regA + arg mem_t0_256,regB + branch string_compare + +sp_calc_b256: + arg mem_gy_256,regA + arg mem_t0_256,contw + call bn_sqrmod_256 + arg mem_gx_256,regA + arg mem_t2_256,contw + call bn_sqrmod_256 + arg mem_t2_256,regA + arg mem_gx_256,regB + arg mem_t2_256,contw + call bn_mulmod_256 + arg mem_a_256,regA + arg mem_gx_256,regB + arg mem_t3_256,contw + call bn_mulmod_256 + arg mem_t3_256,regA + arg mem_t2_256,regB + arg mem_t2_256,contw + call bn_addmod_256 + arg mem_t0_256,regA + arg mem_t2_256,regB + arg mem_t0_256,contw + branch bn_submod_256 + +sp_calc_check_publickey: + call sp_calc_b + arg mem_sp_pubkey_remote_y,regA + arg mem_t7_256,contw + call bn_sqrmod + arg mem_sp_pubkey_remote_x,regA + arg mem_t2_256,contw + call bn_sqrmod + arg mem_t2_256,regA + arg mem_sp_pubkey_remote_x,regB + arg mem_t2_256,contw + call bn_mulmod + arg mem_a,regA + arg mem_sp_pubkey_remote_x,regB + arg mem_t3_256,contw + call bn_mulmod + arg mem_t3_256,regA + arg mem_t2_256,regB + arg mem_t2_256,contw + call bn_addmod + arg mem_t0_256,regA + arg mem_t2_256,regB + arg mem_t0_256,contw + call bn_addmod + arg 24,loopcnt + arg mem_t7_256,regA + arg mem_t0_256,regB + branch string_compare + +sp_calc_b: + arg mem_gy,regA + arg mem_t0_256,contw + call bn_sqrmod + arg mem_gx,regA + arg mem_t2_256,contw + call bn_sqrmod + arg mem_t2_256,regA + arg mem_gx,regB + arg mem_t2_256,contw + call bn_mulmod + arg mem_a,regA + arg mem_gx,regB + arg mem_t3_256,contw + call bn_mulmod + arg mem_t3_256,regA + arg mem_t2_256,regB + arg mem_t2_256,contw + call bn_addmod + arg mem_t0_256,regA + arg mem_t2_256,regB + arg mem_t0_256,contw + branch bn_submod + +sp_calculate_commitment: + fetch 1,mem_sp_calc + bne SP_CALC_STANDBY,sp_calculate_commitment_wait_dhkey_calc + call sp_local_random_key_generator + arg mem_sp_prarm_stack,contw + setarg mem_sp_random_local_end + istore 2,contw + setarg mem_sp_pubkey_local_x_end + istore 2,contw + setarg mem_sp_pubkey_remote_x_end + istore 2,contw + branch sp_calculate_commitment0 +master_sp_calculate_commitment: + arg mem_sp_prarm_stack,contw + setarg mem_sp_random_remote_end + istore 2,contw + setarg mem_sp_pubkey_remote_x_end + istore 2,contw + setarg mem_sp_pubkey_local_x_end + istore 2,contw +sp_calculate_commitment0: + call function_f1 + fetch 1,mem_master_sp_state + beq SP_STAT_COMMIT_CALC,master_sp_calculate_commitment0 + jam SP_FLAG_COMMIT,mem_sp_flag + jam SP_STAT_COMMIT_SEND,mem_sp_state + rtn +master_sp_calculate_commitment0: + jam SP_STAT_COMMITMENT_COMPARE,mem_master_sp_state + call sp_master_generate_local_key + branch master_set_mem_master_sp_flag + +sp_local_random_key_generator: + arg mem_sp_random_local,contw + force 8,queue + branch random_generator + +sp_calculate_commitment_wait_dhkey_calc: + jam SP_FLAG_COMMIT,mem_sp_flag + rtn + +sp_confirm_check: + /* calculate Ea here */ + arg mem_addr_value,contw + fetch 6,mem_lap + istore 6,contw + fetch 6,mem_plap + istore 6,contw + fetch 3,mem_sp_iocap_remote + istore 3,contw + + call function_f3a + + arg mem_sp_calc_result_high,regA + arg mem_sp_check_result,regB + force 4,queue + call compare4 + nbranch sp_confirm_check_failed,true + call sp_calc_check_publickey + nbranch sp_confirm_check_failed,zero + call sp_confirm_check_success + jam LMP_DHKey_Check,mem_lmi_opcode2 + branch tid_set_reply + +sp_confirm_check_success: + fetch 1,mem_master_sp_state + beq SP_STAT_CONFIRM_CHECK,sp_confirm_check_success_master + jam SP_STAT_CONFIRM_CALC,mem_sp_state + jam SP_FLAG_COMMIT,mem_sp_flag + jam LMP_ACCEPTED,mem_lmo_opcode2 + rtn +sp_confirm_check_success_master: + jam LMP_ACCEPTED,mem_lmo_opcode2 + jam SP_STATE_END,mem_master_sp_state + branch master_set_mem_master_sp_flag + +sp_confirm_check_failed: + fetch 1,mem_master_sp_state + beq SP_STAT_CONFIRM_CHECK,sp_confirm_check_failed_master + jam SP_STAT_NULL,mem_sp_state + jam LMP_NOT_ACCEPTED,mem_lmo_opcode2 + jam AUTHENTICATION_FAILURE_ERROR,mem_lmo_reason2 + rtn +sp_confirm_check_failed_master: + jam LMP_NOT_ACCEPTED,mem_lmo_opcode2 + jam SP_STAT_NULL,mem_master_sp_state + rtn + +sp_confirm_calc: + fetch 1,mem_sp_dh_ready + beq SP_FLAG_COMMIT, sp_confirm_calc_ready + jam SP_STAT_CONFIRM_CALC,mem_master_sp_state + branch master_set_mem_master_sp_flag +sp_confirm_calc_ready: + arg mem_addr_value,contw + fetch 6,mem_plap + istore 6,contw + fetch 6,mem_lap + istore 6,contw + fetch 3,mem_sp_iocap_local + istore 3,contw + + call function_f3b + fetch 1,mem_master_sp_state + beq SP_STAT_CONFIRM_CALC,sp_confirm_calc_master + jam SP_STAT_CONFIRM_SEND,mem_sp_state + jam SP_FLAG_COMMIT,mem_sp_flag + rtn +sp_confirm_calc_master: + jam SP_STAT_CONFIRM_SEND,mem_master_sp_state + jam SP_FLAG_COMMIT,mem_master_sp_flag + rtn + +sp_master_key_prarm_push: + arg mem_sp_prarm_stack,contw + fetch 6,mem_plap + istore 6,contw + fetch 6,mem_lap + istore 6,contw + setarg mem_sp_random_local_end + istore 2,contw + setarg mem_sp_random_remote_end + istore 2,contw + branch sp_link_key_calc +sp_link_key_prarm_push: + jam SP_STAT_DONE,mem_sp_state + arg mem_sp_prarm_stack,contw + fetch 6,mem_lap + istore 6,contw + fetch 6,mem_plap + istore 6,contw + setarg mem_sp_random_remote_end + istore 2,contw + setarg mem_sp_random_local_end + istore 2,contw +sp_link_key_calc: + /*calculate Link key here */ + arg mem_addr_value,contw + fetch 6,mem_sp_prarm_stack + istore 6,contw + fetch 6,mem_sp_prarm_stack+6 + istore 6,contw + + call function_f2 + + /*handle linkkey */ + jam 1,mem_link_key_exists + arg mem_link_key,contw + arg mem_sp_calc_result_high,contr + call memcpy16 + branch generate_linkkey_continue + + +sp_pubkey_calc: + bpatchx patch34_3,mem_patch34 + fetch 1,mem_sp_local_key_invalid + rtnne SP_KEY_INVALID + fetch 1,mem_sp_calc + rtnne SP_CALC_STANDBY + arg mem_sp_private_key,contw + force 11,queue + call random_generator + random pdata + rshift pdata,pdata + istore 2,contw +/* we don't need fixed private key,generate random key instead */ + arg mem_k,contw + arg mem_sp_private_key,contr + call memcpy24 //mem_sp_private_key=>mem_k 24BYTES + + arg mem_ax,contw + arg mem_gx,contr + call memcpy48 //mem_gx=>mem_ax 48bytes + + arg mem_az,contw + call bn_zero + jam 1,mem_az //0=>mem_az 24bytes + + call eckp_calc_init + jam SP_CALC_PUBKEY,mem_sp_calc + rtn + +sp_pubkey_generated: + arg mem_sp_pubkey_local,contw + arg mem_bx,contr + call memcpy48 + jam SP_KEY_VALID,mem_sp_local_key_invalid + jam SP_CALC_STANDBY,mem_sp_calc + rtn + +sp_dhkey_calc: + bpatchx patch34_4,mem_patch34 + fetch 1,mem_sp_dhkey_invalid + rtnne SP_KEY_INVALID + fetch 1,mem_sp_calc + rtnne SP_CALC_STANDBY + + arg mem_k,contw + arg mem_sp_private_key,contr + call memcpy24 + + arg mem_ax,contw + arg mem_sp_pubkey_remote,contr + call memcpy48 + + arg mem_az,contw + call bn_zero + jam 1,mem_az + + call eckp_calc_init + jam SP_CALC_DHKEY,mem_sp_calc + rtn + +sp_dhkey_generated: + jam SP_FLAG_COMMIT,mem_sp_dh_ready + arg mem_sp_dhkey,contw + arg mem_bx,contr + call memcpy24 + jam SP_KEY_VALID,mem_sp_dhkey_invalid + jam SP_CALC_STANDBY,mem_sp_calc + rtn + +random_generator: + increase -1,queue + nrtn positive + random pdata + istore 2,contw + branch random_generator +compare4: + increase -1,queue + nbranch compare4_success,positive + ifetch 4,regA + copy pdata,temp + ifetch 4,regB + iflip temp,pdata + nbranch compare4_failed,zero + increase 4,regA + increase 4,regB + branch compare4 +compare4_failed: + disable true + rtn +compare4_success: + enable true + rtn + +/*************************************************/ +/** Message state machine routines ***************/ +/*************************************************/ +// simple pairing support + +simple_pairing_sequence: + bpatchx patch34_5,mem_patch34 + fetch 1,mem_sp_flag + rtn blank + jam SP_FLAG_STANDBY,mem_sp_flag + fetch 1,mem_sp_state + beq SP_STAT_KEY_SEND,sp_send_LMP_ENCAPSULATED_HEADER + beq SP_STAT_COMMIT_SEND,sp_send_LMP_SIMPLE_PAIRING_COMFIRM + beq SP_STAT_RANDOM_SEND,sp_send_LMP_SIMPLE_PAIRING_NUMBER + beq SP_STAT_CONFIRM_SEND,sp_send_LMP_DHKEY_CHECK + beq SP_STAT_KEY_GENERATE,sp_generate_local_key + beq SP_STAT_COMMIT_CALC,sp_calculate_commitment + beq SP_STAT_CONFIRM_CHECK,sp_confirm_check + beq SP_STAT_CONFIRM_CALC,sp_confirm_calc + beq SP_STAT_LINK_KEY_CALC,sp_link_key_prarm_push + //beq SP_STAT_FEATURE_EXT_SEND,send_LMP_FEATURES_REQ_EXT + rtn + +master_simple_paring_sequence: + bpatchx patch34_6,mem_patch34 + fetch 1,mem_master_sp_flag + rtn blank + jam SP_FLAG_STANDBY,mem_master_sp_flag + fetch 1,mem_master_sp_state + beq SP_MASTER_STAT_START_SKIP,sp_master_send_io_cap_get + beq SP_MASTER_STAT_START_DONE,sp_master_send_io_cap_send + beq SP_STAT_KEY_SEND,sp_master_send_LMP_ENCAPSULATED_HEADER + beq SP_STAT_COMMIT_CALC,master_sp_calculate_commitment + beq SP_STAT_COMMITMENT_COMPARE,sp_master_commitment_compare + beq SP_STAT_RANDOM_SEND,sp_master_send_LMP_SIMPLE_PAIRING_NUMBER + beq SP_STAT_CONFIRM_CALC,sp_confirm_calc + beq SP_STAT_CONFIRM_SEND,master_sp_send_lmp_dhkey_check + beq SP_STAT_CONFIRM_CHECK,sp_confirm_check + beq SP_STATE_END,master_sp_sm_end + rtn + +master_set_mem_master_sp_flag: + jam SP_FLAG_COMMIT,mem_master_sp_flag + rtn + +master_clear_mem_master_sp_flag: + jam SP_FLAG_STANDBY,mem_master_sp_flag + rtn +sp_calc_sequence: + bpatchx patch34_7,mem_patch34 + fetch 1,mem_ssp_enable + rtn blank + fetch 1,mem_sp_calc + rtn blank + increase 0x80,pdata + store 1,mem_sp_calc + rtnbit1 7 + fetch 1,mem_ec_loopc + branch sp_calc_sequence_done,blank + branch eckp_calc + +sp_calc_sequence_done: + call ecunmapz + fetch 1,mem_sp_calc + beq SP_CALC_PUBKEY,sp_pubkey_generated + beq SP_CALC_DHKEY,sp_dhkey_generated + rtn + + +bn_testbit: + and pdata,7,queue + rshift3 pdata,pdata + iadd contr,contr + ifetch 1,contr + qisolate0 pdata + rtn + + +ec_copy: + call memcpy24 + call memcpy24 + branch memcpy24 + + +bn_eq_zero: + ifetch 8,contr + nrtn blank + ifetch 8,contr + nrtn blank + ifetch 8,contr + rtn + + + /* return zero if eq */ + +bn_eq_0: + ifetch 4,regA + iforce temp + ifetch 4,regB + isub temp,null + nrtn zero + increase 4,regA + increase 4,regB + loop bn_eq_0 + rtn + + /* return positive if A >= B */ +bn_bigeq: + force 6,loopcnt + increase 20,regA + increase 20,regB +bn_bigeq_0: + ifetch 4,regB + iforce temp + ifetch 4,regA + isub temp,pdata + nrtn positive + nrtn blank + increase -4,regA + increase -4,regB + loop bn_bigeq_0 + rtn + +bn_add: + force 6,loopcnt + force 0,regC +bn_add_0: + ifetch 4,regA + iforce temp + ifetch 4,regB + iadd temp,pdata + iadd regC,pdata + istore 4,contw + isolate1 32,pdata + setflag true,0,regC + increase 4,regA + increase 4,regB + loop bn_add_0 + rtn + +bn_sub: + force 6,loopcnt + force 0,regC +bn_sub_0: + ifetch 4,regB + iforce temp + ifetch 4,regA + isub temp,pdata + isub regC,pdata + istore 4,contw + isolate1 32,pdata + setflag true,0,regC + increase 4,regA + increase 4,regB + loop bn_sub_0 + rtn + +bn_rshift6: + force 6,loopcnt + increase 20,regA +bn_rshift: + force 0,regC +bn_rshift_0: + ifetch 4,regA + isolate1 0,pdata + setflag true,1,regC + rshift pdata,pdata + isolate1 0,regC + setflag true,31,pdata + istore 4,regA + increase -4,regA + rshift regC,regC + loop bn_rshift_0 + rtn + +bn_lshift: + force 6,loopcnt + force 0,regC +bn_lshift_0: + ifetch 4,regA + isolate1 31,pdata + setflag true,1,regC + lshift pdata,pdata + isolate1 0,regC + setflag true,0,pdata + istore 4,regA + increase 4,regA + rshift regC,regC + loop bn_lshift_0 + rtn + +bn_lshiftmod: + call bn_lshift +bn_lshiftmod_ismod: + isolate1 0,regC + branch bn_lshiftmod_0,true + arg mem_p,regB + copy regA,regC + increase -24,regA + call bn_bigeq + nrtn positive + copy regC,regA +bn_lshiftmod_0: + increase -24,regA + arg mem_p,regB + copy regA,contw + branch bn_sub + + +bn_addmod: + call bn_add + copy contw,regA + branch bn_lshiftmod_ismod + +bn_submod: + call bn_sub + isolate0 0,regC + rtn true + arg mem_p,regB + add contw,-24,regA + copy regA,contw + branch bn_add + + +bn_p192mod: + copy contw,timeup /* save result ptr */ + copy regA,alarm /* temp save regA */ + arg mem_tmp2,regB + copy regB,contw + add regA,24,contr + ifetch 8,contr + istore 8,contw + istore 8,contw + force 0,pdata + istore 8,contw + copy timeup,contw + call bn_addmod + arg mem_tmp2,regB + copy regB,contw + force 0,pdata + istore 8,contw + add alarm,32,contr + ifetch 8,contr + istore 8,contw + istore 8,contw + copy timeup,regA + copy regA,contw + call bn_addmod + arg mem_tmp2,regB + copy regB,contw + add alarm,40,contr + ifetch 8,contr + istore 8,contw + istore 8,contw + istore 8,contw + copy timeup,regA + copy regA,contw + branch bn_addmod + + +bn_load: + force 6,loopcnt +bn_load_0: + ifetch 4,contr + iforce regext + increase 1,regext_index + loop bn_load_0 + rtn + + + /* cost 1562 clks */ +bn_mulmod: + copy contw,timeup /* save result ptr */ + arg mem_tmp1,contw + call bn_zero + arg mem_tmp1,contw + copy regA,contr + force 0,regext_index + call bn_load + copy regB,contr + call bn_load + force 0,regB +bn_mulmod_1: + force 0,temp + force 6,regC +bn_mulmod_0: + ifetch 4,contw /* d[i+j] */ + iforce regA + copy regB,regext_index + deposit regext + copy regC,regext_index + imul32 regext,pdata + iadd regA,pdata /* uv = a[i]*b[j] + d[i+j] */ + iadd temp,pdata /* uv += u */ + istore 4,contw /* ->d[i+j] */ + rshift32 pdata,temp /* temp = u = uv >> 32 */ + increase 1,regC + compare 12,regC,0xff + nbranch bn_mulmod_0,true + deposit temp + istore 4,contw /* d[i + 12] = u */ + increase -24,contw + increase 1,regB + compare 6,regB,0xff + nbranch bn_mulmod_1,true + arg mem_tmp1,regA + copy timeup,contw + branch bn_p192mod + + +bn_sqrmod: + copy regA,regB + branch bn_mulmod + +bn_rshifteven: + copy regA,alarm +bn_rshifteven_1: + copy alarm,regA + ifetch 1,regA + isolate1 0,pdata + rtn true + call bn_rshift6 + ifetch 1,regB + isolate0 0,pdata + branch bn_rshifteven_0,true + arg mem_p,regA + copy regB,contw + call bn_add + ifetch 1,regB + iadd regC,pdata + istore 1,regB /* [6] */ + increase -24,regB +bn_rshifteven_0: + add regB,24,regA + force 7,loopcnt + call bn_rshift + branch bn_rshifteven_1 + + /* cost 141910 clks */ +bn_invmod: + copy contw,timeup /* save result ptr */ + arg mem_tmp0,contw /* x */ + call bn_zero + force 0,pdata + store 4,mem_tmp5 + store 4,mem_t2 + jam 1,mem_tmp0 + arg mem_tmp1,contw /* y */ + call bn_zero + arg mem_p,contr + arg mem_tmp2,contw /* a */ + call memcpy24 + copy regA,contr + arg mem_tmp3,contw /* b */ + call memcpy24 +bn_invmod_2: + arg mem_tmp3,contr + call bn_eq_zero + branch bn_invmod_0,blank + arg mem_tmp3,regA + arg mem_tmp0,regB + call bn_rshifteven + + arg mem_tmp2,regA + arg mem_tmp1,regB + call bn_rshifteven + arg mem_tmp3,regA + arg mem_tmp2,regB + call bn_bigeq + branch bn_invmod_1,positive + arg mem_tmp2,regA + arg mem_tmp3,regB + copy regA,contw + call bn_sub + arg mem_tmp0,regA + arg mem_tmp1,regB + copy regB,contw + call bn_add + ifetch 1,regA + iadd regC,regC + ifetch 1,regB + iadd regC,pdata + istore 1,regB + branch bn_invmod_2 +bn_invmod_1: + arg mem_tmp3,regA + arg mem_tmp2,regB + copy regA,contw + call bn_sub + arg mem_tmp1,regA + arg mem_tmp0,regB + copy regB,contw + call bn_add + ifetch 1,regA + iadd regC,regC + ifetch 1,regB + iadd regC,pdata + istore 1,regB + branch bn_invmod_2 +bn_invmod_0: + arg mem_tmp0,contw + call bn_zero + fetch 1,mem_tmp5 + store 1,mem_tmp0 + store 1,mem_tmp0a + arg mem_tmp0,regA + arg mem_tmp1,regB + copy regB,contw + call bn_addmod + arg mem_p,regA + arg mem_tmp1,regB + copy timeup,contw + branch bn_submod + + + + /* cost 64742 clks */ +ecdbl: + arg mem_cz,regA + arg mem_t2,contw + call bn_sqrmod + arg mem_t2,regA + arg mem_t3,contw + call bn_sqrmod + arg mem_a,regA + arg mem_t3,regB + arg mem_t3,contw + call bn_mulmod /* t3=a*z4 */ + arg mem_cx,regA + arg mem_t2,contw + call bn_sqrmod + arg mem_t2,contr + arg mem_t1,contw + call memcpy24 + arg mem_t1,regA + call bn_lshiftmod + arg mem_t2,regA + arg mem_t1,regB + arg mem_t2,contw + call bn_addmod + arg mem_t2,regA + arg mem_t3,regB + arg mem_t2,contw + call bn_addmod /* t2=3*x2 + z*z4 D */ + arg mem_cx,contr + arg mem_t1,contw + call memcpy24 + arg mem_cy,regA + arg mem_t3,contw + call bn_sqrmod + arg mem_t1,regA + call bn_lshiftmod + arg mem_t1,regA + call bn_lshiftmod + arg mem_t1,regA + arg mem_t3,regB + arg mem_t1,contw + call bn_mulmod /* t1=4x*y2 B */ + arg mem_t3,regA + arg mem_t0,contw + call bn_sqrmod + arg mem_t0,regA + call bn_lshiftmod + arg mem_t0,regA + call bn_lshiftmod + arg mem_t0,regA + call bn_lshiftmod /* t0=8*y4 C */ + arg mem_cy,contr + arg mem_t3,contw + call memcpy24 + arg mem_t3,regA + call bn_lshiftmod + arg mem_t3,regA + arg mem_cz,regB + arg mem_cz,contw + call bn_mulmod + arg mem_t2,regA + arg mem_t3,contw + call bn_sqrmod + arg mem_t3,regA + arg mem_t1,regB + arg mem_t3,contw + call bn_submod + arg mem_t3,regA + arg mem_t1,regB + arg mem_cx,contw + call bn_submod + arg mem_t1,regA + arg mem_cx,regB + arg mem_t3,contw + call bn_submod + arg mem_t3,regA + arg mem_t2,regB + arg mem_t3,contw + call bn_mulmod + arg mem_t3,regA + arg mem_t0,regB + arg mem_cy,contw + branch bn_submod + + + /* cost 104904 clks */ +ecadd: + arg mem_az,regA + arg mem_t7,contw + call bn_sqrmod + arg mem_cx,regA + arg mem_t7,regB + arg mem_t0,contw + call bn_mulmod /* n1=t0=xa*zb2 */ + arg mem_az,regA + arg mem_t7,regB + arg mem_t7,contw + call bn_mulmod + arg mem_cy,regA + arg mem_t7,regB + arg mem_t1,contw + call bn_mulmod /* n2=t1=ya*zb3 */ + arg mem_cz,regA + arg mem_t7,contw + call bn_sqrmod + arg mem_ax,regA + arg mem_t7,regB + arg mem_t2,contw + call bn_mulmod /* n3=t2=xb*za2 */ + arg mem_cz,regA + arg mem_t7,regB + arg mem_t7,contw + call bn_mulmod + arg mem_ay,regA + arg mem_t7,regB + arg mem_t3,contw + call bn_mulmod /* n4=t3=yb*za3 */ + arg mem_t0,regA + arg mem_t2,regB + arg mem_t7,contw + call bn_submod /* n5=t7=n1-n3=t0-t2 */ + arg mem_t0,regA + arg mem_t2,regB + arg mem_t0,contw + call bn_addmod /* n7=t0=n1+n3=t0+t2 */ + arg mem_t1,regA + arg mem_t3,regB + arg mem_t2,contw + call bn_submod /* n6=t2=n2-n4=t1-t3 */ + arg mem_t1,regA + arg mem_t3,regB + arg mem_t1,contw + call bn_addmod /* n8=t1=n2+n4=t1+t3 */ + arg mem_t1,regA + arg mem_t7,regB + arg mem_t1,contw + call bn_mulmod /* t1=n8*n5 */ + arg mem_cz,regA + arg mem_az,regB + arg mem_t3,contw + call bn_mulmod + arg mem_t3,regA + arg mem_t7,regB + arg mem_cz,contw + call bn_mulmod /* z=za*zb*n5 */ + arg mem_t7,regA + arg mem_t7,contw + call bn_sqrmod /* t7=n5^2 */ + arg mem_t7,regA + arg mem_t0,regB + arg mem_t3,contw + call bn_mulmod /* t3=n5^2*n7 */ + arg mem_t7,regA + arg mem_t1,regB + arg mem_t1,contw + call bn_mulmod /* t1=n8*n5^3 */ + arg mem_t2,regA + arg mem_cx,contw + call bn_sqrmod + arg mem_cx,regA + arg mem_t3,regB + arg mem_cx,contw + call bn_submod /* x=n6^2-n5^2*n7 */ + arg mem_cx,contr + arg mem_t7,contw + call memcpy24 + arg mem_t7,regA + call bn_lshiftmod /* t7=2*x */ + arg mem_t3,regA + arg mem_t7,regB + arg mem_t3,contw + call bn_submod /* t3=n9 */ + arg mem_t3,regA + arg mem_t2,regB + arg mem_t2,contw + call bn_mulmod /* t2=n9*n6 */ + arg mem_t2,regA + arg mem_t1,regB + arg mem_cy,contw + call bn_submod + arg mem_cy,regA + arg mem_p,regB + arg mem_cy,contw + force 0,regC + fetch 1,mem_cy + isolate1 0,pdata + call bn_add,true + copy regC,alarm + arg mem_cy,regA + call bn_rshift6 + fetch 1,mem_cy5 + isolate1 0,alarm + setflag true,7,pdata + store 1,mem_cy5 + rtn + + /* cost 22276983 clks */ + +eckp_0: + fetch 1,mem_ec_loopc + increase -1,pdata + nrtn positive + store 1,mem_ec_loopc + fetch 1,mem_ec_infinite + call ecdbl,blank + fetch 1,mem_ec_loopc + arg mem_k,contr + call bn_testbit + branch eckp_0,true + fetch 1,mem_ec_infinite + nbranch eckp_1,blank + call ecadd + branch eckp_0 +eckp_1: + jam 0,mem_ec_infinite + arg mem_ax,contr + arg mem_cx,contw + call ec_copy + branch eckp_0 + + /* cost 162522 clks */ +ecunmapz: + arg mem_cz,regA + arg mem_t3,contw + call bn_invmod /* t3 = 1/z */ + arg mem_t3,regA + arg mem_t1,contw + call bn_sqrmod /* t1 = 1/z2 */ + arg mem_cx,regA + arg mem_t1,regB + arg mem_bx,contw + call bn_mulmod + arg mem_t3,regA + arg mem_t1,regB + arg mem_t2,contw + call bn_mulmod /* t2 = 1/z3 */ + arg mem_cy,regA + arg mem_t2,regB + arg mem_by,contw + branch bn_mulmod + + + +sha_endian_swap2: + ifetch 4,contr + force 4,regA + increase 3,contw +sha_endian_loop: + istore 1,contw + rshift8 pdata,pdata + increase -2,contw + increase -1,regA + nbranch sha_endian_loop,zero + increase 5,contw + loop sha_endian_swap2 + rtn + + +sha_getw: + lshift2 queue,pdata + iadd timeup,contr + ifetch 4,contr + rtn + +sha_r: + force 16,alarm + arg memdat,timeup +sha_r_loop: + add alarm,-7,queue + call sha_getw + iforce temp /* W[t - 7] */ + add alarm,-16,queue + call sha_getw + iadd temp,temp /* W[t-7] + W[t-16] */ + add alarm,-2,queue + call sha_getw + shasx pdata,1,pdata + iadd temp,temp /* S1(W[t - 2]) + W[t-7] + W[t-16] */ + add alarm,-15,queue + call sha_getw + shasx pdata,0,pdata + iadd temp,temp /* S0(W[t - 15]) + S1(W[t - 2]) + W[t-7] + W[t-16] */ + lshift2 alarm,pdata + iadd timeup,contw + istoret 4,contw + increase 1,alarm + compare 64,alarm,0xff + nbranch sha_r_loop,true + rtn + + +sha_init: + arg memh0,contr + force 7,regext_index +sha_init_0: + ifetch 4,contr + iforce regext + increase -1,regext_index + branch sha_init_0,positive + rtn + +sha: + bpatchx patch35_0,mem_patch35 + call sha_r /* preprocessing data into R() */ + arg memahbak,contw + force 0,regext_index +sha_0: + deposit regext + istore 4,contw + increase 1,regext_index + compare 8,regext_index,0xff + nbranch sha_0,true + call enable_authrom + arg memk,timeup + arg memdat,alarm + force 64,loopcnt +sha_loop: + ifetcht 4,alarm + ifetch 4,timeup + increase 4,timeup + increase 4,alarm + iadd temp,pdata /* x+K */ + force 7,regext_index + iadd regext,temp /* x+K+h */ + force 4,regext_index + shasx regext,3,pdata + iadd temp,temp /* temp = s3(e)+x+K+h */ + force 5,regext_index + deposit regext + force 6,regext_index + ixor regext,pdata + force 4,regext_index + iand regext,pdata /* (e & (f ^ g)) */ + force 6,regext_index + ixor regext,pdata /* F1(e, f, g) = g ^ (e & (f ^ g)) */ + iadd temp,temp /* temp1 = h + S3(e) + F1(e,f,g) + K + x */ + force 7,regext_index + copy temp,regext /* save to H */ + force 3,regext_index + deposit regext + iadd temp,regext /* save to D */ + force 0,regext_index + deposit regext + force 1,regext_index + iand regext,temp /* a & b */ + ior regext,pdata /* a | b */ + force 2,regext_index + iand regext,pdata /* (c & (a | b)) */ + ior temp,temp /* F0:(a & b) | (c & (a | b)) */ + force 0,regext_index + shasx regext,2,pdata + iadd temp,pdata /* temp2 = S2(a) + F0(a,b,c) */ + force 7,regext_index + iadd regext,regext /* h = temp1 + temp2 */ + regexrot /* rotate move h,a-g => a-h */ + loop sha_loop + arg memahbak,contr + force 0,regext_index +sha_1: + ifetch 4,contr + iadd regext,regext + increase 1,regext_index + compare 8,regext_index,0xff + nbranch sha_1,true + branch disable_authrom + + +sha_result: + arg memresult,contw + force 7,regext_index +sha_regext_save: + deposit regext + istore 4,contw + increase -1,regext_index + branch sha_regext_save,positive + rtn + +pad_xor: +// arg memx_end,contr + arg memdat,contw + increase -4,contr + sub loopcnt,16,regA +pad_xor_0: + ifetch 4,contr + ixor temp,pdata + istore 4,contw + increase -8,contr + loop pad_xor_0 + copy regA,loopcnt + deposit temp +pad_xor_1: + istore 4,contw + loop pad_xor_1 + rtn + +g_noninit_number_confirm: + call g_noninit0 + call sha_result + branch g_common0 + +g_noninit: + call g_noninit0 + branch g_common0 + +g_noninit0: + arg mem_sp_pubkey_remote_x_end,contr + arg memdat,contw + force 6,loopcnt + call memcpy_dword_swap + arg mem_sp_pubkey_local_x_end,contr + force 6,loopcnt + call memcpy_dword_swap + arg mem_sp_random_remote_end,contr + call memcpy_dword_swap4 + call sha_init + call sha + arg mem_sp_random_local_end,contr + arg memdat,contw + branch g_common + +g_init: + arg mem_sp_pubkey_local_x_end,contr + arg memdat,contw + force 6,loopcnt + call memcpy_dword_swap + arg mem_sp_pubkey_remote_x_end,contr + force 6,loopcnt + call memcpy_dword_swap + arg mem_sp_random_local_end,contr + call memcpy_dword_swap4 + call sha_init + call sha + arg mem_sp_random_remote_end,contr + arg memdat,contw + call g_common + branch g_common0 + +g_common: + call memcpy_dword_swap4 + setarg 0x800000 + lshift8 pdata,pdata + istore 4,contw + force 5,loopcnt + call memset0 + setarg 640 + istore 4,contw + branch sha +g_common0: + fetch 4,memresult +// store 4,mem_gkey + arg 1000,rega + idiv rega + call wait_div_end + remainder pdata + store 4,mem_gkey + quotient pdata + arg 1000,rega + idiv rega + call wait_div_end + remainder pdata + arg 1000,rega + imul32 rega,pdata + fetcht 4,mem_gkey + iadd temp,pdata + store 4,mem_gkey + rtn + +function_f1_no_key: + jam 0,mem_passkey_1bit + branch function_f1_common + +function_f1: + fetch 1,mem_ssp_mode_flag + bne SSP_MODE_PASSKEY_ENTRY_FLAG,function_f1_no_key +function_f1_common: + bpatchx patch35_1,mem_patch35 + setarg 0x363636 + lshift8 pdata,temp + or_into 0x36,temp + fetch 2,mem_sp_prarm_stack + copy pdata,contr + force 4,loopcnt + call pad_xor + call sha_init + call sha + fetch 2,mem_sp_prarm_stack+2 + copy pdata,contr + arg memdat,contw + force 6,loopcnt + call memcpy_dword_swap + fetch 2,mem_sp_prarm_stack+4 + copy pdata,contr + force 6,loopcnt + call memcpy_dword_swap + setarg 0x800000 + istore 3,contw + + fetch 1,mem_passkey_1bit + + istore 1,contw + force 0,pdata + istore 8,contw + setarg 0x0388 + istore 4,contw + call sha + call sha_result + arg memresult,contr + arg memahsave,contw + call memcpy32 + + setarg 0x5c5c5c + lshift8 pdata,temp + or_into 0x5c,temp + fetch 2,mem_sp_prarm_stack + copy pdata,contr + force 4,loopcnt + call pad_xor + call sha_init + call sha + arg memahsave_end,contr + arg memdat,contw + force 8,loopcnt + call memcpy_dword_swap + setarg 0x800000 + lshift8 pdata,pdata + istore 4,contw + call bn_zero + setarg 0x0300 + istore 4,contw + call sha + branch sha_result + + +function_f2: + setarg 0x363636 + lshift8 pdata,temp + or_into 0x36,temp + arg mem_sp_dhkey_end,contr + force 6,loopcnt + call pad_xor + call sha_init + call sha + fetch 2,mem_sp_prarm_stack+12 + copy pdata,contr + arg memdat,contw + call memcpy_dword_swap4 + fetch 2,mem_sp_prarm_stack+14 + copy pdata,contr + call memcpy_dword_swap4 + + setarg 0x62746c + lshift8 pdata,pdata + or_into 0x6b,pdata + istore 4,contw + arg mem_addr_value_end,contr + force 3,loopcnt + call memcpy_dword_swap + + setarg 0x800000 + lshift8 pdata,pdata + istore 4,contw + force 0,pdata + istore 8,contw + setarg 0x0380 + istore 4,contw + call sha + + call sha_result + arg memresult,contr + arg memahsave,contw + call memcpy32 + + setarg 0x5c5c5c + lshift8 pdata,temp + or_into 0x5c,temp + arg mem_sp_dhkey_end,contr + force 6,loopcnt + call pad_xor + call sha_init + call sha + arg memahsave_end,contr + arg memdat,contw + force 8,loopcnt + call memcpy_dword_swap + setarg 0x800000 + lshift8 pdata,pdata + istore 4,contw + call bn_zero + setarg 0x0300 + istore 4,contw + call sha + branch sha_result + + +function_f3a: + fetch 1,mem_ssp_mode_flag + bne SSP_MODE_PASSKEY_ENTRY_FLAG,function_f3a_no_pin +function_f3a_common: + bpatchx patch35_2,mem_patch35 + setarg 0x363636 + lshift8 pdata,temp + or_into 0x36,temp + arg mem_sp_dhkey_end,contr + force 6,loopcnt + call pad_xor + call sha_init + call sha + arg mem_sp_random_remote_end,contr + arg memdat,contw + call memcpy_dword_swap4 + arg mem_sp_random_local_end,contr + call memcpy_dword_swap4 + branch function_f3_common + +function_f3a_no_pin: + setarg 0 + store 4,mem_pin + branch function_f3a_common + +function_f3b_no_pin: + setarg 0 + store 4,mem_pin + branch function_f3b_common + + +function_f3b: + fetch 1,mem_ssp_mode_flag + bne SSP_MODE_PASSKEY_ENTRY_FLAG,function_f3b_no_pin +function_f3b_common: + setarg 0x363636 + lshift8 pdata,temp + or_into 0x36,temp + arg mem_sp_dhkey_end,contr + force 6,loopcnt + call pad_xor + call sha_init + call sha + + arg mem_sp_random_local_end,contr + arg memdat,contw + call memcpy_dword_swap4 + arg mem_sp_random_remote_end,contr + call memcpy_dword_swap4 +function_f3_common: + setarg 0x0 + istore 8,contw + istore 4,contw + fetch 4,mem_pin + istore 4,contw + + copy contw,temp + jam 0x80,mem_addr_padding + copy temp,contw + arg mem_addr_iocap_end,contr + call memcpy_dword_swap4 + + call sha + + arg memdat,contw + force 7,loopcnt + call memset0 + istore 4,contw + setarg 0x03F8 + istore 4,contw + call sha + call sha_result + + arg memresult,contr + arg memahsave,contw + call memcpy32 + + setarg 0x5c5c5c + lshift8 pdata,temp + or_into 0x5c,temp + arg mem_sp_dhkey_end,contr + force 6,loopcnt + call pad_xor + call sha_init + call sha + arg memahsave_end,contr + arg memdat,contw + force 8,loopcnt + call memcpy_dword_swap + setarg 0x800000 + lshift8 pdata,pdata + istore 4,contw + call bn_zero + setarg 0x0300 + istore 4,contw + call sha + branch sha_result + +/* +eckp: + jam 192,mem_ec_loopc + jam 1,mem_ec_infinite +*/ +eckp_calc_init: + jam 192,mem_ec_loopc +eckp_calc_init_1: + fetch 1,mem_ec_loopc + rtn blank + increase -1,pdata + store 1,mem_ec_loopc + arg mem_k,contr + call bn_testbit + branch eckp_calc_init_1,true + arg mem_ax,contr + arg mem_cx,contw + branch ec_copy + +eckp_calc: + call ecdbl + fetch 1,mem_ec_loopc + increase -1,pdata + store 1,mem_ec_loopc + arg mem_k,contr + call bn_testbit + rtn true + branch ecadd + +memcpy_dword_swap4: + force 4,loopcnt +memcpy_dword_swap: + increase -4,contr +memcpy_dword_swap_loop: + ifetch 4,contr + istore 4,contw + increase -8,contr + loop memcpy_dword_swap_loop + rtn + +else +sp_initialize: + rtn + +endif + + +ifdef SECURE_CONNECTION + +sp_initialize_256: + bpatchx patch35_3,mem_patch35 + fetch 1,mem_le_secure_connect_enable + branch le_secure_connection_disable,blank + call le_secure_connection_enable + call sp_clear_flags +// jam SP_KEY_INVALID_256,mem_le_sc_local_key_invalid + branch sp_pubkey_calc_256 + + +sp_pubkey_calc_256: + fetch 1,mem_le_sc_local_key_invalid + rtnne SP_KEY_INVALID + fetch 1,mem_le_sc_calc + rtnne SP_CALC_STANDBY + + arg mem_le_private_key_256,contw + force 15,queue + call random_generator + random pdata + rshift pdata,pdata + istore 2,contw + + arg mem_k_256,contw + arg mem_le_private_key_256,contr + call memcpy32 //mem_sp_private_key=>mem_k + + arg mem_ax_256,contw + arg mem_gx_256,contr + call memcpy64 //mem_gx=>mem_ax + + arg mem_az_256,contw + call clear_mem_256 + jam 1,mem_az_256 //0=>mem_az + + call eckp_calc_init_256 + jam SP_CALC_PUBKEY_256,mem_le_sc_calc + rtn + +sp_pubkey_generated_256: + arg mem_le_pubkey_local_x_256,contw + arg mem_bx_256,contr + call memcpy64 + jam SP_KEY_VALID_256,mem_le_sc_local_key_invalid + jam SP_CALC_STANDBY,mem_le_sc_calc + rtn + + + +sp_dhkey_calc_256: + fetch 1,mem_sp_dhkey_invalid + rtnne SP_KEY_INVALID + fetch 1,mem_le_sc_calc + rtnne SP_CALC_STANDBY + + arg mem_k_256,contw + arg mem_le_private_key_256,contr + call memcpy32 + + arg mem_ax_256,contw + arg mem_le_pubkey_remote_x_256,contr + call memcpy64 + + arg mem_az_256,contw + call clear_mem_256 + jam 1,mem_az_256 //0=>mem_az + + call eckp_calc_init_256 + jam SP_CALC_DHKEY_256,mem_le_sc_calc + rtn + + +sp_dhkey_generated_256: +// jam SP_FLAG_COMMIT,mem_sp_dh_ready + arg mem_le_dhkey_256,contw + arg mem_bx_256,contr + call memcpy32 + jam SP_KEY_VALID_256,mem_sp_dhkey_invalid + jam SP_CALC_STANDBY,mem_le_sc_calc + rtn + + + +sp_calc_sequence_256: + fetch 1,mem_le_secure_connect_enable + rtn blank + fetch 1,mem_le_sc_calc + rtn blank + increase 0x80,pdata + store 1,mem_le_sc_calc + rtnbit1 7 + fetch 2,mem_ec_loopc + branch sp_calc_sequence_done_256,blank + branch eckp_calc_256 + +sp_calc_sequence_done_256: + bpatchx patch35_4,mem_patch35 + call ecunmapz_256 + fetch 1,mem_le_sc_calc + beq SP_CALC_PUBKEY_256,sp_pubkey_generated_256 + beq SP_CALC_DHKEY_256,sp_dhkey_generated_256 + rtn + + +eckp_calc_256: + call ecdbl_256 + fetch 2,mem_ec_loopc + increase -1,pdata + store 2,mem_ec_loopc + arg mem_k_256,contr + call bn_testbit + rtn true + branch ecadd_256 + +eckp_calc_init_256: + bpatchx patch35_5,mem_patch35 + setarg 256,pdata + store 2,mem_ec_loopc +eckp_calc_init_256_1: + fetch 2,mem_ec_loopc + rtn blank + increase -1,pdata + store 2,mem_ec_loopc + arg mem_k_256,contr + call bn_testbit + branch eckp_calc_init_256_1,true + arg mem_ax_256,contr + arg mem_cx_256,contw + branch memcpy96 + + +ecunmapz_256: + arg mem_cz_256,regA + arg mem_t3_256,contw + call bn_invmod_256 /* t3 = 1/z */ + arg mem_t3_256,regA + arg mem_t1_256,contw + call bn_sqrmod_256 /* t1 = 1/z2 */ + arg mem_cx_256,regA + arg mem_t1_256,regB + arg mem_bx_256,contw + call bn_mulmod_256 + arg mem_t3_256,regA + arg mem_t1_256,regB + arg mem_t2_256,contw + call bn_mulmod_256 /* t2 = 1/z3 */ + arg mem_cy_256,regA + arg mem_t2_256,regB + arg mem_by_256,contw + branch bn_mulmod_256 + +ecdbl_256: + arg mem_cz_256,regA + arg mem_t2_256,contw + call bn_sqrmod_256 + arg mem_t2_256,regA + arg mem_t3_256,contw + call bn_sqrmod_256 +//call ice_break + arg mem_a_256,regA + arg mem_t3_256,regB + arg mem_t3_256,contw + call bn_mulmod_256 /* t3=a*z4 */ + arg mem_cx_256,regA + arg mem_t2_256,contw + call bn_sqrmod_256 +//call ice_break + arg mem_t2_256,contr + arg mem_t1_256,contw + call memcpy32 + arg mem_t1_256,regA + call bn_lshiftmod_256 + arg mem_t2_256,regA + arg mem_t1_256,regB + arg mem_t2_256,contw + call bn_addmod_256 +//call ice_break + arg mem_t2_256,regA + arg mem_t3_256,regB + arg mem_t2_256,contw + call bn_addmod_256 /* t2=3*x2 + z*z4 D */ +//call ice_break + arg mem_cx_256,contr + arg mem_t1_256,contw + call memcpy32 + arg mem_cy_256,regA + arg mem_t3_256,contw + call bn_sqrmod_256 + arg mem_t1_256,regA + call bn_lshiftmod_256 + arg mem_t1_256,regA + call bn_lshiftmod_256 + arg mem_t1_256,regA + arg mem_t3_256,regB + arg mem_t1_256,contw + call bn_mulmod_256 //S = 4X1Y1^2/* t1=4x*y2 B */ + arg mem_t3_256,regA + arg mem_t0_256,contw + call bn_sqrmod_256 + arg mem_t0_256,regA + call bn_lshiftmod_256 + arg mem_t0_256,regA + call bn_lshiftmod_256 + arg mem_t0_256,regA + call bn_lshiftmod_256 //T = 8Y1^4 /* t0=8*y4 C */ + arg mem_cy_256,contr + arg mem_t3_256,contw + call memcpy32 + arg mem_t3_256,regA + call bn_lshiftmod_256 + arg mem_t3_256,regA + arg mem_cz_256,regB + arg mem_cz_256,contw + call bn_mulmod_256 //z = 2Y1Z1 + + + arg mem_t2_256,regA + arg mem_t3_256,contw + call bn_sqrmod_256 // M ^2 +//call ice_break + arg mem_t3_256,regA + arg mem_t1_256,regB + arg mem_t3_256,contw + call bn_submod_256 // t2^2 - 4*cx *cy^2 + arg mem_t3_256,regA + arg mem_t1_256,regB + arg mem_cx_256,contw + call bn_submod_256 //X2 + arg mem_t1_256,regA + arg mem_cx_256,regB + arg mem_t3_256,contw + call bn_submod_256 //S-X2 + arg mem_t3_256,regA + arg mem_t2_256,regB + arg mem_t3_256,contw + call bn_mulmod_256 //M(S-X2) + arg mem_t3_256,regA + arg mem_t0_256,regB + arg mem_cy_256,contw + branch bn_submod_256 //M(S-X2)-T Y2 + +ecadd_256: + + arg mem_az_256,regA + arg mem_t7_256,contw + call bn_sqrmod_256 + arg mem_cx_256,regA + arg mem_t7_256,regB + arg mem_t0_256,contw + call bn_mulmod_256 /* n1=t0=xa*zb2 U1 = X1Z0^2*/ + + + arg mem_az_256,regA + arg mem_t7_256,regB + arg mem_t7_256,contw + call bn_mulmod_256 + arg mem_cy_256,regA + arg mem_t7_256,regB + arg mem_t1_256,contw + call bn_mulmod_256 /* n2=t1=ya*zb3 S1 = Y1Z0^3*/ + + + arg mem_cz_256,regA + arg mem_t7_256,contw + call bn_sqrmod_256 + arg mem_ax_256,regA + arg mem_t7_256,regB + arg mem_t2_256,contw + call bn_mulmod_256 /* n3=t2=xb*za2 U0 = X0Z1^2*/ + + arg mem_cz_256,regA + arg mem_t7_256,regB + arg mem_t7_256,contw + call bn_mulmod_256 + arg mem_ay_256,regA + arg mem_t7_256,regB + arg mem_t3_256,contw + call bn_mulmod_256 /* n4=t3=yb*za3 S0 = Y0Z1^3*/ + + +// arg mem_t0_256,regA +// arg mem_t2_256,regB + arg mem_t0_256,regb + arg mem_t2_256,rega + arg mem_t7_256,contw + call bn_submod_256 /* n5=t7=n1-n3=t0-t2 W=U1-U0*/ + arg mem_t0_256,regA + arg mem_t2_256,regB + arg mem_t0_256,contw + call bn_addmod_256 /* n7=t0=n1+n3=t0+t2 T=U1+U0 */ +// arg mem_t1_256,regA +// arg mem_t3_256,regB + arg mem_t1_256,regb + arg mem_t3_256,rega + arg mem_t2_256,contw + call bn_submod_256 /* n6=t2=n2-n4=t1-t3 S1-S0 */ + arg mem_t1_256,regA + arg mem_t3_256,regB + arg mem_t1_256,contw + call bn_addmod_256 /* n8=t1=n2+n4=t1+t3 M=S1+S0*/ + arg mem_t1_256,regA + arg mem_t7_256,regB + arg mem_t1_256,contw + call bn_mulmod_256 /* t1=n8*n5 MW */ + arg mem_cz_256,regA + arg mem_az_256,regB + arg mem_t3_256,contw + call bn_mulmod_256 //Z0Z1 + arg mem_t3_256,regA + arg mem_t7_256,regB + arg mem_cz_256,contw + call bn_mulmod_256 /* z=za*zb*n5 Z0Z1W */ + + arg mem_t7_256,regA + arg mem_t7_256,contw + call bn_sqrmod_256 /* t7=n5^2 */ + arg mem_t7_256,regA + arg mem_t0_256,regB + arg mem_t3_256,contw + call bn_mulmod_256 /* t3=n5^2*n7 */ + arg mem_t7_256,regA + arg mem_t1_256,regB + arg mem_t1_256,contw + call bn_mulmod_256 /* t1=n8*n5^3 */ + arg mem_t2_256,regA + arg mem_cx_256,contw + call bn_sqrmod_256 + arg mem_cx_256,regA + arg mem_t3_256,regB + arg mem_cx_256,contw + call bn_submod_256 /* x=n6^2-n5^2*n7 */ + arg mem_cx_256,contr + arg mem_t7_256,contw + call memcpy32 + arg mem_t7_256,regA + call bn_lshiftmod_256 /* t7=2*x */ + arg mem_t3_256,regA + arg mem_t7_256,regB + arg mem_t3_256,contw + call bn_submod_256 /* t3=n9 */ + arg mem_t3_256,regA + arg mem_t2_256,regB + arg mem_t2_256,contw + call bn_mulmod_256 /* t2=n9*n6 */ + arg mem_t2_256,regA + arg mem_t1_256,regB + arg mem_cy_256,contw + call bn_submod_256 + arg mem_cy_256,regA + arg mem_p_256,regB + arg mem_cy_256,contw + force 0,regC + fetch 1,mem_cy_256 + isolate1 0,pdata + call bn_add_256,true + copy regC,alarm + arg mem_cy_256,regA + call bn_rshift_256 + fetch 1,mem_cy5_256 + isolate1 0,alarm + setflag true,7,pdata + store 1,mem_cy5_256 + rtn + +bn_invmod_256: + copy contw,timeup + arg mem_tmp0_256,contw + call clear_mem_256 + force 0,pdata +// store 4,mem_tmp52 + store 4,mem_t2_256 + jam 1,mem_tmp0_256 //y1 + arg mem_tmp1_256,contw //y2 + call clear_mem_512 + arg mem_p_256,contr + arg mem_tmp2_256,contw //j + call memcpy32 + copy regA,contr + arg mem_tmp3_256,contw //i + call memcpy32 + +// arg mem_tmp22,regA +// arg mem_tmp32,regB +// call p_bn_bigeq_256 +// branch assert,positive +bn_invmod_256_2: + arg mem_tmp3_256,contr + call bn_eq_zero_256 + branch bn_invmod_256_0,blank +//call ice_break +//fetch 1,0x4ffe +//increase 1,pdata +//store 1,0x4ffe + arg mem_tmp3_256,regA + arg mem_tmp0_256,regB + call bn_rshifteven_256 + arg mem_tmp2_256,regA + arg mem_tmp1_256,regB + call bn_rshifteven_256 + + arg mem_tmp3_256,regA + arg mem_tmp2_256,regB + call bn_bigeq_256 + branch bn_invmod_256_1,positive + arg mem_tmp2_256,regA + arg mem_tmp3_256,regB + copy regA,contw + call bn_sub_256 + arg mem_tmp0_256,regA + arg mem_tmp1_256,regB + copy regB,contw + call bn_add_256 + ifetch 1,regA + iadd regC,regC + ifetch 1,regB + iadd regC,pdata + istore 1,regB + branch bn_invmod_256_2 +bn_invmod_256_1: + arg mem_tmp3_256,regA + arg mem_tmp2_256,regB + copy regA,contw + call bn_sub_256 + arg mem_tmp1_256,regA + arg mem_tmp0_256,regB + copy regB,contw + call bn_add_256 + ifetch 1,regA + iadd regC,regC + ifetch 1,regB + iadd regC,pdata + istore 1,regB + branch bn_invmod_256_2 +bn_invmod_256_0: +//call ice_break + arg mem_tmp1_256,regA + copy timeup,contw + call bn_p256mod +//call ice_break + arg mem_p_256,regA + copy timeup,regB + copy timeup,contw + branch bn_submod_256 + + +bn_mulmod_256: + copy contw,timeup /* save result ptr */ + + force 0,regext_index + + arg mem_tmp1_256,contw + call clear_mem_512 + arg mem_regext,contw + call clear_mem_512 +// jam 0,mem_regext_index + +// arg mem_tmp12,contw + copy regA,contr +// force 0,regext_index + jam 0,mem_regext + setarg 0 + call bn_load_mem + copy regB,contr + call bn_load_256 +// force 0,regB +// jam 0,mem_regb + force 0,queue + arg mem_tmp1_256,contw +bn_mulmod_256_1: +// copy regb,pdata +// store 1, + arg mem_regext,temp + copy queue,regb + lshift2 regb,pdata +// lshift4 pdata,pdata + iadd temp,regb + force 0,temp + force 0,regC +bn_mulmod_256_0: +// copy contw,pdata +// store 2,mem_contw +//call ice_break +// copy pdata,contw + ifetch 4,contw /* d[i+j] */ + iforce regA +// copy regB,regext_index +// deposit regext + ifetch 4,regb + copy regC,regext_index + imul32 regext,pdata + iadd regA,pdata /* uv = a[i]*b[j] + d[i+j] */ + iadd temp,pdata /* uv += u */ + istore 4,contw /* ->d[i+j] */ + rshift32 pdata,temp /* temp = u = uv >> 32 */ + increase 1,regC + compare 8,regC,0xff + nbranch bn_mulmod_256_0,true +//call ice_break + deposit temp + istore 4,contw /* d[i + 12] = u */ + increase -32,contw +// fetch 1,mem_regb +// copy pdata,regb + increase 1,queue + compare 8,queue,0xff + nbranch bn_mulmod_256_1,true + arg mem_tmp1_256,regA + copy timeup,contw + branch bn_p256mod + +bn_p256mod: + bpatchx patch35_6,mem_patch35 + copy contw,timeup /* save result ptr */ + copy regA,alarm /* temp save regA */ + arg mem_tmp2_256,regB + copy regB,contw + call memset0_4 + istore 8,contw + add regA,44,contr + call memcpy8 + call memcpy12 + copy regb,rega + call bn_lshiftmod_256 //2S1 + arg mem_tmp2_256,regB + copy alarm,rega + copy timeup,contw + call bn_addmod_256 //T+2S1 +//call ice_break + arg mem_tmp2_256,regB + copy regB,contw + call memset0_4 + istore 8,contw + add alarm,48,contr + call memcpy16 + call memset0_4 + copy regb,rega + call bn_lshiftmod_256 //2S2 +//call ice_break +// arg 0,regB + + arg mem_tmp2_256,regB + copy timeup,rega + copy regA,contw + call bn_addmod_256 //+2S2 +//call ice_break +// arg 0,regB + + arg mem_tmp2_256,regB + copy regB,contw + add alarm,32,contr + call memcpy12 + call memset0_4 + istore 8,contw + add alarm,56,contr + call memcpy8 + copy timeup,regA + copy regA,contw + call bn_addmod_256 //+S3 +//call ice_break +// arg 0,regB + + arg mem_tmp2_256,regB + copy regB,contw + add alarm,36,contr + call memcpy12 + add alarm,52,contr + call memcpy12 + add alarm,52,contr + call memcpy4 + add alarm,32,contr + call memcpy4 + copy timeup,regA + copy regA,contw + call bn_addmod_256 //+S4 +//call ice_break +// arg 1,regB + arg mem_tmp2_256,regB + copy regB,contw + add alarm,44,contr + call memcpy12 + call memset0_4 + istore 8,contw + add alarm,32,contr + call memcpy4 + add alarm,40,contr + call memcpy4 + copy timeup,regA + copy regA,contw + call bn_submod_256 //-D1 +//call ice_break +// arg 2,regB + arg mem_tmp2_256,regB + copy regB,contw + add alarm,48,contr + call memcpy8 + call memcpy8 + force 0,pdata + istore 8,contw + add alarm,36,contr + call memcpy4 + add alarm,44,contr + call memcpy4 + copy timeup,regA + copy regA,contw + call bn_submod_256 //-D2 +//call ice_break +// arg 3,regB + arg mem_tmp2_256,regB + copy regB,contw + add alarm,52,contr + call memcpy12 + add alarm,32,contr + call memcpy12 + call memset0_4 + add alarm,48,contr + call memcpy4 + copy timeup,regA + copy regA,contw + call bn_submod_256 //-D3 +//call ice_break +// arg 4,regB + arg mem_tmp2_256,regB + copy regB,contw + add alarm,56,contr + call memcpy8 + call memset0_4 + add alarm,36,contr + call memcpy12 + call memset0_4 + add alarm,52,contr + call memcpy4 + copy timeup,regA + copy regA,contw + branch bn_submod_256 //-D4 + + +bn_load_mem: + force 32,loopcnt + arg mem_regext,contw + iadd contw,contw + branch memcpy + +bn_load_256: + force 8,loopcnt + branch bn_load_0 + +bn_sqrmod_256: + copy regA,regB + branch bn_mulmod_256 + +bn_add_256: + force 8,loopcnt + branch bn_add+1 + +bn_addmod_256: + call bn_add_256 + copy contw,regA + branch bn_lshiftmod_ismod_256 + +bn_lshiftmod_256: + call bn_lshift_256 +bn_lshiftmod_ismod_256: + isolate1 0,regC + branch bn_lshiftmod_p_256,true + arg mem_p_256,regB + copy regA,regC + increase -32,regA + call bn_bigeq_256 + nrtn positive + copy regC,regA + branch sub_p2_256 + +bn_lshiftmod_p_256: + call sub_p2_256 +// nrtn true + copy regA,regC + increase -32,regA + arg mem_p_256,regB + call bn_bigeq_256 + nrtn positive + copy regC,regA + branch sub_p2_256 + + +sub_p2_256: + increase -32,regA + arg mem_p_256,regB + copy regA,contw + branch bn_sub_256 + + + + +bn_submod_256: + call bn_sub_256 +// isolate1 0,regC + branch bn_submod_256_np,true +// copy regA,regC +// increase -32,regA + add contw,-32,regA + arg mem_p_256,regB + call bn_bigeq_256 + nrtn positive + arg mem_p_256,regB + add contw,-32,regA +// copy regC,regA + copy rega,contw + branch bn_sub_256 +bn_submod_256_np: + add contw,-32,regA + arg mem_p_256,regB + copy regA,contw + call bn_add_256 +// isolate1 0,regC + rtn true + add contw,-32,regA + arg mem_p_256,regB + copy regA,contw + branch bn_add_256 + + + +bn_sub_256: + force 8,loopcnt + branch bn_sub+1 + +bn_rshift_256: + force 8,loopcnt + increase 28,regA + branch bn_rshift + +bn_lshift_256: + force 8,loopcnt + force 0,regC + branch bn_lshift_0 + +bn_bigeq_256: + force 8,loopcnt + increase 28,regA + increase 28,regB + branch bn_bigeq_0 + + +bn_eq_zero_256: + ifetch 8,contr + nrtn blank + branch bn_eq_zero + + + + +bn_rshifteven_256: + copy regA,alarm +bn_rshifteven_256_1: + copy alarm,regA + ifetch 1,regA + isolate1 0,pdata + rtn true + call bn_rshift_256 + ifetch 1,regB + isolate0 0,pdata + branch bn_rshifteven_256_0,true + arg mem_p_256,regA + copy regB,contw + call bn_add_256 + ifetch 1,regB + iadd regC,pdata + istore 1,regB + increase -32,regB +bn_rshifteven_256_0: + add regB,32,regA + force 9,loopcnt + call bn_rshift + branch bn_rshifteven_256_1 + +else +sp_initialize_256: + rtn + +endif + + Index: tag/Soft/Librarier/bt_rom/program/tws_m.prog =================================================================== --- /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/tws_m.prog (nonexistent) +++ /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/tws_m.prog (working copy) @@ -0,0 +1,1588 @@ +tws_pairing: + call le_enable + call tws_pairing_work + call le_disable + rtn + + +tws_pairing_work: + bpatchx patch35_7,mem_patch35 + //fix BT 168 + fetch 1,mem_sco_rx_packet_len + bne 30,tws_pairing_state_check + rtnmark1 mark_sco_flag +tws_pairing_state_check: + //fetch 1,mem_pwr_state + //rtnne DEVICE_POWER_ON + fetch 1,mem_tws_state + beq TWS_STATE_PAIRING,tws_recon_remote_work_adv_and_scan + beq TWS_STATE_WAIT_MASTER,tws_s_wait_connecting // slave work only scan + beq TWS_STATE_SLAVE_SWITCH_LISTEN,tws_s_wait_connecting // slave work only scan + beq TWS_STATE_WAIT_SLAVE,tws_recon_remote_work_adv_and_scan + beq TWS_STATE_MASTER_LISTEN,tws_recon_remote_work_adv + rtn +tws_recon_remote_work_adv_and_scan: + bpatchx patch36_0,mem_patch36 + // set flag + //arg LOG_POINT_1300,rega + //fetcht 1,mem_tws_state + //call debug_log_print + + // Check connection + call bt_check_have_classic_link_in_connecting + branch tws_recon_remote_work_adv,user +tws_recon_remote_work_scan: + call tws_s_wait_connecting +tws_recon_remote_work_adv: + branch tws_m_wait_connecting + +// In sco, only transaction packet, do nothing +tws_handle_sco: + call tws_remind_crc_failed_flag + call tws_update_local_packet_rcv_flag + fetch 1,mem_tws_state + beq TWS_STATE_MASTER_CONNECTED,tws_wait_ack_process + beq TWS_STATE_MASTER_LISTEN,tws_wait_ack_process + beq TWS_STATE_SLAVE_CONNECTED,tws_send_ack_process + rtn + +tws_handle_poll: + bpatchx patch36_1,mem_patch36 + call tws_remind_crc_failed_flag + call tws_update_local_packet_rcv_flag + fetch 1,mem_tws_state + beq TWS_STATE_MASTER_CONNECTED,tws_handle_poll_master + beq TWS_STATE_MASTER_LISTEN,tws_handle_poll_master + beq TWS_STATE_SLAVE_CONNECTED,tws_send_ack_process + rtn +tws_handle_poll_master: + fetch 1,mem_tws_poll_null_ack_interval_count + nbranch tws_decrease_ack_interval, blank + fetch 1,mem_tws_poll_null_ack_interval + store 1,mem_tws_poll_null_ack_interval_count + branch tws_wait_ack_process +tws_decrease_ack_interval: + increase -1,pdata + store 1,mem_tws_poll_null_ack_interval_count + rtn + +tws_m_rcv_info_request_check: + enable user + + fetch 6,mem_le_rxbuf+8 // RemoteAddr + fetcht 6,mem_local_bdaddr + isub temp,null + nbranch disable_user,zero + + fetch 6,mem_le_rxbuf+2 // LocalAddr + fetcht 6,mem_tws_last_paired_lap + isub temp,null + rtn zero + + fetch 1,mem_tws_allow_pairing + branch disable_user,blank + + fetch 1,mem_le_rxbuf + and pdata,0x0f,pdata + bne SCAN_REQ,disable_user + + fetch 6,mem_le_rxbuf+2 // LocalAddr + store 6,mem_tws_last_paired_lap + rtn + +tws_m_update_adv_interval: + call tws_m_select_adv_interval + store 2,mem_le_tws_adv_interval + rtn + + +tws_m_select_adv_interval: + fetch 1,mem_tws_state + beq TWS_STATE_MASTER_LISTEN,tws_m_select_adv_interval_master_listen + fetch 2,mem_param_le_tws_adv_interval_normal + rtn + +tws_m_select_adv_interval_master_listen: + fetch 2,mem_param_le_tws_adv_interval_master_listen + rtn + +tws_m_wait_connecting: + bpatchx patch36_2,mem_patch36 + arg le_tws_adv_interval_timer,queue + call timer_check + nrtn blank + call tws_m_update_adv_interval + + arg LOG_POINT_1304,rega + fetcht 1,mem_tws_state + call debug_log_print + // set flag + arg LOG_POINT_1305,rega + fetcht 2,mem_le_tws_adv_interval + call debug_log_print + + call calc_clke + call tws_set_master_slot + enable swfine + fetch 1,mem_le_adv_transmit + increase 1,pdata + store 1,mem_le_adv_transmit + call tws_reset_connecting + call le_init_adv + call tws_select_le_channel + call tws_send_connecting_info + jam TWS_CONNECTING_PHASE1,mem_tws_connecting_phase +tws_m_wait_for_match: + nbranch tws_send_info_not_match,match + + call tws_m_rcv_info_request_check + nbranch tws_send_info_not_match,user + + // set flag + arg LOG_POINT_1308,rega + fetcht 1,mem_tws_connecting_phase + call debug_log_print + +tws_m_wait_for_match_continue: + bpatchx patch36_3,mem_patch36 + + // No connect transaction + fetch 1,mem_tws_no_connect_cmd + nbranch tws_clear_send_no_connect_trans_command,blank + + fetch 1,mem_tws_connecting_phase + beq TWS_CONNECTING_PHASE1,tws_send_context_info_keymap + beq TWS_CONNECTING_PHASE2,tws_send_context_info_sub0//context 30 + beq TWS_CONNECTING_PHASE3,tws_send_context_info_sub1 //context 30 + beq TWS_CONNECTING_PHASE4,tws_send_context_info_sub2 //context 30 + beq TWS_CONNECTING_PHASE5,tws_send_afh_info //context 30 + beq TWS_CONNECTING_PHASE6,tws_send_sco_info //context 30 + beq TWS_CONNECTING_PHASE7,tws_send_a2dp_info //context 30 + beq TWS_CONNECTING_PHASE8,tws_send_context_info_phase_end ////context 30 + branch tws_reset_connecting +tws_send_info_not_match: + bpatchx patch36_4,mem_patch36 + call tws_reset_connecting + fetch 1,mem_tws_adv_count + increase 1,pdata + store 1,mem_tws_adv_count + bmark1 mark_sco_flag,tws_send_info_not_match_end + nop 1000 + sub pdata,4,null + branch tws_m_wait_connecting,positive + jam 0,mem_tws_adv_count +tws_send_info_not_match_end: + arg le_tws_adv_interval_timer,queue//change adv interval to diffault to iphone frame + fetch 2,mem_le_tws_adv_interval + branch timer_init + + +tws_send_context_info_keymap: + fetch 1,mem_tws_state + beq TWS_STATE_PAIRING,tws_slave_is_found + fetch 1,mem_tws_profile_connected + branch tws_send_slave_found_event,blank + deposit mark + store 8,mem_mark_load + jam TWS_CONNECTING_PHASE2,mem_tws_connecting_phase + call tws_set_send_context_header + setarg 0xff1b + istore 2,contw + arg mem_link_key,contr + force 16,loopcnt + call memcpy + arg mem_afh_classify_channel_map,contr + force 10,loopcnt + call memcpy + disable match + call tws_transmit_receive_sifs + branch tws_m_wait_for_match + + +tws_send_context_info_phase_end: + bpatchx patch36_5,mem_patch36 + call tws_send_context_info_phase + force 30,loopcnt + arg mem_l2cap_active_ch_count,contr + call memcpy + force 4,loopcnt + arg mem_avdtp_xmem_start,contr + call memcpy + force 19,loopcnt + arg mem_xmem_hf_state_start,contr + call memcpy + jam 60,mem_le_txlen +tws_send_context_info_phase_end_continue: + disable match + call tws_transmit_receive_sifs + call tws_reset_connecting + + call tws_init_all + jam TWS_STATE_MASTER_LISTEN,mem_tws_state + fetch 1,mem_param_tws_master_wait_slave_timeout + store 1,mem_tws_master_wait_slave_timeout_timer + + rtn + +tws_send_context_info_phase: + bpatchx patch36_6,mem_patch36 + call tws_set_send_context_header + fetcht 1,mem_tws_connecting_phase + istoret 1,contw + setarg mem_state + rtn + +tws_set_send_context_header: + arg SCAN_RSP,temp + set0 LE_SENDER_ADDR_BIT,temp + storet 1,mem_le_txheader + setarg 37 + store 1,mem_le_txlen + fetch 6,mem_tws_bdaddr + store 6,mem_le_txpayload + rtn + +tws_set_master_slot: + bpatchx patch36_7,mem_patch36 + arg 0x79e,timeup +tws_set_master_clk11: + until clke_rt,meet + copy clke_bt,temp + compare 3,temp,3 + nbranch tws_set_master_clk11,true + copy temp,timeup + increase 1,timeup + storer timeup,4,mem_tws_sync_clk + rtn + +tws_select_le_channel: + bpatchx patch37_0,mem_patch37 + fetch 1,mem_tws_state + beq TWS_STATE_MASTER_LISTEN,tws_select_le_channel_end + beq TWS_STATE_SLAVE_LISTEN,tws_select_le_channel_end + call tws_update_le_channel_index +tws_select_le_channel_end: + call tws_get_le_channel_by_index + rtn + +tws_update_le_channel_index: + fetch 1,mem_tws_last_send_channel_index + call tws_select_le_channel_index_loopback + store 1,mem_tws_last_send_channel_index + rtn + +tws_get_le_channel_by_index: + fetch 1,mem_tws_last_send_channel_index + arg mem_param_tws_send_channel_array,contr + iadd contr,contr + ifetch 1,contr + store 1,mem_le_ch_mapped + rtn + +tws_select_le_channel_index_loopback: + increase 1,pdata + sub pdata,3,null + rtn positive + branch setarg0 + +tws_set_first_packet_dynamic_buffer: + bpatchx patch37_1,mem_patch37 + jam 26,mem_le_txlen // This length change must be-careful + + // Status bit + setarg 0 + fetcht 1,mem_tws_allow_pairing + compare 0x01,temp,0xff + setflag true,TWS_PACKET_STATUS_BIT_PAIRING,pdata + + fetcht 1,mem_hsp_role + compare 0x01,temp,0xff + setflag true,TWS_PACKET_STATUS_BIT_HSP_ROLE,pdata + + store 2,mem_tws_first_packet_dynamic_buffer_status + + // Local bdaddr + fetch 6,mem_local_bdaddr // use tws pair + store 6,mem_tws_first_packet_dynamic_buffer_local_bdaddr + + // Remote bdaddr + fetch 6,mem_tws_last_paired_lap // use tws pair + store 6,mem_tws_first_packet_dynamic_buffer_paired_bdaddr + + rtn + +tws_send_recon_adv: + bpatchx patch37_2,mem_patch37 + arg TWS_BLE_ADV_FLAG_POWER_ON,temp + fetch 1,mem_tws_state + beq TWS_STATE_PAIRING,tws_send_recon_adv_set_flag +tws_send_recon_adv_set_flag_master: + arg TWS_BLE_ADV_FLAG_NO_CONNECTED,temp//send arbiter noconnect adv +tws_send_recon_adv_set_flag: + branch tws_send_connecting_info_header + +tws_send_no_connect_trans_info_reach_limit: + call tws_clear_send_no_connect_trans_command + branch tws_send_connecting_info_1 + +tws_send_no_connect_trans_info: + bpatchx patch37_3,mem_patch37 + fetch 1,mem_tws_no_connect_cmd_trans_limit + branch tws_send_no_connect_trans_info_reach_limit,blank + pincrease -1 + store 1,mem_tws_no_connect_cmd_trans_limit + + jam 21,mem_le_txlen // This length change must be-careful + + arg TWS_BLE_ADV_FLAG_TRANS,temp + + jam 0,mem_le_txheader + + fetch 6,mem_tws_bdaddr + store 6,mem_le_txpayload + + // Flag + istoret 2,contw + + // The remote + fetch 6,mem_local_bdaddr + istore 6,contw + fetch 6,mem_tws_last_paired_lap + istore 6,contw + + fetch 1,mem_tws_no_connect_cmd + istore 1,contw + + branch tws_send_connecting_info_header_end + +tws_send_connecting_info: + bpatchx patch37_4,mem_patch37 + + // set flag + arg LOG_POINT_1306,rega + fetcht 1,mem_tws_state + call debug_log_print + + fetch 1,mem_tws_no_connect_cmd + nbranch tws_send_no_connect_trans_info,blank + +tws_send_connecting_info_1: + // clear no connect info + jam 0,mem_tws_no_connect_cmd + fetch 1,mem_tws_state + beq TWS_STATE_PAIRING, tws_send_recon_adv + beq TWS_STATE_WAIT_MASTER, tws_send_recon_adv + + // Check link is already + fetch 1,mem_tws_profile_connected + branch tws_send_recon_adv,blank + //fetch 1,mem_tws_profile_disconnected_after_connected + //nbranch p_tws_send_recon_adv,blank + fetch 1,mem_l2cap_active_ch_count + sub pdata,4,temp //Because we only allow 4 channel to work, becareful the last one channel info lost one byte + nbranch tws_send_recon_adv,positive + //nrtn positive + // set flag + arg TWS_BLE_ADV_FLAG_CONNECTED,temp + +tws_send_connecting_info_header: + bpatchx patch37_5,mem_patch37 + // Print log + copy temp,regb + // set flag + arg LOG_POINT_1307,rega + call debug_log_print + copy regb,temp + + jam 0,mem_le_txheader + + fetch 6,mem_tws_bdaddr + store 6,mem_le_txpayload + + // Flag + istoret 2,contw + + fetch 4,mem_tws_sync_clk + istore 4,contw + + // Becouse first packet is very important, so we need prepare data outside + // Set the dynamic buffer + call tws_set_first_packet_dynamic_buffer + + arg mem_le_txpayload+12,contw + arg mem_tws_first_packet_dynamic_buffer,contr + force 20,loopcnt + call memcpy + +tws_send_connecting_info_header_end: + enable swfine + arg 1800,stop_watch + disable match + branch tws_transmit_receive_sifs + +tws_reset_connecting: + jam 0,mem_tws_connecting_phase + rtn + +// input temp: freq index +tws_set_rcv_rf: + bpatchx patch37_6,mem_patch37 + storet 1,mem_temp_rf_freq_index//stroe freq index + // we should set start rf anchor time, becouse double size may have different time + enable swfine + fetch 2,mem_tws_rf_start_anchor + fetcht 2,mem_tws_rf_rcv_window_size + isub temp,stop_watch + + call set_sync_on + fetch 1,mem_sfreq_enable + nbranch tws_set_rcv_rf_after_set_freq,blank + fetcht 1,mem_temp_rf_freq_index + call set_freq_rx // in some freq, no need do this +tws_set_rcv_rf_after_set_freq: + call start_receiver + + until null,timeout // use for start anchor + + call tws_clear_rcv_op + + enable decode_fec0 + enable swfine + fetch 2,mem_tws_rf_packet_rx_window_size + copy pdata,stop_watch + correlate null,timeout + disable decode_fec0 + rtn + +tws_set_need_send_header: + jam 1,mem_tws_is_need_send_header + rtn +tws_clear_need_send_header: + jam 0,mem_tws_is_need_send_header + rtn + +// input temp: freq index +tws_set_send_rf: + bpatchx patch37_7,mem_patch37 + fetch 1,mem_tx_power + store 1,mem_temp_tx_power + fetch 1,mem_param_tws_tx_power + store 1,mem_tx_power +tws_set_send_rf_common: + storet 1,mem_temp_rf_freq_index//stroe freq index + enable swfine + fetcht 2,mem_tws_rf_start_anchor + copy temp,stop_watch + + call set_sync_on + call tws_set_send_rf_freq + until null,timeout // use for start anchor + + fetch 1,mem_tws_is_slave_send + branch tws_set_send_rf_transmit,blank + fetch 1,mem_tws_is_need_send_header + ncall tws_slave_send_full_packet_delay,blank + + fetch 1,mem_tws_is_need_send_header + call tws_slave_tx_id,blank +tws_set_send_rf_transmit: + call start_transmitter + call send_access_word + + fetch 1,mem_tws_is_need_send_header + branch tws_set_send_rf_end,blank + + call tws_transmit_packet +tws_set_send_rf_end: + fetch 1,mem_temp_tx_power + store 1,mem_tx_power + + branch tws_end_of_packet + +tws_slave_send_full_packet_delay: + fetch 2,mem_tws_rf_slave_send_full_packet_sleep_time + call sleep + rtn + +tws_slave_tx_id: + // set flag + arg LOG_POINT_1313,rega + fetcht 1,mem_tws_state + call debug_log_print + rtn + + +tws_set_send_rf_freq: + bpatchx patch38_0,mem_patch38 + fetch 1,mem_sfreq_enable + nbranch tws_set_send_rf_freq_tx_enable,blank + fetcht 1,mem_temp_rf_freq_index + branch set_freq_tx +tws_set_send_rf_freq_tx_enable: + branch rf_tx_enable + +tws_m_receive_spec_packet: + bpatchx patch38_1,mem_patch38 + // Check rcv ack time + copy stop_watch,temp + fetch 2,mem_tws_rf_master_check_raw_id_time + isub temp,null + nbranch tws_m_receive_raw_id,positive + call tws_receive_packet_header + call rf_debug_active_crc_error_line,crc_failed + rtn crc_failed + call tws_receive_packet_header_handle + rtn crc_failed +tws_m_send_packet: + call tws_send_payload_check + nrtn user + + fetch 2,mem_tws_count_poll + increase 1,pdata + store 2,mem_tws_count_poll + call tws_end_of_packet + jam 0,mem_tws_is_slave_send + call tws_set_need_send_header + call tws_set_ack_access + fetcht 1,mem_last_freq + branch tws_set_send_rf + + +tws_m_receive_raw_id: + // set flag + arg LOG_POINT_1312,rega + fetcht 1,mem_tws_state + call debug_log_print + branch tws_m_send_packet + + +tws_clear_rcv_op: + jam 0,mem_tws_rcv_op + rtn + +tws_send_payload_check: + bpatchx patch38_2,mem_patch38 + enable user + fetch 1,mem_tws_snd_op + nrtn blank + fetcht 1,mem_tws_rcv_op + and temp,0x7f,pdata + nrtn blank + fetch 5,mem_tws_cmd_fifo + nrtn blank + branch disable_user + +tws_receive_packet_header_handle: + bpatchx patch38_3,mem_patch38 + // Check need or not to receive payload + call tws_receive_packet_payload_check + call rf_debug_active_crc_error_line,crc_failed + rtn crc_failed + disable user2 + call tws_update_local_arqn + fetcht 1,mem_tws_rcv_op + and temp,0x7f,pdata + nbranch tws_handle_command,blank + rtn +tws_handle_command: + isolate1 7,temp + setarg 0 + nsetflag true,0,pdata + store 1,mem_tws_snd_op_nextseq + // forbit same packet send twice + fetch 1,mem_tws_rcv_old_seq + isub temp,null + rtn zero + storet 1,mem_tws_rcv_old_seq + and temp,0x7f,pdata + store 1,mem_fifo_temp + +tws_handle_command_cont: + bpatchx patch38_4,mem_patch38 + fetch 1,mem_fifo_temp + beq TWS_SYNC_EVT_MASTER_SWITCH,tws_handle_command_sync_evt_master_switch + + beq TWS_SYNC_EVT_DROP_ONE_PACKET,a2dp_media_buffer_drop_packet_action + beq TWS_SYNC_EVT_ADD_ONE_PACKET,a2dp_media_buffer_add_packet_action + + beq TWS_SYNC_EVT_HFP_START_SYNC,tws_sync_evt_reset_hfp_audio + + branch ipc_tx_tws_event + +tws_handle_command_sync_evt_master_switch: + jam 1,mem_tws_role_switch_in_process + call rf_debug_active_crc_error_line + branch tws_m2s_timeout_refresh + + +tws_update_local_arqn: + fetch 1,mem_tws_snd_cur_arq + rtnbit0 wack + fetcht 1,mem_tws_rcv_op_nextseq + isolate1 seqn,pdata + sub temp,1,null + branch tws_update_local_arqn_0,true + sub temp,0,null +tws_update_local_arqn_0: + rtn zero + //jam 0,mem_tws_snd_op + call tws_clear_sent_cmd + fetch 1,mem_tws_snd_cur_arq + set0 wack,pdata + setflip seqn,pdata + store 1,mem_tws_snd_cur_arq + rtn + +tws_receive_packet_header: + rshift bt_clk,temp + or temp,0x40,white_init + enable enable_white + enable enable_hec + enable decode_fec1 + parse demod,bucket,10 + rshift pwindow,pdata + store 2,mem_tws_rcv_op + parse demod,bucket,8 + disable decode_fec1 + disable enable_hec + rtn +tws_receive_packet_payload_check: + bpatchx patch38_5,mem_patch38 + // set flag + arg LOG_POINT_1311,rega + //fetcht 2,clke + fetcht 2,mem_tws_rcv_op + call debug_log_print + + fetcht 1,mem_tws_rcv_op + and temp,0x7f,pdata + + beq TWS_SYNC_EVT_MASTER_SWITCH,tws_receive_master_switch + beq TWS_SYNC_EVT_AUDIO_PROCESS_INFO,tws_receive_audio_process_info + beq TWS_SYNC_EVT_HFP_START_SYNC,tws_receive_hfp_start_sync + rtn + +tws_receive_audio_process_info: + arg 11,loopcnt + arg mem_process_sync_receive_buffer,contw //lmp_data or test packet + branch tws_receive_packet_payload + +tws_receive_master_switch: + arg 1,loopcnt + arg mem_tws_buffer_master_switch,contw + branch tws_receive_packet_payload + +tws_receive_hfp_start_sync: + arg 4,loopcnt + arg mem_hfp_start_sync_buffer,contw //lmp_data or test packet + branch tws_receive_packet_payload + +// input loopcnt -- packet length +// input contw -- packet buffer ptr +tws_receive_packet_payload: + enable decode_fec2 + enable encrypt + enable enable_crc +tws_process_payload_data: + parse demod,bucket,8 + rshift3 pwindow,pdata + istore 1,contw + loop tws_process_payload_data +tws_process_payload_data_end: + parse demod,bucket,16 /* cycle through the crc */ + rtn + + +tws_transmit_packet_prepare_hfp_start_sync_set_clk: + // do not cover clk overflow + //fetch 4,clke_bt + setarg 700// Becouse we transaction is base basic link, only we let master and slave can work base sco link + iadd clke_bt,pdata + store 4,mem_hfp_start_sync_clk + + branch tws_transmit_packet_header + +tws_transmit_packet: + fetch 1,mem_tws_snd_op + nbranch tws_transmit_packet_header,blank + //fetch 1,mem_tws_command + arg mem_tws_cmd_fifo,rega + call fifo_out + branch tws_transmit_packet_header,blank + fetcht 1,mem_tws_snd_cur_arq + set1 wack,temp + isolate1 seqn,temp + storet 1,mem_tws_snd_cur_arq + setflag true,7,pdata + store 1,mem_tws_snd_op + +tws_transmit_packet_prepare: + bpatchx patch38_6,mem_patch38 + fetch 1,mem_tws_snd_op + and pdata,0x7f,pdata + beq TWS_SYNC_EVT_HFP_START_SYNC,tws_transmit_packet_prepare_hfp_start_sync_set_clk +tws_transmit_packet_header: + rshift bt_clk,temp + or temp,0x40,white_init + enable enable_white + enable enable_hec + enable encode_fec1 + fetch 2,mem_tws_snd_op + inject mod,10 + enable enable_parity + inject mod,8 /* transmit parity */ + disable encode_fec1 + disable enable_parity + disable enable_hec + set0 PSK3M,radio_ctrl + +tws_transmit_packet_payload_check: + bpatchx patch38_7,mem_patch38 + // set flag + arg LOG_POINT_1310,rega + //fetcht 2,clke + fetcht 2,mem_tws_snd_op + call debug_log_print + + fetch 1,mem_tws_snd_op + and pdata,0x7f,pdata + + beq TWS_SYNC_EVT_MASTER_SWITCH,tws_transmit_packet_payload_master_switch + beq TWS_SYNC_EVT_AUDIO_PROCESS_INFO,tws_transmit_packet_payload_audio_process_info + beq TWS_SYNC_EVT_HFP_START_SYNC,tws_transmit_packet_payload_hfp_start_sync + rtn + +tws_transmit_packet_payload_master_switch: + arg 1,loopcnt + arg mem_tws_buffer_master_switch,contr + branch tws_transmit_packet_payload + +tws_transmit_packet_payload_audio_process_info: + arg 11,loopcnt + arg mem_process_sync_buffer,contr + branch tws_transmit_packet_payload + +tws_transmit_packet_payload_hfp_start_sync: + arg 4,loopcnt + arg mem_hfp_start_sync_buffer,contr + branch tws_transmit_packet_payload + +// input loopcnt -- packet length +// input contr -- packet buffer ptr +tws_transmit_packet_payload: + enable encode_fec2 + enable encrypt + enable enable_crc +tws_transmit_packet_payload_data_loop: + ifetch 1,contr + inject mod,8 + loop tws_transmit_packet_payload_data_loop +tws_transmit_packet_payload_data_end: + enable enable_parity + inject mod,16 + disable enable_parity + rtn + + + +tws_check_m_rcv_packet_success: + disable user + fetch 1,mem_tws_rcv_ack + rtn blank + fetch 1,mem_tws_local_rcv_packet + rtn blank + branch enable_user + +// use same freq, no do end of packet process +tws_end_of_packet: + disable encode_fec0 + disable encode_fec2 + disable decode_fec0 + disable decode_fec2 + disable enable_crc + disable encrypt + disable enable_white + branch tws_end_of_packet_0,is_rx + until null,tx_clear + nop 100 /* flush out the last bit */ +tws_end_of_packet_0: + call rf_shutdown_radio_for_debug + // For safe, need force 8 then change to 0 + force 8,radio_ctrl + force 0,radio_ctrl + rtn + +// rx switch to rx must do this +tws_rf_rx_switch_to_rx: + jam 0x20,rfen_mdm + jam 0xa0,rfen_mdm + rtn + +tws_m_check_role_switch_work: + disable user + fetch 1,mem_tws_role_switch_in_process + rtn blank + // set flag + arg LOG_POINT_1322,rega + fetcht 1,mem_tws_m2s_ack_send_timeout_count + call debug_log_print + call tws_check_m2s_timeout_reach + nrtn user + call tws_m_role_switch_success + branch enable_user + +tws_m_role_switch_success: + bpatchx patch39_0,mem_patch39 + // set flag + arg LOG_POINT_1323,rega + fetcht 1,mem_tws_m2s_ack_send_timeout_count + call debug_log_print + jam 0,mem_tws_role_switch_in_process + jam 0,mem_tws_m2s_ack_send_timeout_count + call tws_clear_connect_info + jam 0,mem_tws_poll_slave_timer + jam TWS_STATE_SLAVE_CONNECTED,mem_tws_state + jam TWS_SET_SLAVE,mem_tws_role + + call send_tws_master_switch_ipc_tx_event + + // If receive remote power off switch request + fetch 1,mem_tws_buffer_master_switch_reason + rtn blank + call tws_force_free_local_link + jam 0,mem_tws_buffer_master_switch_reason + branch send_tws_local_power_off_ipc_tx_event + +tws_wait_ack_process: + bpatchx patch39_1,mem_patch39 + call tws_rf_rx_switch_to_rx + call tws_end_of_packet + + call tws_m_check_need_rcv_slave_ack + nbranch tws_wait_ack_process_end,user + + call tws_m_check_role_switch_work + branch tws_not_rcv_ack_error,user + + call tws_set_ack_access + + fetcht 1,mem_last_freq + call tws_set_rcv_rf + + // Check rcv the ack + call rf_debug_active_sync_line,sync + nbranch tws_m_wait_ack_process_no_sync_check,sync //sync error need progress payload + + // rcv the sync + fetch 1,mem_param_tws_timeout_master + store 1,mem_tws_timeout_timer + call tws_master_connected + + call tws_m_update_rcv_slave_ack + + // self special packet transaction + call tws_m_receive_spec_packet + + bpatchx patch39_2,mem_patch39 + fetch 1,mem_tws_ack + increase 1,pdata + store 1,mem_tws_ack + + jam TWS_STATE_MASTER_CONNECTED,mem_tws_state + +tws_wait_ack_process_end: + bmark1 mark_old_packet,ack_payload + + fetch 1,mem_tws_last_rcv_phone_packet_crc_fail + nbranch tws_not_rcv_ack_error,blank + //nbranch error_payload_crc,blank +tws_rcv_ack_success: + fetch 1,mem_rx_type + beq type_poll,end_of_packet + beq type_null,end_of_packet + branch process_dmh_packet + + +tws_wait_ack_process_print_double_ack_info: + // set flag + arg LOG_POINT_2005,rega + fetcht 1,mem_rx_type + call debug_log_print + + // set flag + arg LOG_POINT_2006,rega + fetcht 2,mem_tws_last_rcv_phone_packet_crc_fail + call debug_log_print + + // set flag + arg LOG_POINT_2007,rega + fetcht 2,mem_tws_local_rcv_packet + call debug_log_print + rtn + +tws_m_check_need_rcv_slave_ack: + enable user + // in poll null, don't care remote ack or not, to make sure the new packet is right + fetch 1,mem_rx_type + rtneq type_poll + rtneq type_null + + fetch 1,mem_tws_rcv_ack + nbranch disable_user,blank + rtn + +tws_m_update_rcv_slave_ack: + // in poll null, don't care remote ack or not, to make sure the new packet is right + fetch 1,mem_rx_type + rtneq type_poll + rtneq type_null + + jam 1,mem_tws_rcv_ack + rtn + +tws_m_wait_ack_process_no_sync_check: + + branch tws_wait_ack_process_end + +tws_m_clear_rcv_ack_flag: + jam 0,mem_tws_rcv_ack + rtn +tws_m_set_rcv_ack_flag: + jam 1,mem_tws_rcv_ack + rtn + +tws_m_clear_last_send_ack_flag: + jam 0,mem_tws_last_send_ack + rtn +tws_m_set_last_send_ack_flag: + jam 1,mem_tws_last_send_ack + rtn + +tws_master_connected: + fetch 1,mem_tws_state + rtnne TWS_STATE_MASTER_LISTEN + + call tws_master_poll_slave_timer_refresh + branch tws_set_master_connected + + +tws_master_poll_slave_timer_refresh: + fetcht 1,mem_param_tws_poll_slave + fetch 1,mem_hf_call_state + beq HFP_NONO,tws_master_poll_slave_timer_refresh_end + lshift temp,temp +tws_master_poll_slave_timer_refresh_end: + storet 1,mem_tws_poll_slave_timer + rtn + +tws_set_master_connected: + //call clear_media_buffer + jam TWS_STATE_MASTER_CONNECTED ,mem_tws_state + jam TWS_SET_MASTER,mem_tws_role + jam 0,mem_tws_master_wait_slave_timeout_timer + jam TWS_EVT_MASTER_CONNECTED,mem_fifo_temp + branch ipc_tx_tws_event + +tws_not_rcv_ack_error: + bpatchx patch39_3,mem_patch39 + fetch 1,mem_rx_type + beq type_poll,end_of_packet + beq type_null,end_of_packet + branch error_payload_crc + +tws_set_ack_access: + force 0,uap + fetch 3,mem_tws_bdaddr + iforce lap + pulse recalc + nop 32 + rtn + + +tws_clear_connected_info: + call tws_clear_flag_state + call tws_init_all + rtn + + +tws_send_context_info_sub0: + arg 0,rega // context offset + arg 30,regb // length + branch tws_send_context_info_common + +tws_send_context_info_sub1: + arg 30,rega // context offset + arg 30,regb // length + branch tws_send_context_info_common + +tws_send_context_info_sub2: + arg 60,rega // context offset + arg 30,regb // length + branch tws_send_context_info_common + + +tws_send_afh_info: + call tws_send_context_info_phase + fetch 1,mem_hf_vlm_speaker + istore 1,contw + + fetch 1,mem_avctp_play_state + istore 1,contw + + fetch 2,mem_tws_remote_version + istore 2,contw + + force 26,loopcnt + arg mem_afh_cfg,contr + call memcpy + + branch tws_send_context_info_common_end + + +tws_send_sco_info: + call tws_send_context_info_phase + force 24,loopcnt + arg mem_xmem_sco_start,contr + call memcpy + + fetch 6,mem_lap + istore 6,contw + + branch tws_send_context_info_common_end + +tws_send_a2dp_info: + call tws_send_context_info_phase + force 21,loopcnt + arg mem_rfc_xmem_start,contr + call memcpy + + fetch 4,mem_avctp_xmem_start + istore 4,contw + fetch 3,mem_audio_src_endpoint + istore 3,contw + fetch 1,mem_a2dp_state + istore 1,contw + fetch 1,mem_conf_samplefreq_channelmode + istore 1,contw + branch tws_send_context_info_common_end + +// input +// rega context offset +// regb length +tws_send_context_info_common: + call tws_send_context_info_phase + iadd rega,contr + copy regb,loopcnt + call memcpy + +tws_send_context_info_common_end: + fetch 1,mem_tws_connecting_phase + increase 1,pdata + store 1,mem_tws_connecting_phase + + disable match + call tws_transmit_receive_sifs + branch tws_m_wait_for_match + + +tws_transmit_receive_sifs: + bpatchx patch39_4,mem_patch39 + call le_transmit +tws_transmit_receive_sifs_notx: + fetcht 1,mem_last_freq + call set_freq_rx + call rf_rx_enable + enable swfine + arg 5000,timeup // about 417us +tws_receive_rxon: + call le_prep + disable match + enable decode_fec0 + enable is_rx + disable is_tx + copy timeup,stop_watch + correlate null,timeout + nbranch end_of_packet,sync + nbranch tws_transmit_receive_sifs_end,user3 + arg param_clke_cal_le,clke_rt + force 0,clke_bt +tws_transmit_receive_sifs_end: + branch le_receive_skip + +tws_set_dynamic_freq: + fetcht 1,mem_last_freq + increase 5,temp + sub temp,78,null + rtn positive + copy temp,pdata + arg 78,temp + isub temp,temp + rtn + +tws_check_slave_anchor_pass_or_not: + disable user + deposit clke_bt + fetcht 4,mem_next_btclk + isub temp,pdata + nbranch enable_user,positive // clke_bt < mem_next_btclk means very early + branch enable_user,zero + // if clke_bt > mem_next_btclk, must diff is 1 + rtnne 1 /* missed slave slot */ + // Check clke_rt + fetcht 2,mem_param_rf_setup + increase -10,temp // add -10 to avoid clk pass + deposit clke_rt + isub temp,null + rtn positive // clk_rt is passed + branch enable_user + + +tws_slave_change_to_master: + jam LMP_PING_REQ,mem_lmo_opcode2 + branch tws_change_to_wait_tws_slave + +// Check slave error loss master link +tws_slave_loss_link_switch_polling: + arg mem_tws_slave_loss_link_listen_master_timeout_timer,regc + call timer_single_step + nrtn user + fetch 1,mem_tws_state + rtnne TWS_STATE_SLAVE_SWITCH_LISTEN + branch tws_slave_change_to_master + +tws_check_polling: + arg mem_tws_poll_slave_timer,regc + call timer_single_step + nrtn user + fetch 1,mem_tws_state + beq TWS_STATE_MASTER_CONNECTED,tws_master_polling_slave + rtn + +tws_slave_timeout_switch_to_master: + fetch 1,mem_tws_slave_wait_master_first_polling_flag + nbranch tws_force_free_local_link,blank + + fetch 1,mem_param_tws_slave_loss_link_listen_master_timeout + store 1,mem_tws_slave_loss_link_listen_master_timeout_timer + + call tws_clear_connect_info + branch tws_start_slave_switch_wait_work + +tws_check_observe_connecting: + fetch 1,mem_tws_state + rtnne TWS_STATE_WAIT_MASTER + arg mem_tws_observe_wait_connect_timeout_timer,regc + call timer_single_step + nrtn user + // If Observe wait connecting timer reached, change to arbiter, here for reduce code size + jam TWS_EVT_SLAVE_CHANGE_MASTER_NO_CON,mem_fifo_temp + branch tws_device_is_found + +tws_master_polling_slave: + call tws_master_poll_slave_timer_refresh + + jam TWS_SYNC_EVT_POLLING,mem_fifo_temp + // Check have other command need send + fetch 5,mem_tws_cmd_fifo + nrtn blank + branch tws_push_cmd_fifo + +tws_init_all: + // set flag + arg LOG_POINT_130F,rega + fetcht 1,mem_tws_state + call debug_log_print + call tws_init_all_timer + call tws_init_all_var + rtn + +tws_init_all_timer: + jam 0,mem_tws_timeout_timer + jam 0,mem_tws_observe_wait_connect_timeout_timer + jam 0,mem_tws_slave_loss_link_listen_master_timeout_timer + jam 0,mem_tws_poll_slave_timer + jam 0,mem_tws_master_wait_slave_timeout_timer + jam 0,mem_tws_m2s_ack_send_timeout_count + jam 0,mem_tws_poll_null_ack_interval_count + rtn +tws_init_all_var: + call tws_init_double_ack_var + call tws_init_role_switch_var + call tws_clear_snd_rcv_flag + call tws_clear_snd_cmd_fifo + call tws_clear_snd_no_connect_cmd + jam 0,mem_tws_buffer_master_switch_reason + rtn + +tws_init_double_ack_var: + jam 0,mem_tws_last_rcv_phone_packet_crc_fail + jam 0,mem_tws_rcv_ack + jam 0,mem_tws_local_rcv_packet + jam 0,mem_tws_last_send_ack + rtn + +tws_init_role_switch_var: + jam 0,mem_tws_role_switch_in_process + jam 0,mem_tws_slave_wait_master_first_polling_flag + rtn + + +tws_force_free_local_link: + //jam 0,mem_state // this is important + branch slave_disconnect + +tws_hp_evt_bb_disconnect: + bpatchx patch39_5,mem_patch39 + fetch 1,mem_tws_profile_connected + ncall tws_clear_connected_info,blank + + bmark1 mark_supervision_disconn, bt_abnormal_disc_rec + rtn + +bt_abnormal_disc_rec: + set0 mark_supervision_disconn,mark + jam BT_EVT_ABNORMAL_DISCONNECT,mem_fifo_temp + branch ipc_tx_bt_event + +tws_master_is_found: + jam TWS_EVT_MASTER_FOUND,mem_fifo_temp + branch tws_device_is_found +tws_slave_is_found: + jam TWS_EVT_SLAVE_FOUND,mem_fifo_temp +tws_device_is_found: + jam TWS_STATE_NONE,mem_tws_state + call tws_reset_connecting + branch ipc_tx_tws_event + +tws_send_master_found_event: + jam TWS_EVT_MASTER_FOUND,mem_fifo_temp + call tws_reset_connecting + branch ipc_tx_tws_event + +tws_send_slave_found_event: + jam TWS_EVT_SLAVE_FOUND,mem_fifo_temp + call tws_reset_connecting + branch ipc_tx_tws_event + + + +tws_start_recon_work: + fetch 6,mem_tws_bdaddr + branch tws_recon_fail,blank + + jam TWS_STATE_PAIRING,mem_tws_state + jam TWS_EVT_START_RECON,mem_fifo_temp + branch ipc_tx_tws_event + +tws_exit_work_state: + jam TWS_STATE_NONE,mem_tws_state + jam TWS_EVT_TWS_NONE,mem_fifo_temp + branch ipc_tx_tws_event + +tws_clear_sent_cmd: + bpatchx patch39_6,mem_patch39 + fetch 1,mem_tws_snd_op + jam 0,mem_tws_snd_op + and pdata,0x7f,pdata + beq TWS_SYNC_EVT_POWR_OFF,send_ipc_tx_event + beq TWS_SYNC_EVT_SLAVE_IN_STORAGE,send_ipc_tx_event + + beq TWS_SYNC_EVT_MASTER_SWITCH,tws_sync_evt_master_switch_sent_success + beq TWS_SYNC_EVT_SLAVE_ACK,tws_sync_evt_slave_ack_sent_success + + beq TWS_SYNC_EVT_ALL_PROFILE_DISCONNECTED,send_ipc_tx_event + beq TWS_SYNC_EVT_HFP_START_SYNC,tws_sync_evt_reset_hfp_audio + + beq TWS_SYNC_EVT_DROP_ONE_PACKET,a2dp_media_buffer_drop_packet_action + beq TWS_SYNC_EVT_ADD_ONE_PACKET,a2dp_media_buffer_add_packet_action + + rtn + +tws_sync_evt_reset_hfp_audio: + // Need check slave state, may be slave work error, need restart process + jam 1,mem_enable_hfp_start_sync + setarg TWS_SYNC_EVT_HFP_START_SYNC + branch send_ipc_tx_event + +tws_sync_evt_slave_ack_sent_success: + fetch 1,mem_tws_role_switch_in_process + rtn blank + fetch 1,mem_tws_m2s_ack_send_timeout_count + rtn blank + branch tws_s_role_switch_success + +send_tws_local_power_off_ipc_tx_event: + setarg TWS_EVT_LOCAL_POWER_OFF + branch send_ipc_tx_event + +send_tws_remote_power_off_ipc_tx_event: + setarg TWS_EVT_REMOTE_POWER_OFF + branch send_ipc_tx_event + +send_tws_master_switch_ipc_tx_event: + setarg TWS_SYNC_EVT_MASTER_SWITCH + branch send_ipc_tx_event + + +send_ipc_tx_event: + store 1,mem_fifo_temp + branch ipc_tx_tws_event + +tws_sync_evt_master_switch_sent_success: + call tws_m2s_timeout_refresh + rtn + +tws_m2s_timeout_refresh: + // set flag + arg LOG_POINT_1324,rega + fetcht 1,mem_tws_state + call debug_log_print + fetch 1,mem_param_tws_m2s_ack_send_timeout + store 1,mem_tws_m2s_ack_send_timeout_count + rtn +tws_check_m2s_timeout_reach: + disable user + fetch 1,mem_tws_m2s_ack_send_timeout_count + rtn blank + increase -1,pdata + store 1,mem_tws_m2s_ack_send_timeout_count + nrtn blank + branch enable_user + +send_tws_sync_cmd: + copy pdata,temp + bpatchx patch39_7,mem_patch39 + copy temp,pdata + beq TWS_SYNC_CMD_POWR_OFF,clear_tws_fifo + beq TWS_SYNC_CMD_MASTER_SWITCH,tws_master_switch_to_slave + beq TWS_SYNC_CMD_SLAVE_IN_STORAGE,clear_tws_fifo +send_tws_sync_cmd0: + //TWS_SYNC_CMD_START-TWS_SYNC_EVT_START=0x30 + arg 0x30,temp + isub temp,pdata + store 1,mem_fifo_temp +tws_push_cmd_fifo: + arg mem_tws_cmd_fifo,rega + branch fifo_in + +// only allow send one packet one time +send_tws_no_connect_trans_cmd: + copy pdata,temp + bpatchx patch3a_0,mem_patch3a + copy temp,pdata + //TWS_NO_CONNECT_TRANS_CMD_START-TWS_NO_CONNECT_TRANS_EVT_START=0x50 + arg 0x50,temp + isub temp,pdata + store 1,mem_tws_no_connect_cmd + jam 100,mem_tws_no_connect_cmd_trans_limit + rtn + +// input pdata +tws_clear_send_no_connect_trans_command: + fetch 1,mem_tws_no_connect_cmd + jam 0,mem_tws_no_connect_cmd +tws_handle_no_connect_trans_command: + store 1,mem_fifo_temp + branch ipc_tx_tws_event + + +clear_tws_fifo: + arg 0,temp + storet 5,mem_tws_cmd_fifo + jam 0,mem_tws_snd_op + branch send_tws_sync_cmd0 + +tws_master_switch_to_slave: + fetch 1,mem_tws_state + rtnne TWS_STATE_MASTER_CONNECTED + fetch 1,mem_tws_role_switch_in_process + nrtn blank + // becouse our tws link is base on phone link, so we need set a timeout + jam 1,mem_tws_role_switch_in_process + + setarg TWS_SYNC_CMD_MASTER_SWITCH + branch clear_tws_fifo + +//input: mem_fifo_temp +ipc_tx_tws_event: + //IPC_TYPE_TWS + setarg 0x010c + branch ipc_tx_event +ipc_tx_HFP_event: + //IPC_TYPE_HFP + setarg 0x010b + branch ipc_tx_event +ipc_tx_a2dp_event: + //IPC_TYPE_HFP + setarg 0x010a +ipc_tx_event: + store 2,mem_ipc_tx_buf + fetcht 1,mem_fifo_temp + istoret 1,contw +ipc_tx_data: + fetch 1,mem_ipc_tx_buf+1 + //add 2 bytes header + increase 2,pdata + store 1,mem_ipc_tx_data_len + setarg mem_ipc_tx_buf + branch ipc_tx_buffer + + +tws_check_link_timeout: + arg mem_tws_timeout_timer,regc + call timer_single_step + nrtn user + fetch 1,mem_tws_state + beq TWS_STATE_SLAVE_CONNECTED,tws_slave_timeout_switch_to_master + beq TWS_STATE_MASTER_CONNECTED,tws_change_to_wait_tws_slave + rtn +tws_change_to_wait_tws_slave: + call tws_start_wait_slave + branch tws_clear_connect_info + +tws_clear_connect_info: + call tws_clear_snd_rcv_flag + branch tws_clear_snd_cmd_fifo + + +tws_start_wait_slave: + fetch 6,mem_tws_bdaddr + branch tws_recon_fail,blank + jam TWS_SET_MASTER,mem_tws_role + jam TWS_STATE_WAIT_SLAVE,mem_tws_state + jam TWS_EVT_WAIT_SLAVE,mem_fifo_temp + branch ipc_tx_tws_event + +tws_refresh_slave_no_connect_wait_switch_timeout: + bpatchx patch3a_1,mem_patch3a + fetcht 1,mem_param_tws_observe_wait_connect_timeout_error_disconnect + fetch 1,mem_tws_state + bne TWS_STATE_WAIT_MASTER,tws_refresh_slave_no_connect_wait_switch_timeout_end// becouse sometime mark_supervision_disconn is not right + //bmark1 mark_supervision_disconn,p_tws_refresh_slave_no_connect_wait_switch_timeout_end + fetcht 1,mem_param_tws_observe_wait_connect_timeout_no_connect +tws_refresh_slave_no_connect_wait_switch_timeout_end: + storet 1,mem_tws_observe_wait_connect_timeout_timer + rtn + +tws_start_slave_switch_wait_work: + fetch 6,mem_tws_bdaddr + branch tws_recon_fail,blank + jam TWS_STATE_SLAVE_SWITCH_LISTEN,mem_tws_state + jam TWS_EVT_SLAVE_SWITCH_MASTER_WAIT,mem_fifo_temp + branch ipc_tx_tws_event + +tws_start_wait_master: + fetch 6,mem_tws_bdaddr + branch tws_recon_fail,blank +tws_set_slave_role: + call tws_refresh_slave_no_connect_wait_switch_timeout + jam TWS_SET_SLAVE,mem_tws_role + jam TWS_STATE_WAIT_MASTER,mem_tws_state + jam TWS_EVT_WAIT_MASTER,mem_fifo_temp + branch ipc_tx_tws_event +tws_stop_recon_work: +tws_stop_wait_slave: +tws_stop_wait_master: + jam TWS_STATE_NONE,mem_tws_state +tws_recon_fail: + jam TWS_EVT_RECON_FAILE,mem_fifo_temp + branch ipc_tx_tws_event + +tws_clear_flag_state: + jam 0,mem_tws_profile_connected + jam TWS_STATE_NONE,mem_tws_state +tws_clear_snd_rcv_flag: + setarg 0 + store 6,mem_tws_snd_op + rtn +tws_clear_snd_cmd_fifo: + setarg 0 + store 5,mem_tws_cmd_fifo + rtn +tws_clear_snd_no_connect_cmd: + jam 0,mem_tws_no_connect_cmd + jam 0,mem_tws_no_connect_cmd_trans_limit + rtn + +tws_check_master_wait_slave_connect_timeout: + fetch 1,mem_tws_state + rtnne TWS_STATE_MASTER_LISTEN// Only work on special mode + + arg mem_tws_master_wait_slave_timeout_timer,regc + call timer_single_step + nrtn user + jam TWS_STATE_WAIT_SLAVE,mem_tws_state + jam TWS_SET_MASTER,mem_tws_role + rtn + +// rtn user: enable means master or slave connected, disable is disconnected +tws_check_master_slave_connected: + enable user + fetch 1,mem_tws_state + rtneq TWS_STATE_MASTER_CONNECTED + rtneq TWS_STATE_SLAVE_CONNECTED + branch disable_user + + +tws_save_media_process_info: + // we should think the reserve dac work time + copy clke_bt,pdata + store 4,mem_process_clk + copy clke_rt,pdata + store 2,mem_process_clkrt + // Becouse we use one channel dac, and dac freq is fix 48K. Then 1 second will need 48,000*2Bytes = 96,000Bytes. + // Change to bt clock, 1sub-slot(312.5us) = 30Bytes + call audio_dac_hw_get_use_count // Get current use dac count + store 2,mem_process_used_buffer_size + + jam TWS_SYNC_EVT_UPDATE_AUDIO_PROCESS_INFO,mem_fifo_temp + branch ipc_tx_tws_event + + +tws_check_end_hfp_start_sync: + bpatchx patch3a_2,mem_patch3a + // Clock is not very good work here + fetch 1,mem_enable_hfp_start_sync + rtn blank +tws_check_end_hfp_start_sync_loop: + // set flag + arg LOG_POINT_1210,rega + //fetcht 2,clke + copy clke_bt,temp + call debug_log_print + + fetch 4,mem_hfp_start_sync_clk + isub clke_bt,pdata + // if mem_start_play_clk < clke_bt, means time reached + nbranch tws_check_end_hfp_start_sync_loop_end,positive//need check again + sub pdata,30,null// For safe, we use 30 + // if (mem_start_play_clk - clke_bt) <= 6, wait time with look + branch tws_check_end_hfp_start_sync_loop,positive + // if (mem_start_play_clk - clke_bt) > 6, wait next transaction + rtn +tws_check_end_hfp_start_sync_loop_end: + // set flag + arg LOG_POINT_1211,rega + fetcht 4,mem_hfp_start_sync_clk + //copy clke_bt,temp + call debug_log_print + jam 0,mem_enable_hfp_start_sync + fetch 1,mem_sco_flag + set0 sco_rcv_flag,pdata + store 1,mem_sco_flag + branch tws_restart_hfp_audio + +tws_restart_hfp_audio: + call HFP_voice_stop + call HFP_voice_start + rtn + +tws_100ms_event_polling: + bpatchx patch3a_3,mem_patch3a + call tws_check_polling + call tws_check_link_timeout + call tws_check_observe_connecting + call tws_check_master_wait_slave_connect_timeout + call tws_slave_loss_link_switch_polling + rtn + Index: tag/Soft/Librarier/bt_rom/program/tws_s.prog =================================================================== --- /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/tws_s.prog (nonexistent) +++ /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/tws_s.prog (working copy) @@ -0,0 +1,762 @@ +tws_s_wait_connecting: + bpatchx patch3a_4,mem_patch3a + arg le_tws_scan_interval_timer,queue + call timer_check + nrtn blank + // set flag + arg LOG_POINT_1302,rega + fetcht 1,mem_tws_state + call debug_log_print + // set flag + arg LOG_POINT_1303,rega + fetcht 2,mem_le_tws_scan_interval + call debug_log_print + + fetch 1,mem_tws_state + bne TWS_STATE_SLAVE_SWITCH_LISTEN,tws_s_generate_scan_window + setarg 0x50 + branch tws_s_generate_scan_window_end +tws_s_generate_scan_window: + random pdata + sub pdata,0x40,null + nbranch tws_s_generate_scan_window,positive + arg 0x27,temp + isub temp,null + nbranch tws_s_generate_scan_window,positive +tws_s_generate_scan_window_end: + store 2, mem_le_tws_scan_interval + + fetch 2,mem_le_tws_scan_interval + fetcht 2,mem_le_tws_scan_window + isub temp,pdata + arg le_tws_scan_interval_timer,queue + call timer_init + disable master + call tws_reset_connecting + call le_init_adv + enable user3 + call tws_wait_adv + disable user3 +tws_s_connecting_wait_match: + nbranch tws_reset_connecting,match + fetch 1,mem_tws_adv_match + increase 1,pdata + store 1,mem_tws_adv_match + // set flag + arg LOG_POINT_1309,rega + fetcht 1,mem_tws_connecting_phase + call debug_log_print + +tws_s_connecting_wait_match_continue: + bpatchx patch3a_5,mem_patch3a + + fetch 1,mem_tws_connecting_phase + beq TWS_CONNECTING_PHASE0,tws_rcv_context_info_btclk + beq TWS_CONNECTING_PHASE1,tws_rcv_context_info_keymap + beq TWS_CONNECTING_PHASE2,tws_rcv_context_info_memcontext_sub0 ////context 30 + beq TWS_CONNECTING_PHASE3,tws_rcv_context_info_memcontext_sub1 //context 30 + beq TWS_CONNECTING_PHASE4,tws_rcv_context_info_memcontext_sub2 //context 30 + beq TWS_CONNECTING_PHASE5,tws_rcv_afh_info //context 30 + beq TWS_CONNECTING_PHASE6,tws_rcv_sco_info //context 30 + beq TWS_CONNECTING_PHASE7,tws_rcv_a2dp_info //context 30 + beq TWS_CONNECTING_PHASE8,tws_rcv_context_info_phase_end //context 30 + + branch tws_reset_connecting + +// in pdata: need match addr +tws_check_paired_bdaddr_and_rssi_is_match: + enable user + // Step1: check allow paired or not + fetch 2,mem_tws_first_packet_dynamic_buffer_status + bbit1 TWS_PACKET_STATUS_BIT_PAIRING,tws_check_paired_bdaddr_and_rssi_is_match_not_paired + +tws_check_paired_bdaddr_and_rssi_is_match_allready_paired: + // Check remote want paired or not + fetch 6,mem_tws_first_packet_dynamic_buffer_paired_bdaddr + fetcht 6,mem_local_bdaddr + isub temp,null + nbranch disable_user,zero + +tws_check_paired_bdaddr_and_rssi_is_match_not_paired: + // Check remote is the last paired device + fetch 6,mem_tws_first_packet_dynamic_buffer_local_bdaddr + fetcht 6,mem_tws_last_paired_lap + isub temp,null + rtn zero + + // Check self need pair or not + fetch 1,mem_tws_allow_pairing + branch disable_user,blank + + // Check rssi allow to pair + fetch 1,mem_tws_allow_pairing_rssi_limit// allow rssi limit to -40dBm to pair + // check rssi + fetcht 1,mem_rssi + isub temp,null + rtn positive + branch disable_user + + +// in pdata: status bit +tws_check_hsp_role_is_match: + enable user + fetch 1,mem_auto_hsp_role // need auto check + nrtn blank + + fetch 1,mem_tws_first_packet_dynamic_buffer_status + rshift pdata,pdata // Get TWS_PACKET_STATUS_BIT_HSP_ROLE bit + fetcht 1,mem_hsp_role + icompare 0x01,temp + nbranch disable_user,true + rtn + +tws_slave_check_rcv_context_header: + disable user + call tws_check_bdaddr_is_match + nrtn zero + fetch 1,mem_tws_connecting_phase + fetcht 1,mem_le_rxbuf+8 + isub temp,null + nrtn zero + enable user + rtn + +tws_reset_connecting_with_clear_context: + bpatchx patch3a_6,mem_patch3a + call tws_reset_connecting +tws_clear_slave_context: + arg mem_state,contw + call tws_clear_mem_80 + arg mem_context,contw +tws_clear_mem_80: + arg 10,loopcnt + branch memset0 + + +tws_rcv_pkt_in_slave_listen: + call tws_reset_connecting_with_clear_context + jam 0,mem_tws_slave_loss_link_listen_master_timeout_timer + branch tws_force_free_local_link + +tws_receive_first_adv_in_recon_state: + bpatchx patch3a_7,mem_patch3a + // Think to change flag to one byte? to reduce code size + fetch 2,mem_le_rxbuf+8 + arg TWS_BLE_ADV_FLAG_CONNECTED,temp + isub temp,null + branch tws_receive_arbiter_connected_adv_flag,zero + arg TWS_BLE_ADV_FLAG_POWER_ON,temp + isub temp,null + branch tws_receive_power_on_adv_flag,zero + arg TWS_BLE_ADV_FLAG_NO_CONNECTED,temp// Arbiter noconnected adv + isub temp,null + branch tws_receive_arbiter_noconnect_adv_flag,zero + branch tws_reset_connecting +tws_receive_arbiter_connected_adv_flag: + branch tws_master_is_found + // think to fast? + //branch get_tws_rcv_context_info_btclk +tws_receive_arbiter_noconnect_adv_flag: + //if we are arbiter, and receive other arbiter broadcast + branch tws_master_is_found +tws_receive_power_on_adv_flag: + // Check self state + call tws_state_check_arbiter_in_reconnect + branch tws_reset_connecting,user + call tws_send_info_request + branch tws_master_is_found + +// Check true flag +tws_state_check_arbiter_in_reconnect: + call enable_user + fetch 1,mem_tws_state + rtneq TWS_STATE_WAIT_SLAVE + rtneq TWS_STATE_MASTER_LISTEN + rtneq TWS_STATE_MASTER_CONNECTED + branch disable_user + + +get_tws_rcv_context_info_btclk: + call tws_start_wait_master + branch tws_rcv_context_info_btclk_1 + +// use to check the first packet is right to work or not +tws_rcv_first_packet_allow_check: + bpatchx patch3b_0,mem_patch3b + enable user + + // receive the packet payload + arg mem_le_rxbuf+14,contr + arg mem_tws_first_packet_dynamic_buffer,contw + force 20,loopcnt + call memcpy + + // Step1: check role + call tws_check_hsp_role_is_match + nrtn user + + // Step2: check addr + call tws_check_paired_bdaddr_and_rssi_is_match + nrtn user + + // Step3: store tws addr + fetch 6,mem_tws_first_packet_dynamic_buffer_local_bdaddr // check addr + store 6,mem_tws_last_paired_lap// use for first pair. + rtn + + +tws_rcv_no_connect_trans_info: + bpatchx patch3b_1,mem_patch3b + // first check remote addr + call tws_rcv_no_connect_trans_info_check + nbranch tws_reset_connecting,user + + fetch 1,mem_le_rxbuf+22 // trans code + call tws_handle_no_connect_trans_command + + call tws_reset_connecting + branch tws_send_info_request + +tws_rcv_no_connect_trans_info_check: + enable user + + fetch 6,mem_le_rxbuf+10 // RemoteAddr + fetcht 6,mem_local_bdaddr + isub temp,null + nbranch disable_user,zero + + fetch 6,mem_le_rxbuf+16 // LocalAddr + fetcht 6,mem_tws_last_paired_lap + isub temp,null + nbranch disable_user,zero + + rtn + +tws_rcv_context_info_btclk: + bpatchx patch3b_2,mem_patch3b + call tws_check_bdaddr_is_match + nbranch tws_reset_connecting,zero + + arg LOG_POINT_1301,rega + fetcht 2,mem_le_rxbuf+8 + call debug_log_print + + arg LOG_POINT_130A,rega + fetcht 1,mem_rssi + call debug_log_print + + fetch 2,mem_le_rxbuf+8 + arg TWS_BLE_ADV_FLAG_TRANS,temp + isub temp,null + branch tws_rcv_no_connect_trans_info,zero + + // In this mode do nothing + fetch 1,mem_tws_no_connect_cmd + nbranch tws_reset_connecting,blank + + call tws_rcv_first_packet_allow_check + nbranch tws_reset_connecting,user + + fetch 1,mem_tws_state + beq TWS_STATE_SLAVE_SWITCH_LISTEN,tws_rcv_pkt_in_slave_listen + + fetch 1,mem_tws_state + beq TWS_STATE_PAIRING,tws_receive_first_adv_in_recon_state + beq TWS_STATE_WAIT_SLAVE,tws_receive_first_adv_in_recon_state + // Need update slave recover timer + call tws_refresh_slave_no_connect_wait_switch_timeout +tws_rcv_context_info_btclk_1: + bpatchx patch3b_3,mem_patch3b + call tws_check_bdaddr_is_match + nbranch tws_reset_connecting,zero + fetch 2,mem_le_rxbuf+8 + arg TWS_BLE_ADV_FLAG_CONNECTED,temp + isub temp,null + nbranch tws_rcv_context_info_btclk_no_connect,zero + ifetch 4,contr + copy pdata,timeup + call tws_slave_rcv_first_dynamic_buffer + deposit clke_bt + iadd timeup,timeup + copy timeup,clke_bt + force 0,clke_rt + call calc_clke_offset + jam TWS_CONNECTING_PHASE1,mem_tws_connecting_phase + call tws_send_info_request + branch tws_s_connecting_wait_match + + +tws_rcv_context_info_btclk_no_connect: + // need tell remote + call tws_send_info_request + branch tws_send_master_found_event + +tws_rcv_context_info_keymap: + call tws_check_bdaddr_is_match + nbranch tws_reset_connecting,zero + fetch 2,mem_le_rxbuf+8 + arg 0xff1b,temp + isub temp,null + nbranch tws_reset_connecting,zero + arg mem_link_key,contw + force 16,loopcnt + call memcpy + arg mem_afh_classify_channel_map,contw + force 10,loopcnt + call memcpy + jam TWS_CONNECTING_PHASE2,mem_tws_connecting_phase + call tws_send_info_request + branch tws_s_connecting_wait_match + +tws_rcv_context_info_phase_end: + bpatchx patch3b_4,mem_patch3b + call tws_slave_check_rcv_context_header + nbranch tws_reset_connecting_with_clear_context,user + nrtn user + force 30,loopcnt + arg mem_l2cap_active_ch_count,contw + call memcpy + force 4,loopcnt + arg mem_avdtp_xmem_start,contw + call memcpy + force 19,loopcnt + arg mem_xmem_hf_state_start,contw + call memcpy + +tws_rcv_context_info_phase_end_continue: + call tws_reset_connecting + call tws_init_all + jam TWS_STATE_SLAVE_LISTEN,mem_tws_state + jam TWS_SET_SLAVE,mem_tws_role + + fetch 1,mem_context+coffset_arq + set0 wack,pdata + store 1,mem_context+coffset_arq + + fetch 1,mem_context+coffset_op + set0 op_txl2cap,pdata + store 1,mem_context+coffset_op + + jam 0,mem_context + coffset_lmp_to_send + + arg mem_context,rega + call context_load + + fetch 1,mem_mode + bbit0 afh_enable,tws_rcv_context_info_phase_end_no_afh + set0 afh_change,pdata + store 1,mem_mode + call afh_process_freq_map + jam 0,mem_afh_new_mod +tws_rcv_context_info_phase_end_no_afh: + arg mem_context+80,contr + arg mem_state+80,contw + force 10,loopcnt + call memcpy_fast + setarg 0 + store 8,mem_context+80 + store 8,mem_context+160 + jam 1,mem_link_key_exists + //fetch 8,mem_mark_load + //copy pdata,mark + fetchr mark,8,mem_mark_load + disable master + jam 0,mem_tws_adv_try_num + setarg 0x1420 //600us + store 2,mem_rx_window + + //call ice_break + branch tws_slave_scan_adv + +tws_slave_wait_match: + // set flag + arg LOG_POINT_130C,rega + fetcht 1,mem_tws_adv_try_num + call debug_log_print + + branch tws_slave_scan_adv + +tws_slave_wait_match_loop: + call tws_slave_listen + branch context_save,match + + fetch 2,mem_loss_match + arg 800,temp //1s + isub temp,null + branch tws_slave_wait_match,positive + branch tws_slave_wait_match_loop + +tws_check_master_a2dp_start: + jam 1,mem_slave_force_mute_a2dp_voice + jam 5,mem_slave_force_mute_a2dp_voice_cnt + + fetch 1,mem_a2dp_state + rtnne A2DP_STATE_START + + call a2dp_send_evt_start + rtn + +tws_check_master_sco_start: + rtnmark0 mark_sco_flag + call HFP_voice_start + branch HFP_voice_start_notify + +tws_send_info_request: + bpatchx patch3b_5,mem_patch3b + arg 0x0c03,temp + set0 LE_SENDER_ADDR_BIT,temp + set0 LE_RECEIVER_ADDR_BIT,temp + storet 2,mem_le_txheader + fetch 6,mem_local_bdaddr + istore 6,contw + fetch 6,mem_tws_last_paired_lap + istore 6,contw + branch tws_transmit_receive_sifs + +tws_check_bdaddr_is_match: + fetch 6,mem_le_rxbuf+2 + fetcht 6,mem_tws_bdaddr + isub temp,null + ncall tws_reset_connecting,zero + rtn + +tws_slave_listen: + bpatchx patch3b_6,mem_patch3b + call le_disable + call calc_clke_tws + call role_switch_slave + rtn user + call slave_receive_notsniff + call tws_slave_conn_recv_packet + nbranch tws_slave_listen_not_match, match + + call tws_slave_phone_connected + call supervision_flush + + call tws_check_master_a2dp_start + call tws_check_master_sco_start + setarg 0 + store 2 ,mem_loss_match + + setarg 0x380 + store 2,mem_rx_window + call parse_lmp_tws + call parse_l2cap + call calc_clke_offset + rtn + + +tws_slave_phone_connected: + bpatchx patch3b_7,mem_patch3b + // set flag + arg LOG_POINT_130B,rega + fetcht 1,mem_tws_state + call debug_log_print + + jam TWS_STATE_SLAVE_CONNECTED,mem_tws_state + jam TWS_SET_SLAVE,mem_tws_role + + // point ,tws slave bt connected + jam TWS_EVT_SLAVE_CONNECTED,mem_fifo_temp + call ipc_tx_tws_event + + fetch 1,mem_param_tws_timeout_slave + store 1,mem_tws_timeout_timer + + jam 1,mem_tws_slave_wait_master_first_polling_flag + + //set state map for tws slave + fetch 1,mem_state + rtnbit0 state_inconn + fetcht 2,mem_ui_state_map + or temp,0x03,temp + storet 2,mem_ui_state_map + rtnbit0 state_insniff + set1 UI_STATE_BT_SNIFF,temp + storet 2,mem_ui_state_map + + rtn + +tws_slave_listen_not_match: + fetch 2,mem_loss_match + increase 1,pdata + store 2,mem_loss_match + rtn + + +tws_slave_scan_adv: + bpatchx patch3c_0,mem_patch3c + fetch 1,mem_tws_adv_try_num + increase 1,pdata + store 1,mem_tws_adv_try_num + beq 240,tws_set_slave_role + setarg 0 + store 2,mem_loss_match + nop 3000 + call le_enable + disable master + disable attempt + call le_init_adv + enable user3 + call tws_wait_adv + disable user3 + nbranch tws_slave_scan_adv, match + + call tws_check_bdaddr_is_match + nbranch tws_slave_scan_adv,zero + + fetch 2,mem_le_rxbuf+8 + arg TWS_BLE_ADV_FLAG_CONNECTED,temp + isub temp,null + nbranch tws_slave_scan_adv, zero + + call tws_rcv_first_packet_allow_check + nbranch tws_slave_scan_adv,user + + arg mem_le_rxbuf+10,contr + ifetch 4,contr + copy pdata,timeup + call tws_slave_rcv_first_dynamic_buffer + deposit clke_bt + iadd timeup,timeup + copy timeup,clke_bt + call calc_clke_offset + fetch 1,mem_count_rcv_adv + increase 1,pdata + store 1,mem_count_rcv_adv + branch tws_slave_wait_match_loop + +tws_slave_rcv_first_dynamic_buffer: + // need patch + fetch 2,mem_tws_first_packet_dynamic_buffer // Staus + ifetch 6,contr //mem_local_bdaddr + ifetch 6,contr //mem_tws_last_paired_lap + rtn + +tws_s_check_role_switch_work: + disable user + fetch 1,mem_tws_role_switch_in_process + rtn blank + + // set flag + arg LOG_POINT_1320,rega + fetcht 1,mem_tws_m2s_ack_send_timeout_count + call debug_log_print + + call tws_check_m2s_timeout_reach + nrtn user + call tws_s_role_switch_success + branch enable_user + +tws_s_role_switch_success: + bpatchx patch3c_1,mem_patch3c + // set flag + arg LOG_POINT_1321,rega + fetcht 1,mem_tws_m2s_ack_send_timeout_count + call debug_log_print + + jam 0,mem_tws_role_switch_in_process + jam 0,mem_tws_m2s_ack_send_timeout_count + call tws_clear_connect_info + call tws_master_poll_slave_timer_refresh + jam LMP_PING_REQ,mem_lmo_opcode2 + jam TWS_STATE_MASTER_CONNECTED,mem_tws_state + jam TWS_SET_MASTER,mem_tws_role + + call send_tws_master_switch_ipc_tx_event + + // If receive remote power off switch request + fetch 1,mem_tws_buffer_master_switch_reason + rtn blank + jam 0,mem_tws_buffer_master_switch_reason + + call tws_slave_change_to_master + branch send_tws_remote_power_off_ipc_tx_event + +tws_send_ack_process: + bpatchx patch3c_2,mem_patch3c + call tws_end_of_packet + fetch 1,mem_tws_local_rcv_packet + branch tws_send_ack_process_end,blank + + call tws_s_check_role_switch_work + branch tws_not_rcv_ack_error,user + + jam 1,mem_tws_is_slave_send + call tws_set_need_send_header + call tws_send_payload_check + ncall tws_clear_need_send_header,user + //send ACK packet + call tws_set_ack_access + + fetcht 1,mem_last_freq + call tws_set_send_rf + + //receive + call tws_set_ack_access + fetcht 1,mem_last_freq + call tws_set_rcv_rf + call rf_debug_active_sync_line,sync + nbranch tws_slave_rcv_ack,sync + call tws_sec_link_connected + call tws_receive_packet_header + call rf_debug_active_crc_error_line,crc_failed + branch tws_slave_rcv_ack,crc_failed + call tws_receive_packet_header_handle + branch tws_slave_rcv_ack,crc_failed + // For slave use subline to response master + call tws_slave_ack_response_process +tws_slave_rcv_ack: + fetch 1,mem_tws_ack + increase 1,pdata + store 1,mem_tws_ack +tws_send_ack_process_end: + bmark1 mark_old_packet,ack_payload + + fetch 1,mem_tws_last_rcv_phone_packet_crc_fail + nbranch tws_not_rcv_ack_error,blank + + fetch 1,mem_rx_type + beq type_poll,end_of_packet + beq type_null,end_of_packet + branch process_dmh_packet + + +tws_send_ack_process_print_double_ack_info: + // set flag + arg LOG_POINT_2002,rega + fetcht 1,mem_rx_type + call debug_log_print + + // set flag + arg LOG_POINT_2003,rega + fetcht 2,mem_tws_last_rcv_phone_packet_crc_fail + call debug_log_print + + // set flag + arg LOG_POINT_2004,rega + fetcht 2,mem_tws_local_rcv_packet + call debug_log_print + rtn + +tws_slave_ack_response_process: + fetcht 1,mem_tws_rcv_op + and temp,0x7f,pdata + rtn blank + // If we have packet send, do nothing + fetch 5,mem_tws_cmd_fifo + nrtn blank + jam TWS_SYNC_EVT_SLAVE_ACK,mem_fifo_temp + call tws_push_cmd_fifo + rtn + +tws_sec_link_connected: + jam 0,mem_tws_slave_wait_master_first_polling_flag + + fetcht 1,mem_param_tws_timeout_slave + fetch 1,mem_hf_call_state + beq HFP_NONO,tws_sec_link_connected_end + lshift temp,temp +tws_sec_link_connected_end: + storet 1,mem_tws_timeout_timer + rtn + + +tws_handle_old_packet: + bpatchx patch3c_3,mem_patch3c + nop 100 + arg mem_temp,temp +tws_discard_packet: + parse demod,bucket,8 + rshift3 pwindow,pdata + istore 1,temp + loop tws_discard_packet + branch process_dmh_data_end + +tws_rcv_context_info_memcontext_sub0: + arg 0,rega // context offset + arg 30,regb // length + branch tws_rcv_context_info_memcontext_common + +tws_rcv_context_info_memcontext_sub1: + arg 30,rega // context offset + arg 30,regb // length + branch tws_rcv_context_info_memcontext_common + +tws_rcv_context_info_memcontext_sub2: + arg 60,rega // context offset + arg 30,regb // length + branch tws_rcv_context_info_memcontext_common + +tws_rcv_afh_info: + call tws_slave_check_rcv_context_header + nbranch tws_reset_connecting_with_clear_context,user + ifetch 1,contr + store 1, mem_hf_vlm_speaker + ifetch 1,contr + store 1,mem_avctp_play_state + ifetch 2,contr + store 2,mem_tws_remote_version + force 26,loopcnt + arg mem_afh_cfg,contw + call memcpy + branch tws_rcv_context_info_memcontext_common_end + +tws_rcv_sco_info: + call tws_slave_check_rcv_context_header + nbranch tws_reset_connecting_with_clear_context,user + + force 24,loopcnt + arg mem_xmem_sco_start,contw + call memcpy + + ifetch 6,contr + store 6,mem_lap + + branch tws_rcv_context_info_memcontext_common_end + +tws_rcv_a2dp_info: + call tws_slave_check_rcv_context_header + nbranch tws_reset_connecting_with_clear_context,user + + force 21,loopcnt + arg mem_rfc_xmem_start,contw + call memcpy + ifetch 4,contr + store 4,mem_avctp_xmem_start + ifetch 3,contr + store 3,mem_audio_src_endpoint + ifetch 1,contr + store 1,mem_a2dp_state + ifetch 1,contr + store 1,mem_conf_samplefreq_channelmode + branch tws_rcv_context_info_memcontext_common_end + +// input +// rega context offset +// regb length +tws_rcv_context_info_memcontext_common: + call tws_slave_check_rcv_context_header + nbranch tws_reset_connecting_with_clear_context,user + + setarg mem_context + iadd rega,contw + copy regb,loopcnt + call memcpy +tws_rcv_context_info_memcontext_common_end: + fetch 1,mem_tws_connecting_phase + increase 1,pdata + store 1,mem_tws_connecting_phase + call tws_send_info_request + nbranch tws_reset_connecting_with_clear_context,match + branch tws_s_connecting_wait_match + + +tws_wait_adv: + bpatchx patch3c_4,mem_patch3c + call tws_select_le_channel + disable swfine + fetchr timeup,2,mem_le_tws_scan_window + call lerx_setfreq + branch tws_receive_rxon + Index: tag/Soft/Librarier/bt_rom/program/ui.prog =================================================================== --- /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/ui.prog (nonexistent) +++ /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/ui.prog (working copy) @@ -0,0 +1,614 @@ +ui_init: + rtn wake + branch ui_timer_init + +ui_dispatch: + fetch 1,mem_device_option + rtneq dvc_op_hci + branch ui_timer_check + + +//////////////////////////////////////////////////// BUTTON ///////////////////////////////// + +ui_button_init: + add regb,BUTTON_GPIO_MEM_OFFSET,rega + ifetch 1,rega + rtneq BUTTON_GPIO_DISABLE + copy pdata,temp + call gpio_config_input + call ui_button_set_up + call ui_button_set_timer_0 + branch ui_button_timer + +ui_button_timer: + add regb,BUTTON_GPIO_MEM_OFFSET ,rega + ifetch 1,rega + rtneq BUTTON_GPIO_DISABLE + copy pdata,temp + call gpio_get_bit + add regb,BUTTON_LAST_STATE_MEM_OFFSET ,rega + bpatchx patch3c_5,mem_patch3c + ifetch 1,rega + beq BUTTON_STATE_UP,ui_button_timer_state_up + beq BUTTON_STATE_DOWN,ui_button_timer_state_down + branch assert + +ui_button_timer_state_up: + nbranch ui_button_timer_up_to_up,true +ui_button_up_to_down: + call ui_button_set_down + add regb,BUTTON_PRESS_TIMEOUT_MEM_OFFSET ,rega + ifetch 1,rega + call ui_button_set_timer + add regb,BUTTON_PRESS_COUNT_MEM_OFFSET ,rega + ifetch 1,rega + increase 1,pdata + istore 1,rega + copy pdata,temp + add regb,BUTTON_DOWN_CB_MEM_OFFSET ,rega + ifetch 2,rega + branch callback_func + +ui_button_timer_up_to_up: + add regb,BUTTON_TIMER_MEM_OFFSET ,regc + call timer_single_step + nrtn user +ui_button_up_cb: + add regb,BUTTON_PRESS_COUNT_MEM_OFFSET ,rega + ifetcht 1,rega + setarg 0 + istore 1,rega + add regb,BUTTON_UP_CB_MEM_OFFSET ,rega + ifetch 2,rega + branch callback_func + +ui_button_timer_state_down: + nbranch ui_button_down_to_up,true +ui_button_timer_state_down_to_down: + add regb,BUTTON_TIMER_MEM_OFFSET ,regc + call timer_single_step + nrtn user + branch ui_button_longpress_cb + +ui_button_longpress_cb: + setarg BUTTON_LONGPRESS + add regb,BUTTON_PRESS_COUNT_MEM_OFFSET ,rega + istore 1,rega + add regb,BUTTON_LONGPRESS_CB_MEM_OFFSET ,rega + ifetch 2,rega + branch callback_func + +ui_button_down_to_up: + call ui_button_set_up + add regb,BUTTON_PRESS_COUNT_MEM_OFFSET ,rega + ifetch 1,rega + beq BUTTON_LONGPRESS,ui_button_long_release + call ui_button_set_timer_0 + add regb,BUTTON_TIMEOUT_MEM_OFFSET ,rega + ifetch 1,rega + branch ui_button_up_cb,blank + branch ui_button_set_timer + +ui_button_long_release: + setarg 0 + istore 1,rega + call ui_button_set_timer_0 + add regb,BUTTON_LONG_RELEASE_CB_MEM_OFFSET ,rega + ifetch 2,rega + branch callback_func + +ui_button_set_down: + setarg BUTTON_STATE_DOWN + branch ui_button_set_state + +ui_button_set_up: + setarg BUTTON_STATE_UP +ui_button_set_state: + add regb,BUTTON_LAST_STATE_MEM_OFFSET ,rega + istore 1,rega + rtn + +ui_button_set_timer_0: + setarg 0 +ui_button_set_timer: + add regb,BUTTON_TIMER_MEM_OFFSET ,rega + istore 1,rega + rtn + +//////////////////////////////////////////////////// BUTTON END ///////////////////////////////// + + +//////////////////////////////////////////////////// LED ///////////////////////////////// + +//input temp: led1 gpio; regb : led mem address +ui_led_blink_init: + set1 LED_BLINK_BIT,temp + add regb, LED_GPIO_MEM_OFFSET,rega + istoret 1,rega + add regb, LED_STATE_MEM_OFFSET ,rega + ifetch 1,rega + beq LED_STATE_OFF,ui_led_on_with_timer + beq LED_STATE_ON,ui_led_off_with_timer + branch ui_led_on_with_timer + +//input regb : led mem address +ui_led_blink_check: + add regb, LED_GPIO_MEM_OFFSET,rega + ifetch 1,rega + rtnbit0 LED_BLINK_BIT + add regb, LED_STATE_MEM_OFFSET,rega + ifetch 1,rega + beq LED_STATE_OFF,ui_led_state_off + beq LED_STATE_ON,ui_led_state_on + rtn + +ui_led_state_on: + branch ui_led_off_with_timer + +ui_led_state_off: + add regb, LED_REPEAT_MEM_OFFSET ,rega + ifetch 1,rega + branch ui_led_blink_stop, blank + beq LED_REPEAT_FORERVER,ui_led_on_with_timer + increase -1,pdata + branch ui_led_blink_stop,zero + istore 1,rega + branch ui_led_on_with_timer + +ui_led_on_with_timer: + add regb, LED_ON_TIMER_MEM_OFFSET ,rega + ifetch 1,rega + rtn blank + add regb, LED_TIMER_MEM_OFFSET ,rega + istore 1,rega +ui_led_on: + add regb, LED_STATE_MEM_OFFSET ,rega + setarg LED_STATE_ON + istore 1,rega + add regb, LED_GPIO_MEM_OFFSET ,rega + ifetcht 1,rega + branch gpio_out_active + +ui_led_off_with_timer: + add regb, LED_OFF_TIMER_MEM_OFFSET ,rega + ifetch 1,rega + branch ui_led_blink_stop,blank + add regb, LED_TIMER_MEM_OFFSET ,rega + istore 1,rega +ui_led_off: + add regb, LED_STATE_MEM_OFFSET ,rega + setarg LED_STATE_OFF + istore 1,rega + add regb, LED_GPIO_MEM_OFFSET ,rega + ifetcht 1,rega + branch gpio_out_inactive + +ui_led_blink_stop: + add regb, LED_GPIO_MEM_OFFSET ,rega + ifetch 1,rega + set0 LED_BLINK_BIT,pdata + istore 1,rega + branch ui_led_off + + +//////////////////////////////////////////////////// LED END ///////////////////////////////// + + +ui_timer_timeout: + setarg 0x10 + arg 3,queue + call lshift8_queue + iadd regb,regb + rtn + + +ui_timer_check: + bpatchx patch3c_6,mem_patch3c + arg 0,rega + fetcht 4,mem_ui_timer_last_btclk + copy clkn_bt,regb + copy regb,pdata + isub temp,null + ncall ui_timer_timeout,positive +ui_timer_check_loop: + copy regb,pdata + increase 160,temp //320btclk = 100ms + increase 160,temp + isub temp,null + nbranch ui_timer_check_end,positive + increase 1,rega //increase 1 every 100ms count + and rega,0x0f,pdata + nbranch ui_timer_check_loop,blank + arg 0,rega //reset timer if it's longer than 1.5s between 2 checks + call ui_timer_check_send_evt +ui_timer_init: + copy clkn_bt,pdata + store 4,mem_ui_timer_last_btclk + rtn +ui_timer_check_end: + copy rega,pdata + rtn blank + increase -160,temp //320btclk = 100ms + increase -160,temp + set0 28,temp + storet 4,mem_ui_timer_last_btclk +ui_timer_check_send_evt: + branch app_evt_timer + + + +//**********************************************************// +//************UI Inter-Processor Communication*******// +//**********************************************************// +ui_ipc_get_lock: + jam 1,mem_ipc_lock_bt +ui_ipc_get_lock_wait: + fetch 1,mem_ipc_lock_c51 + nbranch ui_ipc_get_lock_wait,blank + rtn + +ui_ipc_put_lock: + jam 0,mem_ipc_lock_bt + rtn + +ui_ipc_fifo_out: + branch fifo_out + + + +ui_ipc_send_event: + bpatchx patch3c_7,mem_patch3c + call ipc_tx_bt_event + fetch 1,mem_device_option + rtneq dvc_op_hci + call ui_ipc_get_lock + copy rega,regb + arg mem_ipc_fifo_bt2c51,rega + call fifo_in + copy regb,rega + branch ui_ipc_put_lock + +ui_ipc_send_cmd: + bpatchx patch3d_0,mem_patch3d + fetch 1,mem_device_option + rtneq dvc_op_hci + call ui_ipc_get_lock + copy rega,regb + arg mem_ipc_fifo_c512bt,rega + call fifo_in + copy regb,rega + branch ui_ipc_put_lock + +ui_ipc_clean_all_fifo: + setarg 0 + store UTIL_FIFO_LEN,mem_ipc_fifo_c512bt + store UTIL_FIFO_LEN,mem_ipc_fifo_bt2c51 + rtn + +check_51cmd: + bpatchx patch3d_1,mem_patch3d + fetch 1,mem_hci_cmd + nrtn blank + arg mem_ipc_fifo_c512bt,rega + call fifo_is_empty + rtn blank + jam IPC_CONTINUE_PROCESS,mem_ipc_skip_continue_proc + call check_51cmd_once + fetch 1,mem_ipc_skip_continue_proc + branch check_51cmd,blank + rtn + +check_51cmd_once: + bpatchx patch3d_2,mem_patch3d + call ui_ipc_get_lock + arg mem_ipc_fifo_c512bt,rega + call fifo_out + copy pdata,temp + call ui_ipc_put_lock + copy temp,pdata + rtn blank + beq BT_CMD_LE_UPDATE_CONN,le_send_update_paramter + beq BT_CMD_MTU_EXCHANGE,le_send_update_ATT_MTU + beq BT_CMD_LOAD_FLASH_PARAMS,load_le_ltk + beq BT_CMD_START_DISCOVERY,check_51cmd_start_discovery + beq BT_CMD_STOP_DISCOVERY,check_51cmd_stop_discovery + beq BT_CMD_RECONNECT,check_51cmd_reconnect + beq BT_CMD_SNIFF_TEST,check_51cmd_sniff_test + beq BT_CMD_START_INQUIRY,check_51cmd_inq + beq BT_CMD_STOP_INQUIRY,check_51cmd_stop_inq + beq BT_CMD_START_ADV,check_51cmd_adv + beq BT_CMD_STOP_ADV,check_51cmd_stop_adv + beq BT_CMD_START_DIRECT_ADV,check_51cmd_direct_adv + beq BT_CMD_STOP_DIRECT_ADV,check_51cmd_stop_direct_adv + beq BT_CMD_LE_START_SCAN,check_51cmd_start_scan + beq BT_CMD_LE_STOP_SCAN,check_51cmd_stop_scan + beq BT_CMD_ENTER_HIBERNATE,check_51cmd_hibernate + beq BT_CMD_LE_SMP_SECURITY_REQUEST,check_51cmd_le_smp_sec_req + beq BT_CMD_BB_RECONN_CANCEL,check_51cmd_bb_reconn_cancel + beq BT_CMD_VP_END_RECOVER_DAC,check_51cmd_vp_end_recover_dac + + //check tws sync cmd + sub pdata,TWS_SYNC_CMD_START,null + branch check_51cmd_once_1,positive + sub pdata,TWS_SYNC_CMD_END,null + nbranch check_51cmd_once_1,positive + branch send_tws_sync_cmd + +check_51cmd_once_1: + sub pdata,TWS_NO_CONNECT_TRANS_CMD_START,null + branch check_51cmd_once_normal,positive + sub pdata,TWS_NO_CONNECT_TRANS_CMD_END,null + nbranch check_51cmd_once_normal,positive + branch send_tws_no_connect_trans_cmd + + +check_51cmd_once_normal: + //tws cmd + beq BT_CMD_TWS_NONE,tws_exit_work_state + beq BT_CMD_START_WAIT_MASTER,tws_start_wait_master + beq BT_CMD_STOP_WAIT_MASTER,tws_stop_wait_master + beq BT_CMD_START_WAIT_SLAVE,tws_start_wait_slave + beq BT_CMD_STOP_WAIT_SLAVE,tws_stop_wait_slave + beq BT_CMD_START_RECON_TWS,tws_start_recon_work + beq BT_CMD_STOP_RECON_TWS,tws_stop_recon_work + + beq BT_CMD_PLAY_VP,vp_play_by_cmd + beq BT_CMD_PLAY_TISHI_VP,vp_play_tishi_by_cmd + + //context related, process in context + store 1,mem_fifo_temp + fetch 1,mem_lmo_opcode2 + branch check_51cmd_once_continue,blank + call lmo_fifo_process + fetch 1,mem_lmo_opcode2 + nbranch check_51cmd_restore,blank //process this cmd next time while lmo fifo is full +check_51cmd_once_continue: + bpatchx patch3d_3,mem_patch3d + fetch 1,mem_fifo_temp + bmark0 mark_context,check_51cmd_check_idle + beq BT_CMD_RMV_ESCO_REQ, cmd_disconn_esco + beq BT_CMD_EST_ESCO_REQ,cmd_setup_esco + beq BT_CMD_RMV_SCO_REQ, cmd_disconn_sco + beq BT_CMD_EST_SCO_REQ,cmd_setup_sco + beq BT_CMD_ENTER_SNIFF,cmd_in_sniff + beq BT_CMD_EXIT_SNIFF,cmd_exit_sniff + beq BT_CMD_SET_PIN_CODE,check_51cmd_pincode + beq BT_CMD_DISCONNECT,check_51cmd_disconnect + beq BT_CMD_LE_DISCONNECT,check_51cmd_le_disconnect + beq BT_CMD_ROLE_SWITCH,check_51cmd_role_switch + beq BT_CMD_STORE_RECONN_INFO_LE,nv_store_le_reconn_info + beq BT_CMD_STORE_RECONN_INFO_BT,nv_store_bd_reconn_info + beq BT_CMD_DHKEY_NOT_ACCEPT,check_51_cmd_dhkey_not_accept + beq BT_CMD_INCREASE_POWER_REQ,cmd_increase_power_req + beq BT_CMD_PLAY_PAUSE,cmd_play_pause + beq BT_CMD_BACKWARD,cmd_backward + beq BT_CMD_FORWARD,cmd_forward + beq BT_CMD_VOL_UP,cmd_vol_up + beq BT_CMD_VOL_DOWN,cmd_vol_down + beq BT_CMD_ACCEPT_CALL,cmd_accept_call + beq BT_CMD_HANG_UP,cmd_hang_up + beq BT_CMD_REDIAL,cmd_redial + beq BT_CMD_RECOGNITION,cmd_recognition + rtn + +cmd_play_pause: + call avctp_send_play_pause + branch cmd_exit + +cmd_backward: + call avctp_send_backward + branch cmd_exit + +cmd_forward: + call avctp_send_forward + branch cmd_exit + +cmd_vol_up: + call cmd_exit + fetch 1,mem_hf_vlm_speaker + sub pdata, HFP_SPEAKER_MAX_VLM,null + branch HFP_adjust_max_volume,zero + nbranch HFP_adjust_max_volume,positive + increase 2,pdata + sub pdata, HFP_SPEAKER_MAX_VLM,null + branch HFP_adjust_max_volume,zero + nbranch HFP_adjust_max_volume,positive + store 1,mem_hf_vlm_speaker +cmd_adjust_vol: + bmark1 mark_sco_flag,send_AT_vgs + fetch 1,mem_a2dp_state + bne 0,avctp_send_vol_changed + rtn + +cmd_vol_down: + call cmd_exit + fetch 1,mem_hf_vlm_speaker + branch HFP_adjust_min_volume,blank + increase -2,pdata + branch HFP_adjust_min_volume,zero + nbranch HFP_adjust_min_volume,positive + store 1,mem_hf_vlm_speaker + branch cmd_adjust_vol + +cmd_accept_call: + call HFP_send_answer_call + branch cmd_exit + +cmd_hang_up: + call HFP_send_hang_up + branch cmd_exit + +cmd_redial: + call HFP_send_redial + branch cmd_exit + +cmd_recognition: + call HFP_send_recognition + branch cmd_exit + +cmd_increase_power_req: + jam LMP_INCR_POWER_REQ,mem_lmo_opcode2 + branch cmd_exit + +check_51_cmd_dhkey_not_accept: + call tid_set_reply + jam LMP_DHKey_Check,mem_lmi_opcode2 + branch parse_lmp_dhkey_check_reject + + +check_51cmd_check_idle: + store 1,mem_fifo_temp + call context_check_idle + branch check_51cmd_restore,zero + call context_search_plap + nrtn zero +check_51cmd_restore: + jam IPC_SKIP_CONTINUE_PROCESS,mem_ipc_skip_continue_proc + branch ui_ipc_send_cmd + + +check_51cmd_role_switch: + jam LMP_SLOT_OFFSET,mem_lmo_opcode2 + set1 mark_switch_initiated,mark + nrtn master + jam SWITCH_FLAG_INIT,mem_switch_flag + jam LMP_SWITCH_REQ ,mem_lmo_opcode2 + fetch 1,mem_connection_options + set0 CONNECTION_SWITCH,pdata + store 1,mem_connection_options + rtn + +check_51cmd_start_discovery: + jam BT_EVT_ENTER_DISCOVERABLE,mem_fifo_temp + call ipc_tx_bt_event + fetch 2,mem_ui_state_map + set1 UI_STATE_BT_DISCOVERY + store 2,mem_ui_state_map + jam 3,mem_scan_mode + rtn + +check_51cmd_stop_discovery: + jam BT_EVT_EXIT_DISCOVERABLE,mem_fifo_temp + call ipc_tx_bt_event + jam 0,mem_scan_mode + fetch 2,mem_ui_state_map + set0 UI_STATE_BT_DISCOVERY + store 2,mem_ui_state_map + rtn + +check_51cmd_reconnect: + jam hci_cmd_create_conn,mem_hci_cmd + rtn + +check_51cmd_disconnect: + jam LMP_DETACH,mem_lmo_opcode2 + jam OTHER_END_TERMINATED,mem_disconn_reason_send + rtn + +check_51cmd_sniff_test: + rtn + +check_51cmd_pincode: + jam pincode_state_pincode_ready,mem_pincode_state + branch cmd_pair + +check_51cmd_inq: + rtn +check_51cmd_stop_inq: + rtn +check_51cmd_adv: + jam ON,mem_le_adv_enable + jam ADV_IND,mem_le_adv_type + rtn +check_51cmd_stop_adv: + jam OFF,mem_le_adv_enable + rtn +check_51cmd_direct_adv: + jam ON,mem_le_adv_enable + jam ADV_DIRECT_IND,mem_le_adv_type + rtn +check_51cmd_stop_direct_adv: + jam OFF,mem_le_adv_enable + rtn +check_51cmd_le_disconnect: + branch le_send_terminate_remote_user_ended_conn + + +check_51cmd_start_scan: + jam ON,mem_le_scan_enable + rtn +check_51cmd_stop_scan: + jam OFF,mem_le_scan_enable + jam 0,mem_hci_cmd + rtn +check_51cmd_le_smp_sec_req: + branch le_send_smp_security_request +check_51cmd_hibernate: + bpatchx patch3d_4,mem_patch3d + fetch 2,mem_cb_before_hibernate + call callback_func + call ui_ipc_clean_all_fifo + branch lpm_hibernate + +check_51cmd_bb_reconn_cancel: + force page_length_timer,queue + branch timer_stop + +check_51cmd_vp_end_recover_dac: + branch vp_dac_disable + +/* +//rega:ptr to flash +ui_load_audio_from_flash: + fetch 2,mem_audio_offset + nbranch ui_load_audio_continue,blank +ui_load_audio_start: + storer rega,3,mem_flash_address + setarg mem_audio_size + store 2,mem_flash_data_address + setarg 2 + store 2,mem_flash_trans_length + call qspi_nmode + call qspi_read +ui_load_audio_continue: + fetch 2,mem_audio_size + fetcht 2,mem_audio_offset + isub temp,pdata + arg AUDIO_PCM_MAX_BLOCK,temp + call not_greater_than + copy pdata,regb +// fetch 2,core_dac_wptr + fetcht 2,core_dac_saddr + isub temp,temp + fetch 2,core_dac_len + increase 1,pdata + isub temp,pdata + copy regb,temp + call not_greater_than + rtn blank + store 2,mem_flash_trans_length +// fetch 2,core_dac_wptr + store 2,mem_flash_data_address + increase 2,rega + fetch 2,mem_audio_offset + iadd rega,pdata + store 3,mem_flash_address + call qspi_mmode + call mqspi_read + + fetch 2,mem_flash_trans_length + copy pdata,regb + fetcht 2,mem_audio_offset + iadd temp,temp + storet 2,mem_audio_offset + + fetch 2,mem_audio_offset + fetcht 2,mem_audio_size + isub temp,null + nrtn zero + fetch 2,mem_audio_size + arg 0,temp + storet 4,mem_audio_size + rtn +*/ + Index: tag/Soft/Librarier/bt_rom/program/upper_sm.prog =================================================================== --- /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/upper_sm.prog (nonexistent) +++ /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/upper_sm.prog (working copy) @@ -0,0 +1,556 @@ + +upper_init_reconnect: + call upper_clear_upper_sm + fetch 1,mem_ui_profile_supported + isolate1 support_HID,pdata + call upper_init_reconnect_hid,true + fetch 1,mem_ui_profile_supported + isolate1 support_HF_HS,pdata + call upper_init_reconnect_hf,true + rtn + +upper_reset_sm: + bpatchx patch3d_5,mem_patch3d + jam 0,mem_uppersm_disl2capch_index + jam 0,mem_major_uppersm + jam 0,mem_sub_uppersm + arg mem_uppersm_list,rega + branch fifo_out + + +upper_int_reconnect_avctp: + jam UP_MAJOR_SM_CONNECT_SERVER,mem_major_uppersm + jam UP_RECNNECT_AUDIO,mem_fifo_temp + jam UP_SUB_SM_CREAT_AVCTP,mem_sub_uppersm + branch upper_init_reconnect_single + +upper_int_reconnect_audio: + jam UP_MAJOR_SM_CONNECT_SERVER,mem_major_uppersm + jam UP_RECNNECT_AUDIO,mem_fifo_temp + jam UP_SUB_SM_CREAT_AVDTP_SIG,mem_sub_uppersm + branch upper_init_reconnect_single +upper_disconnect_all_l2cap: + fetch 1,mem_major_uppersm + rtnne 0 + jam UP_SUB_DISC_RFC_SEND_SERVER_DISC,mem_sub_uppersm + jam UP_MAJOR_SM_DISCONNECT_SERVER,mem_major_uppersm + branch upper_clear_upper_sm +upper_init_reconnect_hid: + jam UP_MAJOR_SM_CONNECT_SERVER,mem_major_uppersm + jam UP_RECNNECT_HID,mem_fifo_temp + branch upper_init_reconnect_single +upper_init_reconnect_hf: + fetch 2,mem_rfc_l2capch_ptr + nrtn blank + jam UP_MAJOR_SM_ASK_SEVRVER,mem_major_uppersm + jam UP_SUB_SM_CREAT_SDP,mem_sub_uppersm + jam UP_RECNNECT_HF,mem_fifo_temp +upper_init_reconnect_single: + arg mem_uppersm_list,rega + branch fifo_in + +upper_get_first_upper_sm: + fetch 1,mem_uppersm_list+4 + rtn +upper_clear_upper_sm: + bpatchx patch3d_6,mem_patch3d + setarg 0 + store 8,mem_uppersm_xmem_start + rtn + +upper_sm_single_step: + bpatchx patch3d_7,mem_patch3d + fetch 1,mem_lmp_conn_state + rtnbit0 RECEIVED_SETUP_COMPLETE + rtnbit0 SENT_SETUP_COMPLETE + + fetch 1,mem_major_uppersm + rtn blank + beq UP_MAJOR_SM_ASK_SEVRVER,upper_major_sm_ask_sever_process + beq UP_MAJOR_SM_CONNECT_SERVER,upper_major_sm_connect_sever_process + beq UP_MAJOR_SM_DISCONNECT_SERVER,upper_major_sm_disconnect_server_process + branch assert + +upper_major_sm_ask_sever_process: + bpatchx patch3e_0,mem_patch3e + fetch 1,mem_sub_uppersm + beq UP_SUB_SM_CREAT_SDP,upper_sub_sm_create_sdp + beq UP_SUB_SM_CREAT_SDP_WAIT,upper_sub_sm_create_sdp_wait + beq UP_SUB_SM_CONFIG_SDP,upper_sub_sm_config_sdp + beq UP_SUB_SM_CONFIG_SDP_WAIT,upper_sub_sm_config_sdp_wait + beq UP_SUB_SM_SEARCH_SERVICE,upper_sub_sm_search_service + beq UP_SUB_SM_SEARCH_SERVICE_WAIT,upper_sub_sm_search_service_wait + beq UP_SUB_SM_SEARCH_ATTRIB,upper_sub_sm_search_attrib + beq UP_SUB_SM_SEARCH_ATTRIB_WAIT,upper_sub_sm_search_wait + beq UP_SUB_SM_DISCONNECT_SDP,upper_sub_sm_sdp_disconenct + beq UP_SUB_SM_DISCONENCT_SDP_WAIT,upper_sub_sm_sdp_disconenct_wait + rtn + +upper_sub_sm_create_sdp: + jam UP_SUB_SM_CREAT_SDP_WAIT,mem_sub_uppersm + arg PSM_SDP,regd + call l2cap_send_server_conn + storer regc,2,mem_sdp_l2capch_ptr + rtn +upper_sub_sm_create_sdp_wait: + fetchr regc,2,mem_sdp_l2capch_ptr + add regc,offset_lc_state,regc + ifetch 1,regc + rtnbit0 L2CAP_CHANNEL_STATE_CONN_RES + jam UP_SUB_SM_CONFIG_SDP,mem_sub_uppersm + rtn + +upper_sub_sm_config_sdp: + //config is auto in schedule + jam UP_SUB_SM_CONFIG_SDP_WAIT,mem_sub_uppersm + rtn + +upper_sub_sm_config_sdp_wait: + fetchr regc,2,mem_sdp_l2capch_ptr + add regc,offset_lc_state,regc + ifetch 1,regc + rtnbit0 L2CAP_CHANNEL_STATE_RCV_CFG_RES + rtnbit0 L2CAP_CHANNEL_STATE_RCV_CFG_REQ + jam UP_SUB_SM_SEARCH_SERVICE,mem_sub_uppersm + rtn + +upper_sub_sm_search_service: + jam UP_SUB_SM_SEARCH_SERVICE_WAIT,mem_sub_uppersm + call upper_get_first_upper_sm + beq UP_RECNNECT_HF,upper_major_sm_search_service_audio_gateway + branch assert +upper_major_sm_search_service_audio_gateway: + arg 13,rega + setarg SDP_UUID_HS_AUDIO_GATEWAY + store 2,mem_search_uuid + fetchr regd,2,mem_sdp_l2capch_ptr + branch sdp_send_search_req + +upper_sub_sm_search_service_wait: + fetchr regc,2,mem_sdp_l2capch_ptr + add regc,offset_lc_state,regc + ifetch 1,regc + rtnbit0 L2CAP_CHANNEL_STATE_RECV_SEARCH_RES + fetch 4,mem_sdp_record_handle + branch app_bt_disconnect,blank + jam UP_SUB_SM_SEARCH_ATTRIB,mem_sub_uppersm + rtn + +upper_sub_sm_search_attrib: + jam UP_SUB_SM_SEARCH_ATTRIB_WAIT,mem_sub_uppersm + arg 19,rega + fetchr regd,2,mem_sdp_l2capch_ptr + branch sdp_send_attribute_req + +upper_sub_sm_search_wait: + fetchr regc,2,mem_sdp_l2capch_ptr + add regc,offset_lc_state,regc + ifetch 1,regc + rtnbit0 L2CAP_CHANNEL_STATE_RECV_ATTRIB_RES + jam UP_SUB_SM_DISCONNECT_SDP,mem_sub_uppersm + rtn + +upper_sub_sm_sdp_disconenct: + jam UP_SUB_SM_DISCONENCT_SDP_WAIT,mem_sub_uppersm + fetchr regd,2,mem_sdp_l2capch_ptr + branch l2cap_send_server_disconnct + +upper_sub_sm_sdp_disconenct_wait: + fetchr regc,2,mem_sdp_l2capch_ptr + add regc,offset_lc_state,regc + ifetch 1,regc + //nrtn blank + setarg 0 + store 2,mem_sdp_l2capch_ptr + jam UP_MAJOR_SM_CONNECT_SERVER,mem_major_uppersm + jam UP_SUB_SM_CREAT_RFCOMM,mem_sub_uppersm + rtn + +upper_major_sm_connect_sever_process: + bpatchx patch3e_1,mem_patch3e + call upper_get_first_upper_sm + beq UP_RECNNECT_HF,upper_major_connect_hf + beq UP_RECNNECT_HID,upper_major_connect_hid + beq UP_RECNNECT_AUDIO,upper_major_connect_audio + branch assert +upper_major_connect_hf: + fetch 1,mem_sub_uppersm + beq UP_SUB_SM_CREAT_RFCOMM,upper_sub_connect_rfcomm + beq UP_SUB_SM_CREAT_RFCOMM_WAIT,upper_sub_connect_rfcomm_wait + beq UP_SUB_SM_CONFIG_RFCOMM,upper_sub_config_rfcomm + beq UP_SUB_SM_CONFIG_RFCOMM_WAIT,upper_sub_config_rfcomm_wait + beq UP_SUB_SM_RFCOMM_SIGNAL_SABM,upper_sub_rfcomm_singnal_connect + beq UP_SUB_SM_RFCOMM_SIGNAL_SABM_WAIT,upper_sub_rfcomm_singnal_connect_wait + beq UP_SUB_SM_RFCOMM_SIGNAL_CMD_PN,upper_sub_rfcomm_signal_cmd_pn + beq UP_SUB_SM_RFCOMM_SIGNAL_CMD_PN_WAIT,upper_sub_rfcomm_signal_cmd_pn_wait + beq UP_SUB_SM_RFCOMM_SERVER_SABM,upper_sub_connect_rfcomm_server + beq UP_SUB_SM_RFCOMM_SERVER_SABM_WAIT,upper_sub_connect_rfcomm_server_wait + beq UP_SUB_SM_RFCOMM_SEVER_CMD_MS,upper_sub_connect_server_cmd_ms + beq UP_SUB_SM_RFCOMM_SEVER_CMD_MS_WAIT,upper_sub_connect_server_cmd_ms_wait + branch assert + +upper_sub_connect_rfcomm: + fetch 2,mem_rfc_l2capch_ptr + nbranch upper_reset_sm,blank + jam UP_SUB_SM_CREAT_RFCOMM_WAIT,mem_sub_uppersm + arg PSM_RFCOMM,regd + call l2cap_send_server_conn + storer regc,2,mem_rfc_l2capch_ptr + rtn + +upper_sub_connect_rfcomm_wait: + fetchr regc,2,mem_rfc_l2capch_ptr + add regc,offset_lc_state,regc + ifetch 1,regc + rtnbit0 L2CAP_CHANNEL_STATE_CONN_RES + jam UP_SUB_SM_CONFIG_RFCOMM,mem_sub_uppersm + rtn +upper_sub_config_rfcomm: + //config is auto in schedule + jam UP_SUB_SM_CONFIG_RFCOMM_WAIT,mem_sub_uppersm + rtn + +upper_sub_config_rfcomm_wait: + fetchr regc,2,mem_rfc_l2capch_ptr + add regc,offset_lc_state,regc + ifetch 1,regc + rtnbit0 L2CAP_CHANNEL_STATE_RCV_CFG_RES + rtnbit0 L2CAP_CHANNEL_STATE_RCV_CFG_REQ + jam UP_SUB_SM_RFCOMM_SIGNAL_SABM,mem_sub_uppersm + rtn + +upper_sub_rfcomm_singnal_connect: + fetchr regd,2,mem_rfc_l2capch_ptr + call rfc_send_signal_sabm + jam UP_SUB_SM_RFCOMM_SIGNAL_SABM_WAIT,mem_sub_uppersm + fetch 2,mem_rfc_server_state + set1 RFC_SIGNAL_SABM,pdata + store 2,mem_rfc_server_state + rtn + +upper_sub_rfcomm_singnal_connect_wait: + fetch 2,mem_rfc_server_state + rtnbit0 RFC_SIGNAL_UA + rtnbit0 RFC_SIGNAL_SABM + jam UP_SUB_SM_RFCOMM_SIGNAL_CMD_PN,mem_sub_uppersm + rtn + +upper_sub_rfcomm_signal_cmd_pn: + fetchr regd,2,mem_rfc_l2capch_ptr + call rfc_send_signal_cmd_pn + fetch 2,mem_rfc_server_state + set1 RFC_SIGNAL_PN_CMD,pdata + store 2,mem_rfc_server_state + jam UP_SUB_SM_RFCOMM_SIGNAL_CMD_PN_WAIT,mem_sub_uppersm + rtn + +upper_sub_rfcomm_signal_cmd_pn_wait: + fetch 2,mem_rfc_server_state + rtnbit0 RFC_SIGNAL_PN_RES + jam UP_SUB_SM_RFCOMM_SERVER_SABM,mem_sub_uppersm + rtn + +upper_sub_connect_rfcomm_server: + fetchr regd,2,mem_rfc_l2capch_ptr + call rfc_send_server_sabm + fetch 2,mem_rfc_server_state + set1 RFC_SERVER_SABM + store 2,mem_rfc_server_state + jam UP_SUB_SM_RFCOMM_SERVER_SABM_WAIT,mem_sub_uppersm + fetch 1,mem_profile_channel + lshift3 pdata,pdata + or_into 3,pdata + arg mem_HIUfcs_SPP,temp + storet 2,mem_contw_temp + branch rfcomm_save_FCS_uih + +upper_sub_connect_rfcomm_server_wait: + fetch 2,mem_rfc_server_state + rtnbit0 RFC_SERVER_UA + jam UP_SUB_SM_RFCOMM_SEVER_CMD_MS ,mem_sub_uppersm + rtn + +upper_sub_connect_server_cmd_ms: + jam UP_SUB_SM_RFCOMM_SEVER_CMD_MS_WAIT,mem_sub_uppersm + rtn + +upper_sub_connect_server_cmd_ms_wait: + fetch 2,mem_rfc_server_state + rtnne RFCOMM_CHANNEL_SETUP_COMPLETE + branch upper_reset_sm + +upper_major_sm_disconnect_server_process: + fetch 1,mem_sub_uppersm + beq UP_SUB_DISC_RFC_SEND_SERVER_DISC,upper_sub_sm_hf_send_sever_disc + beq UP_SUB_DISC_RFC_SEND_SERVER_DISC_WAIT,upper_sub_sm_hf_wait_ua + beq UP_SUB_DISC_RFC_SEND_SIGNAL_DISC,upper_sub_sm_hf_send_signal_disc + branch upper_sub_sm_disconnect_l2cap + +upper_sub_sm_hf_send_sever_disc: + fetch 2,mem_rfc_l2capch_ptr + copy pdata,regd + branch upper_sub_sm_start_disc_l2cap,blank + fetch 2,mem_rfc_server_state + bne RFCOMM_CHANNEL_SETUP_COMPLETE,upper_sub_sm_hf_send_signal_disc + call rfc_send_server_disc + jam UP_SUB_DISC_RFC_SEND_SERVER_DISC_WAIT,mem_sub_uppersm + rtn + +upper_sub_sm_hf_wait_ua: + fetch 2,mem_rfc_server_state + rtnne 0 + jam UP_SUB_DISC_RFC_SEND_SIGNAL_DISC,mem_sub_uppersm + rtn + +upper_sub_sm_hf_send_signal_disc: + fetchr regd,2,mem_rfc_l2capch_ptr + call rfc_send_signal_disc +upper_sub_sm_start_disc_l2cap: + jam UP_SUB_SM_DISC_L2CAPCH,mem_sub_uppersm + rtn + +upper_sub_sm_disconnect_l2cap: + bpatchx patch3e_2,mem_patch3e + fetch 1,mem_uppersm_disl2capch_index + beq L2CAP_CHANNEL_COUNT,upper_major_sm_disconnect_server_complete + copy pdata,regd + mul32 regd,L2CAP_CHANNEL_SIZE,regd + setarg mem_l2cap_ch_info + iadd regd,regd + add regd,offset_lc_state,contr + ifetch 1,contr + and pdata,0x3,pdata + bne 3,upper_major_sm_disconnect_server_next + fetch 1,mem_sub_uppersm + beq UP_SUB_SM_DISC_L2CAPCH_WAIT,upper_major_sm_disconnect_server_process_wait + jam UP_SUB_SM_DISC_L2CAPCH_WAIT,mem_sub_uppersm + branch l2cap_send_server_disconnct +upper_major_sm_disconnect_server_process_wait: + ifetch 6,regd + nrtn blank +upper_major_sm_disconnect_server_next: + jam UP_SUB_SM_DISC_L2CAPCH,mem_sub_uppersm + fetch 1,mem_uppersm_disl2capch_index + increase 1,pdata + store 1,mem_uppersm_disl2capch_index + rtn +upper_major_sm_disconnect_server_complete: + call upper_reset_sm + branch app_bt_disconnect + +upper_major_connect_hid: + fetch 1,mem_sub_uppersm + beq UP_SUB_SM_CREAT_HID,upper_sub_connect_hid + beq UP_SUB_SM_CREAT_HID_WAIT,upper_sub_connect_hid_wait + beq UP_SUB_SM_CONFIG_HID,upper_sub_config_hid + beq UP_SUB_SM_CONFIG_HID_WAIT,upper_sub_config_hid_wait + beq UP_SUB_SM_CREAT_HIDINT,upper_sub_connect_hidint + beq UP_SUB_SM_CREAT_HIDINT_WAIT,upper_sub_connect_hidint_wait + beq UP_SUB_SM_CONFIG_HIDINT,upper_sub_config_hidint + beq UP_SUB_SM_CONFIG_HIDINT_WAIT,upper_sub_config_hidint_wait + branch assert +upper_sub_connect_hid: + jam UP_SUB_SM_CREAT_HID_WAIT,mem_sub_uppersm + arg PSM_HID_control,regd + call l2cap_send_server_conn + storer regc,2,mem_hid_l2capch_ptr + rtn +upper_sub_connect_hid_wait: + fetchr regc,2,mem_hid_l2capch_ptr + add regc,offset_lc_state,regc + ifetch 1,regc + rtnbit0 L2CAP_CHANNEL_STATE_CONN_RES + jam UP_SUB_SM_CONFIG_HID,mem_sub_uppersm + rtn +upper_sub_config_hid: + //config is auto in schedule + jam UP_SUB_SM_CONFIG_HID_WAIT,mem_sub_uppersm + rtn +upper_sub_config_hid_wait: + fetchr regc,2,mem_hid_l2capch_ptr + add regc,offset_lc_state,regc + ifetch 1,regc + rtnbit0 L2CAP_CHANNEL_STATE_RCV_CFG_RES + rtnbit0 L2CAP_CHANNEL_STATE_RCV_CFG_REQ + jam UP_SUB_SM_CREAT_HIDINT,mem_sub_uppersm + rtn +upper_sub_connect_hidint: + jam UP_SUB_SM_CREAT_HIDINT_WAIT,mem_sub_uppersm + arg PSM_HID_interrupt,regd + call l2cap_send_server_conn +sav_hid_interrupt_l2cap_ptr: + storer regc,2,mem_hidint_l2capch_ptr + rtn +upper_sub_connect_hidint_wait: + fetchr regc,2,mem_hidint_l2capch_ptr + add regc,offset_lc_state,regc + ifetch 1,regc + rtnbit0 L2CAP_CHANNEL_STATE_CONN_RES + jam UP_SUB_SM_CONFIG_HIDINT,mem_sub_uppersm + rtn +upper_sub_config_hidint: + jam UP_SUB_SM_CONFIG_HIDINT_WAIT,mem_sub_uppersm + rtn +upper_sub_config_hidint_wait: + fetchr regc,2,mem_hidint_l2capch_ptr + add regc,offset_lc_state,regc + ifetch 1,regc + rtnbit0 L2CAP_CHANNEL_STATE_RCV_CFG_RES + rtnbit0 L2CAP_CHANNEL_STATE_RCV_CFG_REQ + branch upper_reset_sm + +upper_major_connect_audio: + fetch 1,mem_sub_uppersm + beq UP_SUB_SM_CREAT_AVDTP_SIG,upper_sub_connect_avdtp_sig + beq UP_SUB_SM_CREAT_AVDTP_SIG_WAIT,upper_sub_connect_avdtp_sig_wait + beq UP_SUB_SM_CONFIG_AVDTP_SIG,upper_sub_config_avdtp_sig + beq UP_SUB_SM_CONFIG_AVDTP_SIG_WAIT,upper_sub_config_avdtp_sig_wait + beq UP_SUB_SM_AVDTP_DISCOVER,upper_sub_avdtp_sig_discover + beq UP_SUB_SM_AVDTP_DISCOVER_WAIT,upper_sub_avdtp_sig_discover_wait + beq UP_SUB_SM_AVDTP_GETCAP,upper_sub_avdtp_sig_getcap + beq UP_SUB_SM_AVDTP_GETCAP_WAIT,upper_sub_avdtp_sig_getcap_wait + beq UP_SUB_SM_AVDTP_SETCONF,upper_sub_avdtp_sig_setconf + beq UP_SUB_SM_AVDTP_SETCONF_WAIT,upper_sub_avdtp_sig_setconf_wait + beq UP_SUB_SM_AVDTP_OPEN,upper_sub_avdtp_sig_open + beq UP_SUB_SM_AVDTP_OPEN_WAIT,upper_sub_avdtp_sig_open_wait + beq UP_SUB_SM_CREAT_AVDTP_MEDIA,upper_sub_connect_avdtp_media + beq UP_SUB_SM_CREAT_AVDTP_MEDIA_WAIT,upper_sub_connect_avdtp_media_wait + beq UP_SUB_SM_CONFIG_AVDTP_MEDIA,upper_sub_config_avdtp_media + beq UP_SUB_SM_CONFIG_AVDTP_MEDIA_WAIT,upper_sub_config_avdtp_media_wait + beq UP_SUB_SM_CREAT_AVCTP,upper_sub_connect_avctp + beq UP_SUB_SM_CREAT_AVCTP_WAIT,upper_sub_connect_avctp_wait + beq UP_SUB_SM_CONFIG_AVCTP,upper_sub_config_avctp + beq UP_SUB_SM_CONFIG_AVCTP_WAIT,upper_sub_config_avctp_wait + branch assert + +upper_sub_connect_avdtp_sig: + fetch 2,mem_avdtpsignal_l2capch_ptr + nbranch upper_reset_sm,blank + jam UP_SUB_SM_CREAT_AVDTP_SIG_WAIT,mem_sub_uppersm + arg PSM_AVDTP,regd + call l2cap_send_server_conn + storer regc,2,mem_avdtpsignal_l2capch_ptr + rtn +upper_sub_connect_avdtp_sig_wait: + fetchr regc,2,mem_avdtpsignal_l2capch_ptr + add regc,offset_lc_state,regc + ifetch 1,regc + rtnbit0 L2CAP_CHANNEL_STATE_CONN_RES + jam UP_SUB_SM_CONFIG_AVDTP_SIG,mem_sub_uppersm + rtn +upper_sub_config_avdtp_sig: + jam UP_SUB_SM_CONFIG_AVDTP_SIG_WAIT,mem_sub_uppersm + rtn +upper_sub_config_avdtp_sig_wait: + fetchr regc,2,mem_avdtpsignal_l2capch_ptr + add regc,offset_lc_state,regc + ifetch 1,regc + rtnbit0 L2CAP_CHANNEL_STATE_RCV_CFG_RES + rtnbit0 L2CAP_CHANNEL_STATE_RCV_CFG_REQ + jam UP_SUB_SM_AVDTP_DISCOVER,mem_sub_uppersm + rtn +upper_sub_avdtp_sig_discover: + jam UP_SUB_SM_AVDTP_DISCOVER_WAIT,mem_sub_uppersm + branch avd_signal_send_discover + +upper_sub_avdtp_sig_discover_wait: + fetch 1,mem_audio_src_endpoint + rtn blank + jam UP_SUB_SM_AVDTP_GETCAP,mem_sub_uppersm + rtn + +upper_sub_avdtp_sig_getcap: + jam UP_SUB_SM_AVDTP_GETCAP_WAIT,mem_sub_uppersm + branch avd_signal_send_getcap + + +upper_sub_avdtp_sig_getcap_wait: + fetch 1,mem_audio_src_endpoint_state + rtnbit0 AVD_SRC_ENDPOINT_GETCAP + jam UP_SUB_SM_AVDTP_SETCONF,mem_sub_uppersm + rtn + +upper_sub_avdtp_sig_setconf: + jam UP_SUB_SM_AVDTP_SETCONF_WAIT,mem_sub_uppersm + branch avd_signal_send_setconf + +upper_sub_avdtp_sig_setconf_wait: + fetch 1,mem_audio_src_endpoint_state + rtnbit0 AVD_SRC_ENDPOINT_SETCONF + jam UP_SUB_SM_AVDTP_OPEN,mem_sub_uppersm + rtn + +upper_sub_avdtp_sig_open: + call a2dp_send_evt_open + jam A2DP_STATE_OPEN,mem_a2dp_state + jam UP_SUB_SM_AVDTP_OPEN_WAIT,mem_sub_uppersm + call avd_signal_send_open + jam BT_EVT_A2DP_OPEN,mem_fifo_temp + branch ui_ipc_send_event + +upper_sub_avdtp_sig_open_wait: + fetch 1,mem_audio_src_endpoint_state + rtnbit0 AVD_SRC_ENDPOINT_OPEN + jam UP_SUB_SM_CREAT_AVDTP_MEDIA,mem_sub_uppersm + rtn + +upper_sub_connect_avdtp_media: + jam UP_SUB_SM_CREAT_AVDTP_MEDIA_WAIT,mem_sub_uppersm + arg PSM_AVDTP,regd + call l2cap_send_server_conn + storer regc,2,mem_avdtpmedia_l2capch_ptr + rtn + +upper_sub_connect_avdtp_media_wait: + fetchr regc,2,mem_avdtpmedia_l2capch_ptr + add regc,offset_lc_state,regc + ifetch 1,regc + rtnbit0 L2CAP_CHANNEL_STATE_CONN_RES + jam UP_SUB_SM_CONFIG_AVDTP_MEDIA,mem_sub_uppersm + rtn + +upper_sub_config_avdtp_media: + jam UP_SUB_SM_CONFIG_AVDTP_MEDIA_WAIT,mem_sub_uppersm + rtn + +upper_sub_config_avdtp_media_wait: + fetchr regc,2,mem_avdtpsignal_l2capch_ptr + add regc,offset_lc_state,regc + ifetch 1,regc + rtnbit0 L2CAP_CHANNEL_STATE_RCV_CFG_RES + rtnbit0 L2CAP_CHANNEL_STATE_RCV_CFG_REQ + jam UP_SUB_SM_CREAT_AVCTP,mem_sub_uppersm + rtn + +upper_sub_connect_avctp: + fetchr regc,2,mem_avr_l2capch_ptr + add regc,offset_lc_state,regc + ifetch 1,regc + nbranch upper_reset_sm, blank + jam UP_SUB_SM_CREAT_AVCTP_WAIT,mem_sub_uppersm + arg PSM_AVCTP,regd + call l2cap_send_server_conn + storer regc,2,mem_avr_l2capch_ptr + rtn + +upper_sub_connect_avctp_wait: + fetchr regc,2,mem_avr_l2capch_ptr + add regc,offset_lc_state,regc + ifetch 1,regc + rtnbit0 L2CAP_CHANNEL_STATE_CONN_RES + jam UP_SUB_SM_CONFIG_AVCTP,mem_sub_uppersm + rtn + +upper_sub_config_avctp: + jam UP_SUB_SM_CONFIG_AVCTP_WAIT,mem_sub_uppersm + rtn + +upper_sub_config_avctp_wait: + fetchr regc,2,mem_avr_l2capch_ptr + add regc,offset_lc_state,regc + ifetch 1,regc + rtnbit0 L2CAP_CHANNEL_STATE_RCV_CFG_RES + rtnbit0 L2CAP_CHANNEL_STATE_RCV_CFG_REQ + branch upper_reset_sm + + Index: tag/Soft/Librarier/bt_rom/program/usb.prog =================================================================== --- /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/usb.prog (nonexistent) +++ /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/usb.prog (working copy) @@ -0,0 +1,999 @@ +ifdef COMPILE_USB + +usb_isr: + bpatchx patch3e_3,mem_patch3e + fetch 1,core_usb_status + isolate1 USB_STATUS_RESET,pdata + call usb_init,true + fetch 1,core_usb_status + store 1,core_usb_status + store 1,mem_usb_status + call usb_nak_state_judge + call usb_rx + call usb0_tx + branch usb_tx + +usb_init: + bpatchx patch3e_4,mem_patch3e + jam 0x00,core_usb_config +ifdef SIM + nop 10 +else + nop 10000 +endif + jam 0xc0,core_usb_trig + fetch 2,core_clkoff + set0 CLOCK_OFF_USB,pdata + store 2,core_clkoff + jam 0x0,core_usb_hmode + jam 0x3c,core_usb_config + setarg mem_usb_rxbuf + store 2,core_usb_rx_saddr + store 2,core_usb_rxptr + setarg mem_usb_rxbuf_end + store 2,core_usb_rx_eaddr +ifndef MRAMUSB + jam 0x4,core_usb_hmode +else + jam 0xc,core_usb_hmode +endif + jam 0,core_usb_addr + jam DEV_DEFAULT,mem_usb0_state + setarg 0 + store 1,mem_usb_state + store 1,mem_usb_tx_enable + store 1,mem_usb_remote_wakeup + store 1,mem_usb_ep0_stall_status + store 1,mem_usb_ep1_stall_status + store 1,mem_usb_ep2_stall_status + store 1,mem_usb_ep3_stall_status + store 2,mem_dsc_info_data_pointer + store 1,mem_dsc_info_len + store 1,mem_usb0_data_ready_report + store 1,mem_usb_tx_win_enable + store 1,mem_usb_tx_mac_enable + store 1,mem_usb_clear_remote_wakeup + store 1,mem_usb_device_enumeration_endflag + store 1,mem_usb_wakestate_onetime_flag + store 1,mem_usb_mac_wakeup_trig + store 1,mem_usb_set_high_addr_flag + store 1,mem_usb_set_protocol_status + store 1,mem_usb_get_protocol_flag + store 1,mem_usb_idle_flag + store 1,mem_usb_clear_halt + arg mem_usb_setup,contw + arg 9,loopcnt + call memset0 + arg mem_usb0_get_report_data,contw + arg 8,loopcnt + call memset0 + jam 0xff,core_usb_status + branch usb_tx_fifo_release + + +usb_nak_state_judge: + fetch 1,mem_usb_status + bbit1 USB_STATUS_NAK,usb_nak_state_timer_init + rtn + +usb_nak_state_timer_init: + call usb0_attached_state_judge + call timer_reinit + setarg TIMER_NAK_DELAY + arg TIMER_NAK,queue + branch timer_init + +usb0_attached_state_judge: + fetch 1,mem_usb_state + bne USB_CONNECTED,usb_clear_halt_dispose + jam 0,mem_usb_wakestate_onetime_flag + jam 0,mem_usb_mac_wakeup_trig + rtn +usb_clear_halt_dispose: + fetch 1,mem_usb_clear_halt + rtn blank + jam 0,mem_usb_clear_halt + jam USB_CONNECTED,mem_usb_state + jam 1,mem_usb_device_enumeration_endflag + rtn + + +usb_rx_no_data: + fetch 1,mem_usb_status + bbit1 USB_STATUS_SETUP,usb_class_type + rtn + + +usb_rx_data: + fetch 1,core_usb_txbusy + rtnbit1 USB_STATUS_RXEMPTY +//ifdef MRAMUSB +// enable mram +//endif + fetchr contus,2,core_usb_rx_saddr + fetchr contue,2,core_usb_rx_eaddr + fetchr contu,2,core_usb_rxptr + ifetch 2,contu + rshift8 pdata,temp + rshift4 temp,temp // temp is endpoint + arg 0xfff,contr + iand contr,loopcnt + copy loopcnt,rega +usb_rx_read: + ifetch 1,contu + istore 1,contw + loop usb_rx_read + storer contu,2,core_usb_rxptr + storer rega,2,mem_usb_read_len + rtn +usb_data_rx: + rtn + +usb_rx: + bpatchx patch3e_5,mem_patch3e + fetch 1,mem_usb_status + rtnbit0 USB_STATUS_RXREADY + arg mem_usb_setup,contw + call usb_rx_data + copy temp,pdata + beq 0,usb0_rx + branch usb_data_rx +usb0_rx: + fetch 1,mem_usb_read_len + sub pdata,7,null + rtn positive +usb_class_type: + bpatchx patch3e_6,mem_patch3e + fetch 1,mem_usb_setup_bmRequestType + and_into 0x80,pdata + beq IN_DEVICE,usb_in_device + beq OUT_DEVICE,usb_out_device + branch assert + +usb_in_device: + fetch 1,mem_usb_setup_bmRequestType + rshift4 pdata,pdata + rshift pdata,pdata + and_into 0x03,pdata + beq STANDARD_REQ,usb_in_standard_req + beq CLASS_REQ,usb_in_class_req + beq MANUFACTURER_REQ,usb_in_manufacturer_req + branch assert + +usb_out_device: + fetch 1,mem_usb_setup_bmRequestType + rshift4 pdata,pdata + rshift pdata,pdata + and_into 0x03,pdata + beq STANDARD_REQ,usb_out_standard_req + beq CLASS_REQ,usb_out_class_req + beq MANUFACTURER_REQ,usb_out_manufacturer_req + branch assert + +usb_in_standard_req: + fetch 1,mem_usb_setup_bRequest + beq GET_CONFIGURATION,usb0_request_get_configuration + beq GET_DESCRIPTOR,usb0_request_get_descriptor + beq GET_INTERFACE,usb0_request_get_interface + beq GET_STATUS,usb0_request_get_status + branch usb0_force_stall + +usb_in_class_req: + fetch 1,mem_usb_setup_bRequest + beq GET_IDLE,usb_get_idle + beq GET_REPORT,usb_get_report + beq GET_PROTOCOL,usb_get_protocol_req + branch usb0_force_stall + +usb_in_manufacturer_req: + branch usb0_force_stall + +usb_out_standard_req: + fetch 1,mem_usb_setup_bRequest + beq CLEAR_FEATURE,usb0_request_clear_feature + beq SET_FEATURE,usb0_request_set_feature + beq SET_ADDRESS,usb0_request_set_address + beq SET_CONFIGURATION,usb0_request_set_configuration + beq SET_INTERFACE,usb0_request_set_interface + beq SET_DESCRIPTOR,usb0_force_stall + branch usb0_force_stall + +usb_out_class_req: + fetch 1,mem_usb_setup_bRequest + beq SET_IDLE,usb_set_idle + beq SET_REPORT,usb_set_report + beq SET_PROTOCOL,usb_set_protocol_req + branch usb0_force_stall + +usb_out_manufacturer_req: + branch usb0_force_stall + +usb0_force_stall: + fetch 1,core_usb_stall + set1 0,pdata + store 1,core_usb_stall + branch usb0_reply_zerolen + +usb0_reply_zerolen: + jam 0x10,core_usb_trig + rtn + +usb0_request_get_configuration: + fetch 1,mem_usb_setup_bmRequestType + bne IN_DEVICE,usb0_force_stall + fetch 1,mem_usb_setup_wIndex + bne 0,usb0_force_stall + fetch 1,mem_usb_setup_wIndex+1 + bne 0,usb0_force_stall + fetch 1,mem_usb_setup_bLength + bne 1,usb0_force_stall + fetch 1,mem_usb_setup_bLengthH + bne 0,usb0_force_stall + fetch 1,mem_usb_setup_bValue + bne 0,usb0_force_stall + fetch 1,mem_usb_setup_bValue+1 + bne 0,usb0_force_stall + fetch 1,mem_usb0_state + beq DEV_CONFIGURED,usb0_request_get_cfg_dev_cfg + beq DEV_ADDRESS,usb0_request_get_cfg_dev_addr + branch usb0_force_stall +//Return current config : 1 +usb0_request_get_cfg_dev_cfg: + arg 1,regb + branch usb_send_ones_packet +//Config do not work, return default config : 0 +usb0_request_get_cfg_dev_addr: + arg 1,regb + branch usb_send_zero_packet + +usb0_request_get_descriptor: + bpatchx patch3e_7,mem_patch3e + set0 mark_isstr,mark + fetch 1,mem_usb_setup_bValueH + beq DSC_DEVICE,dsc_device_info + beq DSC_CONFIG,dsc_config_info + beq DSC_STRING,dsc_string_info + beq DSC_HID,dsc_hid_info + beq DSC_HID_REPORT,dsc_hid_report_info + branch usb0_force_stall + +dsc_hid_info: + jam 0,mem_usb_get_protocol_flag + fetch 1,mem_usb_setup_wIndex + beq 0,dsc_hid_info_interface0 + beq 1,dsc_hid_info_interface1 + branch usb0_force_stall +//class_descriptor hid_descriptor--keyboard +dsc_hid_info_interface0: + arg mem_confdesc+19,rega + fetchr regb,1,mem_confdesc+19 + branch usb0_respond +//class_descriptor hid_descriptor--mouse +dsc_hid_info_interface1: + arg mem_confdesc+44,rega + fetchr regb,1,mem_confdesc+44 + branch usb0_respond + +dsc_device_info: +//input : pdata : data poniter +//input : temp: data len +//sets the data pointer and len to correct descriptor + fetch 1,mem_usb_set_high_addr_flag + ncall usb_set_high_addr,blank + setarg mem_devicedesc + fetcht 1,mem_devicedesc +dsc_info_set_data_len: + store 2,mem_dsc_info_data_pointer + storet 1,mem_dsc_info_len + fetch 1,mem_usb_setup_bLength + isub temp,null + nbranch dsc_info_set_current_data_len,positive +dsc_info_set_initial_data_len: + fetch 1,mem_dsc_info_len +dsc_info_set_data_size_completed: + iforce regb + fetch 2,mem_dsc_info_data_pointer + add pdata,1,pdata + iforce rega + branch usb0_respond +dsc_info_set_current_data_len: + fetch 1,mem_usb_setup_bLength + branch dsc_info_set_data_size_completed + +usb_set_high_addr: + fetch 1,core_usb_addr + ncall usb0_set_addr,blank + jam 0,mem_usb_set_high_addr_flag + rtn +usb0_set_addr: + fetch 1,core_usb_addr + set1 7,pdata + store 1,core_usb_addr + rtn + +dsc_config_info: + setarg mem_confdesc + fetcht 1,mem_confdesc + branch dsc_info_set_data_len + +dsc_string_info: + fetch 1,mem_usb_setup_bValue + sub pdata,3,null + nbranch usb0_force_stall,positive + fetch 1,mem_usb_setup_bValue + arg mem_string0,rega + beq 0,usb0_respond_length + set1 mark_isstr,mark + arg mem_string1,rega + beq 1,usb0_respond_length + arg mem_string2,rega + beq 2,usb0_respond_length + arg mem_string3,rega + beq 3,usb0_respond_length + rtn + +dsc_hid_report_info: + fetch 2,mem_usb_setup_wIndex + beq 1,dsc_hid_report_info0 + arg mem_hidreportdesc_kb,rega + branch usb0_respond_length +dsc_hid_report_info0: + jam 1,mem_usb_device_enumeration_endflag + jam USB_GOT_REPORT_REQ,mem_usb_state + arg mem_hidreportdesc_m,rega + branch usb0_respond_length + + +usb0_request_get_interface: + fetch 1,mem_usb0_state + bne DEV_CONFIGURED,usb0_force_stall + fetch 1,mem_usb_setup_bmRequestType + bne IN_INTERFACE,usb0_force_stall + fetch 1,mem_usb_setup_bValue + bne 0,usb0_force_stall + fetch 1,mem_usb_setup_bValueH + bne 0,usb0_force_stall + fetch 1,mem_usb_setup_bLength + bne 1,usb0_force_stall + fetch 1,mem_usb_setup_bLengthH + bne 0,usb0_force_stall + fetch 1,mem_usb_setup_wIndex + bne 0,usb0_force_stall + fetch 1,mem_usb_setup_wIndex+1 + bne 0,usb0_force_stall + arg 1,regb + branch usb_send_zero_packet + + +usb0_request_get_status: + fetch 1,mem_usb0_state + beq DEV_DEFAULT,usb0_force_stall + fetch 1,mem_usb_setup_bValue + bne 0,usb0_force_stall + fetch 1,mem_usb_setup_bValueH + bne 0,usb0_force_stall + fetch 1,mem_usb_setup_bLength + bne 2,usb0_force_stall + fetch 1,mem_usb_setup_bLengthH + bne 0,usb0_force_stall + fetch 1,mem_usb_setup_wIndex+1 + bne 0,usb0_force_stall + fetch 1,mem_usb_setup_bmRequestType + beq IN_DEVICE,usb0_get_status_in_device + beq IN_INTERFACE,usb0_get_status_in_interface + beq IN_ENDPOINT,usb0_get_status_in_endpoint + branch usb0_force_stall + +usb0_get_status_in_device: + fetch 1,mem_usb_setup_wIndex + bne 0,usb0_force_stall + arg 2,regb + fetch 1,mem_usb_remote_wakeup + beq 0x01,usb_send_two_packet +//regb:length +usb_send_zero_packet: + arg mem_usb_zero_packet,rega + branch usb0_respond +usb_send_ones_packet: + arg mem_usb_ones_packet,rega + branch usb0_respond +usb_send_two_packet: + arg mem_usb_two_packet,rega + branch usb0_respond + +usb0_get_status_in_interface: + fetch 1,mem_usb0_state + bne DEV_CONFIGURED,usb0_force_stall + arg 2,regb + branch usb_send_zero_packet + +usb0_get_status_in_endpoint: + fetch 1,mem_usb0_state + bne DEV_CONFIGURED,usb0_force_stall + fetch 1,mem_usb_setup_wIndex + beq IN_EP1,usb0_get_status_in_ep_in_ep1 + beq IN_EP2,usb0_get_status_in_ep_in_ep2 + beq IN_EP3,usb0_get_status_in_ep_in_ep3 + and_into 0x7f,pdata + beq 0x00,usb0_get_status_in_ep_in_ep0 + branch usb0_force_stall + +usb0_get_status_in_ep_in_ep0: + arg 2,regb + fetch 1,mem_usb_ep0_stall_status + beq 1,usb_send_ones_packet + branch usb_send_zero_packet +usb0_get_status_in_ep_in_ep1: + arg 2,regb + fetch 1,mem_usb_ep1_stall_status + beq 1,usb_send_ones_packet + branch usb_send_zero_packet +usb0_get_status_in_ep_in_ep2: + arg 2,regb + fetch 1,mem_usb_ep2_stall_status + beq 1,usb_send_ones_packet + branch usb_send_zero_packet +usb0_get_status_in_ep_in_ep3: + arg 2,regb + fetch 1,mem_usb_ep3_stall_status + beq 1,usb_send_ones_packet + branch usb_send_zero_packet + +usb_get_idle: + jam 1,mem_usb_idle_flag + arg mem_usb_idle_rate,rega + arg 1,regb + branch usb0_respond + +usb_get_report: + fetch 2,mem_usb_setup_bValue + arg PC_GET_REPORT,temp + isub temp,null + nbranch usb0_force_stall,zero + set0 mark_isstr,mark +usb_get_report_dispose: + fetch 1,mem_usb0_data_ready_report + nbranch usb_get_report_data_success,blank + jam PC_GET_NONDATA,mem_usb0_get_report_data +usb_get_report_send_data: + fetch 1,mem_usb_setup_bLength + iforce regb + arg mem_usb0_get_report_data,rega + call usb0_respond +usb_get_report_data_release: + arg mem_usb0_get_report_data,contw + arg 8,loopcnt + branch memset0 +usb_get_report_data_success: + jam 0,mem_usb0_data_ready_report + jam PC_GET_DATA,mem_usb0_get_report_data + branch usb_get_report_send_data + +usb_get_protocol_req: + fetch 1,mem_usb_setup_bLength + bne 1,usb0_force_stall + jam 1,mem_usb_get_protocol_flag + arg 1,regb //length + fetch 1,mem_usb_set_protocol_value + beq 0,usb_get_report_protocol + beq 1,usb_get_boot_protocol + branch usb_send_zero_packet +usb_get_report_protocol: + branch usb_send_ones_packet +usb_get_boot_protocol: + branch usb_send_zero_packet + + + +//in device +usb0_request_clear_feature: + fetch 1,mem_usb0_state + bne DEV_CONFIGURED,usb0_force_stall + fetch 1,mem_usb_setup_bLength + bne 0,usb0_force_stall + fetch 1,mem_usb_setup_bLengthH + bne 0,usb0_force_stall + fetch 1,mem_usb_setup_bValueH + bne 0,usb0_force_stall + fetch 1,mem_usb_setup_wIndex+1 + bne 0,usb0_force_stall + fetch 1,mem_usb_setup_bmRequestType + beq OUT_DEVICE,usb0_request_clear_feature_out_device + beq OUT_INTERFACE,usb0_request_clear_feature_out_interface + beq OUT_ENDPOINT,usb0_request_clear_feature_out_endpoint + branch usb0_force_stall + +usb0_request_clear_feature_out_device: + fetch 1,mem_usb_setup_bValue + bne DEVICE_REMOTE_WAKEUP,usb0_force_stall + fetch 1,core_usb_config + set0 7,pdata + store 1,core_usb_config + jam 0,mem_usb_remote_wakeup + jam 1,mem_usb_clear_remote_wakeup + branch usb0_reply_zerolen + +usb0_request_clear_feature_out_interface: + branch usb0_force_stall + +usb0_request_clear_feature_out_endpoint: + fetch 1,mem_usb_setup_bValue + bne ENDPOINT_HALT,usb0_force_stall + fetch 1,mem_usb_setup_wIndex + beq IN_EP1,usb0_force_stall_ep1_in_off + beq IN_EP2,usb0_force_stall_ep2_in_off + beq IN_EP3,usb0_force_stall_ep3_in_off + and_into 0x7f,pdata + beq 0x00,usb0_force_stall_ep0_in_off + branch usb0_force_stall + +usb0_force_stall_ep0_in_off: + jam 0,mem_usb_ep0_stall_status + branch usb0_reply_zerolen +usb0_force_stall_ep1_in_off: + jam 1,mem_usb_clear_halt + jam 0,mem_usb_ep1_stall_status + branch usb0_reply_zerolen +usb0_force_stall_ep2_in_off: + jam 1,mem_usb_clear_halt + jam 0,mem_usb_ep2_stall_status + branch usb0_reply_zerolen +usb0_force_stall_ep3_in_off: + jam 1,mem_usb_clear_halt + jam 0,mem_usb_ep3_stall_status + branch usb0_reply_zerolen + + +usb0_request_set_feature: +// fetch 1,mem_usb0_state +// bne DEV_ATTACHED,usb0_force_stall + fetch 1,mem_usb_setup_bLength + bne 0,usb0_force_stall + fetch 1,mem_usb_setup_bLengthH + bne 0,usb0_force_stall + fetch 1,mem_usb_setup_bmRequestType + beq OUT_DEVICE,usb0_request_set_feature_out_device + beq OUT_INTERFACE,usb0_request_set_feature_out_interface + beq OUT_ENDPOINT,usb0_request_set_feature_out_endpoint + branch usb0_force_stall + +usb0_request_set_feature_out_device: + fetch 1,mem_usb_setup_bValue + bne DEVICE_REMOTE_WAKEUP,usb0_force_stall + fetch 1,core_usb_config + set1 7,pdata + store 1,core_usb_config + jam 1,mem_usb_remote_wakeup + jam USB_SLEEP,mem_usb_state + jam 0,mem_usb_tx_win_enable + call usb0_reply_zerolen +usb_wakeup_timer_reinit: + call timer_reinit + setarg TIMER_WAKEUP_DELAY + arg TIMER_WAKEUP,queue + branch timer_init + +usb0_request_set_feature_out_interface: + branch usb0_force_stall + +usb0_request_set_feature_out_endpoint: + fetch 1,mem_usb_setup_bValue + bne ENDPOINT_HALT,usb0_force_stall + fetch 1,mem_usb_setup_bValueH + bne 0,usb0_force_stall + fetch 1,mem_usb_setup_wIndex + beq IN_EP1,usb0_force_stall_ep1_in_on + beq IN_EP2,usb0_force_stall_ep2_in_on + beq IN_EP3,usb0_force_stall_ep3_in_on + and_into 0x7f,pdata + beq 0x00,usb0_force_stall_ep0_in_on + branch usb0_force_stall + +usb0_force_stall_ep0_in_on: + jam 1,mem_usb_ep0_stall_status + branch usb0_reply_zerolen +usb0_force_stall_ep1_in_on: + jam 1,mem_usb_ep1_stall_status + branch usb0_reply_zerolen +usb0_force_stall_ep2_in_on: + jam 1,mem_usb_ep2_stall_status + branch usb0_reply_zerolen +usb0_force_stall_ep3_in_on: + jam 1,mem_usb_ep3_stall_status + branch usb0_reply_zerolen + + +usb0_request_set_address: + fetch 1,mem_usb_setup_bmRequestType + bne OUT_DEVICE,usb0_force_stall + fetch 1,mem_usb_setup_wIndex + bne 0,usb0_force_stall + fetch 1,mem_usb_setup_wIndex+1 + bne 0,usb0_force_stall + fetch 1,mem_usb_setup_bLength + bne 0,usb0_force_stall + fetch 1,mem_usb_setup_bLengthH + bne 0,usb0_force_stall + fetch 1,mem_usb_setup_bValueH + bne 0,usb0_force_stall + fetch 1,mem_usb_setup_bValue + and_into 0x80,pdata + bne 0,usb0_force_stall + fetch 1,mem_usb_setup_bValue + bne 0,usb_usb0_state_set_dev_addr +usb_usb0_state_set_dev_default: + jam DEV_DEFAULT,mem_usb0_state +usb0_request_set_wait_address: + fetch 1,mem_usb_setup_bValue + store 1,core_usb_addr + call usb0_reply_zerolen + jam 1,mem_usb_set_high_addr_flag + rtn +usb_usb0_state_set_dev_addr: + jam DEV_ADDRESS,mem_usb0_state + branch usb0_request_set_wait_address + + +usb0_request_set_configuration: + fetch 1,mem_usb0_state + beq DEV_DEFAULT,usb0_force_stall + fetch 1,mem_usb_setup_bmRequestType + bne OUT_DEVICE,usb0_force_stall + fetch 1,mem_usb_setup_wIndex + bne 0,usb0_force_stall + fetch 1,mem_usb_setup_wIndex+1 + bne 0,usb0_force_stall + fetch 1,mem_usb_setup_bLength + bne 0,usb0_force_stall + fetch 1,mem_usb_setup_bLengthH + bne 0,usb0_force_stall + fetch 1,mem_usb_setup_bValue+1 + bne 0,usb0_force_stall + fetch 1,mem_usb_setup_bValue + sub pdata,USB_MAX_NUM_CFG,null + nbranch usb0_force_stall,positive + fetch 1,mem_usb0_state + beq DEV_ADDRESS,usb0_request_set_cfg_addr_state + beq DEV_CONFIGURED,usb0_request_set_cfg_cfg_state + branch usb0_force_stall + // This software only supports config = 0,1 +usb0_request_set_cfg_addr_state: +usb0_request_set_cfg_cfg_state: + fetch 1,mem_usb_setup_bValue //1:Configured state 0:Address state + beq 0,usb0_request_set_cfg_stay_addr_state + jam DEV_CONFIGURED,mem_usb0_state + branch usb0_reply_zerolen +usb0_request_set_cfg_stay_addr_state: + jam DEV_ADDRESS,mem_usb0_state + branch usb0_reply_zerolen + + +usb0_request_set_interface: + fetch 1,mem_usb0_state + bne DEV_CONFIGURED,usb0_force_stall + fetch 1,mem_usb_setup_bmRequestType + bne OUT_INTERFACE,usb0_force_stall + fetch 1,mem_usb_setup_bValue + bne 0,usb0_force_stall + fetch 1,mem_usb_setup_bValueH + bne 0,usb0_force_stall + fetch 1,mem_usb_setup_bLength + bne 0,usb0_force_stall + fetch 1,mem_usb_setup_bLengthH + bne 0,usb0_force_stall + fetch 1,mem_usb_setup_wIndex + bne 0,usb0_force_stall + fetch 1,mem_usb_setup_wIndex+1 + bne 0,usb0_force_stall + branch usb0_reply_zerolen + + +usb_set_idle: + bpatchx patch3f_0,mem_patch3f + jam 1,mem_usb_idle_flag + fetch 1,mem_usb_setup_bValueH + store 1,mem_usb_idle_rate + fetch 1,mem_usb_setup_wIndex + sub pdata,1,null + call usb_clear_remote_wakeup_set0,zero + fetch 1,mem_usb_state + bne USB_RESUME,usb0_reply_zerolen + jam USB_CONNECTED,mem_usb_state + call usb0_reply_zerolen + nop 30000 + nop 30000 + rtn +usb_clear_remote_wakeup_set0: + jam 1,mem_usb_device_enumeration_endflag + jam 0,mem_usb_clear_remote_wakeup + jam USB_RESUME,mem_usb_state + rtn + + +usb_set_report: + fetch 2, mem_usb0_setup_ptr + copy pdata,contw + call usb_rx_data + jam 1,mem_usb0_get_set_report + call usb_set_report_resume_judge + fetch 2,mem_usb_setup_bValue + store 2,mem_usb_setup_bValue_temp + fetch 1,mem_usb_setup_bLength //max 0x40 + iforce loopcnt + fetch 2,mem_usb0_set_report_data_ptr + fetcht 2, mem_usb0_setup_ptr + copy temp,contr + copy pdata,contw + call memcpy + branch usb0_reply_zerolen + +usb_set_report_resume_judge: + fetch 2,mem_usb_setup_bValue + arg PC_SET_REPORT_bValue,temp + isub temp,null + nrtn zero + fetch 2,mem_usb_setup_wIndex + arg PC_SET_REPORT_wIndex,temp + isub temp,null + nrtn zero + fetch 2,mem_usb_setup_bLength + arg PC_SET_REPORT_bLength,temp + isub temp,null + nrtn zero + jam 1,mem_usb_tx_win_enable + rtn + + +usb_set_protocol_req: + fetch 1,mem_usb_setup_bLength + bne 0,usb0_force_stall + fetch 1,mem_usb_setup_bValue + beq BOOT_PROTOCOL,usb_set_boot_protocol + beq REPORT_PROTOCOL,usb_set_report_protocol + branch usb0_force_stall +usb_set_boot_protocol: + jam 0,mem_usb_set_protocol_status + jam 1,mem_usb_set_protocol_value + branch usb0_reply_zerolen +usb_set_report_protocol: + jam 1,mem_usb_tx_mac_enable + jam 1,mem_usb_set_protocol_status + jam 0,mem_usb_set_protocol_value + branch usb0_reply_zerolen + + +usb0_respond_length: + ifetchr regb,1,rega + increase 1,rega +//rega=*buff,reb=size +usb0_respond: + bpatchx patch3f_1,mem_patch3f + set1 mark_usb_first_resp,mark + bmark0 mark_isstr,usb0_respond_nostr + increase 1,regb + lshift regb,regb +usb0_respond_nostr: + storer rega,2,mem_bufptr + storer regb,1,mem_remain + branch usb0_tx + +usb_no_respond_data: + arg 0,queue + branch usb_trig + + + +//mem_bufptr=*buff,mem_remain=size,loopcnt=i,rega=len +usb0_tx: + bpatchx patch3f_2,mem_patch3f + fetch 1,core_usb_txbusy + rtnbit1 0 + fetch 1,mem_remain + rtn blank + copy pdata,loopcnt + iforce temp + fetch 2,mem_usb_setup_bLength + sub pdata,EP0_PACKET_SIZE,null + branch usb0_tx_short,positive + sub loopcnt,EP0_PACKET_SIZE,null + branch usb0_tx_info,positive + force EP0_PACKET_SIZE,loopcnt + branch usb0_tx_info +usb0_tx_short: + isub loopcnt,null + branch usb0_tx_info,positive + iforce loopcnt +usb0_tx_info: + fetch 1,mem_remain + isub loopcnt,pdata + store 1,mem_remain + add loopcnt,-1,pdata + store 1,mem_usb_txbuf + bmark0 mark_isstr,usb0_tx_nostr + rshift pdata,pdata + add loopcnt,-1,pdata + store 1,mem_usb_txbuf + bmark0 mark_usb_first_resp,usb0_tx_nostr + set0 mark_usb_first_resp,mark + istoret 1,contw + setarg 3 + istore 1,contw + increase -1,loopcnt +usb0_tx_nostr: + fetch 2,mem_bufptr + copy pdata,contr +usb0_tx0: + ifetch 1,contr + istore 1,contw + bmark0 mark_isstr,usb0_tx1 + setarg 0 + istore 1,contw +usb0_tx1: + loop usb0_tx0 + copy contr,pdata + store 2,mem_bufptr //mem_bufptr += len + setarg mem_usb_txbuf + store 2,core_usb_tx_saddr0 + arg 0,queue + call usb_trig + fetch 1,mem_remain + nrtn blank + fetch 1,mem_usb_state + rtnne USB_GOT_REPORT_REQ + jam USB_CONNECTED,mem_usb_state + rtn + + + +usb_tx_ep1: + arg 1,queue + arg mem_usb_txbuf1,rega + storer rega,2,core_usb_tx_saddr1 +usb_tx_buf: + add loopcnt,-1,pdata + istore 1,rega +usb_tx_loop: + ifetch 1,contr + istore 1,contw + loop usb_tx_loop +usb_trig: + setarg 0 + qset1 pdata + store 1,core_usb_trig + rtn + +usb_tx_ep2: + arg 2,queue + arg mem_usb_txbuf2,rega + storer rega,2,core_usb_tx_saddr2 + branch usb_tx_buf + +usb_tx: + bpatchx patch3f_3,mem_patch3f + fetch 1,mem_usb_tx_enable + rtn blank + fetch 1,mem_usb_device_enumeration_endflag + branch usb_tx_fifo_release,blank + fetch 1,mem_usb_state + beq USB_SLEEP,usb_windows_wakeup + bne USB_CONNECTED,usb_tx_fifo_release + fetch 1,mem_usb_clear_remote_wakeup + nbranch usb_tx_fifo_release,blank + call usb_tx_data_ep1 + branch usb_tx_data_ep2 + +usb_tx_data_ep1: + fetch 1,core_usb_txbusy + rtnbit1 1 + fetch 1,mem_usb_tx_enable + rtnbit0 1 + fetch 1,mem_usb_tx_enable + set0 1,pdata + store 1,mem_usb_tx_enable + fetch 1,mem_usb_ep1_data + rtn blank + beq USB_EP1_KB,usb_tx_kb_normal_data + branch assert + +usb_tx_data_ep2: + fetch 1,core_usb_txbusy + rtnbit1 2 + fetch 1,mem_usb_tx_enable + rtnbit0 2 + fetch 1,mem_usb_tx_enable + set0 2,pdata + store 1,mem_usb_tx_enable + fetch 1,mem_usb_ep2_data + rtn blank + beq USB_EP2_MS,usb_tx_ms_data + beq USB_EP2_MULTIKEY,usb_tx_kb_multikey_data + branch assert + +usb_tx_fifo_release: + arg mem_usb_mouse_data,contw + arg 2,loopcnt + call memset0 + arg mem_usb_kb_data,contw + arg 2,loopcnt + call memset0 + arg mem_usb_kb_multikey,contw + arg 2,loopcnt + branch memset0 + +usb_tx_ms_data: + fetch 1,mem_usb_idle_flag + fetcht 1,mem_usb_get_protocol_flag + iand temp,pdata + branch usb_tx_ms_data_normal_mode,blank + fetcht 1,mem_usb_set_protocol_status + iadd temp,pdata + beq MAC_BOOT_MODE,usb_tx_ms_data_mac_boot_mode + branch usb_tx_ms_data_normal_mode + +usb_tx_ms_data_mac_boot_mode: + jam 0,mem_usb_ep2_data +usb_tx_ms_data_mac_boot_regroup: + fetch 1,mem_usb_mouse_data+1 //key + beq R_KEY,usb_tx_mac_boot_ms_regroup_r_or_lrkey + beq LR_KEY,usb_tx_mac_boot_ms_regroup_r_or_lrkey + fetch 1,mem_usb_mouse_data+1 //key + store 1,mem_usb_mouse_data + fetch 1,mem_usb_mouse_data+2 //x low + istore 1,contw + fetch 1,mem_usb_mouse_data+4 //y low + istore 1,contw + fetch 1,mem_usb_mouse_data+6 //wheel + istore 1,contw + arg 4,loopcnt + arg mem_usb_mouse_data,contr + branch usb_tx_ep2 + +usb_tx_ms_data_normal_mode: + jam 0,mem_usb_ep2_data +usb_tx_mac_boot_ms_regroup_r_or_lrkey: + arg 8,loopcnt + arg mem_usb_mouse_data,contr + branch usb_tx_ep2 + +usb_tx_kb_multikey_data: +// fetch 1,core_usb_txbusy +// rtnbit1 2 + jam 0,mem_usb_ep2_data + arg 3,loopcnt + arg mem_usb_kb_multikey,contr + branch usb_tx_ep2 + +usb_tx_kb_normal_data: +// fetch 1,core_usb_txbusy +// rtnbit1 1 + jam 0,mem_usb_ep1_data + arg 8,loopcnt + arg mem_usb_kb_data,contr + branch usb_tx_ep1 + +usb_inwake_state_tx_dispose: + fetch 1,mem_usb_state + beq USB_CONNECTED, usb_mac_wakeup_trig + rtn +usb_mac_wakeup_trig: + fetch 1,core_usb_config + set1 7,pdata + store 1,core_usb_config + jam 1,mem_usb_mac_wakeup_trig + rtn + +usb_windows_wakeup: + arg TIMER_WAKEUP,queue + call timer_check + nrtn blank +usb_wakeup: + fetch 1,core_usb_config + rtnbit0 7 //endpoint wakeup enable + jam 0xfc,core_usb_config + nop 30000 + jam 0x3c,core_usb_config + rtn + + +endif + Index: tag/Soft/Librarier/bt_rom/program/utility.prog =================================================================== --- /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/utility.prog (nonexistent) +++ /YC1121E/SoftCode/MCU/tag/Soft/Librarier/bt_rom/program/utility.prog (working copy) @@ -0,0 +1,1009 @@ + +right_shift_n: //rshiftN pdata,pdata + sub loopcnt,0,null + rtn zero +right_shift_n_loop: + rshift pdata,pdata + loop right_shift_n_loop + rtn + +/* lshift. 0:1 byte; 1:2byte; 2:4byte; 3:8byte; 4:16byte*/ +left_shift_n: + force 1,pdata + sub loopcnt,0,null + rtn zero +left_shift_n_loop: + lshift pdata,pdata + loop left_shift_n_loop + rtn + +push_stack: + deposit contw + store 2,mem_contw + storet 8,mem_temp + storer timeup,4,mem_timeup + storer rega,4,mem_rega + storer regb,4,mem_regb + storer regc,3,mem_regc + storer contr,2,mem_contr + rtn +pop_stack: + fetcht 8,mem_temp + fetchr timeup,4,mem_timeup + fetchr rega,4,mem_rega + fetchr regb,4,mem_regb + fetchr regc,3,mem_regc + fetch 2,mem_contw + iforce contw + fetch 2,mem_contr + iforce contr + rtn +// +save_cont_pointers: + copy contw,pdata + store 2,mem_hold_contw + copy contr,pdata + store 2,mem_hold_contr + rtn +load_cont_pointers: + fetch 2,mem_hold_contw + copy pdata,contw + fetch 2,mem_hold_contr + copy pdata,contr + rtn + +delay_10ms: + copy clkn_bt,pdata + increase 16,pdata + increase 16,pdata +delay_ms_wait: + copy clkn_bt,temp + isub temp,null + branch delay_ms_wait,positive + rtn + +memcpy96: + call memcpy32 +memcpy64: + call memcpy32 + branch memcpy32 +memcpy12: + call memcpy8 +memcpy4: + ifetch 4,contr + istore 4,contw + rtn +memcpy8: + ifetch 8,contr + istore 8,contw + rtn + +memcpy48: + ifetch 8,contr + istore 8,contw +memcpy40: + ifetch 8,contr + istore 8,contw +memcpy32: + ifetch 8,contr + istore 8,contw +memcpy24: + ifetch 8,contr + istore 8,contw +memcpy16: + ifetch 8,contr + istore 8,contw + ifetch 8,contr + istore 8,contw + rtn + +bn_zero: + force 3,loopcnt +memset0: + setarg 0 +memset8: + istore 8,contw + loop memset8 + rtn + + +memset0_8: + setarg 0 +istore8_pdata: + istore 8,contw + rtn +memset0_4: + setarg 0 +istore4_pdata: + istore 4,contw + rtn + +clear_mem_256: + force 4,loopcnt + branch memset0 +clear_mem_512: + force 8,loopcnt + branch memset0 + +clear_mem_fast: + deposit loopcnt + rtn blank + setarg 0 +set_mem_fast_loop: + increase -8,loopcnt + call istore8_pdata ,positive + rtn zero + branch set_mem_fast_loop,positive + increase 8,loopcnt +set_mem_fast_loop_four: + increase -4,loopcnt + call istore4_pdata,positive + rtn zero + branch set_mem_fast_loop_four,positive + increase 4,loopcnt + branch istore_mem_loop + +clear_mem: + deposit loopcnt + rtn blank + setarg 0 +istore_mem_loop: + istore 1,contw + loop istore_mem_loop + rtn + +set_0x55_fast: + deposit loopcnt + rtn blank + setsect 0,0x15555 + setsect 1,0x15555 + setsect 2,0x15555 + setsect 3,0x155 + branch set_mem_fast_loop + +get_contw: + fetch 2,mem_contw +get_pdata_contw: + copy pdata,contw + rtn +get_contr: + fetch 2,mem_contr +get_pdata_contr: + copy pdata,contr + rtn +store_contw: + copy contw,pdata + store 2,mem_contw + rtn +store_contr: + copy contr,pdata + store 2,mem_contr + rtn + +//contw +//regb:saddr +//regc:eaddr +//loopcnt:count +memcpy_smart: + copy regc,pdata + isub contw,temp + copy loopcnt,pdata + call not_greater_than + copy pdata,temp + copy loopcnt,pdata + copy temp,loopcnt + isub loopcnt,temp + nbranch memcpy_smart_long,zero + call memcpy + branch memcpy_smart_update_contw +memcpy_smart_long: + //copy pdata,loopcnt + call memcpy + copy temp,loopcnt + copy regb,contw + call memcpy +memcpy_smart_update_contw: + copy contw,pdata + isub regc,null + nrtn zero + copy regb,contw + rtn + + + +memcpy_fast: + deposit loopcnt + rtn blank +memcpy_fast_loop: + increase -8,loopcnt + call memcpy8,positive + rtn zero + branch memcpy_fast_loop,positive + increase 8,loopcnt +memcpy_fast_loop_four: + increase -4,loopcnt + call memcpy4,positive + rtn zero + branch memcpy_fast_loop_four,positive + increase 4,loopcnt + branch memcpy + +memcpy: + deposit loopcnt + rtn blank +memcpy_loop: + ifetch 1,contr + istore 1,contw + loop memcpy_loop + rtn + +timer_stop: + setarg 0 +timer_init: + arg mem_timers,contw + iforce temp + lshift queue,pdata + iadd contw,contw + istoret 2,contw + rtn + +timer_reinit: + arg 0,queue +timer_check: + bpatchx patch3f_4,mem_patch3f + fetcht 4,mem_last_clkn + rshift clkn_bt,pdata + store 4,mem_last_clkn + isub temp,timeup + copy timeup,temp + arg mem_timers,contr + copy contr,contw + arg 32,loopcnt +timer_loop: + ifetch 2,contr + isub temp,pdata + branch timer_counting,positive + force 0,pdata +timer_counting: + istore 2,contw + loop timer_loop + arg mem_timers,contr + lshift queue,pdata + iadd contr,contr + ifetch 2,contr + rtn + + /* lshift pdata 8*queue */ +lshift8_queue: + increase 1,queue +lshift8_queue_loop: + increase -1,queue + rtn zero + lshift8 pdata,pdata + branch lshift8_queue_loop + +xor_loop: + ifetch 4,regc + ifetcht 4,rega + ixor temp,pdata + istore 4,contw + increase 4,rega + increase 4,regc + loop xor_loop + rtn + +// 11 22 -> 22 11; 11 22 33 -> 33 22 11 +// rega:data addr ;loopnct:length +inverse_data: + copy loopcnt,pdata + sub pdata,1,null + rtn positive + iadd rega,regb + increase -1,regb + rshift loopcnt,loopcnt +inverse_loop: + ifetcht 1,rega + ifetch 1,regb + istore 1,rega + istoret 1,regb + increase -1,regb + increase 1,rega + loop inverse_loop + rtn + + /* pdata 28+16 bit add temp 26+16 bit, result in temp */ +clk_add: + iadd temp,temp + copy temp, loopcnt + setarg 3750 + isub loopcnt,pdata + rtn positive + sub pdata,0,pdata + rshift16 temp,temp + increase 1,temp + lshift16 temp,temp + ior temp,temp + rtn + +clk_diff_rt: + call clk_diff + branch clk2rt + +/* pdata -temp -> pdata, all are 28+16 bits, set user if negative */ +clk_diff: + disable user + isub temp,pdata + branch clk_diff_pos,positive + enable user + sub pdata,0,pdata +clk_diff_pos: + rtnbit0 15 + arg -61786,temp + iadd temp,pdata + set0 64,pdata + rtn + +clk2rt: + arg 0xffff,contr + iand contr,contr + rshift16 pdata,pdata + arg 3750,temp + imul32 temp,pdata + iadd contr,pdata + rtn + + /* pdata = clks in, temp = lpo out */ +clk2lpo: + lshift8 pdata,pdata + lshift4 pdata,pdata + fetcht 3,mem_clks_per_lpo + idiv temp + call wait_div_end + quotient temp + rtn + + /* rt clk -> bt+rt clk */ +clk2bt: + arg 3750,temp + idiv temp + call wait_div_end + quotient pdata + lshift16 pdata,pdata + remainder temp + ior temp,temp + rtn + + +pn9: + copy temp,alarm + setarg 0x1ff + force 0,regb +pn9_loop: + rshift3 pdata,rega + rshift rega,rega + ixor rega,rega + isolate1 0,rega + setflag true,9,pdata + rshift temp,temp + isolate1 0,pdata + setflag true,7,temp + rshift pdata,pdata + increase 1,regb + compare 0,regb,0x7 + nbranch pn9_loop,true + istoret 1,contw + loop pn9_loop + copy alarm,temp + rtn + +bcd_byte: + div pdata,10 + call wait_div_end + quotient pdata + lshift2 pdata,rega + lshift2 rega,rega + remainder pdata + ior rega,pdata + rtn + +bcd_pack: + isolate1 0,rega + branch bcd_pack_hi,true + iforce regb + rtn +bcd_pack_hi: + lshift2 pdata,pdata + lshift2 pdata,pdata + ior regb,pdata + istore 1,contw + increase -2,contw + rtn + +wait_div_end: + rtn modone + branch wait_div_end + + +bcd2: + store 8,mem_pdatatemp + force 0x20,pdata + force 8,loopcnt + arg mem_bcd,contw +lpo_clear: + istore 1,contw + loop lpo_clear + arg mem_bcd,contw + increase 7,contw + fetch 8,mem_pdatatemp +bcd_loop: + div pdata,10 + call wait_div_end + remainder pdata + or_into 0x30,pdata + istore 1,contw + increase -2,contw + quotient pdata + rtn blank + branch bcd_loop + +/* store as packed bcd digits */ +bcd: + store 8,mem_pdatatemp + force 0,pdata + store 8,mem_bcd + arg mem_bcd,contw + increase 7,contw + fetch 8,mem_pdatatemp + force 0,rega +bcd_pack_loop: + div pdata,10 + call wait_div_end + remainder pdata + call bcd_pack + increase 1,rega + quotient pdata + sub pdata,9,null + nbranch bcd_pack_loop,positive + call bcd_pack + isolate1 0,rega + rtn true + istore 1,contw + rtn + +//input: +// count:loopcnt str1:rega str2:regb +//output: +// same:set falg true ,diff set falg false +// using: +// reg:temp null flag:zero +string_compare: + ifetch 1,rega + ifetcht 1,regb + isub temp,null + nrtn zero + increase 1,rega + increase 1,regb + loop string_compare + force 0,null + rtn + + /* pdata = temp if pdata > temp */ +ceiling: + isub temp,null + nrtn positive + deposit temp + rtn + +swap: + iadd temp,pdata + isub temp,temp + isub temp,pdata + rtn + +clean_mem: + arg 0x200,loopcnt + arg 0x4000,contw + branch memset0 // clear xram at boot + +slave_savelist: + fetch 5,mem_sync_clke + store 5,mem_pdatatemp + fetch 2,mem_clks_per_lpo + istore 2,contw + setarg 0 + setflag match,7,pdata + setflag wake,6,pdata + setflag sync,5,pdata + setflag attempt,4,pdata + istore 1,contw + branch savelist_2 + + +le_savelist: + fetch 5,mem_sync_clke + store 5,mem_pdatatemp + fetch 1,mem_le_ch_mapped + istore 1,contw + fetch 2,mem_le_event_count + arg 0x0fff,contr + iand contr,pdata + setflag match,15,pdata + setflag wake,14,pdata + setflag sync,13,pdata + setflag attempt,12,pdata + istore 2,contw + branch savelist_2 +savelpo: + deposit lpo_time + branch savelist +saveclke: + store 1,mem_pdatatemp+7 + deposit clke + store 7,mem_pdatatemp + branch savelist_2 +savelist: + store 8,mem_pdatatemp +savelist_2: + fetch 1,mem_seqi + rtneq 0x3f + and_into 0x3f,pdata + lshift3 pdata,pdata + arg mem_savelist,contw + iadd contw,contw + fetch 8,mem_pdatatemp + istore 8,contw + fetch 1,mem_seqi + isolate1 7,pdata + increase 1,pdata + and_into 0x3f,pdata + setflag true,7,pdata + store 1,mem_seqi + fetch 8,mem_pdatatemp + rtn + +dirty_mem: + arg 0x800,loopcnt + arg 0,contw + setarg 0x01010101 + branch memset8 + + //cb function ptr in pdata +callback_func: + rtn blank + copy pdata,pc //rtn through cb functon. + //branch assert + + + +ice_break: + jam 0x1,core_ice_ctrl + rtn + +ice_setbp: + store 2,core_ice_break0 + fetch 1,core_ice_ctrl + set1 4,pdata + store 1,core_ice_ctrl + rtn +ice_setbp2: + store 2,core_ice_break1 + fetch 1,core_ice_ctrl + set1 6,pdata + store 1,core_ice_ctrl + rtn + +ice_set_write_bp: + store 2,core_ice_break0 + jam 0x30,core_ice_ctrl + rtn + +test_no_white: + fetch 1,core_config + set1 whiteoff_bit,pdata + store 1,core_config /* whitening off */ + rtn + +test_enable_white: + fetch 1,core_config + set0 whiteoff_bit,pdata + store 1,core_config /* whitening on */ + rtn + + + //fuction fifo_in + //rega pointer to fifo memory , *(rega+len) is the end of fifo + //mem_fifo_temp data into fifo + //assert if fifo was full +fifo_in: + bpatchx patch3f_5,mem_patch3f + ifetcht UTIL_FIFO_LEN,rega + and temp,0xff,pdata + nbranch fifo_in_push,blank + rshift8 temp,pdata + istore UTIL_FIFO_LEN,rega +fifo_in_push: + increase UTIL_FIFO_LEN+UTIL_FIFO_OFFSET,rega + ifetch 1,rega + nbranch assert,blank //fifo full + fetch 1,mem_fifo_temp + istore 1,rega + rtn + + //fuction fifo_out + //rega pointer to fifo memory + //pdata data from fifo, blank mains fifo empty +fifo_out: + bpatchx patch3f_6,mem_patch3f + arg UTIL_FIFO_LEN,loopcnt + ifetch UTIL_FIFO_LEN,rega + rtn blank +fifo_out_loop: + ifetch 1,rega + nbranch fifo_out_end,blank + increase 1,rega + loop fifo_out_loop + branch assert +fifo_out_end: + arg 0,temp + istoret 1,rega + rtn + + //fuction fifo_is_empty + //rega pointer to fifo memory + //blank--- fifo is empty +fifo_is_empty: + ifetch UTIL_FIFO_LEN,rega + rtn + + //fuction fifo_is_full + //rega pointer to fifo memory + //blank--- fifo is NOT full +fifo_is_full: + ifetch 1,rega + rtn + //rega pointer to fifo memory + //blank--- fifo is NOT near full +fifo_is_near_full: + ifetch 2,rega + rtn + +not_greater_than: + isub temp,null + nrtn positive + copy temp,pdata + rtn + +greater_than: + isub temp,null + rtn positive + copy temp,pdata + rtn + +//pdata:a regext:b loopcnt:c +//check a>=b && a=temp +// set1 positive +//else set0 positive +//if pdata == temp set1 zero +int_diff: + isub temp,null + branch enable_positive,zero + isolate1 31,pdata + branch int_diff_pdata_negative,true + isolate1 31,temp + branch enable_positive,true + isub temp,null + rtn +int_diff_pdata_negative: + isolate0 31,temp + branch disable_positive,true + isub temp,null + rtn +disable_positive: + force -1,null + rtn +enable_positive: +disable_zero: + force 1,null + rtn +enable_zero: + force 0,null + rtn + +p_delay: + nop 1 + loop p_delay + rtn + +enable_user: + enable user + rtn + +enable_user2: + enable user2 + rtn + +setarg1: + setarg 1 + rtn + +setarg0: + setarg 0 + rtn +setarg2: + setarg 2 + rtn + +//regc:timer +timer_single_step: + disable user + ifetch 1,regc + rtn blank + increase -1,pdata + istore 1,regc + nrtn blank + branch enable_user + +//regc:timer +timer_single_step2: + disable user + ifetch 2,regc + rtn blank + increase -1,pdata + istore 2,regc + nrtn blank + branch enable_user + +////////////////////////////////////////// NV /////////////////////////////////////////// + +nv_store_le_reconn_info: + fetch 6,mem_le_plap + store 6,mem_temp_lap + jam REC_4_MODE,mem_record_bt_mode + branch nv_update_device_record +nv_store_bd_reconn_info: + fetch 6,mem_plap + store 6,mem_temp_lap + jam REC_3_MODE,mem_record_bt_mode +nv_store_reconn_info: + branch nv_update_device_record + +// rtn: rega point to the linkKey +nv_find_addr_from_bd_list: + disable user + fetch 1,mem_nv_data_number + rtn blank // not nv data + fetch 2,mem_nv_data_ptr + ifetcht 1,pdata // index + pincrease 1 // pdata point to save_mode + store 2,mem_list_item_ptr // point to save mode + storet 1,mem_select_list_item // index + fetch 1,mem_nv_data_number + icopy regc +nv_find_addr_from_list: + fetch 2,mem_list_item_ptr + copy pdata,rega + call nv_find_addr_from_list_compare + rtn user + fetcht 2,mem_list_item_ptr + increase NV_DATA_LEN,temp + storet 2,mem_list_item_ptr + increase -1,temp + ifetch 1,temp + store 1,mem_select_list_item + increase -1,regc + nbranch nv_find_addr_from_list,zero + fetch 1,mem_nv_data_number + pincrease DECREASED_ONE + store 1,mem_select_list_item + rtn + +nv_find_addr_from_list_compare: + arg mem_temp_reconn_record,regb + arg 7,loopcnt + call string_compare + branch enable_user,zero + rtn + +// uart send the new linkkey +nv_update_device_record: + fetch 1,mem_param_use_cm0_control_flag + nrtn blank + fetch 1,mem_nv_data_number + rtn blank // not nv data + call nv_check_nvram + ncall nv_init_device_list,user + call nv_find_addr_from_bd_list +nv_write_device_record: + fetch 1,mem_nv_data_number + icopy regc + fetcht 2,mem_nv_data_ptr + storet 2,mem_list_item_ptr // point to nv data +nv_write_device_loop_find: + copy regc,pdata + branch nv_store_device,blank //EEPROM + increase -1,regc + copy temp,rega // point store to nv + ifetch 1,rega + fetcht 1,mem_select_list_item + isub temp,null // judge if the select list item + call nv_set_index_finded_device,zero + branch nv_write_device_loop_find0,positive + ifetch 1,rega + increase 1,pdata + istore 1,rega +nv_write_device_loop_find0: + fetcht 2,mem_list_item_ptr + increase NV_DATA_LEN,temp + storet 2,mem_list_item_ptr + branch nv_write_device_loop_find +nv_set_index_finded_device: + setarg 0 + istore 1,rega + fetch 7,mem_temp_reconn_record + istore 7,contw + bne REC_3_MODE,set_index_finded_device_ble_mode + arg mem_link_key,contr +store_rec_data_common: + call memcpy16 + force 1,null + rtn + +set_index_finded_device_ble_mode: + arg mem_le_ltk,contr + branch store_rec_data_common + + +nv_init_device_list: + fetchr loopcnt,1,mem_nv_data_number + fetcht 2,mem_nv_data_ptr + setarg 0 +init_device_list_loop: + istore 1,temp + increase NV_DATA_LEN,temp + pincrease 1 + loop init_device_list_loop + rtn + +nv_check_nvram: + disable user + fetchr loopcnt,1,mem_nv_data_number + add loopcnt,-1,pdata + rtn zero + imul32 loopcnt,rega + rshift rega,rega + fetcht 2,mem_nv_data_ptr + setarg 0 +nv_check_nvram_loop: + ifetchr regb,1,temp + increase NV_DATA_LEN,temp + iadd regb,pdata + loop nv_check_nvram_loop + isub rega,null + nrtn zero + branch enable_user + + +nv_load_device_list: + jam REC_3_MODE,mem_temp_reconn_record + fetch 6,mem_plap + store 6,mem_temp_reconn_record+1 + call nv_find_addr_from_bd_list + nbranch nv_clear_key_exists,user + copy rega,contr + arg mem_link_key,contw + call memcpy16 + branch nv_check_link_key_load +nv_clear_key_exists: + jam 0,mem_link_key_exists + rtn + +nv_check_link_key_load: + fetch 8,mem_link_key + fetcht 8,mem_link_key+8 + ior temp,pdata + rtn blank + jam 1,mem_link_key_exists + rtn + +nv_store_device: + fetch 3,mem_ef_base + bbit1 23,nv_flash_store_device + fetch 1,mem_nv_data_number + mul32 pdata,NV_DATA_LEN,temp + fetchr rega,2,mem_nv_data_ptr + arg ef_nvram_offset,regb + branch iicd_write_eep_data +nv_flash_store_device: + fetch 3,mem_ef_base + set0 23,pdata + arg ef_nvram_offset,temp + iadd temp,pdata + store 3,mem_flash_address + fetch 2,mem_nv_data_ptr + store 2,mem_flash_data_address + fetch 1,mem_nv_data_number + mul32 pdata,NV_DATA_LEN,pdata + store 2,mem_flash_trans_length + branch qspi_write + +nv_ng_load_nvram: + fetch 1,mem_param_use_cm0_control_flag + nrtn blank + fetch 3,mem_ef_base + bbit1 23,nv_flash_load_device + fetch 1,mem_nv_data_number + mul32 pdata,NV_DATA_LEN,temp + fetchr rega,2,mem_nv_data_ptr + arg ef_nvram_offset,regb + branch iicd_read_eep_data +nv_flash_load_device: + fetch 3,mem_ef_base + set0 23,pdata + arg ef_nvram_offset,temp + iadd temp,pdata + store 3,mem_flash_address + fetch 2,mem_nv_data_ptr + store 2,mem_flash_data_address + fetch 1,mem_nv_data_number + mul32 pdata,NV_DATA_LEN,pdata + store 2,mem_flash_trans_length + call qspi_read + call nv_check_nvram + ncall nv_init_device_list,zero + rtn + +//wairing :no protect here!!! +nv_get_last_record_ptr: + fetch 2,mem_nv_data_ptr + copy pdata,contr +nv_get_last_connect_address_loop: + ifetch 1,contr + beq 0,nv_get_last_connect_rtn + increase 23,contr + branch nv_get_last_connect_address_loop + rtn +nv_get_last_connect_rtn: + increase 1,contr + copy contr,regc + rtn + +//input :queue +clk_on: + fetch 2,core_clkoff + qset0 pdata +store_clkoff: + store 2,core_clkoff + rtn + +//input :queue +clk_off: + fetch 2,core_clkoff + qset1 pdata + branch store_clkoff + +// error function, becarefull +mram_clkoff: + arg CLOCK_OFF_MRAM + branch clk_off +// error function, becarefull +mram_clkon: + arg CLOCK_OFF_MRAM + branch clk_on + + + Index: tag/Soft/ModuleDemo/ADC/AD_Sound_Recording/BT/do.bat =================================================================== --- /YC1121E/SoftCode/MCU/tag/Soft/ModuleDemo/ADC/AD_Sound_Recording/BT/do.bat (revision 4280) +++ /YC1121E/SoftCode/MCU/tag/Soft/ModuleDemo/ADC/AD_Sound_Recording/BT/do.bat (working copy) @@ -28,10 +28,13 @@ ::set progs= %program%\a2dp.prog + %program%\app.prog + %program%\avctp.prog + %program%\c51.prog + %program%\cvsd.prog + %program%\hci_main.prog + %program%\audio.prog + %program%\hid.prog + %program%\hsphfp.prog + %program%\ipc.prog + %program%\l2cap.prog + %program%\le_att.prog + %program%\le.prog + %program%\le_smp.prog + %program%\lmp.prog + %program%\peripherals.prog + %program%\rfcomm.prog + %program%\scheduler.prog + %program%\sdp.prog + %program%\security.prog + %program%\simple_pairing.prog + %program%\ui.prog + %program%\upper_sm.prog + %program%\usb.prog + %program%\utility.prog + %program%\tws_m.prog + %program%\tws_s.prog + %program%\headset.prog + %program%\debug.prog + %program%\ota.prog ::copy %program%\bt.prog + %progs% output\bt_program23.meta > nul -copy patch\patch_sdk.prog + patch\patch.prog output\bt_program23.meta +::copy patch\patch_sdk.prog + patch\patch.prog output\bt_program23.meta +::set fmts= %format%\a2dp.format + %format%\app.format + %format%\avctp.format + %format%\cvsd.format + %format%\hci.format + %format%\headset.format + %format%\hid.format + %format%\hsphfp.format + %format%\ipc.format + %format%\l2cap.format + %format%\le.format + %format%\lmp.format + %format%\memblocks.format + %format%\patch.format + %format%\prcp.format + %format%\regs.format + %format%\rfcomm.format + %format%\sdp.format + %format%\security.format + %format%\simple_pairing.format + %format%\ui.format + %format%\upper_sm.format + %format%\usb.format + %format%\utility.format + %format%\var.format + %format%\xip.format + %format%\tws.format + %format%\remote.format + %format%\mSBC.format + %format%\debug.format + %format%\tishi.format + %format%\ota.format + %format%\audio_dac_adc.format +::copy %format%\bt.format + %fmts% + format\labels.format + %format%\command.format output\bt_format.meta > nul +set progs= %program%\a2dp.prog + %program%\app.prog + %program%\avctp.prog + %program%\c51.prog + %program%\cvsd.prog + %program%\hci_main.prog + %program%\audio.prog + %program%\hid.prog + %program%\hsphfp.prog + %program%\ipc.prog + %program%\l2cap.prog + %program%\le_att.prog + %program%\le.prog + %program%\le_smp.prog + %program%\lmp.prog + %program%\peripherals.prog + %program%\rfcomm.prog + %program%\scheduler.prog + %program%\sdp.prog + %program%\security.prog + %program%\simple_pairing.prog + %program%\ui.prog + %program%\upper_sm.prog + %program%\usb.prog + %program%\utility.prog + %program%\tws_m.prog + %program%\tws_s.prog + %program%\headset.prog + %program%\debug.prog + %program%\ota.prog +copy %program%\bt.prog + %progs% output\bt_program23.meta > nul set fmts= %format%\a2dp.format + %format%\app.format + %format%\avctp.format + %format%\cvsd.format + %format%\hci.format + %format%\headset.format + %format%\hid.format + %format%\hsphfp.format + %format%\ipc.format + %format%\l2cap.format + %format%\le.format + %format%\lmp.format + %format%\memblocks.format + %format%\patch.format + %format%\prcp.format + %format%\regs.format + %format%\rfcomm.format + %format%\sdp.format + %format%\security.format + %format%\simple_pairing.format + %format%\ui.format + %format%\upper_sm.format + %format%\usb.format + %format%\utility.format + %format%\var.format + %format%\xip.format + %format%\tws.format + %format%\remote.format + %format%\mSBC.format + %format%\debug.format + %format%\tishi.format + %format%\ota.format + %format%\audio_dac_adc.format -copy %format%\bt.format + %fmts% + format\labels.format + %format%\command.format output\bt_format.meta > nul - +copy %format%\bt.format + %fmts% + %format%\command.format output\bt_format.meta > nul perl %util%/mergepatch.pl output/bt_program23.meta %patch_path% Index: tag/Soft/ModuleDemo/ADC/AD_Sound_Recording/BT/patch/patch.prog =================================================================== --- /YC1121E/SoftCode/MCU/tag/Soft/ModuleDemo/ADC/AD_Sound_Recording/BT/patch/patch.prog (revision 4280) +++ /YC1121E/SoftCode/MCU/tag/Soft/ModuleDemo/ADC/AD_Sound_Recording/BT/patch/patch.prog (working copy) @@ -1,11 +1,7 @@ //define EFUSE_CODE -//define ENABLE_F3DB -define ENABLE_8DB -define RF_DEBUG - -//define TWS_FUNC_TEST_BOX -define PATCH_DEBUG_LOG +//define RF_DEBUG +//define PATCH_DEBUG_LOG //define SPECIAL_SLEEP_MODE //define ENABLE_BEFORE_SBC_DEBUG @@ -22,200 +18,23 @@ p_start: bbit1 8,p_start_ext - beq patch07_0,p_sconn_successful - beq patch07_2,p_slave_loop - beq patch07_3,p_slave_notmatch - beq patch07_4,p_prepare_sco_packet - beq patch07_5,p_process_sco_packet - beq patch0a_4,p_rx_type_dispatch - beq patch0b_0,p_process_dmh_common - beq patch0b_4,p_process_dmh_data_end - beq patch0c_0,p_ack_payload_tws - beq patch0d_4,p_check_attempt - beq patch10_1,p_shutdown_radio - beq patch10_5,p_set_freq_tx + beq patch00_2,p_main_loop beq patch13_6,p_initialize_radio_cont beq patch14_0,p_lpm_hibernate - beq patch14_4,p_lpm_dispatch - beq patch16_1,p_l2cap_call_proc_avdtp_media_allow - beq patch16_4,p_l2cap_call_proc_avdtp_media_data - beq patch16_6,p_avd_signal_parse_cmd beq patch17_1,p_app_init - beq patch18_0,p_audio_dac_init - beq patch18_3,p_audio_dac_stop - beq patch18_4,p_audio_dac_vol_adjust - beq patch19_0,p_sbc_clear - beq patch1a_2,p_cvsd_init - beq patch1b_1,p_mSBC_init - beq patch1c_0,p_vp_check_get_data - beq patch1d_1,p_process_avctp_notify - beq patch1d_3,p_process_avctp_control_set_vol - beq patch1e_0,p_headset_clear_parms branch assert p_start_ext: - beq patch20_4,p_HFP_voice_start - beq patch20_5,p_HFP_voice_stop - beq patch20_6,p_HFP_get_vol beq patch20_7,p_ipc_init - beq patch21_2,p_ipc_check_enter_lpm - beq patch21_4,p_ipc_rx_process - beq patch21_7,p_ipc_tx_common - beq patch22_0,p_ipc_tx_bt_event - beq patch26_2,p_l2cap_send_server_conn - beq patch27_1,p_l2cap_clear_server_ptr - beq patch2a_7,p_le_parse_l2cap - beq patch2b_3,p_le_adv - beq patch2e_0,p_parse_lmp beq patch31_0,p_check_m0_qspi_lock_and_pause beq patch31_1,p_check_m0_qspi_continue - beq patch35_7,p_tws_pairing_work - beq patch36_0,p_tws_recon_remote_work_adv_and_scan - beq patch36_1,p_tws_handle_poll - beq patch36_2,p_tws_m_wait_connecting - beq patch36_3,p_tws_m_wait_for_match_continue - beq patch37_4,p_tws_send_connecting_info - beq patch39_1,p_tws_wait_ack_process - beq patch3a_2,p_tws_check_end_hfp_start_sync - beq patch3a_4,p_tws_s_wait_connecting - beq patch3a_5,p_tws_s_connecting_wait_match_continue - beq patch3b_0,p_tws_rcv_first_packet_allow_check - beq patch3b_2,p_tws_rcv_context_info_btclk - beq patch3b_7,p_tws_slave_phone_connected - beq patch3c_0,p_tws_slave_scan_adv - beq patch3c_2,p_tws_send_ack_process - beq patch3d_1,p_check_51cmd - beq patch3d_2,p_check_51cmd_once - beq patch3d_3,p_check_51cmd_once_continue branch assert -p_HFP_get_vol: - fetch 1,mem_hf_vlm_speaker - arg HFP_SPEAKER_MAX_VLM_NEW,temp - isub temp,null - branch p_HFP_get_max_vol,positive - increase 2,pdata - lshift2 pdata,temp - rtn -p_HFP_get_max_vol: - arg 0x80,temp - rtn -p_tws_rcv_first_packet_allow_check: - enable user - - // receive the packet payload - arg mem_le_rxbuf+14,contr - arg mem_tws_first_packet_dynamic_buffer,contw - force 20,loopcnt - call memcpy - - // Step1: check role - call p_tws_check_hsp_role_is_match - branch tws_rcv_first_packet_allow_check+7 -p_tws_check_hsp_role_is_match: - enable user - fetch 1,mem_auto_hsp_role // need auto check - nrtn blank - - fetch 1,mem_tws_first_packet_dynamic_buffer_status - rshift pdata,pdata // Get TWS_PACKET_STATUS_BIT_HSP_ROLE bit - fetcht 1,mem_hsp_role - icompare 0x01,temp - branch disable_user,true - rtn -p_process_avctp_control_set_vol: - increase 3,contr - ifetch 1,contr - store 1,mem_avrcp_vol - beq 0x7f,p_process_avctp_control_set_vol_max - //lshift2 pdata,pdata - pincrease 1 - div pdata,4 - call wait_div_end - quotient pdata - branch process_avctp_control_set_vol+9 -p_process_avctp_control_set_vol_max: - jam HFP_SPEAKER_MAX_VLM_NEW,mem_hf_vlm_speaker - jam BT_EVT_HFP_UP_TO_MAX_VLM,mem_fifo_temp - call ui_ipc_send_event - branch process_avctp_control_set_vol_max+1 -p_slave_notmatch: - call lpm_set_mult - call supervision_update - branch slave_discon_supervision_timeout,positive - call check_disconnect_timeout - nbranch slave_disconnect,user - call p_media_queue - branch slave_notmatch+7 - -///adv change bt name function//// -p_tws_send_connecting_info: -ifdef TWS_FUNC_TEST_BOX - jam 0,mem_le_txheader//box send bt name - arg 37,pdata - store 1,mem_le_txlen - - fetch 6,mem_tws_bdaddr - store 6,mem_le_txpayload - - arg TWS_BLE_ADV_FLAG_SPEC_SETTING,temp - istoret 2,contw - - // Header need about 8bytes, total rx buffer is 40, remove 2, total is 38, reserve one is 37. - arg TWS_SPEC_ADV_FLAG_NAME,temp - istoret 1,contw - - force 28,loopcnt - arg mem_tws_fac_adv_name,contr - call memcpy - disable match // no need receive - call le_transmit - branch end_of_packet -else - branch tws_send_connecting_info+1 -endif //TWS_FUNC_TEST_BOX - -p_tws_rcv_context_info_btclk: -ifdef TWS_FUNC_TEST_BOX - branch tws_reset_connecting -endif //TWS_FUNC_TEST_BOX - call tws_check_bdaddr_is_match - nbranch tws_reset_connecting,zero -ifdef PATCH_DEBUG_LOG - arg LOG_POINT_1301,rega - fetcht 2,mem_le_rxbuf+8 - call debug_log_print - - arg LOG_POINT_130A,rega - fetcht 1,mem_rssi - call debug_log_print -endif //PATCH_DEBUG_LOG - fetch 2,mem_le_rxbuf+8 - arg TWS_BLE_ADV_FLAG_SPEC_SETTING,temp - isub temp,null - branch p_tws_scan_spec_adv_info,zero//receice name from box - branch tws_rcv_context_info_btclk+9 - -p_tws_scan_spec_adv_info: - fetch 1,mem_rssi - sub pdata,0x45,null // Only allow -45dBm to work - nrtn positive - - force 29,loopcnt - arg mem_le_rxbuf+10,contr - arg mem_tws_receive_spec_le_adv,contw - branch memcpy -////////////adv change bt name function end//////////////// - - p_app_init: fetch 1,mem_device_option beq dvc_op_headset,p_headset_init branch p_app_init p_app_init_for_power_save: - // No need do below, it not affect current. - //call clear_gpio_before_lpm - //call p_set_gpio_second_part p_app_clk_init: //clk init fetch 2,core_clkoff @@ -268,57 +87,28 @@ p_charge_setting_by_efuse_data: store 1,mem_lpm_write_temp_charge_control+1 rtn -ifdef ENABLE_BEFORE_SBC_DEBUG -p_uartA_debuginit: - call gpio_config_uart - setarg uart_baud_1_5M - store 2,mem_baud - call uart_set_baud_by_mem - fetch 4,mem_uart_tx_buffer - store 4,core_uart_tx_saddr - fetch 4,mem_uart_rx_buffer - store 4,core_uart_rx_saddr - store 2,core_uart_rx_rptr - fetch 2,mem_uart_tx_buffer - store 2,core_uart_tx_wptr - jam 0x81,core_uart_ctrl - fetch 2,core_clkoff - set0 CLOCK_OFF_UART,pdata - store 2,core_clkoff - fetch 1,core_config - set1 0,pdata - store 1,core_config - rtn -endif p_headset_init: // Temp Code: Current CM0 load flash must work on dpll jam 0x5,0x8042 - // For LPM debug, need change address if debug address changed - //jam DEBUG_LOG_INITIAL_SUCCESS_FLAG,0x1d310 call p_app_init_for_power_save - setarg 0xaa55 + setarg 0x1721 store 2,mem_encryp_inital_value call p_efuse_custom_encryption - //revert lpm state(fix bug) - fetch 1,mem_xlmp_conn_state - store 1,mem_lmp_conn_state - // Must get before p_buck_setting fetch 1,0x8341 store 1,mem_hibernate_flag call p_app_init_efuse_data - //call p_bbldo_setting call p_lpm_init ifdef FUNCTION_WATCH_DOG call wdt_init_reset_with_start endif //FUNCTION_WATCH_DOG - //call p_enable_m0_work_clk + call headset_init //callback function init @@ -326,9 +116,7 @@ store 2,mem_cb_bb_event_process setarg p_headset_evt_100ms_timer store 2,mem_cb_event_timer -ifdef ENABLE_BEFORE_SBC_DEBUG - call p_uartA_debuginit -endif + setarg p_headset_cb_idle_process store 2,mem_cb_idle_process //call headset_check_reconnet @@ -342,7 +130,7 @@ call p_set_gpio_after_lpm,wake call enable_xip - branch assert +// branch assert nbranch wake_from_power,wake wake_for_lpm: call ipc_lock_m0_lmp_wait_work_flag @@ -350,61 +138,20 @@ branch ipc_tx_bt_event p_headset_cb_idle_process: - call p_headset_cb_saradc_read_hvin_wait ifdef FUNCTION_WATCH_DOG call p_wdt_kick_watchdog endif //FUNCTION_WATCH_DOG - branch p_media_queue -p_media_queue: -// fetch 1,mem_init_a2dp_dac -// ncall p_hp_stero_init,blank -// call l2cap_malloc_is_fifo_nearly_full -// nrtn blank - arg mem_media_block,rega - call queue_get_len - rtn blank - - // fetch 1,mem_media_release -// rtn blank - call l2cap_call_proc_avdtp_media - fetch 1 ,mem_l2cap_rx_done - rtnne L2CAP_RX_DONE - call pop_media_queue -ifdef ENABLE_BEFORE_SBC_DEBUG - call print_media_data -endif - branch p_media_queue -ifdef ENABLE_BEFORE_SBC_DEBUG -print_media_data: - call wait_uarttx - fetcht 2,core_sbc_swp - copy temp,loopcnt - fetcht 2,core_sbc_saddr - copy temp,contr - call p_send_mem_to_uart rtn -endif - -p_send_mem_to_uart: - copy contr,rega - call uartd_prepare_tx - copy rega,contr -p_send_mem_to_uart0: - call uart_copy_tx_bytes - branch uartd_send wake_from_power: // store local addr fetch 6,mem_lap store 6,mem_local_bdaddr - fetcht 2,core_sumdata - storet 2,mem_adc_current_value - jam 1,mem_bat_read_timer + // Check if last is charge shutdown fetch 1,mem_hibernate_flag bbit1 5,p_evt_restart - // For charge power up setting - call p_lpm_charge_init_pwr_on + jam BT_EVT_RESET,mem_fifo_temp branch ipc_tx_bt_event @@ -417,619 +164,9 @@ p_evt_restart: - // Check if last have shutdown charge or not - fetch 1,mem_hibernate_flag - bbit0 4,p_evt_restart_continue - // If last shutdown charge, need restart it. - call p_lpm_charge_init_start_charge_ctrl -p_evt_restart_continue: - call p_clear_charge_stop_power_off_flag call p_clear_charge_reset_flag jam BT_EVT_RESTART,mem_fifo_temp branch ipc_tx_bt_event - -p_headset_cb_saradc_read_hvin_wait: - fetch 1,mem_saradc_flag - rtn blank - call saradc_read_hvin_wait - fetch 1,mem_saradc_flag - nrtn blank - storet 2,mem_adc_current_value - rtn - -p_headset_evt_100ms_timer: - //call p_headset_discovery_timer -// call ui_button_polling - call headset_timer_l2cap_reconnect_audio - call check_adc_value - - branch p_headset_timer_connect_avrcp_timer - - -check_adc_value: - fetch 1,mem_vp_enable - nrtn blank - - //branch p_saradc_read_hvin_timer -//output temp : adcdata -p_saradc_read_hvin_timer: - arg mem_bat_read_timer,regc - call timer_single_step - nrtn user - call saradc_check_hvin - branch saradc_enable_hvin - -p_headset_timer_connect_avrcp_timer: - arg mem_hp_avctp_timer,regc - call timer_single_step - nrtn user - // Shoud not allow reconnect while tws connect, becouse the timer with two side is not same. - fetch 1,mem_tws_state - rtneq TWS_STATE_SLAVE_CONNECTED - rtneq TWS_STATE_MASTER_CONNECTED - branch upper_int_reconnect_avctp - -p_master_page_canceled: - jam 0,mem_state - call init_lmp_work - jam BT_EVT_RECONN_PAGE_CANCELED,mem_fifo_temp - call ipc_tx_bt_event - branch page_exit - -p_sconn_successful: - // Check if in paging. - call p_context_search_in_paging_work - call p_master_page_canceled,user - branch sconn_successful+1 - - -// For safe, should add this patch for tws. -p_l2cap_send_server_conn: - fetch 2,mem_l2cap_temp_remote_cid - store 2,mem_temp1 - setarg 0 - store 6,mem_l2cap_temp_ch_info - call l2cap_get_req_id - arg 8,rega - call l2cap_malloc_signal_channel - setarg signal_connect_req - istore 1,contw - fetch 1,mem_ML2CAP_comm_id - istore 1,contw - setarg 0x0004 - istore 2,contw - istorer regd,2,contw - call p_l2cap_get_server_conn_local_cid - branch l2cap_send_server_conn+14 - -p_l2cap_get_server_conn_local_cid: - fetch 2,mem_temp1 - branch l2cap_get_random_local_cid,blank - copy pdata,rega - branch l2cap_get_tws_fix_local_cid_loop - -p_headset_discovery_timer: - arg mem_discovery_timer_count,regc - call timer_single_step2 - nrtn user - branch app_bt_stop_discovery - -p_prepare_sco_packet: - rtnmark0 mark_sco_flag - call mSBC_pop_packet - fetch 1,mem_param_sco_use_cm0 - nbranch prepare_sco_packet_cm0,blank - branch pop_cvsd_data_send - -p_process_sco_packet: - rtnmark0 mark_sco_flag - call mSBC_packet_process - fetch 1,mem_param_sco_use_cm0 - nbranch process_sco_packet_cm0,blank - branch cvsd_check_decoded_data - -p_mSBC_init: - call sbc_clear - call mSBC_encode_init - call mSBC_decode_init - branch aduio_adc_msbc_init - -// Voice all process by cm0 -p_vp_check_get_data: - rtn - -p_check_51cmd_once: - call ui_ipc_get_lock - arg mem_ipc_fifo_c512bt,rega - call fifo_out - copy pdata,temp - call ui_ipc_put_lock - copy temp,pdata - rtn blank - - beq BT_CMD_RECOVER_AUDIO,p_recover_audio - beq BT_CMD_CHARGE_POWER_OFF,p_cmd_charge_power_off - beq BT_CMD_CHARGE_STOP_POWEROFF,p_cmd_charge_stop_power_off - beq BT_CMD_CHARGE_INSCENB,p_lpm_charge_insc_enb_set - beq BT_CMD_CHARGE_INSCENB_CLEAR,p_lpm_charge_insc_enb_clear - beq BT_CMD_OTA_RESET,p_cmd_ota_reset - beq BT_CMD_OTA_SWITCH,p_cmd_ota_start - beq BT_CMD_SHUTDOWN_QSPI,p_bt_shutdown_qspi - branch check_51cmd_once +8 -//////soft reset///////////// -p_cmd_ota_start: - jam OTA_SOFT_CHANGE_FLAG,mem_change_ota_soft_flag - rtn - -// For soft reset, we must make sure it work on the second loop -p_check_51cmd: - fetch 1,mem_change_ota_soft_flag - beq OTA_SOFT_CHANGE_FLAG, p_ota_loadcode - branch check_51cmd+1 -p_ota_loadcode: -// call p_change_flash_start_addr//m0 change addr - call p_ota_copy_ram - jam OTA_NEED_ENABLE_XIP_FLAG,mem_ota_enable_xip_flag - call check_m0_qspi_lock_and_pause -ifdef FUNCTION_WATCH_DOG - call p_wdt_kick_watchdog -endif //FUNCTION_WATCH_DOG - branch loadcode_spi+2 -// For soft reset, some var must be saved -p_ota_copy_ram: - // store the ota GATT handle - fetch 1,mem_ota_notify_handle - store 1,mem_ota_notify_handle_mram - fetch 1,mem_ota_write_handle - store 1,mem_ota_write_handle_mram - // Skip patch point var - arg 504,loopcnt - arg 0x4040,contr - arg 0x1c800,contw -p_copy_loop: - ifetch 8,contr - istore 8,contw - loop p_copy_loop - rtn - -p_le_parse_l2cap: - call p_le_check_l2cap_complete - nrtn user - fetch 2,mem_le_payload_ptr - copy pdata,contr - ifetch 2,contr //l2cap len - store 2,mem_le_l2cap_size - ifetch 2,contr - beq LE_L2CAP_CID_ATT,le_parse_att - beq LE_L2CAP_CID_SMP,le_parse_smp - beq LE_L2CAP_CID_SIGNAL,p_le_parse_signaling - rtn -p_le_parse_signaling: - ifetch 1,contr - beq L2CAP_CONNECTION_PARAMETER_UPDATE_RESPONSE,p_parse_connection_param_update_response - rtn -p_parse_connection_param_update_response: - ifetch 3,contr - ifetch 2,contr - bne 0,p_repeat_sent_param_updata_request - rtn -p_repeat_sent_param_updata_request: - jam 0x09,mem_le_connection_updata_param+2 - branch le_send_update_paramter -p_le_check_l2cap_complete: - fetch 1,mem_le_packet_llid - beq LLID_START,p_le_check_l2cap_llid_start - beq LLID_CONTINUE,p_le_check_l2cap_llid_continue - rtn -p_le_check_l2cap_llid_start: - fetch 2,mem_le_payload_ptr - copy pdata,contr - ifetch 2,contr - store 2,mem_le_l2cap_size - fetcht 1,mem_le_packet_size - storet 1,mem_le_packet_len_recved - increase 4,pdata - isub temp,null - branch enable_user,zero - fetchr loopcnt,1,mem_le_packet_size - arg mem_coef_table_temp,contw // origin mem_le_l2capbuf - branch le_check_l2cap_llid_start+11 -p_le_check_l2cap_llid_continue: - fetch 1,mem_le_packet_len_recved - arg mem_coef_table_temp,contw // origin mem_le_l2capbuf - iadd contw,rega - fetcht 1,mem_le_packet_size - iadd temp,pdata - store 1,mem_le_packet_len_recved - fetchr loopcnt,1,mem_le_packet_size - copy rega,contw - fetch 2,mem_le_payload_ptr - copy pdata,contr - call memcpy - setarg mem_coef_table_temp // origin mem_le_l2capbuf - branch le_check_l2cap_llid_continue+12 - -////////soft reset end//////////// - - -p_recover_audio: - fetch 1,mem_vp_enable - nrtn blank - - bmark1 mark_sco_flag,p_tws_restart_hfp - - fetch 1,mem_a2dp_state - beq A2DP_STATE_START,vp_restart_a2dp - rtn - - - -p_avd_signal_parse_cmd: - ifetch 1,contr - and pdata,0x3f,pdata - store 1,mem_avdtp_signal_cmd - beq AVDTP_IDENTIFIER_SUSPEND,p_avd_signal_parse_cmd_suspend - beq AVDTP_IDENTIFIER_OPEN,p_avd_signal_parse_cmd_open - beq AVDTP_IDENTIFIER_START,p_avd_signal_parse_cmd_start - beq AVDTP_IDENTIFIER_CLOSE,p_avd_signal_parse_cmd_close - branch avd_signal_parse_cmd+4 - -p_avd_signal_parse_cmd_open: - jam 0,mem_play_button_state - branch avd_signal_parse_cmd_open - -p_avd_signal_parse_cmd_start: - jam 0,mem_play_button_state - branch avd_signal_parse_cmd_start - -p_avd_signal_parse_cmd_close: - jam 0,mem_play_button_state - call a2dp_send_evt_close - jam A2DP_STATE_CLOSE,mem_a2dp_state - call avd_signal_parse_cmd_common - branch p_avd_close_sbc_dac - -p_avd_signal_parse_cmd_suspend: - jam 0,mem_play_button_state - call a2dp_send_evt_suspend - jam A2DP_STATE_SUSPEND,mem_a2dp_state - call avd_signal_parse_cmd_common - branch p_avd_close_sbc_dac - -p_avd_close_sbc_dac: - fetch 1,mem_telephone_dialing_state - rtneq HFP_DIALING_STATE_START - rtnmark1 mark_sco_flag - fetch 1,mem_audio_allow // Check media real start or not - rtn blank - branch avd_stop_sbc_dac - -p_HFP_voice_start: - rtn - -p_HFP_voice_stop: - rtn - -p_check_51cmd_once_continue: - fetch 1,mem_fifo_temp - bmark0 mark_context,check_51cmd_check_idle - beq BT_CMD_RECOGNITION_STOP,p_cmd_recognition_stop - beq BT_CMD_PLAY_PAUSE, p_cmd_play_pause - beq BT_CMD_VOL_UP,p_cmd_vol_up - beq BT_CMD_VOL_DOWN,p_cmd_vol_down - - beq BT_CMD_ENTER_SNIFF,p_cmd_in_sniff - branch check_51cmd_once_continue+3 -p_cmd_vol_up: - call cmd_exit - fetch 1,mem_hf_vlm_speaker - sub pdata, HFP_SPEAKER_MAX_VLM_NEW,null - branch p_HFP_adjust_max_volume,zero - nbranch p_HFP_adjust_max_volume,positive - increase 2,pdata - store 1,mem_hf_vlm_speaker - sub pdata, HFP_SPEAKER_MAX_VLM_NEW,null - call p_HFP_adjust_max_volume,zero - ncall p_HFP_adjust_max_volume,positive -p_cmd_adjust_vol: - bmark1 mark_sco_flag,send_AT_vgs - fetch 1,mem_a2dp_state - bne 0,p_avctp_send_vol_changed - rtn -p_HFP_adjust_max_volume: - jam HFP_SPEAKER_MAX_VLM_NEW,mem_hf_vlm_speaker - branch HFP_adjust_max_volume+1 - -p_cmd_vol_down: - call cmd_exit - //call ice_break - fetch 1,mem_hf_vlm_speaker - branch HFP_adjust_min_volume,blank - increase -2,pdata - store 1,mem_hf_vlm_speaker - //branch p_zero_HFP_adjust_min_volume,zero - call HFP_adjust_min_volume,zero - ncall HFP_adjust_min_volume,positive - branch p_cmd_adjust_vol -p_zero_HFP_adjust_min_volume: - call HFP_adjust_min_volume - branch p_cmd_adjust_vol -p_avctp_send_vol_changed: - fetch 1,mem_vlm_notify_enable - rtn blank - jam 0,mem_vlm_notify_enable -//0f 0D 48 00 00 19 58 31 00 00 02 0d 08 - arg 0xf,rega - jam AVCTP_TYPE_RESPONSE,mem_avctp_command_response - fetch 1,mem_vlm_notify_label - store 1,mem_avctp_tx_label - call avctp_malloc_tx_buff - setarg AVRCP_RES_CHANGED -p_avctp_send_vol_changed2: - call avctp_send_vd_common - setarg AVRCP_PDU_RIGISTER_NOTIFY - istore 1,contw - setarg AVRCP_OP_PACKET_TYPE_NON_FRA - istore 1,contw - setarg 2 //length - byteswap pdata,pdata - istore 2,contw - setarg AVRCP_EVENT_VOLUME_CHANGED - istore 1,contw - call p_avctp_get_vol - istore 1,contw - rtn -p_avctp_get_vol: - fetch 1,mem_hf_vlm_speaker - //sub pdata,HFP_SPEAKER_MAX_VLM_NEW,null - //nbranch p_send_full,positive - beq HFP_SPEAKER_MAX_VLM_NEW,p_send_full - mul32 pdata,4,pdata - rtn -p_send_full: - force 0x7f,pdata - rtn - - -p_cmd_in_sniff: - fetch 2,mem_ui_state_map - rtnbit0 UI_STATE_BT_CONNECTED - fetch 1,core_dac_ctrl - rtnbit1 DAC_ENABLE - fetch 1,mem_hf_state - rtnne HF_STATE_CONNECTED - fetch 1,mem_audio_allow - rtnne AVD_AUDIO_FORBID - fetch 1,mem_hf_call_state - rtnne HFP_NONO - branch cmd_in_sniff - -p_process_avctp_notify: - ifetch 1,contr - bne AVRCP_OPERA_CODE_VENDOR_DEPENDENT,l2cap_rx_reset_state - ifetcht 3,contr - setarg AVRCP_OP_COMPANYID_SIG - isub temp,null - nbranch l2cap_rx_reset_state,zero - ifetch 1,contr - beq AVRCP_PDU_RIGISTER_NOTIFY,p_process_avctp_notify_register_notification - branch l2cap_rx_reset_state -p_process_avctp_notify_register_notification: - ifetch 3,contr - ifetch 1,contr - beq AVRCP_EVENT_VOLUME_CHANGED,p_process_avctp_notify_vol_changed - branch l2cap_rx_reset_state -p_process_avctp_notify_vol_changed: - call p_avctp_send_notify_rsp - branch l2cap_rx_reset_state -p_avctp_send_notify_rsp: - call l2cap_rx_reset_state - jam 1,mem_vlm_notify_enable - fetch 1,mem_avctp_rx_label - store 1,mem_vlm_notify_label - store 1,mem_avctp_tx_label - arg 0xf,rega - jam AVCTP_TYPE_RESPONSE,mem_avctp_command_response - call avctp_malloc_tx_buff - setarg AVRCP_RES_INTERIM - branch p_avctp_send_vol_changed2 -p_cmd_recognition_stop: - call p_HFP_send_recognition_stop - branch cmd_exit - -p_HFP_send_recognition_stop: - call HFP_send_credit_return -p_send_recognition_stop: //AT+BVRA=0 - setarg 0x0a - call send_AT_common - setarg 0x525642 - istore 3,contw - setarg 0x303D41 - istore 3,contw - branch send_0d_common - -p_tws_slave_phone_connected: - call p_tws_slave_set_esco_state_before_send_connected_evt - // fix mem_lmp_conn_state not same. - jam 0x0c,mem_lmp_conn_state //RECEIVED_SETUP_COMPLETE, SENT_SETUP_COMPLETE - // Change sniff param - call p_init_lmp_sniff_param - branch tws_slave_phone_connected+1 - -p_tws_slave_set_esco_state_before_send_connected_evt: - rtnmark0 mark_sco_flag - jam 1,mem_sco_transaction_enable - rtn - - -p_cmd_play_pause: - call p_avctp_send_play_pause - branch cmd_exit - -p_avctp_send_play_pause: - call l2cap_malloc_is_fifo_nearly_full - nrtn blank - fetch 1,mem_play_button_state - beq A2DP_STATE_PALY_RELEASE,p_avctp_send_pause - beq A2DP_STATE_PAUSE_RELEASE,p_avctp_send_play - fetch 1,mem_a2dp_state - beq A2DP_STATE_OPEN,p_avctp_send_play - beq A2DP_STATE_START,p_avctp_send_pause - beq A2DP_STATE_SUSPEND,p_avctp_send_play - rtn - -p_avctp_send_play: - call avctp_play_press+1 -p_avctp_play_release: - jam A2DP_STATE_PALY_RELEASE ,mem_play_button_state - branch avctp_play_release+1 - -p_avctp_send_pause: - call avctp_pause_press+1 -p_avctp_pause_release: - jam A2DP_STATE_PAUSE_RELEASE ,mem_play_button_state - branch avctp_pause_release+1 - -p_tws_pairing_work: - // For tws no connecting transmit - fetch 1,mem_tws_no_connect_cmd - nbranch tws_recon_remote_work_scan,blank - branch tws_pairing_work+1 - - -p_tws_recon_remote_work_adv_and_scan: - // Check connection - call p_context_search_have_classic_link - branch tws_recon_remote_work_adv_and_scan+2 - -// Check connection -// Change user flag -p_context_search_have_classic_link: - disable user - arg mem_context,rega - force context_num,loopcnt -p_context_search_have_classic_link_loop: - // get mem_state - ifetch 1,rega - // For tws no connect transmit can work good, we should allow paging to process tws scan work? - //bbit1 state_inpage,enable_user - bbit1 state_inconn,enable_user -p_context_search_have_classic_link_next: - increase context_size,rega - loop p_context_search_have_classic_link_loop - force 1,null - rtn - -// Check in paging -// Change user flag -p_context_search_in_paging_work: - disable user - arg mem_context,rega - force context_num,loopcnt -p_context_search_in_paging_work_loop: - // get mem_state - ifetch 1,rega - bbit1 state_inpage,enable_user -p_context_search_in_paging_work_next: - increase context_size,rega - loop p_context_search_in_paging_work_loop - force 1,null - rtn - -p_tws_m_wait_connecting: - arg le_tws_adv_interval_timer,queue - call timer_check - nrtn blank - call tws_m_update_adv_interval - fetch 1,mem_tws_no_connect_cmd - ncall p_tws_m_wait_connecting_select_no_connect_trans_interval,blank - - // make sure send clk info is valid - call p_tws_send_connecting_info_check_clk_invalid - rtn user - - branch tws_m_wait_connecting+5 - -p_tws_m_wait_connecting_select_no_connect_trans_interval: - // interval to 50ms - arg 0x50,pdata - store 2,mem_le_tws_adv_interval - rtn - - - - -p_tws_s_wait_connecting: - arg le_tws_scan_interval_timer,queue - call timer_check - nrtn blank -ifdef PATCH_DEBUG_LOG - // set flag - arg LOG_POINT_1302,rega - fetcht 1,mem_tws_state - call debug_log_print - // set flag - arg LOG_POINT_1303,rega - fetcht 2,mem_le_tws_scan_interval - call debug_log_print -endif //PATCH_DEBUG_LOG - - call p_context_search_in_paging_work - nbranch tws_s_wait_connecting+10,user - // To avoid affect page work, we should limit the tws slave work, 0x140=200ms - setarg 0x140 - branch tws_s_generate_scan_window_end - -p_tws_s_connecting_wait_match_continue: - fetch 1,mem_tws_connecting_phase - beq TWS_CONNECTING_PHASE8,p_tws_rcv_context_info_phase_end_sub_0 - beq TWS_CONNECTING_PHASE9,p_tws_rcv_context_info_phase_end_sub_1 - branch tws_s_connecting_wait_match_continue+1 - -p_tws_rcv_context_info_phase_end_sub_0: - call tws_slave_check_rcv_context_header - nbranch tws_reset_connecting_with_clear_context,user - force 30,loopcnt - arg mem_l2cap_active_ch_count,contw - call memcpy - branch tws_rcv_context_info_memcontext_common_end - -p_tws_rcv_context_info_phase_end_sub_1: - call tws_slave_check_rcv_context_header - nbranch tws_reset_connecting_with_clear_context,user - force 4,loopcnt - arg mem_avdtp_xmem_start,contw - call memcpy - force 19,loopcnt - arg mem_xmem_hf_state_start,contw - call memcpy - branch tws_rcv_context_info_phase_end_continue - -p_cmd_ota_reset: -p_cmd_charge_power_off: - branch p_set_charge_reset_flag - -p_cmd_charge_stop_power_off: - call p_lpm_charge_init_stop_charge_ctrl -p_set_charge_stop_power_off_flag: - // 0x8341 bit4, for next wakeup to judge need charge full power on - fetch 4,core_lpm_buck_cfg - set1 28,pdata - store 4,core_lpm_reg - branch p_lpm_write_ctrl_buck - -p_clear_charge_stop_power_off_flag: - fetch 4,core_lpm_buck_cfg - set0 28,pdata - store 4,core_lpm_reg - branch p_lpm_write_ctrl_buck - -p_set_charge_reset_flag: - // 0x8341 bit5, for next wakeup to judge need auto power on - fetch 4,core_lpm_buck_cfg - set1 29,pdata - store 4,core_lpm_reg - branch p_lpm_write_ctrl_buck p_clear_charge_reset_flag: fetch 4,core_lpm_buck_cfg @@ -1041,31 +178,13 @@ call p_lpm_write_wait_clock jam lpmreg_sel_buck_cfg,core_lpm_wr branch p_lpm_write_wait_clock + p_lpm_hibernate: - // set charge wake up - call p_lpm_charge_set_wakeup_setting -ifdef SPECIAL_SLEEP_MODE - // special hard sleep mode - branch p_lpm_hard_sleep -endif //SPECIAL_SLEEP_MODE - -p_lpm_hibernate_final: arg -1,temp // Here must be -1, the rom code is error branch lpm_doze -p_ipc_rx_process: - fetch 1,mem_ipc_enable - rtn blank - call ipc_rx_items_inquire - rtn zero // no data - icopy contr - call ipc_rx_byte_read - beq IPC_TYPE_SPP,ipc_rx_spp - beq IPC_TYPE_ADV,ipc_rx_adv - branch ipc_rx_process+7 - p_mram_clkon: arg CLOCK_OFF_MRAM,queue branch clk_on @@ -1077,59 +196,7 @@ call p_ipc_notify_m0_wakeup_flag_init call p_mram_clkon branch ipc_init+5 -ipc_rx_spp: - rtn - -ipc_rx_adv: - call ipc_rx_byte_read // fetch the ipc length - copy pdata,loopcnt - arg mem_le_adv_data_len,contw // set the ipc wptr - call ipc_rx_block_read // read all data - // Get the le action, the first 3 bit is the le action type - fetch 1,mem_le_adv_data_len - rshift4 pdata,pdata - rshift pdata,pdata - store 1,mem_leadv_action - // Get the real adv info - fetch 1,mem_le_adv_data_len - and pdata,0x1f,pdata - store 1,mem_le_adv_data_len - rtn -p_le_adv: - // becouse tws will change le ch, so here need change to initial value - jam 36,mem_le_ch_mapped - fetch 1,mem_leadv_action - rtn blank - arg le_adv_interval_timer,queue - call timer_check - nrtn blank - disable master - enable swfine - call le_init_adv - call le_next_adv_channel - fetch 1,mem_tx_power - store 1,mem_temp_tx_power - fetch 1,mem_param_tws_tx_power - store 1,mem_tx_power - call le_send_adv_ind - fetch 1,mem_temp_tx_power - store 1,mem_tx_power - nbranch p_le_adv_not_match,match - fetch 1,mem_le_req_rcv - increase 1,pdata - store 1,mem_le_req_rcv - fetch 1,mem_le_rxbuf - and pdata,0x0f,pdata - beq SCAN_REQ,le_send_scan_response - beq CONNECT_REQ,parse_connect_req -p_le_adv_not_match: - nop 10000 - fetch 1,mem_le_ch_mapped - bne 39,p_le_adv+1 - arg le_adv_interval_timer,queue - fetch 2,mem_le_adv_interval_max - branch timer_init p_ipc_notify_m0_wakeup_flag_init: jam 1,mem_wake_flag @@ -1138,371 +205,6 @@ rtn -p_process_dmh_data_end: - parse demod,bucket,16 /* cycle through the crc */ - - call rf_debug_active_crc_error_line,crc_failed - - fetch 1,mem_tws_state - beq TWS_STATE_SLAVE_CONNECTED,process_dmh_data_end_tws - beq TWS_STATE_MASTER_LISTEN,p_process_dmh_data_end_tws_master_listen - beq TWS_STATE_MASTER_CONNECTED,process_dmh_data_end_tws -p_process_dmh_data_end_normal: - branch error_payload_crc,crc_failed - // redundant_payload may error for some case - bmark1 mark_old_packet,ack_payload - branch process_dmh_packet - -p_process_dmh_data_end_tws_master_listen: - fetch 1,mem_tws_master_skip_count - nbranch p_process_dmh_data_end_tws_master_listen_decrease,blank - jam 4,mem_tws_master_skip_count - branch p_process_dmh_data_end_normal - -p_process_dmh_data_end_tws_master_listen_decrease: - increase -1,pdata - store 1,mem_tws_master_skip_count - branch process_dmh_data_end_tws - - -p_check_attempt: - //branch p_check_attempt_normal - fetch 1,mem_state - bbit1 state_insniff,check_attempt_normal - fetch 1,mem_tws_state - beq TWS_STATE_MASTER_LISTEN,check_attempt_nomore - branch check_attempt_normal - -p_tws_m_wait_for_match_continue: - fetch 1,mem_tws_state - beq TWS_STATE_MASTER_LISTEN,p_tws_rcv_info_request_in_master_listen - fetch 1,mem_tws_connecting_phase - beq TWS_CONNECTING_PHASE8,p_tws_send_context_info_phase_end_sub_0 - beq TWS_CONNECTING_PHASE9,p_tws_send_context_info_phase_end_sub_1 - branch tws_m_wait_for_match_continue+1 -p_tws_rcv_info_request_in_master_listen: - call tws_reset_connecting - branch tws_start_wait_slave -p_slave_loop: -ifdef FUNCTION_WATCH_DOG - call p_wdt_kick_watchdog -endif //FUNCTION_WATCH_DOG - call p_media_queue - call scheduler_process - call slave_conn_recv_packet /* go listen for a packet */ - nbranch slave_notmatch,match - jam 1,mem_xlmp_clock_offset_valid -p_check_rssi: - fetch 1,mem_rssi - store 1,mem_rssi_sum - jam 1,mem_rssi_update - branch slave_loop+4 - - -p_tws_send_context_info_phase_end_sub_0: - call tws_send_context_info_phase - force 30,loopcnt - arg mem_l2cap_active_ch_count,contr - call memcpy - branch tws_send_context_info_common_end - - -p_tws_send_context_info_phase_end_sub_1: - call tws_send_context_info_phase - force 4,loopcnt - arg mem_avdtp_xmem_start,contr - call memcpy - force 19,loopcnt - arg mem_xmem_hf_state_start,contr - call memcpy - jam 30,mem_le_txlen // 23+7=30 - branch tws_send_context_info_phase_end_continue - -p_ack_payload_tws: - //call check_amaddr_is_esco - //branch p_ack_payload_tws_sco,true - branch ack_payload_tws+1 - -// For FPGA, if master always nack, in transaction with iphone, master will be error -p_ack_payload_tws_sco: - //branch ack_payload_force_nack - branch ack_payload_normal - - - -p_sbc_clear: - call sbc_clk_on - // For safe, init work should close sbc block first - jam 0,core_sbc_ctrl2 - setarg 0 - store 2,core_sbc_swp - // clear last info, include the write wptr or rptr - jam 0xff,core_sbc_clr - nop 1 - jam 0,core_sbc_clr - // here need to think should enbale here? - jam 1,core_sbc_ctrl2 - branch sbc_busy_wait - -p_l2cap_call_proc_avdtp_media_allow: -ifdef TEST_FUNCTION_USE_SPECIAL_VOICE_ENABLE - branch l2cap_call_proc_avdtp_media_free_packet -endif //TEST_FUNCTION_USE_SPECIAL_VOICE_ENABLE - // Wait dac init ok - fetch 1,core_dac_ctrl - rtnbit0 DAC_ENABLE - // Step 1: check sbc idle or not - fetch 1,mem_audio_state - beq AUDIO_STATE_WAIT_SBC,p_l2cap_call_proc_avdtp_media_allow_sbc_in_work - branch l2cap_call_proc_avdtp_media_allow_sbc_idle - -p_l2cap_call_proc_avdtp_media_allow_sbc_in_work: - call p_sbc_hw_check_error_and_reinit - branch p_proc_avdtp_with_sbc_error_work,user - - // Step 3.1: check sbc work ready or not - // If sbc work busy, do nothing - call sbc_hw_check_busy - nrtn zero - - // To reduce code size, not support this anymore - //fetch 1,mem_param_a2dp_dac_sbc_same_buffer_flag - //call ice_break,blank - - jam AUDIO_STATE_IDLE,mem_audio_state - - // Step 3.2: get sbc decode buffer size - call p_audio_dac_get_sbc_decode_buffer_size - store 2,mem_temp_sbc_decode_buffer_size - - // Step 3.3: update tws slave loss sync farrow filter work cnt - call a2dp_update_farrow_filter_work_sample - - // Step 3.4: media buffer add process - call a2dp_media_buffer_add_packet_process - - // For tws start sync, we need let slave to sync master fast, so we use drop/add packet to deal it - // to change mem_temp_sbc_decode_buffer_size to reach the focus - call p_l2cap_sbc_adjust_data - - // For reduce power - call sbc_clk_off - - // Step 3.5: check dac buffer empty - call p_l2cap_call_proc_avdtp_media_with_dac_empty_detect - - // Step 3.6: get sbc decode buffer size - call sbc_update_dac_wptr - - // Step 3.7: adjust vol - call a2dp_soft_dma_update_vol - - // Step 3.8: free packet - branch l2cap_call_proc_avdtp_media_free_packet - -p_l2cap_call_proc_avdtp_media_with_dac_empty_detect: - fetch 1,mem_media_voice_not_good_detect_packet_total_cnt - increase 1,pdata - sub pdata,60,null - nbranch p_media_empty_judge,positive - store 1,mem_media_voice_not_good_detect_packet_total_cnt - - call audio_dac_hw_check_empty - nrtn zero - - // check empty cnt - fetch 1,mem_media_voice_not_good_detect_empty_detect_cnt - increase 1,pdata - store 1,mem_media_voice_not_good_detect_empty_detect_cnt - - branch l2cap_call_proc_avdtp_media_with_dac_empty_detect - -p_media_empty_judge: - jam 0,mem_media_voice_not_good_force_mute - fetch 1,mem_media_voice_not_good_detect_empty_detect_cnt - sub pdata,5,null - branch p_media_empty_judge_clear,positive - jam 1,mem_media_voice_not_good_force_mute -ifdef PATCH_DEBUG_LOG - // set flag - arg LOG_POINT_1641,rega - fetcht 2,mem_media_voice_not_good_detect_empty_detect_cnt - call debug_log_print -endif PATCH_DEBUG_LOG -p_media_empty_judge_clear: - jam 0,mem_media_voice_not_good_detect_packet_total_cnt - jam 0,mem_media_voice_not_good_detect_empty_detect_cnt - rtn - - -// out: pdata: decode real size -p_audio_dac_get_sbc_decode_buffer_size: - // get current sbc write ptr - fetch 2,core_sbc_dwp - fetcht 2,core_sbc_daddr - iadd temp,rega - - copy rega,pdata - fetcht 2,core_dac_wptr - isub temp,pdata - rtn positive - - fetch 2,core_dac_wptr - copy rega,temp - isub temp,temp - fetch 2,core_dac_len - increase 1,pdata - isub temp,pdata - rtn - -p_l2cap_sbc_adjust_data: - fetch 2,mem_a2dp_adjust_delta_bytes - rtn blank - - // Check new packet length - call p_a2dp_soft_dma_tws_add_or_drop_bytes - - // change sbc length - fetch 2,core_dac_wptr - fetcht 2,mem_temp_sbc_decode_buffer_size - iadd temp,pdata - store 2,mem_temp_dac_soft_dma_work_wptr - - // need check reach end? - call p_a2dp_update_dac_wptr_loopback - store 2,core_sbc_dwp - - rtn - - -p_a2dp_soft_dma_tws_add_or_drop_bytes: - // In reduce code size case, do not check again - //fetch 2,mem_a2dp_adjust_delta_bytes - //rtn blank - - fetch 1,mem_a2dp_adjust_delta_bytes_sign_bit - branch p_a2dp_soft_dma_tws_drop_bytes,blank - branch a2dp_soft_dma_tws_add_bytes -p_a2dp_soft_dma_tws_drop_bytes: - // the drop bytes should not big to half sbc buffer size - fetch 2,mem_temp_sbc_decode_buffer_size - // TODO: For TWS, only one channel data. if two channel case, need change below - rshift2 pdata,pdata - lshift pdata,pdata // avoid simgle byte case - branch a2dp_soft_dma_tws_drop_bytes+2 - -p_a2dp_update_dac_wptr_loopback: - fetch 2,core_dac_saddr - fetcht 2,core_dac_len - iadd temp,rega - increase 1,rega - fetch 2,mem_temp_dac_soft_dma_work_wptr - isub rega,temp - nrtn positive - fetch 2,core_dac_saddr - iadd temp,pdata - store 2,mem_temp_dac_soft_dma_work_wptr - rtn - -p_l2cap_call_proc_avdtp_media_data: - call sbc_clk_on - branch l2cap_call_proc_avdtp_media_data+1 - -p_sbc_hw_check_error_and_reinit: - disable user - fetch 1,core_sbc_status - and pdata,0xc0,pdata - rtneq 0 - call sbc_hw_check_error - branch enable_user - -p_proc_avdtp_with_sbc_error_work: - jam AUDIO_STATE_IDLE,mem_audio_state - // Step 3.8: free packet - branch l2cap_call_proc_avdtp_media_free_packet - -p_process_dmh_common: - //storer loopcnt,2,mem_len - deposit loopcnt - store 2,mem_len - branch p_process_dmh_common_zero_len,blank - isub mask3ff,null - branch error_payload,positive /* packet too large, discard */ - set0 mark_fhs_eir,mark - fetch 1,mem_tws_state - beq TWS_STATE_SLAVE_CONNECTED,p_process_dmh_common_packet_tws - beq TWS_STATE_MASTER_CONNECTED,p_process_dmh_common_packet_tws - beq TWS_STATE_MASTER_LISTEN,p_process_dmh_common_packet_tws -p_process_dmh_common_packet: - fetch 1,mem_lch_code - and_into 0x03,pdata - beq LLID_LMP,p_process_lmp - branch process_dmh_common_packet+3 - -p_process_dmh_common_packet_tws: - bmark1 mark_old_packet,tws_handle_old_packet - branch p_process_dmh_common_packet - -p_process_lmp: - call lmp_buffer_full_check - nbranch error_payload,blank - branch process_lmp - -lmp_buffer_full_check: - fetch 1,mem_lmo_opcode1 - rtn blank - fetch 1,mem_lmo_opcode2 - rtn blank - fetch 1,mem_lmp_to_send - rtn - -p_process_dmh_common_zero_len: - fetch 1,mem_lch_code - and_into 0x03,pdata - bne LLID_L2CAP_CONT,process_dmh_data_end - // If we have no buffer to receive packet, then stop receive new packet - arg mem_alloc_block,rega - call queue_get_len - branch end_of_packet,blank - branch process_dmh_data_end - - -p_cvsd_init: - // Must disable cvsd group before - call cvsd_disable_group - branch cvsd_init+1 - - -p_headset_clear_parms: - call headset_clear_parms+1 - jam HFP_SPEAKER_MAX_VLM_NEW,mem_hf_vlm_speaker - rtn - -p_tws_s_check_conflict_packet_send: - disable user - fetch 1,mem_slave_conflict_cnt - jam 0,mem_slave_conflict_cnt - rtnmark0 mark_old_packet - increase 1,pdata - store 1,mem_slave_conflict_cnt - sub pdata,3,null - rtn positive - jam 0,mem_slave_conflict_cnt - branch enable_user - -p_tws_wait_ack_process: - call tws_rf_rx_switch_to_rx - call tws_end_of_packet - - // To avoid already receive slave ack, than the role switch work error. - call tws_m_check_role_switch_work - branch tws_not_rcv_ack_error,user - - call tws_m_check_need_rcv_slave_ack - nbranch tws_wait_ack_process_end,user - - branch tws_wait_ack_process+7 - p_check_m0_qspi_lock_and_pause: call wait_m0_lock_qspi @@ -1534,85 +236,7 @@ rtn -p_audio_dac_init: - jam BT_EVT_START_DAC,mem_fifo_temp - branch ipc_tx_bt_event - - -p_audio_dac_stop: - jam BT_EVT_STOP_DAC,mem_fifo_temp - branch ipc_tx_bt_event -p_audio_dac_vol_adjust: - //avoid error play area - fetch 1,mem_media_voice_not_good_force_mute - nbranch audio_dac_mute_vol,blank - fetch 1,mem_tws_master_connect_with_a2dp_start - nbranch p_audio_dac_vol_adjust_0,blank - // Check in fast sync - fetch 1,mem_media_in_fast_mode - nbranch audio_dac_mute_vol,blank -p_audio_dac_vol_adjust_0: - // Avoid sco change to a2dp pop. - fetch 1,mem_a2dp_start_force_mute_voice_cnt - branch p_audio_dac_vol_adjust_continue,blank - increase -1,pdata - store 1,mem_a2dp_start_force_mute_voice_cnt - rtn -p_audio_dac_vol_adjust_continue: - fetch 1,mem_hf_vlm_speaker - mul32 pdata,4,pdata - fetcht 1,core_dac_lvol - isub temp,null - rtn zero - branch p_audio_dac_vol_adjust_increase,positive -p_audio_dac_vol_adjust_decrease: - increase -1,temp - copy temp,pdata - branch audio_dac_vol_adjust_end -p_audio_dac_vol_adjust_increase: - add temp,1,pdata - branch audio_dac_vol_adjust_end - - -p_tws_check_end_hfp_start_sync: - // Clock is not very good work here - fetch 1,mem_enable_hfp_start_sync - rtn blank -p_tws_check_end_hfp_start_sync_loop: -ifdef PATCH_DEBUG_LOG - // set flag - arg LOG_POINT_1210,rega - //fetcht 2,clke - copy clke_bt,temp - call debug_log_print -endif PATCH_DEBUG_LOG - - fetch 4,mem_hfp_start_sync_clk - isub clke_bt,pdata - // if mem_start_play_clk < clke_bt, means time reached - nbranch p_tws_check_end_hfp_start_sync_loop_end,positive//need check again - sub pdata,30,null// For safe, we use 30 - // if (mem_start_play_clk - clke_bt) <= 6, wait time with look - branch p_tws_check_end_hfp_start_sync_loop,positive - // if (mem_start_play_clk - clke_bt) > 6, wait next transaction - rtn -p_tws_check_end_hfp_start_sync_loop_end: -ifdef PATCH_DEBUG_LOG - // set flag - arg LOG_POINT_1211,rega - fetcht 4,mem_hfp_start_sync_clk - //copy clke_bt,temp - call debug_log_print -endif PATCH_DEBUG_LOG - jam 0,mem_enable_hfp_start_sync - fetch 1,mem_sco_flag - set0 sco_rcv_flag,pdata - store 1,mem_sco_flag - -p_tws_restart_hfp: - jam BT_EVT_RESTART_HFP,mem_fifo_temp - branch ipc_tx_bt_event // input pdata @@ -1627,208 +251,6 @@ jam lpmreg_sel_buck_cfg,core_lpm_wr branch p_lpm_write_wait_clock -p_bbldo_setting: - // change pmu_bbldo_vctrim<3:0> - fetch 1,core_lpm_ctrl+3 - and pdata,0x0f,pdata - or pdata,0xc0,pdata // dpll below 96M use 8, set to c when dpll is 192M - store 1,core_lpm_reg+3 - - fetch 3,core_lpm_ctrl - store 3,core_lpm_reg - call p_lpm_write_wait_clock - jam lpmreg_sel_ctrl,core_lpm_wr - branch p_lpm_write_wait_clock - - - - - -p_delay_xxms: - call delay_10ms - loop p_delay_xxms - rtn - -delay_5ms: - copy clkn_bt,pdata - increase 16,pdata - branch delay_ms_wait - - -/////////////////////////////////////////////////////// CHARGE ////////////////////////////////////////////////////////////////// -p_lpm_charge_set_wakeup_setting: - fetcht 2,mem_lpm_write_temp_charge_wakeup_low_active - fetch 2,mem_lpm_write_temp_charge_wakeup_high_active - lshift8 pdata,pdata - lshift2 pdata,pdata - ior temp,pdata -p_lpm_write2_charge_wakeup_cfg: - store 4,core_lpm_reg - call p_lpm_write_wait_clock - jam lpmreg_sel_charger_low_high_wakeup_reg,core_lpm_wr2 - branch p_lpm_write_wait_clock - -p_lpm_charge_init_pwr_on: -ifdef PATCH_DEBUG_LOG - // set flag - arg LOG_POINT_1700,rega - fetcht 2,mem_lpm_write_temp_charge_control - call debug_log_print -endif //PATCH_DEBUG_LOG - fetch 4,mem_lpm_write_temp_charge_control - branch p_lpm_write_charge_cfg - -//Because we don't have last setting value -p_lpm_charge_init_start_charge_ctrl: -ifdef PATCH_DEBUG_LOG - // set flag - arg LOG_POINT_1701,rega - fetcht 2,mem_lpm_write_temp_charge_control - call debug_log_print -endif //PATCH_DEBUG_LOG - fetch 4,mem_lpm_write_temp_charge_control - set1 CHARGE_CHGR_SHUTDOWN_CORE,pdata - set1 CHARGE_CHGR_SHUTDOWN_SW,pdata - set1 CHARGE_CHGR_SHUTDOWN_BIAS,pdata - store 4,mem_lpm_write_temp_charge_control - - // For generate bias clock - arg 50,loopcnt - call p_charge_reset_bias - - //call p_lpm_charge_insc_enb_set - - fetch 4,mem_lpm_write_temp_charge_control - set0 CHARGE_CHGR_SHUTDOWN_BIAS,pdata - call p_lpm_write_charge_cfg - - fetch 4,mem_lpm_write_temp_charge_control - set0 CHARGE_CHGR_SHUTDOWN_SW,pdata - call p_lpm_write_charge_cfg - // delay 10us - nop 1200 - - fetch 4,mem_lpm_write_temp_charge_control - set0 CHARGE_CHGR_SHUTDOWN_CORE,pdata - call p_lpm_write_charge_cfg - // delay 10us - nop 1200 - rtn - -// Charge need this to generate clock. -p_charge_reset_bias: - // Enable Bias - fetch 4,mem_lpm_write_temp_charge_control - set0 CHARGE_CHGR_SHUTDOWN_BIAS,pdata - call p_lpm_write_charge_cfg - - // Enable Bias - fetch 4,mem_lpm_write_temp_charge_control - set1 CHARGE_CHGR_SHUTDOWN_BIAS,pdata - call p_lpm_write_charge_cfg - - loop p_charge_reset_bias - rtn - -p_lpm_charge_init_stop_charge_ctrl: -ifdef PATCH_DEBUG_LOG - // set flag - arg LOG_POINT_1702,rega - fetcht 2,mem_lpm_write_temp_charge_control - call debug_log_print -endif //PATCH_DEBUG_LOG - //call ice_break - // Enable Bias - fetch 4,mem_lpm_write_temp_charge_control - set1 CHARGE_CHGR_SHUTDOWN_CORE,pdata - call p_lpm_write_charge_cfg - // delay 10us - nop 1200 - - fetch 4,mem_lpm_write_temp_charge_control - set1 CHARGE_CHGR_SHUTDOWN_SW,pdata - call p_lpm_write_charge_cfg - // delay 10us - nop 1200 - - fetch 4,mem_lpm_write_temp_charge_control - set1 CHARGE_CHGR_SHUTDOWN_BIAS,pdata - call p_lpm_write_charge_cfg - // delay 10us - nop 1200 - rtn - -p_lpm_charge_insc_enb_set: -ifdef PATCH_DEBUG_LOG - // set flag - arg LOG_POINT_1703,rega - fetcht 2,mem_lpm_write_temp_charge_control - call debug_log_print -endif //PATCH_DEBUG_LOG - // Enable Bias - fetch 4,mem_lpm_write_temp_charge_control - set1 CHARGE_CHGR_INSC_ENB,pdata - branch p_lpm_write_charge_cfg - -p_lpm_charge_insc_enb_clear: -ifdef PATCH_DEBUG_LOG - // set flag - arg LOG_POINT_1704,rega - fetcht 2,mem_lpm_write_temp_charge_control - call debug_log_print -endif //PATCH_DEBUG_LOG - // Enable Bias - fetch 4,mem_lpm_write_temp_charge_control - set0 CHARGE_CHGR_INSC_ENB,pdata - branch p_lpm_write_charge_cfg - -//input: pdata -p_lpm_write_charge_cfg: - store 4,mem_lpm_write_temp_charge_control - store 4,core_lpm_reg - call p_lpm_write_wait_clock - jam lpmreg_sel_charge_ctrl,core_lpm_wr - branch p_lpm_write_wait_clock - -/////////////////////////////////////////////////////// CHARGE ////////////////////////////////////////////////////////////////// - - -/////////////////////////////////////////////////////// Hard sleep mode ////////////////////////////////////////////////////////////////// -// In this sleep mode, gpio must set to low output. it means we cannot be wakeup by gpio. -// Limit for first 12 vef. 2020/04/09 -p_lpm_hard_sleep: - // Step1: set all gpio to low output - // Step1a: First 32 gpio - setarg 0x3e - arg 32,loopcnt - arg core_gpio_conf,contw - call p_gpio_pd - - // Step1b: Second 8 gpio - call p_set_gpio_second_part - - // Step2: Set special sleep mode - setarg 0x102000 - store 3,mem_lpm_xtalcnt - //setarg 0xc6ff //6: xram on, patch ram on, mram off - setarg 0xc7ff //7: xram on, patch ram on, mram on - istore 2,contw - - // Step3: force close ice wakeup - ncall p_turnoff_ice_wakeuplow,wake - - //call ice_break - - // Step4: set sleep time, it work with 32K clock. 0x20000 is 4.096s. 0x3200 is 400ms. 0x7D00 is 1000ms - //arg 0x20000,temp - arg 0x3200,temp - branch lpm_sleep+8 - -p_set_gpio_second_part: - setarg 0x3e - arg 8,loopcnt - arg core_gpio_conf1,contw - branch p_gpio_pd p_lpm_init: setarg 0x182000 @@ -1838,76 +260,6 @@ rtn -p_gpio_pd: - istore 1,contw - loop p_gpio_pd - rtn - -p_turnoff_ice_wakeuplow: - fetch 4,core_lpm_buck_cfg - set0 30,pdata - store 4,core_lpm_reg - jam lpmreg_sel_buck_cfg,core_lpm_wr - branch p_lpm_write_wait_clock - -// When we work in special sleep mode, to limit work time. -// the function is return to patch00(soft_reset) -// Scene1: When work with first power on. just branch back. -// Scene2: When work second time, to limit work time, it must check if real need to wake up. -// 1: check gpio have input or not. -// 2: check charge wakeup or not. -p_efuse_wakeup_process: - // In this time is 1.584mA - // Step1: Check if have GPIO detect. - // Becareful, here is limit for application, we need know the power key active flag, in this mode - // For 32Pin EVB 2020-040 - //jam GPCFG_PULLUP, CORE_GPIO_CONF+6 - //fetch 2,CORE_GPIO_IN - //bbit0 6,p_efuse_entry_reload_code - - // For i11 - jam GPCFG_PULLDOWN, CORE_GPIO_CONF+27 - fetch 2,core_gpio_in2 - //bbit1 11,p_efuse_entry_reload_code - - // Step2: Check if have charge detect. - call p_efuse_wakeup_check_if_charge_interrupt_wakeup - //branch p_efuse_entry_reload_code,match - - branch p_lpm_hard_sleep - - -// Becareful here, should not use flag: user, it use for aes -p_efuse_wakeup_check_if_charge_interrupt_wakeup: - disable match - call p_mram_clkon - fetcht 2,BT_RESPIN_HIBERNATE_FLAG - setarg BT_RESPIN_FLAG_VALID_FLAG - isub temp,null - nrtn zero - - fetch 2,BT_RESPIN_HIBERNATE_CHG_HIGH - fetcht 2,core_chgr_event - iand temp,pdata - nbranch p_enable_match,blank - - fetch 2,BT_RESPIN_HIBERNATE_CHG_LOW - fetcht 2,core_chgr_event - invert temp,temp - iand temp,pdata - nbranch p_enable_match,blank - -p_disable_match: - disable match - rtn - -p_enable_match: - enable match - rtn - -/////////////////////////////////////////////////////// Hard sleep mode ////////////////////////////////////////////////////////////////// - - p_lpm_write_wait_clock: until null,lpo_edge until null,lpo_edge @@ -1916,77 +268,6 @@ until null,lpo_edge rtn - - -/////////////////////////////////////////////////////// RF ////////////////////////////////////////////////////////////////// -p_set_freq_tx: - storet 1,mem_last_freq - add temp,0,rega /* index to frequency */ - fetch 1,mem_sfreq_enable - ncall set_offset_sfreq,blank - call rf_write_freq - setarg param_pll_setup_min - call sleep -p_rf_tx_enable: - // becouse we will change the tx power, so need initial again - call p_initialize_radio_tx_power - fetch 1,rfen_adc - set1 0,pdata - store 1,rfen_adc - jam 0x3c,rfen_rx - jam 0xe0,rfen_tx - nop 10 /* wait LDOs to turn ON*/ - jam 0x01, rfen_mdm - jam 0x3d, rfen_mdm - nop 10 /* wait tx blocks to turn ON*/ - jam 0xb7,rfen_sn - nop 10 /* wait tx lo buffer to turn ON*/ - jam 0x7d, rfen_mdm - fetch 1,mem_tx_power - beq TX_POWER_0DB,p_set_tx_power_0db -ifdef ENABLE_F3DB - beq TX_POWER_f3DB,set_tx_power_f3db -endif //ENABLE_F3DB - beq TX_POWER_f5DB,p_set_tx_power_f5db -p_rx_high_sens: - jam 0xfb,0x894c - jam 0xef,0x894d - jam 0xec,0x894e - jam 0x5e,0x894f - beq TX_POWER_3DB,p_set_tx_power_3db -p_set_tx_power_5db: - branch set_tx_power_5db - -p_set_tx_power_f5db: - call p_rx_low_sens - jam 0xcc,0x8956 - call txon_common - jam 0xd8,0x8955 - rtn - -p_set_tx_power_0db: - call p_rx_high_sens - branch set_tx_power_0db - - -p_set_tx_power_3db: - jam 0xf7,0x8956 - call txon_common - jam 0xdf,0x8955 - rtn - -p_rx_low_sens: - jam 0x5b,0x894c - jam 0x96,0x894d - jam 0x2c,0x894e - jam 0x46,0x894f - rtn - -p_lpm_load_mark: - fetch 8,mem_saved_mark - iforce mark - rtn - p_initialize_radio_cont: // in efuse will enable wdt @@ -1996,247 +277,16 @@ call wdt_disable_watchdog endif //FUNCTION_WATCH_DOG - call p_doze_sleep_check - - // Be-careful, mark register may loss, reason unknow. - call p_lpm_load_mark,wake - // Change mixer power - jam 0xba,0x894b - call p_initialize_radio_tx_power call initialize_radio_cont+1 - jam 0x74,0x8950 - jam 0x0e,0x8952 - jam 0x07,0x896d - - //jam 0x40,0x8913 - // becouse patch is from branch init_param_cont -p_doze_sleep_check: - rtn wake - // check if the doze mode - fetch 1,core_lpm_ldotrim - rtnbit0 reload_code - deposit auxcnt - branch p_doze_sleep_continue,blank // doze wake up, sleep again. - rtn - -p_doze_sleep_continue: - // recover gpio wakeup setting - call lpm_load_context - branch p_lpm_hibernate_final - -p_initialize_radio_tx_power: - fetch 1,mem_tx_power -// beq TX_POWER_0DB,p_initialize_radio_tx_power_0db -ifdef ENABLE_F3DB - beq TX_POWER_f3DB,p_initialize_radio_tx_power_f3db -endif // ENABLE_F3DB - beq TX_POWER_3DB,p_initialize_radio_tx_power_3db - beq TX_POWER_f5DB,p_initialize_radio_tx_power_f5db - beq TX_POWER_5DB,p_initialize_radio_tx_power_5db -ifdef ENABLE_8DB - beq TX_POWER_8DB,p_initialize_radio_tx_power_8db -endif // ENABLE_8DB -p_initialize_radio_tx_power_0db: - setarg 0x88e0d0 - store 3,0x8955 - setarg 0x106c - branch p_initialize_radio_tx_power_common2 -ifdef ENABLE_8DB -p_initialize_radio_tx_power_8db: - setarg 0xcce0d0 - store 3,0x8955 - branch p_initialize_radio_tx_power_common -endif // ENABLE_8DB - -p_initialize_radio_tx_power_3db: -p_initialize_radio_tx_power_5db: - setarg 0x88e0d0 - store 3,0x8955 -p_initialize_radio_tx_power_common: - setarg 0x103c -p_initialize_radio_tx_power_common2: - store 2,0x8958 - rtn - -p_initialize_radio_tx_power_f3db: -p_initialize_radio_tx_power_f5db: - setarg 0x88c0d0 - store 3,0x8955 - setarg 0x106c - store 2,0x8958 - rtn - - -p_shutdown_radio: -ifdef RF_DEBUG - call rf_shutdown_radio_for_debug -endif //RF_DEBUG - branch p_shutdown_radio0,is_rx - jam 0xd4, 0x8955 - nop 4 - jam 0xd2, 0x8955 - nop 4 - jam 0xd1, 0x8955 - nop 4 - fetch 1,mem_tx_power -ifdef ENABLE_F3DB - beq TX_POWER_f3DB,p_shutdown_radio_f3db -endif //ENABLE_F3DB - beq TX_POWER_3DB,p_shutdown_radio_3db - beq TX_POWER_f5DB,p_shutdown_radio_f5db -// beq TX_POWER_0DB,p_shutdown_radio_0db -// beq TX_POWER_5DB,p_shutdown_radio_5db -// beq TX_POWER_8DB,p_shutdown_radio_8db -p_shutdown_radio_8db: -p_shutdown_radio_5db: -p_shutdown_radio_3db: -p_shutdown_radio_0db: - jam 0xd0, 0x8955 - jam 0xe0, 0x8956 -p_shutdown_radio0: - force 8,radio_ctrl - force 0,radio_ctrl - disable is_rx - disable is_tx - pulse packet_end - jam 0x0,rfen_mdm - jam 0x0,rfen_tx - jam 0x0,rfen_rx - jam 0,rfen_sn - jam 0x70,rfen_msc - fetch 1,rfen_adc - set0 0,pdata - store 1,rfen_adc -// jam 0x0,rfen_adc - rtn - -p_shutdown_radio_f5db: -p_shutdown_radio_f3db: - jam 0xd0,0x8955 - jam 0xc0,0x8956 - branch p_shutdown_radio0 -/////////////////////////////////////////////////////// RF ////////////////////////////////////////////////////////////////// - - - -/////////////////////////////////////////////////////// CM0 light sleep ////////////////////////////////////////////////////////////////// -p_bt_shutdown_qspi: - fetch 2,core_clkoff - rtnbit0 CLOCK_OFF_CM0 - - // Only for 32pin. 20200417 - setarg 0x404040 - store 3,0x8090 - - setarg 0x404040 - store 3,0x8094 - rtn - - -p_bt_wake_up_m0_light_sleep: - fetch 2,core_clkoff - rtnbit0 CLOCK_OFF_CM0 - - // Start qspi, Becouse io1 and io2 have 180uA current. - // Only for 32pin. 20200417 - setarg 0x060502 - store 3,0x8090 - - setarg 0x040307 - store 3,0x8094 - - fetch 2,core_clkoff - set0 CLOCK_OFF_CM0,pdata - store 2,core_clkoff - rtn - - -p_ipc_tx_common: - call p_bt_wake_up_m0_light_sleep - branch ipc_tx_common+1 - -p_ipc_tx_bt_event: - call p_bt_wake_up_m0_light_sleep - branch ipc_tx_bt_event+1 -/////////////////////////////////////////////////////// CM0 light sleep ////////////////////////////////////////////////////////////////// - - - -p_parse_lmp: -ifdef PATCH_DEBUG_LOG - // set flag - arg LOG_POINT_1000,rega - fetcht 2,mem_rxbuf - call debug_log_print -endif //PATCH_DEBUG_LOG - fetch 1,mem_lmi_opcode2 - beq LMP_AU_RAND, p_parse_lmp_au_rand - branch parse_lmp_process+4 - -// For reconnect action -p_parse_lmp_au_rand: - fetch 1,mem_connection_options - set0 CONNECTION_AUTH,pdata - store 1,mem_connection_options - branch parse_lmp_au_rand - - - -p_lpm_dispatch: - rtnmark1 mark_sco_flag - - fetch 1,mem_tws_state - rtneq TWS_STATE_PAIRING - rtneq TWS_STATE_SLAVE_LISTEN - rtneq TWS_STATE_SLAVE_SWITCH_LISTEN - rtneq TWS_STATE_MASTER_LISTEN - rtneq TWS_STATE_WAIT_MASTER - - fetch 1,mem_tws_no_connect_cmd - nrtn blank - - fetch 1,core_aadc_9 - rtnbit1 DA_EN_ADAC_OPAL - rtnbit1 DA_EN_ADAC_OPAR - - fetch 1,mem_tws_snd_op - nrtn blank - fetch 5,mem_tws_cmd_fifo - nrtn blank - -p_lpm_dispatch0: - fetch 1,mem_hf_call_state - rtnne HFP_NONO - - fetch 1,mem_lmp_conn_state - store 1,mem_xlmp_conn_state - branch lpm_dispatch+1 - - - -p_tws_slave_scan_adv: - // avoid invalid param work too long - fetch 2,mem_loss_match - arg 800,temp //1s - isub temp,null - branch p_tws_slave_scan_adv_timeout,positive - branch tws_slave_scan_adv+1 - - -p_tws_slave_scan_adv_timeout: - arg 0,pdata - store 2,mem_loss_match - branch tws_set_slave_role - cb_enter_hibernate: jam MCU_STATE_HIBERNATE,mem_ipc_mcu_state call ipc_check_ack call qspi_powerdown_flash // close gpio - //jam 0x3e,core_gpio_conf+26 + jam 0x3e,core_gpio_conf+26 clear_gpio_before_sleep: call clear_gpio_before_sleep_sub2 arg 32,loopcnt @@ -2270,120 +320,12 @@ branch clear_gpio_before_sleep -p_tws_send_connecting_info_check_clk_invalid: - disable user - //setarg TWS_BLE_ADV_FLAG_CONNECTED - //isub temp,null - //nrtn zero - - fetch 1,mem_tws_profile_connected - rtn blank - - fetch 1,mem_xlmp_clock_offset_valid - nrtn blank - branch enable_user - - -p_check_link_in_sniff: - disable user - fetch 1,mem_context - compare 3,pdata,0x7 /* sco won't sleep */ - nrtn true - fetch 2,mem_context + coffset_tsniff - rtn blank /* role switch */ - branch enable_user - -p_tws_handle_poll: - call tws_remind_crc_failed_flag - call tws_update_local_packet_rcv_flag - fetch 1,mem_tws_state - beq TWS_STATE_MASTER_CONNECTED,p_tws_handle_poll_master - beq TWS_STATE_MASTER_LISTEN,p_tws_handle_poll_master - beq TWS_STATE_SLAVE_CONNECTED,tws_send_ack_process - rtn - -p_tws_handle_poll_master: - call p_check_link_in_sniff - branch tws_wait_ack_process,user - branch tws_handle_poll_master - - -p_lpm_check_link_allow_in_lpm: - disable user - fetch 1,mem_context - bbit0 state_inconn,enable_user - // Check in sniff or not - rtnbit0 state_insniff - fetch 2,mem_context + coffset_tsniff - rtn blank /* role switch */ - rtn wake - branch enable_user - -p_ipc_check_enter_lpm: - call p_lpm_check_link_allow_in_lpm - nbranch setarg1,user - branch ipc_check_enter_lpm+3 - -p_tws_send_ack_process: - call tws_end_of_packet - - call p_tws_s_check_conflict_packet_send - branch end_of_packet,user - - branch tws_send_ack_process+2 - - -p_hp_user_evt: - copy regc,pdata - beq BT_EVT_BB_CONNECTED,app_lpm_mult_enable - // Change sniff param - beq BT_EVT_EXIT_SNIFF,p_init_lmp_sniff_param - branch headset_cb_bb_event_process - p_wdt_kick_watchdog: call wdt_set_watchdog_mode_reset branch wdt_kick_watchdog_1_5s -// For Tws slave error sniff param. -p_init_lmp_sniff_param: - setarg 0x40 - store 2,mem_sniff_param_interval - setarg 0x10001 - store 4,mem_sniff_param_attempt - - setarg 0 - store 2,mem_acl_dsniff - fetch 2,mem_sniff_param_interval - lshift pdata,pdata - store 2,mem_acl_tsniff - fetch 1,mem_sniff_param_attempt - store 1,mem_acl_attempt - fetch 1,mem_sniff_param_timeout - store 1,mem_acl_timeout - rtn -p_l2cap_clear_server_ptr: - fetch 1,mem_l2cap_temp_ch_psm - beq PSM_AVCTP,p_l2cap_clear_avr_ptr - beq PSM_AVDTP,p_l2cap_clear_a2dp_ptr - branch l2cap_clear_server_ptr+1 - -p_l2cap_clear_avr_ptr: - call l2cap_clear_avr_ptr - branch p_l2cap_clear_ptr -p_l2cap_clear_a2dp_ptr: - call l2cap_clear_a2dp_ptr -p_l2cap_clear_ptr: - fetch 1,mem_l2cap_active_ch_count - sub pdata,2,null - nrtn positive - branch app_bt_disconnect - -// Some time may receive error packet. -p_rx_type_dispatch: - deposit type - beq type_hv3, process_2ev3 - branch rx_type_dispatch+2 + // input --- mem_encryp_inital_value output --- mem_encryp_inital_value p_efuse_custom_encryption: @@ -2438,4 +380,14 @@ fetcht 2,mem_encryp_param isub temp,null nbranch assert,zero - rtn \ No newline at end of file + rtn + +p_main_loop: + call app_process_idle + branch main_loop + +p_headset_evt_100ms_timer: + rtn +p_hp_user_evt: + rtn + \ No newline at end of file Index: tag/Soft/ModuleDemo/ADC/AD_Sound_Recording/BT/sched/patch.dat =================================================================== --- /YC1121E/SoftCode/MCU/tag/Soft/ModuleDemo/ADC/AD_Sound_Recording/BT/sched/patch.dat (revision 4280) +++ /YC1121E/SoftCode/MCU/tag/Soft/ModuleDemo/ADC/AD_Sound_Recording/BT/sched/patch.dat (working copy) @@ -1,66 +1,66 @@ mem_patch00: -00 #mem_patch00 +04 #mem_patch00 00 #mem_patch01 00 #mem_patch02 00 #mem_patch03 00 #mem_patch04 00 #mem_patch05 00 #mem_patch06 -35 #mem_patch07 +00 #mem_patch07 00 #mem_patch08 00 #mem_patch09 -10 #mem_patch0A -11 #mem_patch0B -01 #mem_patch0C -10 #mem_patch0D +00 #mem_patch0A +00 #mem_patch0B +00 #mem_patch0C +00 #mem_patch0D 00 #mem_patch0E 00 #mem_patch0F -22 #mem_patch10 +00 #mem_patch10 00 #mem_patch11 00 #mem_patch12 40 #mem_patch13 -11 #mem_patch14 +01 #mem_patch14 00 #mem_patch15 -52 #mem_patch16 +00 #mem_patch16 02 #mem_patch17 -19 #mem_patch18 -01 #mem_patch19 -04 #mem_patch1A -02 #mem_patch1B -01 #mem_patch1C -0a #mem_patch1D -01 #mem_patch1E +00 #mem_patch18 +00 #mem_patch19 +00 #mem_patch1A +00 #mem_patch1B +00 #mem_patch1C +00 #mem_patch1D +00 #mem_patch1E 00 #mem_patch1F -f0 #mem_patch20 -94 #mem_patch21 -01 #mem_patch22 +80 #mem_patch20 +00 #mem_patch21 +00 #mem_patch22 00 #mem_patch23 00 #mem_patch24 00 #mem_patch25 -04 #mem_patch26 -02 #mem_patch27 +00 #mem_patch26 +00 #mem_patch27 00 #mem_patch28 00 #mem_patch29 -80 #mem_patch2A -08 #mem_patch2B +00 #mem_patch2A +00 #mem_patch2B 00 #mem_patch2C 00 #mem_patch2D -01 #mem_patch2E +00 #mem_patch2E 00 #mem_patch2F 00 #mem_patch30 03 #mem_patch31 00 #mem_patch32 00 #mem_patch33 00 #mem_patch34 -80 #mem_patch35 -0f #mem_patch36 -10 #mem_patch37 +00 #mem_patch35 +00 #mem_patch36 +00 #mem_patch37 00 #mem_patch38 -02 #mem_patch39 -34 #mem_patch3A -85 #mem_patch3B -05 #mem_patch3C -0e #mem_patch3D +00 #mem_patch39 +00 #mem_patch3A +00 #mem_patch3B +00 #mem_patch3C +00 #mem_patch3D 00 #mem_patch3E 00 #mem_patch3F Index: tag/Soft/ModuleDemo/ADC/AD_Sound_Recording/CM0/Prj/MDK/Listings/yc11xx.map =================================================================== --- /YC1121E/SoftCode/MCU/tag/Soft/ModuleDemo/ADC/AD_Sound_Recording/CM0/Prj/MDK/Listings/yc11xx.map (revision 4280) +++ /YC1121E/SoftCode/MCU/tag/Soft/ModuleDemo/ADC/AD_Sound_Recording/CM0/Prj/MDK/Listings/yc11xx.map (nonexistent) @@ -1,700 +0,0 @@ -Component: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed] - -============================================================================== - -Section Cross References - - main.o(.text) refers to yc11xx_uart.o(.text) for USART_SendDataFromBuff - main.o(.text) refers to yc_timer.o(.text) for SYS_TimerInit - main.o(.text) refers to yc11xx_audio.o(.text) for Audio_AdcInit - main.o(.text) refers to main.o(.data) for AdcBufferReadPtr - startup.o(RESET) refers to startup.o(.text) for Reset_Handler - startup.o(RESET) refers to main.o(.text) for SysTick_Handler - startup.o(.text) refers to entry.o(.ARM.Collect$$$$00000000) for __main - startup.o(.text) refers to main.o(.text) for main - yc11xx_gpio.o(.text) refers to yc_timer.o(.text) for SYS_delay_ms - yc11xx_gpio.o(.text) refers to yc_drv_common.o(.text) for whileDelay - yc_timer.o(.text) refers to yc11xx_systick.o(.text) for SysTick_Config - yc_timer.o(.text) refers to yc_timer.o(.data) for gSystemInFastDpll - yc_timer.o(.text) refers to yc_timer.o(.bss) for header_Timer - yc11xx_systick.o(.text) refers to yc11xx_systick.o(.data) for SystickCount - yc11xx_pwm.o(.text) refers to yc11xx_gpio.o(.text) for GPIO_SetGpioMultFunction - yc11xx_pwm.o(.text) refers to yc11xx_timer.o(.text) for TIM_Init - yc_uart.o(.text) refers to yc11xx_uart.o(.text) for USART_SendDataFromBuff - yc_uart.o(.text) refers to uidiv.o(.text) for __aeabi_uidivmod - yc_uart.o(.text) refers to yc_uart.o(.constdata) for g_pcHex1 - yc_uart.o(.text) refers to yc_uart.o(.data) for is_open_log_print - yc_uart.o(.constdata) refers to yc_uart.o(.conststring) for .conststring - yc11xx_uart.o(.text) refers to main.o(.text) for _assert_handler - yc11xx_uart.o(.text) refers to yc_drv_common.o(.text) for HW_REG_16BIT - yc11xx_uart.o(.text) refers to yc11xx_gpio.o(.text) for GPIO_SetGpioMultFunction - yc11xx_uart.o(.text) refers to yc11xx_uart.o(.constdata) for __FUNCTION__ - yc11xx_uart.o(.text) refers to yc11xx_uart.o(.bss) for regBeck - yc11xx_uart.o(.text) refers to yc11xx_uart.o(.data) for uartB_TX_buf - yc11xx_bt.o(.text) refers to memcpya.o(.text) for __aeabi_memcpy4 - yc11xx_bt.o(.text) refers to yc_drv_common.o(.text) for HR_REG_24BIT - yc11xx_bt.o(.text) refers to yc11xx_bt.o(.data) for gIPC_test - yc11xx_bt.o(.text) refers to yc11xx_bt.o(.bss) for ipcCb - yc11xx_bt.o(.text) refers to yc11xx_bt.o(.constdata) for .constdata - yc11xx_timer.o(.text) refers to main.o(.text) for _assert_handler - yc11xx_timer.o(.text) refers to yc_drv_common.o(.text) for HW_REG_16BIT - yc11xx_timer.o(.text) refers to yc11xx_timer.o(.constdata) for __FUNCTION__ - yc11xx_audio.o(.text) refers to yc_timer.o(.text) for SYS_delay_us - yc11xx_audio.o(.text) refers to yc11xx_qspi.o(.text) for QSPI_ReadFlashDataToXRAM - yc11xx_audio.o(.text) refers to yc11xx_audio.o(.bss) for gClosePaDelayTimer - yc11xx_audio.o(.text) refers to idiv.o(.text) for __aeabi_idivmod - yc11xx_audio.o(.text) refers to yc11xx_audio.o(.data) for gLastStartDacClk - yc11xx_qspi.o(.text) refers to memseta.o(.text) for __aeabi_memclr4 - yc11xx_qspi.o(.text) refers to yc_drv_common.o(.text) for xmemcpy - yc_8kto48k.o(.text) refers to yc_8kto48k.o(.data) for gpFilter8kTo48KOut - yc_8kto48k.o(.text) refers to yc_8kto48k.o(.bss) for gFilter8kTo48KData - yc_8kto48k.o(.text) refers to yc_8kto48k.o(.constdata) for filter8kTo48KParams - yc11xx_wdt.o(.text) refers to yc11xx_wdt.o(.data) for gpWdtInit - entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry10a.o(.ARM.Collect$$$$0000000D) for __rt_final_cpp - entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry11a.o(.ARM.Collect$$$$0000000F) for __rt_final_exit - entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry7b.o(.ARM.Collect$$$$00000008) for _main_clock - entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry8b.o(.ARM.Collect$$$$0000000A) for _main_cpp_init - entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry9a.o(.ARM.Collect$$$$0000000B) for _main_init - entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry5.o(.ARM.Collect$$$$00000004) for _main_scatterload - entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry2.o(.ARM.Collect$$$$00000001) for _main_stk - idiv.o(.text) refers to uidiv.o(.text) for __aeabi_uidivmod - entry2.o(.ARM.Collect$$$$00000001) refers to entry2.o(.ARM.Collect$$$$00002712) for __lit__00000000 - entry2.o(__vectab_stack_and_reset_area) refers to entry.o(.ARM.Collect$$$$00000000) for __main - entry5.o(.ARM.Collect$$$$00000004) refers to init.o(.text) for __scatterload - entry9a.o(.ARM.Collect$$$$0000000B) refers to main.o(.text) for main - entry9b.o(.ARM.Collect$$$$0000000C) refers to main.o(.text) for main - init.o(.text) refers to entry5.o(.ARM.Collect$$$$00000004) for __main_after_scatterload - - -============================================================================== - -Removing Unused input sections from the image. - - Removing startup.o(STACK), (46656 bytes). - Removing startup.o(HEAP), (256 bytes). - Removing yc11xx_pwm.o(.text), (84 bytes). - Removing yc_uart.o(.text), (784 bytes). - Removing yc_uart.o(.constdata), (8 bytes). - Removing yc_uart.o(.conststring), (37 bytes). - Removing yc_uart.o(.data), (1 bytes). - Removing yc11xx_bt.o(.text), (2764 bytes). - Removing yc11xx_bt.o(.bss), (280 bytes). - Removing yc11xx_bt.o(.constdata), (3 bytes). - Removing yc11xx_bt.o(.data), (8 bytes). - Removing yc11xx_timer.o(.text), (560 bytes). - Removing yc11xx_timer.o(.constdata), (17 bytes). - Removing yc_8kto48k.o(.text), (372 bytes). - Removing yc_8kto48k.o(.bss), (12 bytes). - Removing yc_8kto48k.o(.constdata), (72 bytes). - Removing yc_8kto48k.o(.data), (24 bytes). - Removing yc11xx_wdt.o(.text), (244 bytes). - Removing yc11xx_wdt.o(.data), (4 bytes). - -19 unused section(s) (total 52186 bytes) removed from the image. - -============================================================================== - -Image Symbol Table - - Local Symbols - - Symbol Name Value Ov Type Size Object(Section) - - RESET 0x00000000 Section 192 startup.o(RESET) - ../clib/microlib/division.c 0x00000000 Number 0 uidiv.o ABSOLUTE - ../clib/microlib/division.c 0x00000000 Number 0 idiv.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11a.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry10b.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry9b.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry9a.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8b.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8a.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7b.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7a.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry5.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry10a.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry2.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11b.o ABSOLUTE - ../clib/microlib/string/memcpy.c 0x00000000 Number 0 memcpyb.o ABSOLUTE - ../clib/microlib/string/memcpy.c 0x00000000 Number 0 memcpya.o ABSOLUTE - ../clib/microlib/string/memset.c 0x00000000 Number 0 memseta.o ABSOLUTE - ..\..\..\..\..\..\Librarier\drivers\audio\yc11xx_audio.c 0x00000000 Number 0 yc11xx_audio.o ABSOLUTE - ..\..\..\..\..\..\Librarier\drivers\bt\yc11xx_bt.c 0x00000000 Number 0 yc11xx_bt.o ABSOLUTE - ..\..\..\..\..\..\Librarier\drivers\filter\yc_8kto48k.c 0x00000000 Number 0 yc_8kto48k.o ABSOLUTE - ..\..\..\..\..\..\Librarier\drivers\gpio\yc11xx_gpio.c 0x00000000 Number 0 yc11xx_gpio.o ABSOLUTE - ..\..\..\..\..\..\Librarier\drivers\hal_comm\yc_drv_common.c 0x00000000 Number 0 yc_drv_common.o ABSOLUTE - ..\..\..\..\..\..\Librarier\drivers\pwm\yc11xx_pwm.c 0x00000000 Number 0 yc11xx_pwm.o ABSOLUTE - ..\..\..\..\..\..\Librarier\drivers\qspi\yc11xx_qspi.c 0x00000000 Number 0 yc11xx_qspi.o ABSOLUTE - ..\..\..\..\..\..\Librarier\drivers\systick\yc11xx_systick.c 0x00000000 Number 0 yc11xx_systick.o ABSOLUTE - ..\..\..\..\..\..\Librarier\drivers\timer\yc11xx_timer.c 0x00000000 Number 0 yc11xx_timer.o ABSOLUTE - ..\..\..\..\..\..\Librarier\drivers\timer\yc_timer.c 0x00000000 Number 0 yc_timer.o ABSOLUTE - ..\..\..\..\..\..\Librarier\drivers\uart\yc11xx_uart.c 0x00000000 Number 0 yc11xx_uart.o ABSOLUTE - ..\..\..\..\..\..\Librarier\drivers\uart\yc_uart.c 0x00000000 Number 0 yc_uart.o ABSOLUTE - ..\..\..\..\..\..\Librarier\drivers\wdt\yc11xx_wdt.c 0x00000000 Number 0 yc11xx_wdt.o ABSOLUTE - ..\..\User\main.c 0x00000000 Number 0 main.o ABSOLUTE - Objects\startup\startup.s 0x00000000 Number 0 startup.o ABSOLUTE - dc.s 0x00000000 Number 0 dc.o ABSOLUTE - handlers.s 0x00000000 Number 0 handlers.o ABSOLUTE - init.s 0x00000000 Number 0 init.o ABSOLUTE - .text 0x000000c0 Section 40 startup.o(.text) - RUN_TO_MAIN 0x000000cf Thumb Code 4 startup.o(.text) - LOADRAMFLAG 0x000000d4 Data 4 startup.o(.text) - .ARM.Collect$$$$00000000 0x00001000 Section 0 entry.o(.ARM.Collect$$$$00000000) - .ARM.Collect$$$$00000001 0x00001000 Section 4 entry2.o(.ARM.Collect$$$$00000001) - .ARM.Collect$$$$00000004 0x00001004 Section 4 entry5.o(.ARM.Collect$$$$00000004) - .ARM.Collect$$$$00000008 0x00001008 Section 0 entry7b.o(.ARM.Collect$$$$00000008) - .ARM.Collect$$$$0000000A 0x00001008 Section 0 entry8b.o(.ARM.Collect$$$$0000000A) - .ARM.Collect$$$$0000000B 0x00001008 Section 8 entry9a.o(.ARM.Collect$$$$0000000B) - .ARM.Collect$$$$0000000D 0x00001010 Section 0 entry10a.o(.ARM.Collect$$$$0000000D) - .ARM.Collect$$$$0000000F 0x00001010 Section 0 entry11a.o(.ARM.Collect$$$$0000000F) - .ARM.Collect$$$$00002712 0x00001010 Section 4 entry2.o(.ARM.Collect$$$$00002712) - __lit__00000000 0x00001010 Data 4 entry2.o(.ARM.Collect$$$$00002712) - .text 0x00001014 Section 0 main.o(.text) - .text 0x00001238 Section 0 yc11xx_gpio.o(.text) - hw_delay 0x00001cdd Thumb Code 12 yc11xx_gpio.o(.text) - .text 0x00001cf4 Section 0 yc_timer.o(.text) - hw_delay 0x000021bf Thumb Code 12 yc_timer.o(.text) - .text 0x000021dc Section 0 yc11xx_systick.o(.text) - .text 0x00002234 Section 0 yc11xx_uart.o(.text) - .text 0x00002ae0 Section 0 yc_drv_common.o(.text) - hw_delay 0x00002ce7 Thumb Code 12 yc_drv_common.o(.text) - .text 0x00002d00 Section 0 yc11xx_audio.o(.text) - .text 0x00006edc Section 0 yc11xx_qspi.o(.text) - __tagsym$$noinline 0x00006edd Number 0 yc11xx_qspi.o(.text) - __tagsym$$noinline 0x00006eeb Number 0 yc11xx_qspi.o(.text) - __tagsym$$noinline 0x00006ef9 Number 0 yc11xx_qspi.o(.text) - __tagsym$$noinline 0x000075bb Number 0 yc11xx_qspi.o(.text) - .text 0x000076f0 Section 0 uidiv.o(.text) - .text 0x0000771c Section 0 idiv.o(.text) - .text 0x00007744 Section 0 memseta.o(.text) - .text 0x00007768 Section 36 init.o(.text) - i.__scatterload_copy 0x0000778c Section 14 handlers.o(i.__scatterload_copy) - i.__scatterload_null 0x0000779a Section 2 handlers.o(i.__scatterload_null) - i.__scatterload_zeroinit 0x0000779c Section 14 handlers.o(i.__scatterload_zeroinit) - .constdata 0x000077aa Section 154 yc11xx_uart.o(.constdata) - __FUNCTION__ 0x000077aa Data 11 yc11xx_uart.o(.constdata) - __FUNCTION__ 0x000077b5 Data 13 yc11xx_uart.o(.constdata) - __FUNCTION__ 0x000077c2 Data 15 yc11xx_uart.o(.constdata) - __FUNCTION__ 0x000077d1 Data 18 yc11xx_uart.o(.constdata) - __FUNCTION__ 0x000077e3 Data 17 yc11xx_uart.o(.constdata) - __FUNCTION__ 0x000077f4 Data 21 yc11xx_uart.o(.constdata) - __FUNCTION__ 0x00007809 Data 23 yc11xx_uart.o(.constdata) - __FUNCTION__ 0x00007820 Data 17 yc11xx_uart.o(.constdata) - __FUNCTION__ 0x00007831 Data 19 yc11xx_uart.o(.constdata) - .data 0x10011000 Section 2 main.o(.data) - .data 0x10011004 Section 14 yc_timer.o(.data) - .data 0x10011014 Section 4 yc11xx_systick.o(.data) - .data 0x10011018 Section 8 yc11xx_uart.o(.data) - printportcb 0x10011018 Data 4 yc11xx_uart.o(.data) - .data 0x10011020 Section 9 yc11xx_audio.o(.data) - .bss 0x1001102c Section 24 yc_timer.o(.bss) - .bss 0x10011044 Section 8226 yc11xx_uart.o(.bss) - .bss 0x10013068 Section 24 yc11xx_audio.o(.bss) - - Global Symbols - - Symbol Name Value Ov Type Size Object(Section) - - BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$EBA8$MICROLIB$REQ8$PRES8$EABIv2 0x00000000 Number 0 anon$$obj.o ABSOLUTE - __ARM_use_no_argv 0x00000000 Number 0 main.o ABSOLUTE - __Vectors 0x00000000 Data 4 startup.o(RESET) - __cpp_initialize__aeabi_ - Undefined Weak Reference - __cxa_finalize - Undefined Weak Reference - __decompress - Undefined Weak Reference - _clock_init - Undefined Weak Reference - _microlib_exit - Undefined Weak Reference - Reset_Handler 0x000000c1 Thumb Code 14 startup.o(.text) - __Vectors_End 0x000000c0 Data 0 startup.o(RESET) - __Vectors_Size 0x000000c0 Number 0 startup.o ABSOLUTE - ADC_IRQHandler 0x000000d9 Thumb Code 0 startup.o(.text) - BT_IRQHandler 0x000000d9 Thumb Code 0 startup.o(.text) - DMA_IRQHandler 0x000000d9 Thumb Code 0 startup.o(.text) - FFT_IRQHandler 0x000000d9 Thumb Code 0 startup.o(.text) - GPIO_IRQHandler 0x000000d9 Thumb Code 0 startup.o(.text) - HardFault_Handler 0x000000d9 Thumb Code 0 startup.o(.text) - IIC_IRQHandler 0x000000d9 Thumb Code 0 startup.o(.text) - IIS_IRQHandler 0x000000d9 Thumb Code 0 startup.o(.text) - NMI_Handler 0x000000d9 Thumb Code 0 startup.o(.text) - OTP_IRQHandler 0x000000d9 Thumb Code 0 startup.o(.text) - PendSV_Handler 0x000000d9 Thumb Code 0 startup.o(.text) - QSPI_IRQHandler 0x000000d9 Thumb Code 0 startup.o(.text) - SBC_ERR0_IRQHandler 0x000000d9 Thumb Code 0 startup.o(.text) - SBC_ERR1_IRQHandler 0x000000d9 Thumb Code 0 startup.o(.text) - SD_IRQHandler 0x000000d9 Thumb Code 0 startup.o(.text) - SPI_IRQHandler 0x000000d9 Thumb Code 0 startup.o(.text) - SVC_Handler 0x000000d9 Thumb Code 0 startup.o(.text) - TIMER0_IRQHandler 0x000000d9 Thumb Code 0 startup.o(.text) - TIMER1_IRQHandler 0x000000d9 Thumb Code 0 startup.o(.text) - TIMER2_IRQHandler 0x000000d9 Thumb Code 0 startup.o(.text) - TIMER3_IRQHandler 0x000000d9 Thumb Code 0 startup.o(.text) - TIMER4_IRQHandler 0x000000d9 Thumb Code 0 startup.o(.text) - TIMER5_IRQHandler 0x000000d9 Thumb Code 0 startup.o(.text) - TIMER6_IRQHandler 0x000000d9 Thumb Code 0 startup.o(.text) - TIMER7_IRQHandler 0x000000d9 Thumb Code 0 startup.o(.text) - UARTB_IRQHandler 0x000000d9 Thumb Code 0 startup.o(.text) - UART_IRQHandler 0x000000d9 Thumb Code 0 startup.o(.text) - USB_IRQHandler 0x000000d9 Thumb Code 0 startup.o(.text) - WDT2_IRQHandler 0x000000d9 Thumb Code 0 startup.o(.text) - WDT_IRQHandler 0x000000d9 Thumb Code 0 startup.o(.text) - __main 0x00001001 Thumb Code 0 entry.o(.ARM.Collect$$$$00000000) - _main_stk 0x00001001 Thumb Code 0 entry2.o(.ARM.Collect$$$$00000001) - _main_scatterload 0x00001005 Thumb Code 0 entry5.o(.ARM.Collect$$$$00000004) - __main_after_scatterload 0x00001009 Thumb Code 0 entry5.o(.ARM.Collect$$$$00000004) - _main_clock 0x00001009 Thumb Code 0 entry7b.o(.ARM.Collect$$$$00000008) - _main_cpp_init 0x00001009 Thumb Code 0 entry8b.o(.ARM.Collect$$$$0000000A) - _main_init 0x00001009 Thumb Code 0 entry9a.o(.ARM.Collect$$$$0000000B) - __rt_final_cpp 0x00001011 Thumb Code 0 entry10a.o(.ARM.Collect$$$$0000000D) - __rt_final_exit 0x00001011 Thumb Code 0 entry11a.o(.ARM.Collect$$$$0000000F) - updata_addr 0x00001015 Thumb Code 32 main.o(.text) - UART_Tx_Adc_Buffer 0x00001035 Thumb Code 242 main.o(.text) - main 0x00001127 Thumb Code 232 main.o(.text) - _assert_handler 0x0000120f Thumb Code 4 main.o(.text) - SysTick_Handler 0x00001213 Thumb Code 8 main.o(.text) - GPIO_SetOut 0x00001239 Thumb Code 160 yc11xx_gpio.o(.text) - GPIO_SetInput 0x000012d9 Thumb Code 88 yc11xx_gpio.o(.text) - GPIO_SetWakeup 0x00001331 Thumb Code 382 yc11xx_gpio.o(.text) - gpioGetBit 0x000014af Thumb Code 54 yc11xx_gpio.o(.text) - GPIO_GetInputStatus 0x000014e5 Thumb Code 54 yc11xx_gpio.o(.text) - GPIO_SetWakeupByCurrentState 0x0000151b Thumb Code 42 yc11xx_gpio.o(.text) - GPIO_ClearWakeup 0x00001545 Thumb Code 194 yc11xx_gpio.o(.text) - GPIO_SetGpioMultFunction 0x00001607 Thumb Code 34 yc11xx_gpio.o(.text) - GPIO_GetInputStatusWithJitter 0x00001629 Thumb Code 72 yc11xx_gpio.o(.text) - GPIO_CheckGpioIsInputFunction 0x00001671 Thumb Code 56 yc11xx_gpio.o(.text) - GPIO_Set_High_Interrupt 0x000016a9 Thumb Code 354 yc11xx_gpio.o(.text) - GPIO_Set_Low_Interrupt 0x0000180b Thumb Code 352 yc11xx_gpio.o(.text) - GPIO_Clear_High_Interrupt 0x0000196b Thumb Code 376 yc11xx_gpio.o(.text) - GPIO_Clear_Low_Interrupt 0x00001ae3 Thumb Code 358 yc11xx_gpio.o(.text) - GPIO_Clear_All_Interrupt 0x00001c49 Thumb Code 148 yc11xx_gpio.o(.text) - SYS_TimerExpireDefaultHandle 0x00001cf5 Thumb Code 6 yc_timer.o(.text) - SYS_TimerGet1usTicks 0x00001cfb Thumb Code 68 yc_timer.o(.text) - SYS_ChangeDPLL 0x00001d3f Thumb Code 68 yc_timer.o(.text) - SYS_ChangeToFastDPLL 0x00001d83 Thumb Code 130 yc_timer.o(.text) - SYS_ChangeToNormalDPLL 0x00001e05 Thumb Code 130 yc_timer.o(.text) - SystemCheckInFastSpeed 0x00001e87 Thumb Code 6 yc_timer.o(.text) - SYS_ClkTicks 0x00001e8d Thumb Code 166 yc_timer.o(.text) - SYS_TimerStartTickTimer 0x00001f33 Thumb Code 16 yc_timer.o(.text) - SYS_TimerInit 0x00001f43 Thumb Code 52 yc_timer.o(.text) - SYS_TimerisExist 0x00001f77 Thumb Code 46 yc_timer.o(.text) - SYS_SetTimer 0x00001fa5 Thumb Code 92 yc_timer.o(.text) - SYS_ResetTimer 0x00002001 Thumb Code 56 yc_timer.o(.text) - SYS_TimerTest 0x00002039 Thumb Code 20 yc_timer.o(.text) - SYS_ReleaseTimer 0x0000204d Thumb Code 82 yc_timer.o(.text) - SYS_timerPolling 0x0000209f Thumb Code 126 yc_timer.o(.text) - SYS_ReleaseAllTimer 0x0000211d Thumb Code 38 yc_timer.o(.text) - SYStick_handle 0x00002143 Thumb Code 14 yc_timer.o(.text) - Bt_100ms_timer 0x00002151 Thumb Code 16 yc_timer.o(.text) - SYS_delay_us 0x00002161 Thumb Code 76 yc_timer.o(.text) - SYS_delay_ms 0x000021ad Thumb Code 18 yc_timer.o(.text) - SysTick_Config 0x000021dd Thumb Code 58 yc11xx_systick.o(.text) - SysTick_GetTick 0x00002217 Thumb Code 6 yc11xx_systick.o(.text) - SysTick_IsTimeOut 0x0000221d Thumb Code 6 yc11xx_systick.o(.text) - SysTick_GetRelativeTime 0x00002223 Thumb Code 6 yc11xx_systick.o(.text) - USART_Init 0x00002235 Thumb Code 668 yc11xx_uart.o(.text) - UARTx_Configuration 0x000024d1 Thumb Code 94 yc11xx_uart.o(.text) - USART_DeInit 0x0000252f Thumb Code 370 yc11xx_uart.o(.text) - USART_SendData 0x000026a1 Thumb Code 278 yc11xx_uart.o(.text) - USART_ReceiveData 0x000027b7 Thumb Code 94 yc11xx_uart.o(.text) - USART_GetRxCount 0x00002815 Thumb Code 46 yc11xx_uart.o(.text) - USART_ReadDatatoBuff 0x00002843 Thumb Code 204 yc11xx_uart.o(.text) - USART_SendDataFromBuff 0x0000290f Thumb Code 272 yc11xx_uart.o(.text) - USART_SetRxITNum 0x00002a1f Thumb Code 56 yc11xx_uart.o(.text) - USART_SetRxTimeout 0x00002a57 Thumb Code 134 yc11xx_uart.o(.text) - HW_REG_24BIT 0x00002ae1 Thumb Code 30 yc_drv_common.o(.text) - HW_REG_16BIT 0x00002aff Thumb Code 18 yc_drv_common.o(.text) - HR_REG_16BIT 0x00002b11 Thumb Code 34 yc_drv_common.o(.text) - HR_REG_24BIT 0x00002b33 Thumb Code 36 yc_drv_common.o(.text) - xmemcpy 0x00002b57 Thumb Code 80 yc_drv_common.o(.text) - xstrlen 0x00002ba7 Thumb Code 20 yc_drv_common.o(.text) - error_handle 0x00002bbb Thumb Code 4 yc_drv_common.o(.text) - Lpm_LockLpm 0x00002bbf Thumb Code 24 yc_drv_common.o(.text) - Lpm_unLockLpm 0x00002bd7 Thumb Code 24 yc_drv_common.o(.text) - Lpm_CheckLpmFlag 0x00002bef Thumb Code 20 yc_drv_common.o(.text) - whileDelay 0x00002c03 Thumb Code 26 yc_drv_common.o(.text) - whileDelayshort 0x00002c1d Thumb Code 28 yc_drv_common.o(.text) - xramcmp 0x00002c39 Thumb Code 80 yc_drv_common.o(.text) - xramcpy 0x00002c89 Thumb Code 80 yc_drv_common.o(.text) - math_abs 0x00002cd9 Thumb Code 14 yc_drv_common.o(.text) - Audio_EqDisable 0x00002d01 Thumb Code 56 yc11xx_audio.o(.text) - Audio_DACClkOff 0x00002d39 Thumb Code 462 yc11xx_audio.o(.text) - Audio_ClosePaDelay 0x00002f07 Thumb Code 2 yc11xx_audio.o(.text) - Audio_AdacPrepareSoftMute 0x00002f09 Thumb Code 2 yc11xx_audio.o(.text) - Audio_DacClearRampDown 0x00002f0b Thumb Code 138 yc11xx_audio.o(.text) - Audio_DacWaitRampDown 0x00002f95 Thumb Code 200 yc11xx_audio.o(.text) - Audio_DacStop 0x0000305d Thumb Code 156 yc11xx_audio.o(.text) - Audio_LpmWrite2AdcHigh 0x000030f9 Thumb Code 140 yc11xx_audio.o(.text) - Audio_AnaAdcHighControlDisable 0x00003185 Thumb Code 108 yc11xx_audio.o(.text) - Audio_LpmWrite2AdcLow 0x000031f1 Thumb Code 140 yc11xx_audio.o(.text) - Audio_AnaAdcLowControlDisable 0x0000327d Thumb Code 130 yc11xx_audio.o(.text) - Audio_AnaStopAdcWork 0x000032ff Thumb Code 12 yc11xx_audio.o(.text) - Audio_AdcStop 0x0000330b Thumb Code 90 yc11xx_audio.o(.text) - Audio_CvsdClkEnable 0x00003365 Thumb Code 630 yc11xx_audio.o(.text) - Audio_CvsdClkDisable 0x000035db Thumb Code 2 yc11xx_audio.o(.text) - Audio_CvsdWaitCvsdFilterClrDone 0x000035dd Thumb Code 30 yc11xx_audio.o(.text) - Audio_GetCoefStartAddr 0x000035fb Thumb Code 136 yc11xx_audio.o(.text) - Audio_CvsdCoefInit 0x00003683 Thumb Code 278 yc11xx_audio.o(.text) - Audio_CvsdStart 0x00003799 Thumb Code 54 yc11xx_audio.o(.text) - Audio_CvsdStop 0x000037cf Thumb Code 16 yc11xx_audio.o(.text) - Audio_CheckAdcDmaEnable 0x000037df Thumb Code 30 yc11xx_audio.o(.text) - Audio_RelasePaDelay 0x000037fd Thumb Code 10 yc11xx_audio.o(.text) - Audio_DacMono 0x00003807 Thumb Code 66 yc11xx_audio.o(.text) - Audio_DacStero 0x00003849 Thumb Code 66 yc11xx_audio.o(.text) - Audio_DacMonoStero 0x0000388b Thumb Code 20 yc11xx_audio.o(.text) - Audio_DacCloseR 0x0000389f Thumb Code 66 yc11xx_audio.o(.text) - Audio_DacSetR 0x000038e1 Thumb Code 94 yc11xx_audio.o(.text) - Audio_DacCloseL 0x0000393f Thumb Code 56 yc11xx_audio.o(.text) - Audio_DacSetL 0x00003977 Thumb Code 60 yc11xx_audio.o(.text) - Audio_AdacToolGetSrcToDstVal 0x000039b3 Thumb Code 32 yc11xx_audio.o(.text) - Audio_AdacToolGetAdjustInterval 0x000039d3 Thumb Code 64 yc11xx_audio.o(.text) - Audio_AdacAdjustDigitalVolToZero 0x00003a13 Thumb Code 68 yc11xx_audio.o(.text) - Audio_AdacAdjustDCCaliToZero 0x00003a57 Thumb Code 120 yc11xx_audio.o(.text) - Audio_AdacPrepareReadyWork 0x00003acf Thumb Code 12 yc11xx_audio.o(.text) - Audio_DacSetDaAdacOpaDummyToMainR 0x00003adb Thumb Code 44 yc11xx_audio.o(.text) - Audio_DacSetDaAdacOpaDummyToMainL 0x00003b07 Thumb Code 44 yc11xx_audio.o(.text) - Audio_DacSetDaAdacOpaDummyToMain 0x00003b33 Thumb Code 56 yc11xx_audio.o(.text) - Audio_DacSetDaAdacDepopSwR 0x00003b6b Thumb Code 56 yc11xx_audio.o(.text) - Audio_DacSetDaAdacDepopSwL 0x00003ba3 Thumb Code 56 yc11xx_audio.o(.text) - Audio_DacSetDaAdacDepopSw 0x00003bdb Thumb Code 56 yc11xx_audio.o(.text) - Audio_DacSetDaAdacPathR 0x00003c13 Thumb Code 56 yc11xx_audio.o(.text) - Audio_DacSetDaAdacPathL 0x00003c4b Thumb Code 56 yc11xx_audio.o(.text) - Audio_DacSetDaAdacPath 0x00003c83 Thumb Code 56 yc11xx_audio.o(.text) - Audio_DacSetDaAdacOpaR 0x00003cbb Thumb Code 74 yc11xx_audio.o(.text) - Audio_DacSetDaAdacOpaL 0x00003d05 Thumb Code 56 yc11xx_audio.o(.text) - Audio_DacSetDaAdacOpa 0x00003d3d Thumb Code 56 yc11xx_audio.o(.text) - Audio_DacSetDaAdacIntR 0x00003d75 Thumb Code 56 yc11xx_audio.o(.text) - Audio_DacSetDaAdacIntL 0x00003dad Thumb Code 56 yc11xx_audio.o(.text) - Audio_DacSetDaAdacInt 0x00003de5 Thumb Code 56 yc11xx_audio.o(.text) - Audio_DacSetDaAdacRstIntDisable 0x00003e1d Thumb Code 40 yc11xx_audio.o(.text) - Audio_DacSetDaAdacRstIntR 0x00003e45 Thumb Code 56 yc11xx_audio.o(.text) - Audio_DacSetDaAdacRstIntL 0x00003e7d Thumb Code 56 yc11xx_audio.o(.text) - Audio_DacSetDaEnAdacOpaDummy 0x00003eb5 Thumb Code 60 yc11xx_audio.o(.text) - Audio_DacSetDaAdacRstInt 0x00003ef1 Thumb Code 56 yc11xx_audio.o(.text) - Audio_DaAaddaBgEn 0x00003f29 Thumb Code 144 yc11xx_audio.o(.text) - Audio_DacSetRampDownEnR 0x00003fb9 Thumb Code 56 yc11xx_audio.o(.text) - Audio_DacSetRampDownEnL 0x00003ff1 Thumb Code 56 yc11xx_audio.o(.text) - Audio_DacSetRampDownEn 0x00004029 Thumb Code 56 yc11xx_audio.o(.text) - Audio_DacInitRampDown 0x00004061 Thumb Code 76 yc11xx_audio.o(.text) - Audio_AdacAdjustDigitalVolToCali 0x000040ad Thumb Code 96 yc11xx_audio.o(.text) - Audio_DacSetVolBeforeCalibration 0x0000410d Thumb Code 8 yc11xx_audio.o(.text) - Audio_DacAnaClkEnable 0x00004115 Thumb Code 208 yc11xx_audio.o(.text) - Audio_DacSdm 0x000041e5 Thumb Code 56 yc11xx_audio.o(.text) - Audio_DacFilter 0x0000421d Thumb Code 56 yc11xx_audio.o(.text) - Audio_DacCoefInit 0x00004255 Thumb Code 488 yc11xx_audio.o(.text) - Audio_DacAnalogSel44k 0x0000443d Thumb Code 56 yc11xx_audio.o(.text) - Audio_LoadDacCoefCommon 0x00004475 Thumb Code 16 yc11xx_audio.o(.text) - Audio_LoadDac44kCoef 0x00004485 Thumb Code 18 yc11xx_audio.o(.text) - Audio_DacSamplefreqSel44k 0x00004497 Thumb Code 12 yc11xx_audio.o(.text) - Audio_DacAnalogSel48k 0x000044a3 Thumb Code 56 yc11xx_audio.o(.text) - Audio_LoadDac48kCoef 0x000044db Thumb Code 18 yc11xx_audio.o(.text) - Audio_DacSamplefreqSel48k 0x000044ed Thumb Code 32 yc11xx_audio.o(.text) - Audio_LoadDac8kCoef 0x0000450d Thumb Code 20 yc11xx_audio.o(.text) - Audio_LoadDac16kCoef 0x00004521 Thumb Code 8 yc11xx_audio.o(.text) - Audio_DacSamplefreqSel16k 0x00004529 Thumb Code 12 yc11xx_audio.o(.text) - Audio_DacSamplefreqSel8k 0x00004535 Thumb Code 12 yc11xx_audio.o(.text) - Audio_DacClkCheck 0x00004541 Thumb Code 56 yc11xx_audio.o(.text) - Audio_DlychainDacInit 0x00004579 Thumb Code 326 yc11xx_audio.o(.text) - Audio_DacSdmDisable 0x000046bf Thumb Code 56 yc11xx_audio.o(.text) - Audio_DacFilterDisable 0x000046f7 Thumb Code 56 yc11xx_audio.o(.text) - Audio_DacAnaClkDisable 0x0000472f Thumb Code 208 yc11xx_audio.o(.text) - Audio_DacSetSampleRate 0x000047ff Thumb Code 98 yc11xx_audio.o(.text) - Audio_DacInitForPop 0x00004861 Thumb Code 330 yc11xx_audio.o(.text) - Audio_AdacStartPAWithPop 0x000049ab Thumb Code 230 yc11xx_audio.o(.text) - Audio_DaAaddaBgDisable 0x00004a91 Thumb Code 106 yc11xx_audio.o(.text) - Audio_DacDisableDaAdacOpaDummy 0x00004afb Thumb Code 40 yc11xx_audio.o(.text) - Audio_DacDisableDaAdacInt 0x00004b23 Thumb Code 48 yc11xx_audio.o(.text) - Audio_DacDisableDaAdacOpa 0x00004b53 Thumb Code 48 yc11xx_audio.o(.text) - Audio_DacDisableDaAdacPath 0x00004b83 Thumb Code 48 yc11xx_audio.o(.text) - Audio_DacDisableDaAdacDepopSw 0x00004bb3 Thumb Code 48 yc11xx_audio.o(.text) - Audio_DacSetDaAdacOpaMainToDummyR 0x00004be3 Thumb Code 44 yc11xx_audio.o(.text) - Audio_DacSetDaAdacOpaMainToDummyL 0x00004c0f Thumb Code 44 yc11xx_audio.o(.text) - Audio_DacSetDaAdacOpaMainToDummy 0x00004c3b Thumb Code 56 yc11xx_audio.o(.text) - Audio_AdacAdjustDCCaliToNormal 0x00004c73 Thumb Code 124 yc11xx_audio.o(.text) - Audio_AdacPreparePAClose 0x00004cef Thumb Code 12 yc11xx_audio.o(.text) - Audio_DacCheckDaAdacOpaEnable 0x00004cfb Thumb Code 34 yc11xx_audio.o(.text) - Audio_AdacStopPAWithPop 0x00004d1d Thumb Code 804 yc11xx_audio.o(.text) - Audio_AdacCheckLastDacClkSame 0x00005041 Thumb Code 18 yc11xx_audio.o(.text) - Audio_DacInit 0x00005053 Thumb Code 826 yc11xx_audio.o(.text) - Audio_DacInitMono 0x0000538d Thumb Code 30 yc11xx_audio.o(.text) - Audio_DacInitTwsRightMonoStero 0x000053ab Thumb Code 30 yc11xx_audio.o(.text) - Audio_DacInitTwsLeftMonoStero 0x000053c9 Thumb Code 30 yc11xx_audio.o(.text) - Audio_DacInitVpCall 0x000053e7 Thumb Code 84 yc11xx_audio.o(.text) - Audio_CvsdInitDac 0x0000543b Thumb Code 152 yc11xx_audio.o(.text) - NrAec_Init 0x000054d3 Thumb Code 2 yc11xx_audio.o(.text) - Audio_AdcDmaEnable 0x000054d5 Thumb Code 66 yc11xx_audio.o(.text) - Audio_AdcStart8K 0x00005517 Thumb Code 386 yc11xx_audio.o(.text) - Audio_AdcFilterInit 0x00005699 Thumb Code 354 yc11xx_audio.o(.text) - Audio_AnaAdcHighControlEn 0x000057fb Thumb Code 104 yc11xx_audio.o(.text) - Audio_AnaAdcLowControlEn 0x00005863 Thumb Code 118 yc11xx_audio.o(.text) - Audio_AnaStartAdcWork 0x000058d9 Thumb Code 16 yc11xx_audio.o(.text) - Audio_AdcInit 0x000058e9 Thumb Code 188 yc11xx_audio.o(.text) - Audio_AdcCvsdInit 0x000059a5 Thumb Code 652 yc11xx_audio.o(.text) - Audio_CvsdInitProcess 0x00005c31 Thumb Code 1540 yc11xx_audio.o(.text) - Audio_CvsdInit 0x00006235 Thumb Code 12 yc11xx_audio.o(.text) - Audio_SbcBusyWait 0x00006241 Thumb Code 30 yc11xx_audio.o(.text) - Audio_SbcClkOff 0x0000625f Thumb Code 208 yc11xx_audio.o(.text) - Audio_SbcStop 0x0000632f Thumb Code 164 yc11xx_audio.o(.text) - Audio_mSbcStop 0x000063d3 Thumb Code 8 yc11xx_audio.o(.text) - Audio_DacVolAdjust 0x000063db Thumb Code 104 yc11xx_audio.o(.text) - Audio_CheckDacMRAMSelect 0x00006443 Thumb Code 30 yc11xx_audio.o(.text) - Audio_DacInitStero 0x00006461 Thumb Code 30 yc11xx_audio.o(.text) - Audio_DacInitMedia 0x0000647f Thumb Code 84 yc11xx_audio.o(.text) - Audio_CheckDacEmpty 0x000064d3 Thumb Code 110 yc11xx_audio.o(.text) - Audio_TishiAddressInit 0x00006541 Thumb Code 114 yc11xx_audio.o(.text) - Audio_TishiEnable 0x000065b3 Thumb Code 30 yc11xx_audio.o(.text) - Audio_TishiDisable 0x000065d1 Thumb Code 90 yc11xx_audio.o(.text) - Audio_CheckTishiMRAMSelect 0x0000662b Thumb Code 26 yc11xx_audio.o(.text) - Audio_AdacOpaCmnSel 0x00006645 Thumb Code 84 yc11xx_audio.o(.text) - Audio_AdacHPPAOutputStageQuiescentCurrentControl 0x00006699 Thumb Code 84 yc11xx_audio.o(.text) - Audio_HPPACascodeVoltageControl 0x000066ed Thumb Code 162 yc11xx_audio.o(.text) - Audio_AdacRefCtrl 0x0000678f Thumb Code 44 yc11xx_audio.o(.text) - Audio_AdacBiasSel 0x000067bb Thumb Code 44 yc11xx_audio.o(.text) - Audio_AdacOpacmpSel 0x000067e7 Thumb Code 44 yc11xx_audio.o(.text) - Audio_AdacOpaBiasSel 0x00006813 Thumb Code 44 yc11xx_audio.o(.text) - Audio_AdacOpamcmpSel 0x0000683f Thumb Code 44 yc11xx_audio.o(.text) - Audio_AdacVCMIOPA_SEL 0x0000686b Thumb Code 44 yc11xx_audio.o(.text) - Audio_AdacComVoltageBufferModeSet 0x00006897 Thumb Code 44 yc11xx_audio.o(.text) - Audio_AdacFeedbackCapControl 0x000068c3 Thumb Code 44 yc11xx_audio.o(.text) - Audio_DacLDOOutputControl 0x000068ef Thumb Code 44 yc11xx_audio.o(.text) - Audio_AdacDacCommonModeVoltageControl 0x0000691b Thumb Code 44 yc11xx_audio.o(.text) - Audio_AdacLdoAvddByPassEnable 0x00006947 Thumb Code 36 yc11xx_audio.o(.text) - Audio_AdacLdoHpvddByPassEnable 0x0000696b Thumb Code 36 yc11xx_audio.o(.text) - Audio_AdacSetAnaVolRight 0x0000698f Thumb Code 44 yc11xx_audio.o(.text) - Audio_AdacSetAnaVolLeft 0x000069bb Thumb Code 98 yc11xx_audio.o(.text) - Audio_AdacPorDefaultInit 0x00006a1d Thumb Code 820 yc11xx_audio.o(.text) - Audio_DacSetDaEnAdacOpaDummyL 0x00006d51 Thumb Code 56 yc11xx_audio.o(.text) - Audio_DacSetDaEnAdacOpaDummyR 0x00006d89 Thumb Code 56 yc11xx_audio.o(.text) - Audio_AdacGetAnaVolLeft 0x00006dc1 Thumb Code 50 yc11xx_audio.o(.text) - Audio_AdacGetAnaVolRight 0x00006df3 Thumb Code 26 yc11xx_audio.o(.text) - Audio_AdacCheckAnaVolAlreadyNormal 0x00006e0d Thumb Code 22 yc11xx_audio.o(.text) - Audio_AdacAdjustAnaVolToNormal 0x00006e23 Thumb Code 34 yc11xx_audio.o(.text) - Audio_AdacCheckAnaVolAlreadyLimit 0x00006e45 Thumb Code 22 yc11xx_audio.o(.text) - Audio_AdacAdjustAnaVolToLimit 0x00006e5b Thumb Code 60 yc11xx_audio.o(.text) - Audio_CBClosePaDelay 0x00006e97 Thumb Code 10 yc11xx_audio.o(.text) - Audio_AvdStopSbcDac 0x00006ea1 Thumb Code 24 yc11xx_audio.o(.text) - Audio_CheckDacEnable 0x00006eb9 Thumb Code 24 yc11xx_audio.o(.text) - SetLockQSPI 0x00006edd Thumb Code 14 yc11xx_qspi.o(.text) - SetReleaseQSPI 0x00006eeb Thumb Code 14 yc11xx_qspi.o(.text) - prefetch 0x00006ef9 Thumb Code 24 yc11xx_qspi.o(.text) - qspi_dma_start 0x00006f11 Thumb Code 132 yc11xx_qspi.o(.text) - qspi_dma_wait 0x00006f95 Thumb Code 48 yc11xx_qspi.o(.text) - qspi_write 0x00006fc5 Thumb Code 112 yc11xx_qspi.o(.text) - qspi_read_write 0x00007035 Thumb Code 116 yc11xx_qspi.o(.text) - qspi_flash_cmd 0x000070a9 Thumb Code 16 yc11xx_qspi.o(.text) - qspi_flash_readstatus1 0x000070b9 Thumb Code 22 yc11xx_qspi.o(.text) - qspi_flash_readstatus2 0x000070cf Thumb Code 22 yc11xx_qspi.o(.text) - qspi_flash_waitfinish 0x000070e5 Thumb Code 48 yc11xx_qspi.o(.text) - qspi_flash_writestatus 0x00007115 Thumb Code 44 yc11xx_qspi.o(.text) - qspi_flash_quadenable 0x00007141 Thumb Code 72 yc11xx_qspi.o(.text) - qspi_flash_writeenable 0x00007189 Thumb Code 10 yc11xx_qspi.o(.text) - qspi_flash_writedisable 0x00007193 Thumb Code 10 yc11xx_qspi.o(.text) - qspi_flash_precmd 0x0000719d Thumb Code 20 yc11xx_qspi.o(.text) - _qspi_flash_write 0x000071b1 Thumb Code 132 yc11xx_qspi.o(.text) - _qspi_flash_chiperase 0x00007235 Thumb Code 30 yc11xx_qspi.o(.text) - _qspi_flash_erase 0x00007253 Thumb Code 60 yc11xx_qspi.o(.text) - _qspi_flash_read 0x0000728f Thumb Code 362 yc11xx_qspi.o(.text) - _qspi_flash_JEDECID 0x000073f9 Thumb Code 44 yc11xx_qspi.o(.text) - qspi_flash_sectorerase 0x00007425 Thumb Code 22 yc11xx_qspi.o(.text) - qspi_flash_blockerase32k 0x0000743b Thumb Code 22 yc11xx_qspi.o(.text) - qspi_flash_blockerase64k 0x00007451 Thumb Code 22 yc11xx_qspi.o(.text) - qspi_flash_blockerasepage 0x00007467 Thumb Code 22 yc11xx_qspi.o(.text) - qspi_flash_chiperase 0x0000747d Thumb Code 16 yc11xx_qspi.o(.text) - qspi_flash_write 0x0000748d Thumb Code 28 yc11xx_qspi.o(.text) - qspi_flash_read 0x000074a9 Thumb Code 32 yc11xx_qspi.o(.text) - qspi_flash_JEDECID 0x000074c9 Thumb Code 16 yc11xx_qspi.o(.text) - QSPI_ReadFlashDataToXRAM 0x000074d9 Thumb Code 124 yc11xx_qspi.o(.text) - QSPI_ReadFlashData 0x00007555 Thumb Code 38 yc11xx_qspi.o(.text) - QSPI_WriteFlashData 0x0000757b Thumb Code 36 yc11xx_qspi.o(.text) - QSPI_SectorEraseFlash 0x0000759f Thumb Code 28 yc11xx_qspi.o(.text) - _QSPI_WriteFlashData 0x000075bb Thumb Code 30 yc11xx_qspi.o(.text) - _Qspi_WritebyEarsePage 0x000075d9 Thumb Code 80 yc11xx_qspi.o(.text) - QSPI_WriteFlashDatabyPage 0x00007629 Thumb Code 128 yc11xx_qspi.o(.text) - YC_FlashWrite 0x000076a9 Thumb Code 22 yc11xx_qspi.o(.text) - __aeabi_uidiv 0x000076f1 Thumb Code 0 uidiv.o(.text) - __aeabi_uidivmod 0x000076f1 Thumb Code 44 uidiv.o(.text) - __aeabi_idiv 0x0000771d Thumb Code 0 idiv.o(.text) - __aeabi_idivmod 0x0000771d Thumb Code 40 idiv.o(.text) - __aeabi_memset 0x00007745 Thumb Code 14 memseta.o(.text) - __aeabi_memset4 0x00007745 Thumb Code 0 memseta.o(.text) - __aeabi_memset8 0x00007745 Thumb Code 0 memseta.o(.text) - __aeabi_memclr 0x00007753 Thumb Code 4 memseta.o(.text) - __aeabi_memclr4 0x00007753 Thumb Code 0 memseta.o(.text) - __aeabi_memclr8 0x00007753 Thumb Code 0 memseta.o(.text) - _memset$wrapper 0x00007757 Thumb Code 18 memseta.o(.text) - __scatterload 0x00007769 Thumb Code 28 init.o(.text) - __scatterload_rt2 0x00007769 Thumb Code 0 init.o(.text) - __scatterload_copy 0x0000778d Thumb Code 14 handlers.o(i.__scatterload_copy) - __scatterload_null 0x0000779b Thumb Code 2 handlers.o(i.__scatterload_null) - __scatterload_zeroinit 0x0000779d Thumb Code 14 handlers.o(i.__scatterload_zeroinit) - Region$$Table$$Base 0x00007844 Number 0 anon$$obj.o(Region$$Table) - Region$$Table$$Limit 0x00007864 Number 0 anon$$obj.o(Region$$Table) - AdcBufferReadPtr 0x10011000 Data 2 main.o(.data) - pheader 0x10011004 Data 4 yc_timer.o(.data) - sys_tick_count 0x10011008 Data 4 yc_timer.o(.data) - gSystemTimerAdjustClknbt 0x1001100c Data 4 yc_timer.o(.data) - sys_Timer_Check_Flag 0x10011010 Data 1 yc_timer.o(.data) - gSystemInFastDpll 0x10011011 Data 1 yc_timer.o(.data) - SystickCount 0x10011014 Data 4 yc11xx_systick.o(.data) - uartB_TX_buf 0x1001101c Data 2 yc11xx_uart.o(.data) - uartB_RX_buf 0x1001101e Data 2 yc11xx_uart.o(.data) - gDacBufOffset 0x10011020 Data 2 yc11xx_audio.o(.data) - gDacDcCaliTargetLeft 0x10011022 Data 2 yc11xx_audio.o(.data) - gDacDcCaliTargetRight 0x10011024 Data 2 yc11xx_audio.o(.data) - gDacAnaVolTargetLeft 0x10011026 Data 1 yc11xx_audio.o(.data) - gDacAnaVolTargetRight 0x10011027 Data 1 yc11xx_audio.o(.data) - gLastStartDacClk 0x10011028 Data 1 yc11xx_audio.o(.data) - header_Timer 0x1001102c Data 24 yc_timer.o(.bss) - regBeck 0x10011044 Data 32 yc11xx_uart.o(.bss) - uartA_TX_buf 0x10011064 Data 4097 yc11xx_uart.o(.bss) - uartA_RX_buf 0x10012065 Data 4097 yc11xx_uart.o(.bss) - gClosePaDelayTimer 0x10013068 Data 24 yc11xx_audio.o(.bss) - __initial_sp 0x1001b640 Number 0 startup.o ABSOLUTE - - - -============================================================================== - -Memory Map of the image - - Image Entry point : 0x00001001 - - Load Region LR_IROM1 (Base: 0x00000000, Size: 0x000000e8, Max: 0x00001000, ABSOLUTE) - - Execution Region ER_IROM1 (Exec base: 0x00000000, Load base: 0x00000000, Size: 0x000000e8, Max: 0x00001000, ABSOLUTE) - - Exec Addr Load Addr Size Type Attr Idx E Section Name Object - - 0x00000000 0x00000000 0x000000c0 Data RO 76 RESET startup.o - 0x000000c0 0x000000c0 0x00000028 Code RO 77 .text startup.o - - - - Load Region LR_IROM2 (Base: 0x00001000, Size: 0x00006890, Max: 0x00080000, ABSOLUTE) - - Execution Region ER_IROM2 (Exec base: 0x00001000, Load base: 0x00001000, Size: 0x00006864, Max: 0xffffffff, ABSOLUTE) - - Exec Addr Load Addr Size Type Attr Idx E Section Name Object - - 0x00001000 0x00001000 0x00000000 Code RO 343 * .ARM.Collect$$$$00000000 mc_p.l(entry.o) - 0x00001000 0x00001000 0x00000004 Code RO 356 .ARM.Collect$$$$00000001 mc_p.l(entry2.o) - 0x00001004 0x00001004 0x00000004 Code RO 359 .ARM.Collect$$$$00000004 mc_p.l(entry5.o) - 0x00001008 0x00001008 0x00000000 Code RO 361 .ARM.Collect$$$$00000008 mc_p.l(entry7b.o) - 0x00001008 0x00001008 0x00000000 Code RO 363 .ARM.Collect$$$$0000000A mc_p.l(entry8b.o) - 0x00001008 0x00001008 0x00000008 Code RO 364 .ARM.Collect$$$$0000000B mc_p.l(entry9a.o) - 0x00001010 0x00001010 0x00000000 Code RO 366 .ARM.Collect$$$$0000000D mc_p.l(entry10a.o) - 0x00001010 0x00001010 0x00000000 Code RO 368 .ARM.Collect$$$$0000000F mc_p.l(entry11a.o) - 0x00001010 0x00001010 0x00000004 Code RO 357 .ARM.Collect$$$$00002712 mc_p.l(entry2.o) - 0x00001014 0x00001014 0x00000224 Code RO 1 .text main.o - 0x00001238 0x00001238 0x00000abc Code RO 82 .text yc11xx_gpio.o - 0x00001cf4 0x00001cf4 0x000004e8 Code RO 113 .text yc_timer.o - 0x000021dc 0x000021dc 0x00000058 Code RO 129 .text yc11xx_systick.o - 0x00002234 0x00002234 0x000008ac Code RO 188 .text yc11xx_uart.o - 0x00002ae0 0x00002ae0 0x00000220 Code RO 234 .text yc_drv_common.o - 0x00002d00 0x00002d00 0x000041dc Code RO 259 .text yc11xx_audio.o - 0x00006edc 0x00006edc 0x00000814 Code RO 281 .text yc11xx_qspi.o - 0x000076f0 0x000076f0 0x0000002c Code RO 346 .text mc_p.l(uidiv.o) - 0x0000771c 0x0000771c 0x00000028 Code RO 348 .text mc_p.l(idiv.o) - 0x00007744 0x00007744 0x00000024 Code RO 352 .text mc_p.l(memseta.o) - 0x00007768 0x00007768 0x00000024 Code RO 370 .text mc_p.l(init.o) - 0x0000778c 0x0000778c 0x0000000e Code RO 374 i.__scatterload_copy mc_p.l(handlers.o) - 0x0000779a 0x0000779a 0x00000002 Code RO 375 i.__scatterload_null mc_p.l(handlers.o) - 0x0000779c 0x0000779c 0x0000000e Code RO 376 i.__scatterload_zeroinit mc_p.l(handlers.o) - 0x000077aa 0x000077aa 0x0000009a Data RO 190 .constdata yc11xx_uart.o - 0x00007844 0x00007844 0x00000020 Data RO 372 Region$$Table anon$$obj.o - - - Execution Region RW_IRAM1 (Exec base: 0x10010000, Load base: 0x00007864, Size: 0x00000000, Max: 0x00001000, ABSOLUTE) - - **** No section assigned to this execution region **** - - - Execution Region RW_IRAM3 (Exec base: 0x10011000, Load base: 0x00007864, Size: 0x00002080, Max: 0x0000c800, ABSOLUTE) - - Exec Addr Load Addr Size Type Attr Idx E Section Name Object - - 0x10011000 0x00007864 0x00000002 Data RW 2 .data main.o - 0x10011002 0x00007866 0x00000002 PAD - 0x10011004 0x00007868 0x0000000e Data RW 115 .data yc_timer.o - 0x10011012 0x00007876 0x00000002 PAD - 0x10011014 0x00007878 0x00000004 Data RW 130 .data yc11xx_systick.o - 0x10011018 0x0000787c 0x00000008 Data RW 191 .data yc11xx_uart.o - 0x10011020 0x00007884 0x00000009 Data RW 261 .data yc11xx_audio.o - 0x10011029 0x0000788d 0x00000003 PAD - 0x1001102c - 0x00000018 Zero RW 114 .bss yc_timer.o - 0x10011044 - 0x00002022 Zero RW 189 .bss yc11xx_uart.o - 0x10013066 0x0000788d 0x00000002 PAD - 0x10013068 - 0x00000018 Zero RW 260 .bss yc11xx_audio.o - - -============================================================================== - -Image component sizes - - - Code (inc. data) RO Data RW Data ZI Data Debug Object Name - - 548 30 0 2 0 9973 main.o - 40 20 192 0 0 528 startup.o - 16860 340 0 9 24 31545 yc11xx_audio.o - 2748 42 0 0 0 28448 yc11xx_gpio.o - 2068 66 0 0 0 12696 yc11xx_qspi.o - 88 12 0 4 0 1618 yc11xx_systick.o - 2220 162 154 8 8226 6114 yc11xx_uart.o - 544 14 0 0 0 4750 yc_drv_common.o - 1256 62 0 14 24 6548 yc_timer.o - 0 0 0 0 0 4272 yc_uart.o - - ---------------------------------------------------------------------- - 26372 748 378 44 8276 106492 Object Totals - 0 0 32 0 0 0 (incl. Generated) - 0 0 0 7 2 0 (incl. Padding) - - ---------------------------------------------------------------------- - - Code (inc. data) RO Data RW Data ZI Data Debug Library Member Name - - 0 0 0 0 0 0 entry.o - 0 0 0 0 0 0 entry10a.o - 0 0 0 0 0 0 entry11a.o - 8 4 0 0 0 0 entry2.o - 4 0 0 0 0 0 entry5.o - 0 0 0 0 0 0 entry7b.o - 0 0 0 0 0 0 entry8b.o - 8 4 0 0 0 0 entry9a.o - 30 0 0 0 0 0 handlers.o - 40 0 0 0 0 72 idiv.o - 36 8 0 0 0 68 init.o - 36 0 0 0 0 100 memseta.o - 44 0 0 0 0 72 uidiv.o - - ---------------------------------------------------------------------- - 206 16 0 0 0 312 Library Totals - 0 0 0 0 0 0 (incl. Padding) - - ---------------------------------------------------------------------- - - Code (inc. data) RO Data RW Data ZI Data Debug Library Name - - 206 16 0 0 0 312 mc_p.l - - ---------------------------------------------------------------------- - 206 16 0 0 0 312 Library Totals - - ---------------------------------------------------------------------- - -============================================================================== - - - Code (inc. data) RO Data RW Data ZI Data Debug - - 26578 764 378 44 8276 106164 Grand Totals - 26578 764 378 44 8276 106164 ELF Image Totals - 26578 764 378 44 0 0 ROM Totals - -============================================================================== - - Total RO Size (Code + RO Data) 26956 ( 26.32kB) - Total RW Size (RW Data + ZI Data) 8320 ( 8.13kB) - Total ROM Size (Code + RO Data + RW Data) 27000 ( 26.37kB) - -============================================================================== - Index: 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-5f545241 -74696e49 -41535500 -445f5452 -696e4965 -53550074 -5f545241 -646e6553 -61746144 -41535500 -525f5452 -69656365 -61446576 -55006174 -54524153 -7465475f -6f437852 -00746e75 -52415355 -65525f54 -61446461 -6f746174 -66667542 -41535500 -535f5452 -44646e65 -46617461 -426d6f72 -00666675 -52415355 -65535f54 -49785274 -6d754e54 -41535500 -535f5452 -78527465 -656d6954 -0074756f -00007864 -10011000 -0000002c -0000778c -00007890 -1001102c -00002054 -0000779c -0000b800 -00000000 -00000000 -00000000 -00000000 -00000000 -170c1c19 -00000000 -00000000 -00000000 -00000000 Index: tag/Soft/ModuleDemo/ADC/AD_Sound_Recording/CM0/Prj/MDK/yc11xx_asm.txt =================================================================== --- /YC1121E/SoftCode/MCU/tag/Soft/ModuleDemo/ADC/AD_Sound_Recording/CM0/Prj/MDK/yc11xx_asm.txt (revision 4280) +++ /YC1121E/SoftCode/MCU/tag/Soft/ModuleDemo/ADC/AD_Sound_Recording/CM0/Prj/MDK/yc11xx_asm.txt (working copy) @@ -31,8 +31,8 @@ Program header entries: 2 Section header entries: 17 - Program header offset: 166028 (0x0002888c) - Section header offset: 166092 (0x000288cc) + Program header offset: 108792 (0x0001a8f8) + Section header offset: 108856 (0x0001a938) Section header string table index: 16 @@ -46,7 +46,7 @@ ==================================== ** Program header #1 (PT_LOAD) [PF_X + PF_W + PF_R + PF_ARM_ENTRY] - Size : 35044 bytes (26768 bytes in file) + Size : 8196 bytes (7892 bytes in file) Virtual address: 0x00001000 (Alignment 4) @@ -74,7 +74,7 @@ 0x00000030: 00000000 .... DCD 0 0x00000034: 00000000 .... DCD 0 0x00000038: 000000d9 .... DCD 217 - 0x0000003c: 00001213 .... DCD 4627 + 0x0000003c: 00001135 5... DCD 4405 0x00000040: 000000d9 .... DCD 217 0x00000044: 000000d9 .... DCD 217 0x00000048: 000000d9 .... DCD 217 @@ -119,7 +119,7 @@ 0x000000ca: 4805 .H LDR r0,[pc,#20] ; [0xe0] = 0x1001 0x000000cc: 4700 .G BX r0 RUN_TO_MAIN - 0x000000ce: 4805 .H LDR r0,[pc,#20] ; [0xe4] = 0x1127 + 0x000000ce: 4805 .H LDR r0,[pc,#20] ; [0xe4] = 0x10d7 0x000000d0: 4700 .G BX r0 $d 0x000000d2: 0000 .. DCW 0 @@ -161,10 +161,10 @@ 0x000000da: 0000 .. DCW 0 0x000000dc: 000000d4 .... DCD 212 0x000000e0: 00001001 .... DCD 4097 - 0x000000e4: 00001127 '... DCD 4391 + 0x000000e4: 000010d7 .... DCD 4311 ** Section #2 'ER_IROM2' (SHT_PROGBITS) [SHF_ALLOC + SHF_EXECINSTR] - Size : 26724 bytes (alignment 4) + Size : 7864 bytes (alignment 4) Address: 0x00001000 $t @@ -176,7 +176,7 @@ 0x00001002: 4685 .F MOV sp,r0 .ARM.Collect$$$$00000004 _main_scatterload - 0x00001004: f006fbb0 .... BL __scatterload ; 0x7768 + 0x00001004: f001ff24 ..$. BL __scatterload ; 0x2e50 .ARM.Collect$$$$00000008 .ARM.Collect$$$$0000000A .ARM.Collect$$$$0000000B @@ -184,10 +184,10 @@ _main_clock _main_cpp_init _main_init - 0x00001008: 4800 .H LDR r0,[pc,#0] ; [0x100c] = 0x1127 + 0x00001008: 4800 .H LDR r0,[pc,#0] ; [0x100c] = 0x10d7 0x0000100a: 4700 .G BX r0 $d - 0x0000100c: 00001127 '... DCD 4391 + 0x0000100c: 000010d7 .... DCD 4311 .ARM.Collect$$$$00002712 __lit__00000000 .ARM.Collect$$$$0000000D @@ -197,13069 +197,3885 @@ 0x00001010: 1001b640 @... DCD 268547648 $t .text - updata_addr - 0x00001014: 4a81 .J LDR r2,[pc,#516] ; [0x121c] = 0x10011000 - 0x00001016: 8812 .. LDRH r2,[r2,#0] - 0x00001018: 1852 R. ADDS r2,r2,r1 - 0x0000101a: 4b80 .K LDR r3,[pc,#512] ; [0x121c] = 0x10011000 - 0x0000101c: 801a .. STRH r2,[r3,#0] - 0x0000101e: 461a .F MOV r2,r3 - 0x00001020: 8812 .. LDRH r2,[r2,#0] - 0x00001022: 231b .# MOVS r3,#0x1b - 0x00001024: 02db .. LSLS r3,r3,#11 - 0x00001026: 429a .B CMP r2,r3 - 0x00001028: db03 .. BLT 0x1032 ; updata_addr + 30 - 0x0000102a: 2217 ." MOVS r2,#0x17 - 0x0000102c: 02d2 .. LSLS r2,r2,#11 - 0x0000102e: 4b7b {K LDR r3,[pc,#492] ; [0x121c] = 0x10011000 - 0x00001030: 801a .. STRH r2,[r3,#0] - 0x00001032: 4770 pG BX lr - UART_Tx_Adc_Buffer - 0x00001034: b510 .. PUSH {r4,lr} - 0x00001036: 487a zH LDR r0,[pc,#488] ; [0x1220] = 0x10004fe0 - 0x00001038: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x0000103a: 2000 . MOVS r0,#0 - 0x0000103c: 4979 yI LDR r1,[pc,#484] ; [0x1224] = 0x10008300 - 0x0000103e: 7d89 .} LDRB r1,[r1,#0x16] - 0x00001040: 4300 .C ORRS r0,r0,r0 - 0x00001042: 4978 xI LDR r1,[pc,#480] ; [0x1224] = 0x10008300 - 0x00001044: 7d89 .} LDRB r1,[r1,#0x16] - 0x00001046: 4308 .C ORRS r0,r0,r1 - 0x00001048: 4975 uI LDR r1,[pc,#468] ; [0x1220] = 0x10004fe0 - 0x0000104a: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x0000104c: 2100 .! MOVS r1,#0 - 0x0000104e: 4a75 uJ LDR r2,[pc,#468] ; [0x1224] = 0x10008300 - 0x00001050: 7dd2 .} LDRB r2,[r2,#0x17] - 0x00001052: 4309 .C ORRS r1,r1,r1 - 0x00001054: 4a73 sJ LDR r2,[pc,#460] ; [0x1224] = 0x10008300 - 0x00001056: 7dd2 .} LDRB r2,[r2,#0x17] - 0x00001058: 4311 .C ORRS r1,r1,r2 - 0x0000105a: 0209 .. LSLS r1,r1,#8 - 0x0000105c: 4308 .C ORRS r0,r0,r1 - 0x0000105e: 4604 .F MOV r4,r0 - 0x00001060: 486e nH LDR r0,[pc,#440] ; [0x121c] = 0x10011000 - 0x00001062: 8800 .. LDRH r0,[r0,#0] - 0x00001064: 4284 .B CMP r4,r0 - 0x00001066: dd17 .. BLE 0x1098 ; UART_Tx_Adc_Buffer + 100 - 0x00001068: 486c lH LDR r0,[pc,#432] ; [0x121c] = 0x10011000 - 0x0000106a: 8800 .. LDRH r0,[r0,#0] - 0x0000106c: 1a20 . SUBS r0,r4,r0 - 0x0000106e: 2802 .( CMP r0,#2 - 0x00001070: db12 .. BLT 0x1098 ; UART_Tx_Adc_Buffer + 100 - 0x00001072: 486a jH LDR r0,[pc,#424] ; [0x121c] = 0x10011000 - 0x00001074: 8800 .. LDRH r0,[r0,#0] - 0x00001076: 1a20 . SUBS r0,r4,r0 - 0x00001078: b282 .. UXTH r2,r0 - 0x0000107a: 4868 hH LDR r0,[pc,#416] ; [0x121c] = 0x10011000 - 0x0000107c: 8800 .. LDRH r0,[r0,#0] - 0x0000107e: 496a jI LDR r1,[pc,#424] ; [0x1228] = 0x10010000 - 0x00001080: 1841 A. ADDS r1,r0,r1 - 0x00001082: 2000 . MOVS r0,#0 - 0x00001084: f001fc43 ..C. BL USART_SendDataFromBuff ; 0x290e - 0x00001088: 4864 dH LDR r0,[pc,#400] ; [0x121c] = 0x10011000 - 0x0000108a: 8800 .. LDRH r0,[r0,#0] - 0x0000108c: 1a21 !. SUBS r1,r4,r0 - 0x0000108e: 4863 cH LDR r0,[pc,#396] ; [0x121c] = 0x10011000 - 0x00001090: 8800 .. LDRH r0,[r0,#0] - 0x00001092: f7ffffbf .... BL updata_addr ; 0x1014 - 0x00001096: e045 E. B 0x1124 ; UART_Tx_Adc_Buffer + 240 - 0x00001098: 4860 `H LDR r0,[pc,#384] ; [0x121c] = 0x10011000 - 0x0000109a: 8800 .. LDRH r0,[r0,#0] + Bt_ActionBeforeHibernate + 0x00001014: b510 .. PUSH {r4,lr} + 0x00001016: 2400 .$ MOVS r4,#0 + 0x00001018: e05a Z. B 0x10d0 ; Bt_ActionBeforeHibernate + 188 + 0x0000101a: 2c1a ., CMP r4,#0x1a + 0x0000101c: d04d M. BEQ 0x10ba ; Bt_ActionBeforeHibernate + 166 + 0x0000101e: 4847 GH LDR r0,[pc,#284] ; [0x113c] = 0x10004fe0 + 0x00001020: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x00001022: 2000 . MOVS r0,#0 + 0x00001024: 4946 FI LDR r1,[pc,#280] ; [0x1140] = 0x10004340 + 0x00001026: 7989 .y LDRB r1,[r1,#6] + 0x00001028: 4300 .C ORRS r0,r0,r0 + 0x0000102a: 4945 EI LDR r1,[pc,#276] ; [0x1140] = 0x10004340 + 0x0000102c: 7989 .y LDRB r1,[r1,#6] + 0x0000102e: 4308 .C ORRS r0,r0,r1 + 0x00001030: 06c0 .. LSLS r0,r0,#27 + 0x00001032: 0ec0 .. LSRS r0,r0,#27 + 0x00001034: 42a0 .B CMP r0,r4 + 0x00001036: d040 @. BEQ 0x10ba ; Bt_ActionBeforeHibernate + 166 + 0x00001038: 4840 @H LDR r0,[pc,#256] ; [0x113c] = 0x10004fe0 + 0x0000103a: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x0000103c: 2000 . MOVS r0,#0 + 0x0000103e: 4940 @I LDR r1,[pc,#256] ; [0x1140] = 0x10004340 + 0x00001040: 79c9 .y LDRB r1,[r1,#7] + 0x00001042: 4300 .C ORRS r0,r0,r0 + 0x00001044: 493e >I LDR r1,[pc,#248] ; [0x1140] = 0x10004340 + 0x00001046: 79c9 .y LDRB r1,[r1,#7] + 0x00001048: 4308 .C ORRS r0,r0,r1 + 0x0000104a: 06c0 .. LSLS r0,r0,#27 + 0x0000104c: 0ec0 .. LSRS r0,r0,#27 + 0x0000104e: 42a0 .B CMP r0,r4 + 0x00001050: d033 3. BEQ 0x10ba ; Bt_ActionBeforeHibernate + 166 + 0x00001052: 483a :H LDR r0,[pc,#232] ; [0x113c] = 0x10004fe0 + 0x00001054: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x00001056: 2000 . MOVS r0,#0 + 0x00001058: 4939 9I LDR r1,[pc,#228] ; [0x1140] = 0x10004340 + 0x0000105a: 7a09 .z LDRB r1,[r1,#8] + 0x0000105c: 4300 .C ORRS r0,r0,r0 + 0x0000105e: 4938 8I LDR r1,[pc,#224] ; [0x1140] = 0x10004340 + 0x00001060: 7a09 .z LDRB r1,[r1,#8] + 0x00001062: 4308 .C ORRS r0,r0,r1 + 0x00001064: 06c0 .. LSLS r0,r0,#27 + 0x00001066: 0ec0 .. LSRS r0,r0,#27 + 0x00001068: 42a0 .B CMP r0,r4 + 0x0000106a: d026 &. BEQ 0x10ba ; Bt_ActionBeforeHibernate + 166 + 0x0000106c: 4833 3H LDR r0,[pc,#204] ; [0x113c] = 0x10004fe0 + 0x0000106e: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x00001070: 2000 . MOVS r0,#0 + 0x00001072: 4933 3I LDR r1,[pc,#204] ; [0x1140] = 0x10004340 + 0x00001074: 7a49 Iz LDRB r1,[r1,#9] + 0x00001076: 4300 .C ORRS r0,r0,r0 + 0x00001078: 4931 1I LDR r1,[pc,#196] ; [0x1140] = 0x10004340 + 0x0000107a: 7a49 Iz LDRB r1,[r1,#9] + 0x0000107c: 4308 .C ORRS r0,r0,r1 + 0x0000107e: 06c0 .. LSLS r0,r0,#27 + 0x00001080: 0ec0 .. LSRS r0,r0,#27 + 0x00001082: 42a0 .B CMP r0,r4 + 0x00001084: d019 .. BEQ 0x10ba ; Bt_ActionBeforeHibernate + 166 + 0x00001086: 482d -H LDR r0,[pc,#180] ; [0x113c] = 0x10004fe0 + 0x00001088: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x0000108a: 2000 . MOVS r0,#0 + 0x0000108c: 492c ,I LDR r1,[pc,#176] ; [0x1140] = 0x10004340 + 0x0000108e: 7a89 .z LDRB r1,[r1,#0xa] + 0x00001090: 4300 .C ORRS r0,r0,r0 + 0x00001092: 492b +I LDR r1,[pc,#172] ; [0x1140] = 0x10004340 + 0x00001094: 7a89 .z LDRB r1,[r1,#0xa] + 0x00001096: 4308 .C ORRS r0,r0,r1 + 0x00001098: 06c0 .. LSLS r0,r0,#27 + 0x0000109a: 0ec0 .. LSRS r0,r0,#27 0x0000109c: 42a0 .B CMP r0,r4 - 0x0000109e: dd41 A. BLE 0x1124 ; UART_Tx_Adc_Buffer + 240 - 0x000010a0: 485f _H LDR r0,[pc,#380] ; [0x1220] = 0x10004fe0 + 0x0000109e: d00c .. BEQ 0x10ba ; Bt_ActionBeforeHibernate + 166 + 0x000010a0: 4826 &H LDR r0,[pc,#152] ; [0x113c] = 0x10004fe0 0x000010a2: 7fc0 .. LDRB r0,[r0,#0x1f] 0x000010a4: 2000 . MOVS r0,#0 - 0x000010a6: 4961 aI LDR r1,[pc,#388] ; [0x122c] = 0x10004ac0 + 0x000010a6: 4926 &I LDR r1,[pc,#152] ; [0x1140] = 0x10004340 0x000010a8: 7ac9 .z LDRB r1,[r1,#0xb] 0x000010aa: 4300 .C ORRS r0,r0,r0 - 0x000010ac: 495f _I LDR r1,[pc,#380] ; [0x122c] = 0x10004ac0 + 0x000010ac: 4924 $I LDR r1,[pc,#144] ; [0x1140] = 0x10004340 0x000010ae: 7ac9 .z LDRB r1,[r1,#0xb] 0x000010b0: 4308 .C ORRS r0,r0,r1 - 0x000010b2: 495b [I LDR r1,[pc,#364] ; [0x1220] = 0x10004fe0 - 0x000010b4: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x000010b6: 2100 .! MOVS r1,#0 - 0x000010b8: 4a5c \J LDR r2,[pc,#368] ; [0x122c] = 0x10004ac0 - 0x000010ba: 7b12 .{ LDRB r2,[r2,#0xc] - 0x000010bc: 4309 .C ORRS r1,r1,r1 - 0x000010be: 4a5b [J LDR r2,[pc,#364] ; [0x122c] = 0x10004ac0 - 0x000010c0: 7b12 .{ LDRB r2,[r2,#0xc] - 0x000010c2: 4311 .C ORRS r1,r1,r2 - 0x000010c4: 0209 .. LSLS r1,r1,#8 - 0x000010c6: 4308 .C ORRS r0,r0,r1 - 0x000010c8: 4954 TI LDR r1,[pc,#336] ; [0x121c] = 0x10011000 - 0x000010ca: 8809 .. LDRH r1,[r1,#0] - 0x000010cc: 1b09 .. SUBS r1,r1,r4 - 0x000010ce: 1a40 @. SUBS r0,r0,r1 - 0x000010d0: 2802 .( CMP r0,#2 - 0x000010d2: dd27 '. BLE 0x1124 ; UART_Tx_Adc_Buffer + 240 - 0x000010d4: 4851 QH LDR r0,[pc,#324] ; [0x121c] = 0x10011000 - 0x000010d6: 8800 .. LDRH r0,[r0,#0] - 0x000010d8: 211b .! MOVS r1,#0x1b - 0x000010da: 02c9 .. LSLS r1,r1,#11 - 0x000010dc: 1a08 .. SUBS r0,r1,r0 - 0x000010de: b282 .. UXTH r2,r0 - 0x000010e0: 484e NH LDR r0,[pc,#312] ; [0x121c] = 0x10011000 - 0x000010e2: 8800 .. LDRH r0,[r0,#0] - 0x000010e4: 4950 PI LDR r1,[pc,#320] ; [0x1228] = 0x10010000 - 0x000010e6: 1841 A. ADDS r1,r0,r1 - 0x000010e8: 2000 . MOVS r0,#0 - 0x000010ea: f001fc10 .... BL USART_SendDataFromBuff ; 0x290e - 0x000010ee: 484b KH LDR r0,[pc,#300] ; [0x121c] = 0x10011000 - 0x000010f0: 8800 .. LDRH r0,[r0,#0] - 0x000010f2: 221b ." MOVS r2,#0x1b - 0x000010f4: 02d2 .. LSLS r2,r2,#11 - 0x000010f6: 1a11 .. SUBS r1,r2,r0 - 0x000010f8: 4848 HH LDR r0,[pc,#288] ; [0x121c] = 0x10011000 - 0x000010fa: 8800 .. LDRH r0,[r0,#0] - 0x000010fc: f7ffff8a .... BL updata_addr ; 0x1014 - 0x00001100: 2017 . MOVS r0,#0x17 - 0x00001102: 02c0 .. LSLS r0,r0,#11 - 0x00001104: 1a20 . SUBS r0,r4,r0 - 0x00001106: b282 .. UXTH r2,r0 - 0x00001108: 4844 DH LDR r0,[pc,#272] ; [0x121c] = 0x10011000 - 0x0000110a: 8800 .. LDRH r0,[r0,#0] - 0x0000110c: 4946 FI LDR r1,[pc,#280] ; [0x1228] = 0x10010000 - 0x0000110e: 1841 A. ADDS r1,r0,r1 - 0x00001110: 2000 . MOVS r0,#0 - 0x00001112: f001fbfc .... BL USART_SendDataFromBuff ; 0x290e - 0x00001116: 2017 . MOVS r0,#0x17 - 0x00001118: 02c0 .. LSLS r0,r0,#11 - 0x0000111a: 1a21 !. SUBS r1,r4,r0 - 0x0000111c: 483f ?H LDR r0,[pc,#252] ; [0x121c] = 0x10011000 - 0x0000111e: 8800 .. LDRH r0,[r0,#0] - 0x00001120: f7ffff78 ..x. BL updata_addr ; 0x1014 - 0x00001124: bd10 .. POP {r4,pc} + 0x000010b2: 06c0 .. LSLS r0,r0,#27 + 0x000010b4: 0ec0 .. LSRS r0,r0,#27 + 0x000010b6: 42a0 .B CMP r0,r4 + 0x000010b8: d100 .. BNE 0x10bc ; Bt_ActionBeforeHibernate + 168 + 0x000010ba: e007 .. B 0x10cc ; Bt_ActionBeforeHibernate + 184 + 0x000010bc: 2180 .! MOVS r1,#0x80 + 0x000010be: 4620 F MOV r0,r4 + 0x000010c0: f000fa27 ..'. BL GPIO_SetGpioMultFunction ; 0x1512 + 0x000010c4: 4620 F MOV r0,r4 + 0x000010c6: f000f9c3 .... BL GPIO_ClearWakeup ; 0x1450 + 0x000010ca: bf00 .. NOP + 0x000010cc: 1c60 `. ADDS r0,r4,#1 + 0x000010ce: b2c4 .. UXTB r4,r0 + 0x000010d0: 2c28 (, CMP r4,#0x28 + 0x000010d2: dba2 .. BLT 0x101a ; Bt_ActionBeforeHibernate + 6 + 0x000010d4: bd10 .. POP {r4,pc} main - 0x00001126: 2000 . MOVS r0,#0 - 0x00001128: f000ff0b .... BL SYS_TimerInit ; 0x1f42 - 0x0000112c: 4940 @I LDR r1,[pc,#256] ; [0x1230] = 0x8034 - 0x0000112e: 2000 . MOVS r0,#0 - 0x00001130: f001f9ce .... BL UARTx_Configuration ; 0x24d0 - 0x00001134: bf00 .. NOP - 0x00001136: bf00 .. NOP - 0x00001138: 4839 9H LDR r0,[pc,#228] ; [0x1220] = 0x10004fe0 - 0x0000113a: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x0000113c: 2000 . MOVS r0,#0 - 0x0000113e: 493d =I LDR r1,[pc,#244] ; [0x1234] = 0x10008040 - 0x00001140: 7c09 .| LDRB r1,[r1,#0x10] - 0x00001142: 4300 .C ORRS r0,r0,r0 - 0x00001144: 493b ;I LDR r1,[pc,#236] ; [0x1234] = 0x10008040 - 0x00001146: 7c09 .| LDRB r1,[r1,#0x10] - 0x00001148: 4308 .C ORRS r0,r0,r1 - 0x0000114a: 4935 5I LDR r1,[pc,#212] ; [0x1220] = 0x10004fe0 - 0x0000114c: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x0000114e: 4a39 9J LDR r2,[pc,#228] ; [0x1234] = 0x10008040 - 0x00001150: 7c52 R| LDRB r2,[r2,#0x11] - 0x00001152: 4311 .C ORRS r1,r1,r2 - 0x00001154: 4a37 7J LDR r2,[pc,#220] ; [0x1234] = 0x10008040 - 0x00001156: 7c52 R| LDRB r2,[r2,#0x11] - 0x00001158: 4311 .C ORRS r1,r1,r2 - 0x0000115a: 0209 .. LSLS r1,r1,#8 - 0x0000115c: 4308 .C ORRS r0,r0,r1 - 0x0000115e: 2140 @! MOVS r1,#0x40 - 0x00001160: 4388 .C BICS r0,r0,r1 - 0x00001162: 4934 4I LDR r1,[pc,#208] ; [0x1234] = 0x10008040 - 0x00001164: 7408 .t STRB r0,[r1,#0x10] - 0x00001166: 482e .H LDR r0,[pc,#184] ; [0x1220] = 0x10004fe0 - 0x00001168: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x0000116a: 2000 . MOVS r0,#0 - 0x0000116c: 7c09 .| LDRB r1,[r1,#0x10] - 0x0000116e: 4300 .C ORRS r0,r0,r0 - 0x00001170: 4930 0I LDR r1,[pc,#192] ; [0x1234] = 0x10008040 - 0x00001172: 7c09 .| LDRB r1,[r1,#0x10] - 0x00001174: 4308 .C ORRS r0,r0,r1 - 0x00001176: 492a *I LDR r1,[pc,#168] ; [0x1220] = 0x10004fe0 - 0x00001178: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x0000117a: 4a2e .J LDR r2,[pc,#184] ; [0x1234] = 0x10008040 - 0x0000117c: 7c52 R| LDRB r2,[r2,#0x11] - 0x0000117e: 4311 .C ORRS r1,r1,r2 - 0x00001180: 4a2c ,J LDR r2,[pc,#176] ; [0x1234] = 0x10008040 - 0x00001182: 7c52 R| LDRB r2,[r2,#0x11] - 0x00001184: 4311 .C ORRS r1,r1,r2 - 0x00001186: 0209 .. LSLS r1,r1,#8 - 0x00001188: 4308 .C ORRS r0,r0,r1 - 0x0000118a: 2140 @! MOVS r1,#0x40 - 0x0000118c: 4388 .C BICS r0,r0,r1 - 0x0000118e: 4929 )I LDR r1,[pc,#164] ; [0x1234] = 0x10008040 - 0x00001190: 7408 .t STRB r0,[r1,#0x10] - 0x00001192: bf00 .. NOP - 0x00001194: bf00 .. NOP - 0x00001196: 4822 "H LDR r0,[pc,#136] ; [0x1220] = 0x10004fe0 - 0x00001198: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x0000119a: 2000 . MOVS r0,#0 - 0x0000119c: 7c09 .| LDRB r1,[r1,#0x10] - 0x0000119e: 4300 .C ORRS r0,r0,r0 - 0x000011a0: 4924 $I LDR r1,[pc,#144] ; [0x1234] = 0x10008040 - 0x000011a2: 7c09 .| LDRB r1,[r1,#0x10] - 0x000011a4: 4308 .C ORRS r0,r0,r1 - 0x000011a6: 491e .I LDR r1,[pc,#120] ; [0x1220] = 0x10004fe0 - 0x000011a8: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x000011aa: 2100 .! MOVS r1,#0 - 0x000011ac: 4a21 !J LDR r2,[pc,#132] ; [0x1234] = 0x10008040 - 0x000011ae: 7c52 R| LDRB r2,[r2,#0x11] - 0x000011b0: 4309 .C ORRS r1,r1,r1 - 0x000011b2: 4a20 J LDR r2,[pc,#128] ; [0x1234] = 0x10008040 - 0x000011b4: 7c52 R| LDRB r2,[r2,#0x11] - 0x000011b6: 4311 .C ORRS r1,r1,r2 - 0x000011b8: 0209 .. LSLS r1,r1,#8 - 0x000011ba: 4308 .C ORRS r0,r0,r1 - 0x000011bc: 2140 @! MOVS r1,#0x40 - 0x000011be: 4388 .C BICS r0,r0,r1 - 0x000011c0: 1200 .. ASRS r0,r0,#8 - 0x000011c2: 491c .I LDR r1,[pc,#112] ; [0x1234] = 0x10008040 - 0x000011c4: 7448 Ht STRB r0,[r1,#0x11] - 0x000011c6: 4816 .H LDR r0,[pc,#88] ; [0x1220] = 0x10004fe0 - 0x000011c8: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x000011ca: 2000 . MOVS r0,#0 - 0x000011cc: 7c09 .| LDRB r1,[r1,#0x10] - 0x000011ce: 4300 .C ORRS r0,r0,r0 - 0x000011d0: 4918 .I LDR r1,[pc,#96] ; [0x1234] = 0x10008040 - 0x000011d2: 7c09 .| LDRB r1,[r1,#0x10] - 0x000011d4: 4308 .C ORRS r0,r0,r1 - 0x000011d6: 4912 .I LDR r1,[pc,#72] ; [0x1220] = 0x10004fe0 - 0x000011d8: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x000011da: 2100 .! MOVS r1,#0 - 0x000011dc: 4a15 .J LDR r2,[pc,#84] ; [0x1234] = 0x10008040 - 0x000011de: 7c52 R| LDRB r2,[r2,#0x11] - 0x000011e0: 4309 .C ORRS r1,r1,r1 - 0x000011e2: 4a14 .J LDR r2,[pc,#80] ; [0x1234] = 0x10008040 - 0x000011e4: 7c52 R| LDRB r2,[r2,#0x11] - 0x000011e6: 4311 .C ORRS r1,r1,r2 - 0x000011e8: 0209 .. LSLS r1,r1,#8 - 0x000011ea: 4308 .C ORRS r0,r0,r1 - 0x000011ec: 2140 @! MOVS r1,#0x40 - 0x000011ee: 4388 .C BICS r0,r0,r1 - 0x000011f0: 1200 .. ASRS r0,r0,#8 - 0x000011f2: 4910 .I LDR r1,[pc,#64] ; [0x1234] = 0x10008040 - 0x000011f4: 7448 Ht STRB r0,[r1,#0x11] - 0x000011f6: bf00 .. NOP - 0x000011f8: bf00 .. NOP - 0x000011fa: 2201 ." MOVS r2,#1 - 0x000011fc: 0351 Q. LSLS r1,r2,#13 - 0x000011fe: 2017 . MOVS r0,#0x17 - 0x00001200: 02c0 .. LSLS r0,r0,#11 - 0x00001202: f004fb71 ..q. BL Audio_AdcInit ; 0x58e8 - 0x00001206: e001 .. B 0x120c ; main + 230 - 0x00001208: f7ffff14 .... BL UART_Tx_Adc_Buffer ; 0x1034 - 0x0000120c: e7fc .. B 0x1208 ; main + 226 + 0x000010d6: 2000 . MOVS r0,#0 + 0x000010d8: f000feb9 .... BL SYS_TimerInit ; 0x1e4e + 0x000010dc: 2019 . MOVS r0,#0x19 + 0x000010de: f001fc6b ..k. BL IPC_TxControlCmd ; 0x29b8 + 0x000010e2: e024 $. B 0x112e ; main + 88 + 0x000010e4: 4815 .H LDR r0,[pc,#84] ; [0x113c] = 0x10004fe0 + 0x000010e6: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x000010e8: 2000 . MOVS r0,#0 + 0x000010ea: 4915 .I LDR r1,[pc,#84] ; [0x1140] = 0x10004340 + 0x000010ec: 3180 .1 ADDS r1,r1,#0x80 + 0x000010ee: 7f49 I. LDRB r1,[r1,#0x1d] + 0x000010f0: 4300 .C ORRS r0,r0,r0 + 0x000010f2: 4913 .I LDR r1,[pc,#76] ; [0x1140] = 0x10004340 + 0x000010f4: 3180 .1 ADDS r1,r1,#0x80 + 0x000010f6: 7f49 I. LDRB r1,[r1,#0x1d] + 0x000010f8: 4308 .C ORRS r0,r0,r1 + 0x000010fa: 2800 .( CMP r0,#0 + 0x000010fc: d004 .. BEQ 0x1108 ; main + 50 + 0x000010fe: 2801 .( CMP r0,#1 + 0x00001100: d008 .. BEQ 0x1114 ; main + 62 + 0x00001102: 2803 .( CMP r0,#3 + 0x00001104: d112 .. BNE 0x112c ; main + 86 + 0x00001106: e010 .. B 0x112a ; main + 84 + 0x00001108: f000ff4f ..O. BL SYS_timerPolling ; 0x1faa + 0x0000110c: 2040 @ MOVS r0,#0x40 + 0x0000110e: f001fdf8 .... BL Lpm_unLockLpm ; 0x2d02 + 0x00001112: e00b .. B 0x112c ; main + 86 + 0x00001114: b672 r. CPSID i + 0x00001116: f7ffff7d ..}. BL Bt_ActionBeforeHibernate ; 0x1014 + 0x0000111a: bf00 .. NOP + 0x0000111c: 2003 . MOVS r0,#3 + 0x0000111e: 4908 .I LDR r1,[pc,#32] ; [0x1140] = 0x10004340 + 0x00001120: 3180 .1 ADDS r1,r1,#0x80 + 0x00001122: 7748 Hw STRB r0,[r1,#0x1d] + 0x00001124: 7748 Hw STRB r0,[r1,#0x1d] + 0x00001126: bf00 .. NOP + 0x00001128: e000 .. B 0x112c ; main + 86 + 0x0000112a: bf00 .. NOP + 0x0000112c: bf00 .. NOP + 0x0000112e: e7d9 .. B 0x10e4 ; main + 14 _assert_handler - 0x0000120e: bf00 .. NOP - 0x00001210: e7fe .. B 0x1210 ; _assert_handler + 2 + 0x00001130: bf00 .. NOP + 0x00001132: e7fe .. B 0x1132 ; _assert_handler + 2 SysTick_Handler - 0x00001212: b510 .. PUSH {r4,lr} - 0x00001214: f000ff95 .... BL SYStick_handle ; 0x2142 - 0x00001218: bd10 .. POP {r4,pc} + 0x00001134: b510 .. PUSH {r4,lr} + 0x00001136: f000ff8a .... BL SYStick_handle ; 0x204e + 0x0000113a: bd10 .. POP {r4,pc} $d - 0x0000121a: 0000 .. DCW 0 - 0x0000121c: 10011000 .... DCD 268505088 - 0x00001220: 10004fe0 .O.. DCD 268455904 - 0x00001224: 10008300 .... DCD 268468992 - 0x00001228: 10010000 .... DCD 268500992 - 0x0000122c: 10004ac0 .J.. DCD 268454592 - 0x00001230: 00008034 4... DCD 32820 - 0x00001234: 10008040 @... DCD 268468288 + 0x0000113c: 10004fe0 .O.. DCD 268455904 + 0x00001140: 10004340 @C.. DCD 268452672 $t .text GPIO_SetOut - 0x00001238: b570 p. PUSH {r4-r6,lr} - 0x0000123a: 4604 .F MOV r4,r0 - 0x0000123c: 460d .F MOV r5,r1 - 0x0000123e: f000fd4d ..M. BL hw_delay ; 0x1cdc - 0x00001242: 2c28 (, CMP r4,#0x28 - 0x00001244: d100 .. BNE 0x1248 ; GPIO_SetOut + 16 - 0x00001246: bd70 p. POP {r4-r6,pc} - 0x00001248: 2080 . MOVS r0,#0x80 - 0x0000124a: 4020 @ ANDS r0,r0,r4 - 0x0000124c: 2800 .( CMP r0,#0 - 0x0000124e: d023 #. BEQ 0x1298 ; GPIO_SetOut + 96 - 0x00001250: 2d00 .- CMP r5,#0 - 0x00001252: d010 .. BEQ 0x1276 ; GPIO_SetOut + 62 - 0x00001254: bf00 .. NOP - 0x00001256: 203f ? MOVS r0,#0x3f - 0x00001258: 06e1 .. LSLS r1,r4,#27 - 0x0000125a: 0ec9 .. LSRS r1,r1,#27 - 0x0000125c: 4afb .J LDR r2,[pc,#1004] ; [0x164c] = 0x8080 - 0x0000125e: 1889 .. ADDS r1,r1,r2 - 0x00001260: 0552 R. LSLS r2,r2,#21 - 0x00001262: 1889 .. ADDS r1,r1,r2 - 0x00001264: 7008 .p STRB r0,[r1,#0] - 0x00001266: 06e1 .. LSLS r1,r4,#27 - 0x00001268: 0ec9 .. LSRS r1,r1,#27 - 0x0000126a: 4af8 .J LDR r2,[pc,#992] ; [0x164c] = 0x8080 - 0x0000126c: 1889 .. ADDS r1,r1,r2 - 0x0000126e: 0552 R. LSLS r2,r2,#21 - 0x00001270: 1889 .. ADDS r1,r1,r2 - 0x00001272: 7008 .p STRB r0,[r1,#0] - 0x00001274: e02c ,. B 0x12d0 ; GPIO_SetOut + 152 - 0x00001276: bf00 .. NOP - 0x00001278: 203e > MOVS r0,#0x3e - 0x0000127a: 06e1 .. LSLS r1,r4,#27 - 0x0000127c: 0ec9 .. LSRS r1,r1,#27 - 0x0000127e: 4af3 .J LDR r2,[pc,#972] ; [0x164c] = 0x8080 - 0x00001280: 1889 .. ADDS r1,r1,r2 - 0x00001282: 0552 R. LSLS r2,r2,#21 - 0x00001284: 1889 .. ADDS r1,r1,r2 - 0x00001286: 7008 .p STRB r0,[r1,#0] - 0x00001288: 06e1 .. LSLS r1,r4,#27 - 0x0000128a: 0ec9 .. LSRS r1,r1,#27 - 0x0000128c: 4aef .J LDR r2,[pc,#956] ; [0x164c] = 0x8080 - 0x0000128e: 1889 .. ADDS r1,r1,r2 - 0x00001290: 0552 R. LSLS r2,r2,#21 - 0x00001292: 1889 .. ADDS r1,r1,r2 - 0x00001294: 7008 .p STRB r0,[r1,#0] - 0x00001296: e01b .. B 0x12d0 ; GPIO_SetOut + 152 - 0x00001298: 2d00 .- CMP r5,#0 - 0x0000129a: d00c .. BEQ 0x12b6 ; GPIO_SetOut + 126 - 0x0000129c: bf00 .. NOP - 0x0000129e: 203e > MOVS r0,#0x3e - 0x000012a0: 49ea .I LDR r1,[pc,#936] ; [0x164c] = 0x8080 - 0x000012a2: 1861 a. ADDS r1,r4,r1 - 0x000012a4: 2201 ." MOVS r2,#1 - 0x000012a6: 0712 .. LSLS r2,r2,#28 - 0x000012a8: 1889 .. ADDS r1,r1,r2 - 0x000012aa: 7008 .p STRB r0,[r1,#0] - 0x000012ac: 49e7 .I LDR r1,[pc,#924] ; [0x164c] = 0x8080 - 0x000012ae: 1861 a. ADDS r1,r4,r1 - 0x000012b0: 1889 .. ADDS r1,r1,r2 - 0x000012b2: 7008 .p STRB r0,[r1,#0] - 0x000012b4: e00c .. B 0x12d0 ; GPIO_SetOut + 152 - 0x000012b6: bf00 .. NOP - 0x000012b8: 203f ? MOVS r0,#0x3f - 0x000012ba: 49e4 .I LDR r1,[pc,#912] ; [0x164c] = 0x8080 - 0x000012bc: 1861 a. ADDS r1,r4,r1 - 0x000012be: 2201 ." MOVS r2,#1 - 0x000012c0: 0712 .. LSLS r2,r2,#28 - 0x000012c2: 1889 .. ADDS r1,r1,r2 - 0x000012c4: 7008 .p STRB r0,[r1,#0] - 0x000012c6: 49e1 .I LDR r1,[pc,#900] ; [0x164c] = 0x8080 - 0x000012c8: 1861 a. ADDS r1,r4,r1 - 0x000012ca: 1889 .. ADDS r1,r1,r2 - 0x000012cc: 7008 .p STRB r0,[r1,#0] - 0x000012ce: bf00 .. NOP - 0x000012d0: f000fd04 .... BL hw_delay ; 0x1cdc - 0x000012d4: bf00 .. NOP - 0x000012d6: e7b6 .. B 0x1246 ; GPIO_SetOut + 14 + 0x00001144: b570 p. PUSH {r4-r6,lr} + 0x00001146: 4604 .F MOV r4,r0 + 0x00001148: 460d .F MOV r5,r1 + 0x0000114a: f000fd4d ..M. BL hw_delay ; 0x1be8 + 0x0000114e: 2c28 (, CMP r4,#0x28 + 0x00001150: d100 .. BNE 0x1154 ; GPIO_SetOut + 16 + 0x00001152: bd70 p. POP {r4-r6,pc} + 0x00001154: 2080 . MOVS r0,#0x80 + 0x00001156: 4020 @ ANDS r0,r0,r4 + 0x00001158: 2800 .( CMP r0,#0 + 0x0000115a: d023 #. BEQ 0x11a4 ; GPIO_SetOut + 96 + 0x0000115c: 2d00 .- CMP r5,#0 + 0x0000115e: d010 .. BEQ 0x1182 ; GPIO_SetOut + 62 + 0x00001160: bf00 .. NOP + 0x00001162: 203f ? MOVS r0,#0x3f + 0x00001164: 06e1 .. LSLS r1,r4,#27 + 0x00001166: 0ec9 .. LSRS r1,r1,#27 + 0x00001168: 4afb .J LDR r2,[pc,#1004] ; [0x1558] = 0x8080 + 0x0000116a: 1889 .. ADDS r1,r1,r2 + 0x0000116c: 0552 R. LSLS r2,r2,#21 + 0x0000116e: 1889 .. ADDS r1,r1,r2 + 0x00001170: 7008 .p STRB r0,[r1,#0] + 0x00001172: 06e1 .. LSLS r1,r4,#27 + 0x00001174: 0ec9 .. LSRS r1,r1,#27 + 0x00001176: 4af8 .J LDR r2,[pc,#992] ; [0x1558] = 0x8080 + 0x00001178: 1889 .. ADDS r1,r1,r2 + 0x0000117a: 0552 R. LSLS r2,r2,#21 + 0x0000117c: 1889 .. ADDS r1,r1,r2 + 0x0000117e: 7008 .p STRB r0,[r1,#0] + 0x00001180: e02c ,. B 0x11dc ; GPIO_SetOut + 152 + 0x00001182: bf00 .. NOP + 0x00001184: 203e > MOVS r0,#0x3e + 0x00001186: 06e1 .. LSLS r1,r4,#27 + 0x00001188: 0ec9 .. LSRS r1,r1,#27 + 0x0000118a: 4af3 .J LDR r2,[pc,#972] ; [0x1558] = 0x8080 + 0x0000118c: 1889 .. ADDS r1,r1,r2 + 0x0000118e: 0552 R. LSLS r2,r2,#21 + 0x00001190: 1889 .. ADDS r1,r1,r2 + 0x00001192: 7008 .p STRB r0,[r1,#0] + 0x00001194: 06e1 .. LSLS r1,r4,#27 + 0x00001196: 0ec9 .. LSRS r1,r1,#27 + 0x00001198: 4aef .J LDR r2,[pc,#956] ; [0x1558] = 0x8080 + 0x0000119a: 1889 .. ADDS r1,r1,r2 + 0x0000119c: 0552 R. LSLS r2,r2,#21 + 0x0000119e: 1889 .. ADDS r1,r1,r2 + 0x000011a0: 7008 .p STRB r0,[r1,#0] + 0x000011a2: e01b .. B 0x11dc ; GPIO_SetOut + 152 + 0x000011a4: 2d00 .- CMP r5,#0 + 0x000011a6: d00c .. BEQ 0x11c2 ; GPIO_SetOut + 126 + 0x000011a8: bf00 .. NOP + 0x000011aa: 203e > MOVS r0,#0x3e + 0x000011ac: 49ea .I LDR r1,[pc,#936] ; [0x1558] = 0x8080 + 0x000011ae: 1861 a. ADDS r1,r4,r1 + 0x000011b0: 2201 ." MOVS r2,#1 + 0x000011b2: 0712 .. LSLS r2,r2,#28 + 0x000011b4: 1889 .. ADDS r1,r1,r2 + 0x000011b6: 7008 .p STRB r0,[r1,#0] + 0x000011b8: 49e7 .I LDR r1,[pc,#924] ; [0x1558] = 0x8080 + 0x000011ba: 1861 a. ADDS r1,r4,r1 + 0x000011bc: 1889 .. ADDS r1,r1,r2 + 0x000011be: 7008 .p STRB r0,[r1,#0] + 0x000011c0: e00c .. B 0x11dc ; GPIO_SetOut + 152 + 0x000011c2: bf00 .. NOP + 0x000011c4: 203f ? MOVS r0,#0x3f + 0x000011c6: 49e4 .I LDR r1,[pc,#912] ; [0x1558] = 0x8080 + 0x000011c8: 1861 a. ADDS r1,r4,r1 + 0x000011ca: 2201 ." MOVS r2,#1 + 0x000011cc: 0712 .. LSLS r2,r2,#28 + 0x000011ce: 1889 .. ADDS r1,r1,r2 + 0x000011d0: 7008 .p STRB r0,[r1,#0] + 0x000011d2: 49e1 .I LDR r1,[pc,#900] ; [0x1558] = 0x8080 + 0x000011d4: 1861 a. ADDS r1,r4,r1 + 0x000011d6: 1889 .. ADDS r1,r1,r2 + 0x000011d8: 7008 .p STRB r0,[r1,#0] + 0x000011da: bf00 .. NOP + 0x000011dc: f000fd04 .... BL hw_delay ; 0x1be8 + 0x000011e0: bf00 .. NOP + 0x000011e2: e7b6 .. B 0x1152 ; GPIO_SetOut + 14 GPIO_SetInput - 0x000012d8: b510 .. PUSH {r4,lr} - 0x000012da: 4604 .F MOV r4,r0 - 0x000012dc: f000fcfe .... BL hw_delay ; 0x1cdc - 0x000012e0: 2c28 (, CMP r4,#0x28 - 0x000012e2: d100 .. BNE 0x12e6 ; GPIO_SetInput + 14 - 0x000012e4: bd10 .. POP {r4,pc} - 0x000012e6: 2080 . MOVS r0,#0x80 - 0x000012e8: 4020 @ ANDS r0,r0,r4 - 0x000012ea: 2800 .( CMP r0,#0 - 0x000012ec: d010 .. BEQ 0x1310 ; GPIO_SetInput + 56 - 0x000012ee: bf00 .. NOP - 0x000012f0: 2080 . MOVS r0,#0x80 - 0x000012f2: 06e1 .. LSLS r1,r4,#27 - 0x000012f4: 0ec9 .. LSRS r1,r1,#27 - 0x000012f6: 4ad5 .J LDR r2,[pc,#852] ; [0x164c] = 0x8080 - 0x000012f8: 1889 .. ADDS r1,r1,r2 - 0x000012fa: 0542 B. LSLS r2,r0,#21 - 0x000012fc: 1889 .. ADDS r1,r1,r2 - 0x000012fe: 7008 .p STRB r0,[r1,#0] - 0x00001300: 06e1 .. LSLS r1,r4,#27 - 0x00001302: 0ec9 .. LSRS r1,r1,#27 - 0x00001304: 4ad1 .J LDR r2,[pc,#836] ; [0x164c] = 0x8080 - 0x00001306: 1889 .. ADDS r1,r1,r2 - 0x00001308: 0542 B. LSLS r2,r0,#21 - 0x0000130a: 1889 .. ADDS r1,r1,r2 - 0x0000130c: 7008 .p STRB r0,[r1,#0] - 0x0000130e: e00b .. B 0x1328 ; GPIO_SetInput + 80 - 0x00001310: bf00 .. NOP - 0x00001312: 2040 @ MOVS r0,#0x40 - 0x00001314: 49cd .I LDR r1,[pc,#820] ; [0x164c] = 0x8080 - 0x00001316: 1861 a. ADDS r1,r4,r1 - 0x00001318: 0582 .. LSLS r2,r0,#22 - 0x0000131a: 1889 .. ADDS r1,r1,r2 - 0x0000131c: 7008 .p STRB r0,[r1,#0] - 0x0000131e: 49cb .I LDR r1,[pc,#812] ; [0x164c] = 0x8080 - 0x00001320: 1861 a. ADDS r1,r4,r1 - 0x00001322: 1889 .. ADDS r1,r1,r2 - 0x00001324: 7008 .p STRB r0,[r1,#0] - 0x00001326: bf00 .. NOP - 0x00001328: f000fcd8 .... BL hw_delay ; 0x1cdc - 0x0000132c: bf00 .. NOP - 0x0000132e: e7d9 .. B 0x12e4 ; GPIO_SetInput + 12 + 0x000011e4: b510 .. PUSH {r4,lr} + 0x000011e6: 4604 .F MOV r4,r0 + 0x000011e8: f000fcfe .... BL hw_delay ; 0x1be8 + 0x000011ec: 2c28 (, CMP r4,#0x28 + 0x000011ee: d100 .. BNE 0x11f2 ; GPIO_SetInput + 14 + 0x000011f0: bd10 .. POP {r4,pc} + 0x000011f2: 2080 . MOVS r0,#0x80 + 0x000011f4: 4020 @ ANDS r0,r0,r4 + 0x000011f6: 2800 .( CMP r0,#0 + 0x000011f8: d010 .. BEQ 0x121c ; GPIO_SetInput + 56 + 0x000011fa: bf00 .. NOP + 0x000011fc: 2080 . MOVS r0,#0x80 + 0x000011fe: 06e1 .. LSLS r1,r4,#27 + 0x00001200: 0ec9 .. LSRS r1,r1,#27 + 0x00001202: 4ad5 .J LDR r2,[pc,#852] ; [0x1558] = 0x8080 + 0x00001204: 1889 .. ADDS r1,r1,r2 + 0x00001206: 0542 B. LSLS r2,r0,#21 + 0x00001208: 1889 .. ADDS r1,r1,r2 + 0x0000120a: 7008 .p STRB r0,[r1,#0] + 0x0000120c: 06e1 .. LSLS r1,r4,#27 + 0x0000120e: 0ec9 .. LSRS r1,r1,#27 + 0x00001210: 4ad1 .J LDR r2,[pc,#836] ; [0x1558] = 0x8080 + 0x00001212: 1889 .. ADDS r1,r1,r2 + 0x00001214: 0542 B. LSLS r2,r0,#21 + 0x00001216: 1889 .. ADDS r1,r1,r2 + 0x00001218: 7008 .p STRB r0,[r1,#0] + 0x0000121a: e00b .. B 0x1234 ; GPIO_SetInput + 80 + 0x0000121c: bf00 .. NOP + 0x0000121e: 2040 @ MOVS r0,#0x40 + 0x00001220: 49cd .I LDR r1,[pc,#820] ; [0x1558] = 0x8080 + 0x00001222: 1861 a. ADDS r1,r4,r1 + 0x00001224: 0582 .. LSLS r2,r0,#22 + 0x00001226: 1889 .. ADDS r1,r1,r2 + 0x00001228: 7008 .p STRB r0,[r1,#0] + 0x0000122a: 49cb .I LDR r1,[pc,#812] ; [0x1558] = 0x8080 + 0x0000122c: 1861 a. ADDS r1,r4,r1 + 0x0000122e: 1889 .. ADDS r1,r1,r2 + 0x00001230: 7008 .p STRB r0,[r1,#0] + 0x00001232: bf00 .. NOP + 0x00001234: f000fcd8 .... BL hw_delay ; 0x1be8 + 0x00001238: bf00 .. NOP + 0x0000123a: e7d9 .. B 0x11f0 ; GPIO_SetInput + 12 GPIO_SetWakeup - 0x00001330: b530 0. PUSH {r4,r5,lr} - 0x00001332: 4602 .F MOV r2,r0 - 0x00001334: 2a28 (* CMP r2,#0x28 - 0x00001336: d100 .. BNE 0x133a ; GPIO_SetWakeup + 10 - 0x00001338: bd30 0. POP {r4,r5,pc} - 0x0000133a: 06d3 .. LSLS r3,r2,#27 - 0x0000133c: 0f98 .. LSRS r0,r3,#30 - 0x0000133e: 0751 Q. LSLS r1,r2,#29 - 0x00001340: 0f49 I. LSRS r1,r1,#29 - 0x00001342: 2380 .# MOVS r3,#0x80 - 0x00001344: 4013 .@ ANDS r3,r3,r2 - 0x00001346: 2b00 .+ CMP r3,#0 - 0x00001348: d057 W. BEQ 0x13fa ; GPIO_SetWakeup + 202 - 0x0000134a: bf00 .. NOP - 0x0000134c: 4bc0 .K LDR r3,[pc,#768] ; [0x1650] = 0x10004fe0 - 0x0000134e: 7fdb .. LDRB r3,[r3,#0x1f] - 0x00001350: 2300 .# MOVS r3,#0 - 0x00001352: 4604 .F MOV r4,r0 - 0x00001354: 34ab .4 ADDS r4,r4,#0xab - 0x00001356: 2501 .% MOVS r5,#1 - 0x00001358: 072d -. LSLS r5,r5,#28 - 0x0000135a: 1964 d. ADDS r4,r4,r5 - 0x0000135c: 7824 $x LDRB r4,[r4,#0] - 0x0000135e: 431b .C ORRS r3,r3,r3 - 0x00001360: 4604 .F MOV r4,r0 - 0x00001362: 34ab .4 ADDS r4,r4,#0xab - 0x00001364: 1964 d. ADDS r4,r4,r5 - 0x00001366: 7824 $x LDRB r4,[r4,#0] - 0x00001368: 4323 #C ORRS r3,r3,r4 - 0x0000136a: 2401 .$ MOVS r4,#1 - 0x0000136c: 408c .@ LSLS r4,r4,r1 - 0x0000136e: 43a3 .C BICS r3,r3,r4 + 0x0000123c: b530 0. PUSH {r4,r5,lr} + 0x0000123e: 4602 .F MOV r2,r0 + 0x00001240: 2a28 (* CMP r2,#0x28 + 0x00001242: d100 .. BNE 0x1246 ; GPIO_SetWakeup + 10 + 0x00001244: bd30 0. POP {r4,r5,pc} + 0x00001246: 06d3 .. LSLS r3,r2,#27 + 0x00001248: 0f98 .. LSRS r0,r3,#30 + 0x0000124a: 0751 Q. LSLS r1,r2,#29 + 0x0000124c: 0f49 I. LSRS r1,r1,#29 + 0x0000124e: 2380 .# MOVS r3,#0x80 + 0x00001250: 4013 .@ ANDS r3,r3,r2 + 0x00001252: 2b00 .+ CMP r3,#0 + 0x00001254: d057 W. BEQ 0x1306 ; GPIO_SetWakeup + 202 + 0x00001256: bf00 .. NOP + 0x00001258: 4bc0 .K LDR r3,[pc,#768] ; [0x155c] = 0x10004fe0 + 0x0000125a: 7fdb .. LDRB r3,[r3,#0x1f] + 0x0000125c: 2300 .# MOVS r3,#0 + 0x0000125e: 4604 .F MOV r4,r0 + 0x00001260: 34ab .4 ADDS r4,r4,#0xab + 0x00001262: 2501 .% MOVS r5,#1 + 0x00001264: 072d -. LSLS r5,r5,#28 + 0x00001266: 1964 d. ADDS r4,r4,r5 + 0x00001268: 7824 $x LDRB r4,[r4,#0] + 0x0000126a: 431b .C ORRS r3,r3,r3 + 0x0000126c: 4604 .F MOV r4,r0 + 0x0000126e: 34ab .4 ADDS r4,r4,#0xab + 0x00001270: 1964 d. ADDS r4,r4,r5 + 0x00001272: 7824 $x LDRB r4,[r4,#0] + 0x00001274: 4323 #C ORRS r3,r3,r4 + 0x00001276: 2401 .$ MOVS r4,#1 + 0x00001278: 408c .@ LSLS r4,r4,r1 + 0x0000127a: 43a3 .C BICS r3,r3,r4 + 0x0000127c: 4604 .F MOV r4,r0 + 0x0000127e: 34ab .4 ADDS r4,r4,#0xab + 0x00001280: 1964 d. ADDS r4,r4,r5 + 0x00001282: 7023 #p STRB r3,[r4,#0] + 0x00001284: 4bb5 .K LDR r3,[pc,#724] ; [0x155c] = 0x10004fe0 + 0x00001286: 7fdb .. LDRB r3,[r3,#0x1f] + 0x00001288: 2300 .# MOVS r3,#0 + 0x0000128a: 4604 .F MOV r4,r0 + 0x0000128c: 34ab .4 ADDS r4,r4,#0xab + 0x0000128e: 1964 d. ADDS r4,r4,r5 + 0x00001290: 7824 $x LDRB r4,[r4,#0] + 0x00001292: 431b .C ORRS r3,r3,r3 + 0x00001294: 4604 .F MOV r4,r0 + 0x00001296: 34ab .4 ADDS r4,r4,#0xab + 0x00001298: 1964 d. ADDS r4,r4,r5 + 0x0000129a: 7824 $x LDRB r4,[r4,#0] + 0x0000129c: 4323 #C ORRS r3,r3,r4 + 0x0000129e: 2401 .$ MOVS r4,#1 + 0x000012a0: 408c .@ LSLS r4,r4,r1 + 0x000012a2: 43a3 .C BICS r3,r3,r4 + 0x000012a4: 4604 .F MOV r4,r0 + 0x000012a6: 34ab .4 ADDS r4,r4,#0xab + 0x000012a8: 1964 d. ADDS r4,r4,r5 + 0x000012aa: 7023 #p STRB r3,[r4,#0] + 0x000012ac: bf00 .. NOP + 0x000012ae: bf00 .. NOP + 0x000012b0: 4baa .K LDR r3,[pc,#680] ; [0x155c] = 0x10004fe0 + 0x000012b2: 7fdb .. LDRB r3,[r3,#0x1f] + 0x000012b4: 2300 .# MOVS r3,#0 + 0x000012b6: 4604 .F MOV r4,r0 + 0x000012b8: 34b0 .4 ADDS r4,r4,#0xb0 + 0x000012ba: 1964 d. ADDS r4,r4,r5 + 0x000012bc: 7824 $x LDRB r4,[r4,#0] + 0x000012be: 431b .C ORRS r3,r3,r3 + 0x000012c0: 4604 .F MOV r4,r0 + 0x000012c2: 34b0 .4 ADDS r4,r4,#0xb0 + 0x000012c4: 1964 d. ADDS r4,r4,r5 + 0x000012c6: 7824 $x LDRB r4,[r4,#0] + 0x000012c8: 4323 #C ORRS r3,r3,r4 + 0x000012ca: 2401 .$ MOVS r4,#1 + 0x000012cc: 408c .@ LSLS r4,r4,r1 + 0x000012ce: 4323 #C ORRS r3,r3,r4 + 0x000012d0: b2dc .. UXTB r4,r3 + 0x000012d2: 4603 .F MOV r3,r0 + 0x000012d4: 33b0 .3 ADDS r3,r3,#0xb0 + 0x000012d6: 195b [. ADDS r3,r3,r5 + 0x000012d8: 701c .p STRB r4,[r3,#0] + 0x000012da: 4ba0 .K LDR r3,[pc,#640] ; [0x155c] = 0x10004fe0 + 0x000012dc: 7fdb .. LDRB r3,[r3,#0x1f] + 0x000012de: 2300 .# MOVS r3,#0 + 0x000012e0: 4604 .F MOV r4,r0 + 0x000012e2: 34b0 .4 ADDS r4,r4,#0xb0 + 0x000012e4: 1964 d. ADDS r4,r4,r5 + 0x000012e6: 7824 $x LDRB r4,[r4,#0] + 0x000012e8: 431b .C ORRS r3,r3,r3 + 0x000012ea: 4604 .F MOV r4,r0 + 0x000012ec: 34b0 .4 ADDS r4,r4,#0xb0 + 0x000012ee: 1964 d. ADDS r4,r4,r5 + 0x000012f0: 7824 $x LDRB r4,[r4,#0] + 0x000012f2: 4323 #C ORRS r3,r3,r4 + 0x000012f4: 2401 .$ MOVS r4,#1 + 0x000012f6: 408c .@ LSLS r4,r4,r1 + 0x000012f8: 4323 #C ORRS r3,r3,r4 + 0x000012fa: b2dc .. UXTB r4,r3 + 0x000012fc: 4603 .F MOV r3,r0 + 0x000012fe: 33b0 .3 ADDS r3,r3,#0xb0 + 0x00001300: 195b [. ADDS r3,r3,r5 + 0x00001302: 701c .p STRB r4,[r3,#0] + 0x00001304: e057 W. B 0x13b6 ; GPIO_SetWakeup + 378 + 0x00001306: bf00 .. NOP + 0x00001308: 4b94 .K LDR r3,[pc,#592] ; [0x155c] = 0x10004fe0 + 0x0000130a: 7fdb .. LDRB r3,[r3,#0x1f] + 0x0000130c: 2300 .# MOVS r3,#0 + 0x0000130e: 4604 .F MOV r4,r0 + 0x00001310: 34b0 .4 ADDS r4,r4,#0xb0 + 0x00001312: 2501 .% MOVS r5,#1 + 0x00001314: 072d -. LSLS r5,r5,#28 + 0x00001316: 1964 d. ADDS r4,r4,r5 + 0x00001318: 7824 $x LDRB r4,[r4,#0] + 0x0000131a: 431b .C ORRS r3,r3,r3 + 0x0000131c: 4604 .F MOV r4,r0 + 0x0000131e: 34b0 .4 ADDS r4,r4,#0xb0 + 0x00001320: 1964 d. ADDS r4,r4,r5 + 0x00001322: 7824 $x LDRB r4,[r4,#0] + 0x00001324: 4323 #C ORRS r3,r3,r4 + 0x00001326: 2401 .$ MOVS r4,#1 + 0x00001328: 408c .@ LSLS r4,r4,r1 + 0x0000132a: 43a3 .C BICS r3,r3,r4 + 0x0000132c: 4604 .F MOV r4,r0 + 0x0000132e: 34b0 .4 ADDS r4,r4,#0xb0 + 0x00001330: 1964 d. ADDS r4,r4,r5 + 0x00001332: 7023 #p STRB r3,[r4,#0] + 0x00001334: 4b89 .K LDR r3,[pc,#548] ; [0x155c] = 0x10004fe0 + 0x00001336: 7fdb .. LDRB r3,[r3,#0x1f] + 0x00001338: 2300 .# MOVS r3,#0 + 0x0000133a: 4604 .F MOV r4,r0 + 0x0000133c: 34b0 .4 ADDS r4,r4,#0xb0 + 0x0000133e: 1964 d. ADDS r4,r4,r5 + 0x00001340: 7824 $x LDRB r4,[r4,#0] + 0x00001342: 431b .C ORRS r3,r3,r3 + 0x00001344: 4604 .F MOV r4,r0 + 0x00001346: 34b0 .4 ADDS r4,r4,#0xb0 + 0x00001348: 1964 d. ADDS r4,r4,r5 + 0x0000134a: 7824 $x LDRB r4,[r4,#0] + 0x0000134c: 4323 #C ORRS r3,r3,r4 + 0x0000134e: 2401 .$ MOVS r4,#1 + 0x00001350: 408c .@ LSLS r4,r4,r1 + 0x00001352: 43a3 .C BICS r3,r3,r4 + 0x00001354: 4604 .F MOV r4,r0 + 0x00001356: 34b0 .4 ADDS r4,r4,#0xb0 + 0x00001358: 1964 d. ADDS r4,r4,r5 + 0x0000135a: 7023 #p STRB r3,[r4,#0] + 0x0000135c: bf00 .. NOP + 0x0000135e: bf00 .. NOP + 0x00001360: 4b7e ~K LDR r3,[pc,#504] ; [0x155c] = 0x10004fe0 + 0x00001362: 7fdb .. LDRB r3,[r3,#0x1f] + 0x00001364: 2300 .# MOVS r3,#0 + 0x00001366: 4604 .F MOV r4,r0 + 0x00001368: 34ab .4 ADDS r4,r4,#0xab + 0x0000136a: 1964 d. ADDS r4,r4,r5 + 0x0000136c: 7824 $x LDRB r4,[r4,#0] + 0x0000136e: 431b .C ORRS r3,r3,r3 0x00001370: 4604 .F MOV r4,r0 0x00001372: 34ab .4 ADDS r4,r4,#0xab 0x00001374: 1964 d. ADDS r4,r4,r5 - 0x00001376: 7023 #p STRB r3,[r4,#0] - 0x00001378: 4bb5 .K LDR r3,[pc,#724] ; [0x1650] = 0x10004fe0 - 0x0000137a: 7fdb .. LDRB r3,[r3,#0x1f] - 0x0000137c: 2300 .# MOVS r3,#0 - 0x0000137e: 4604 .F MOV r4,r0 - 0x00001380: 34ab .4 ADDS r4,r4,#0xab - 0x00001382: 1964 d. ADDS r4,r4,r5 - 0x00001384: 7824 $x LDRB r4,[r4,#0] - 0x00001386: 431b .C ORRS r3,r3,r3 - 0x00001388: 4604 .F MOV r4,r0 - 0x0000138a: 34ab .4 ADDS r4,r4,#0xab - 0x0000138c: 1964 d. ADDS r4,r4,r5 - 0x0000138e: 7824 $x LDRB r4,[r4,#0] - 0x00001390: 4323 #C ORRS r3,r3,r4 - 0x00001392: 2401 .$ MOVS r4,#1 - 0x00001394: 408c .@ LSLS r4,r4,r1 - 0x00001396: 43a3 .C BICS r3,r3,r4 - 0x00001398: 4604 .F MOV r4,r0 - 0x0000139a: 34ab .4 ADDS r4,r4,#0xab - 0x0000139c: 1964 d. ADDS r4,r4,r5 - 0x0000139e: 7023 #p STRB r3,[r4,#0] - 0x000013a0: bf00 .. NOP - 0x000013a2: bf00 .. NOP - 0x000013a4: 4baa .K LDR r3,[pc,#680] ; [0x1650] = 0x10004fe0 - 0x000013a6: 7fdb .. LDRB r3,[r3,#0x1f] - 0x000013a8: 2300 .# MOVS r3,#0 - 0x000013aa: 4604 .F MOV r4,r0 - 0x000013ac: 34b0 .4 ADDS r4,r4,#0xb0 - 0x000013ae: 1964 d. ADDS r4,r4,r5 - 0x000013b0: 7824 $x LDRB r4,[r4,#0] - 0x000013b2: 431b .C ORRS r3,r3,r3 - 0x000013b4: 4604 .F MOV r4,r0 - 0x000013b6: 34b0 .4 ADDS r4,r4,#0xb0 - 0x000013b8: 1964 d. ADDS r4,r4,r5 - 0x000013ba: 7824 $x LDRB r4,[r4,#0] - 0x000013bc: 4323 #C ORRS r3,r3,r4 - 0x000013be: 2401 .$ MOVS r4,#1 - 0x000013c0: 408c .@ LSLS r4,r4,r1 - 0x000013c2: 4323 #C ORRS r3,r3,r4 - 0x000013c4: b2dc .. UXTB r4,r3 - 0x000013c6: 4603 .F MOV r3,r0 - 0x000013c8: 33b0 .3 ADDS r3,r3,#0xb0 - 0x000013ca: 195b [. ADDS r3,r3,r5 - 0x000013cc: 701c .p STRB r4,[r3,#0] - 0x000013ce: 4ba0 .K LDR r3,[pc,#640] ; [0x1650] = 0x10004fe0 - 0x000013d0: 7fdb .. LDRB r3,[r3,#0x1f] - 0x000013d2: 2300 .# MOVS r3,#0 - 0x000013d4: 4604 .F MOV r4,r0 - 0x000013d6: 34b0 .4 ADDS r4,r4,#0xb0 - 0x000013d8: 1964 d. ADDS r4,r4,r5 - 0x000013da: 7824 $x LDRB r4,[r4,#0] - 0x000013dc: 431b .C ORRS r3,r3,r3 - 0x000013de: 4604 .F MOV r4,r0 - 0x000013e0: 34b0 .4 ADDS r4,r4,#0xb0 - 0x000013e2: 1964 d. ADDS r4,r4,r5 - 0x000013e4: 7824 $x LDRB r4,[r4,#0] - 0x000013e6: 4323 #C ORRS r3,r3,r4 - 0x000013e8: 2401 .$ MOVS r4,#1 - 0x000013ea: 408c .@ LSLS r4,r4,r1 - 0x000013ec: 4323 #C ORRS r3,r3,r4 - 0x000013ee: b2dc .. UXTB r4,r3 - 0x000013f0: 4603 .F MOV r3,r0 - 0x000013f2: 33b0 .3 ADDS r3,r3,#0xb0 - 0x000013f4: 195b [. ADDS r3,r3,r5 - 0x000013f6: 701c .p STRB r4,[r3,#0] - 0x000013f8: e057 W. B 0x14aa ; GPIO_SetWakeup + 378 - 0x000013fa: bf00 .. NOP - 0x000013fc: 4b94 .K LDR r3,[pc,#592] ; [0x1650] = 0x10004fe0 - 0x000013fe: 7fdb .. LDRB r3,[r3,#0x1f] - 0x00001400: 2300 .# MOVS r3,#0 - 0x00001402: 4604 .F MOV r4,r0 - 0x00001404: 34b0 .4 ADDS r4,r4,#0xb0 - 0x00001406: 2501 .% MOVS r5,#1 - 0x00001408: 072d -. LSLS r5,r5,#28 - 0x0000140a: 1964 d. ADDS r4,r4,r5 - 0x0000140c: 7824 $x LDRB r4,[r4,#0] - 0x0000140e: 431b .C ORRS r3,r3,r3 - 0x00001410: 4604 .F MOV r4,r0 - 0x00001412: 34b0 .4 ADDS r4,r4,#0xb0 - 0x00001414: 1964 d. ADDS r4,r4,r5 - 0x00001416: 7824 $x LDRB r4,[r4,#0] - 0x00001418: 4323 #C ORRS r3,r3,r4 - 0x0000141a: 2401 .$ MOVS r4,#1 - 0x0000141c: 408c .@ LSLS r4,r4,r1 - 0x0000141e: 43a3 .C BICS r3,r3,r4 - 0x00001420: 4604 .F MOV r4,r0 - 0x00001422: 34b0 .4 ADDS r4,r4,#0xb0 - 0x00001424: 1964 d. ADDS r4,r4,r5 - 0x00001426: 7023 #p STRB r3,[r4,#0] - 0x00001428: 4b89 .K LDR r3,[pc,#548] ; [0x1650] = 0x10004fe0 - 0x0000142a: 7fdb .. LDRB r3,[r3,#0x1f] - 0x0000142c: 2300 .# MOVS r3,#0 - 0x0000142e: 4604 .F MOV r4,r0 - 0x00001430: 34b0 .4 ADDS r4,r4,#0xb0 - 0x00001432: 1964 d. ADDS r4,r4,r5 - 0x00001434: 7824 $x LDRB r4,[r4,#0] - 0x00001436: 431b .C ORRS r3,r3,r3 - 0x00001438: 4604 .F MOV r4,r0 - 0x0000143a: 34b0 .4 ADDS r4,r4,#0xb0 - 0x0000143c: 1964 d. ADDS r4,r4,r5 - 0x0000143e: 7824 $x LDRB r4,[r4,#0] - 0x00001440: 4323 #C ORRS r3,r3,r4 - 0x00001442: 2401 .$ MOVS r4,#1 - 0x00001444: 408c .@ LSLS r4,r4,r1 - 0x00001446: 43a3 .C BICS r3,r3,r4 - 0x00001448: 4604 .F MOV r4,r0 - 0x0000144a: 34b0 .4 ADDS r4,r4,#0xb0 - 0x0000144c: 1964 d. ADDS r4,r4,r5 - 0x0000144e: 7023 #p STRB r3,[r4,#0] - 0x00001450: bf00 .. NOP - 0x00001452: bf00 .. NOP - 0x00001454: 4b7e ~K LDR r3,[pc,#504] ; [0x1650] = 0x10004fe0 - 0x00001456: 7fdb .. LDRB r3,[r3,#0x1f] - 0x00001458: 2300 .# MOVS r3,#0 - 0x0000145a: 4604 .F MOV r4,r0 - 0x0000145c: 34ab .4 ADDS r4,r4,#0xab - 0x0000145e: 1964 d. ADDS r4,r4,r5 - 0x00001460: 7824 $x LDRB r4,[r4,#0] - 0x00001462: 431b .C ORRS r3,r3,r3 - 0x00001464: 4604 .F MOV r4,r0 - 0x00001466: 34ab .4 ADDS r4,r4,#0xab - 0x00001468: 1964 d. ADDS r4,r4,r5 - 0x0000146a: 7824 $x LDRB r4,[r4,#0] - 0x0000146c: 4323 #C ORRS r3,r3,r4 - 0x0000146e: 2401 .$ MOVS r4,#1 - 0x00001470: 408c .@ LSLS r4,r4,r1 - 0x00001472: 4323 #C ORRS r3,r3,r4 - 0x00001474: b2dc .. UXTB r4,r3 - 0x00001476: 4603 .F MOV r3,r0 - 0x00001478: 33ab .3 ADDS r3,r3,#0xab - 0x0000147a: 195b [. ADDS r3,r3,r5 - 0x0000147c: 701c .p STRB r4,[r3,#0] - 0x0000147e: 4b74 tK LDR r3,[pc,#464] ; [0x1650] = 0x10004fe0 - 0x00001480: 7fdb .. LDRB r3,[r3,#0x1f] - 0x00001482: 2300 .# MOVS r3,#0 - 0x00001484: 4604 .F MOV r4,r0 - 0x00001486: 34ab .4 ADDS r4,r4,#0xab - 0x00001488: 1964 d. ADDS r4,r4,r5 - 0x0000148a: 7824 $x LDRB r4,[r4,#0] - 0x0000148c: 431b .C ORRS r3,r3,r3 - 0x0000148e: 4604 .F MOV r4,r0 - 0x00001490: 34ab .4 ADDS r4,r4,#0xab - 0x00001492: 1964 d. ADDS r4,r4,r5 - 0x00001494: 7824 $x LDRB r4,[r4,#0] - 0x00001496: 4323 #C ORRS r3,r3,r4 - 0x00001498: 2401 .$ MOVS r4,#1 - 0x0000149a: 408c .@ LSLS r4,r4,r1 - 0x0000149c: 4323 #C ORRS r3,r3,r4 - 0x0000149e: b2dc .. UXTB r4,r3 - 0x000014a0: 4603 .F MOV r3,r0 - 0x000014a2: 33ab .3 ADDS r3,r3,#0xab - 0x000014a4: 195b [. ADDS r3,r3,r5 - 0x000014a6: 701c .p STRB r4,[r3,#0] - 0x000014a8: bf00 .. NOP - 0x000014aa: bf00 .. NOP - 0x000014ac: e744 D. B 0x1338 ; GPIO_SetWakeup + 8 + 0x00001376: 7824 $x LDRB r4,[r4,#0] + 0x00001378: 4323 #C ORRS r3,r3,r4 + 0x0000137a: 2401 .$ MOVS r4,#1 + 0x0000137c: 408c .@ LSLS r4,r4,r1 + 0x0000137e: 4323 #C ORRS r3,r3,r4 + 0x00001380: b2dc .. UXTB r4,r3 + 0x00001382: 4603 .F MOV r3,r0 + 0x00001384: 33ab .3 ADDS r3,r3,#0xab + 0x00001386: 195b [. ADDS r3,r3,r5 + 0x00001388: 701c .p STRB r4,[r3,#0] + 0x0000138a: 4b74 tK LDR r3,[pc,#464] ; [0x155c] = 0x10004fe0 + 0x0000138c: 7fdb .. LDRB r3,[r3,#0x1f] + 0x0000138e: 2300 .# MOVS r3,#0 + 0x00001390: 4604 .F MOV r4,r0 + 0x00001392: 34ab .4 ADDS r4,r4,#0xab + 0x00001394: 1964 d. ADDS r4,r4,r5 + 0x00001396: 7824 $x LDRB r4,[r4,#0] + 0x00001398: 431b .C ORRS r3,r3,r3 + 0x0000139a: 4604 .F MOV r4,r0 + 0x0000139c: 34ab .4 ADDS r4,r4,#0xab + 0x0000139e: 1964 d. ADDS r4,r4,r5 + 0x000013a0: 7824 $x LDRB r4,[r4,#0] + 0x000013a2: 4323 #C ORRS r3,r3,r4 + 0x000013a4: 2401 .$ MOVS r4,#1 + 0x000013a6: 408c .@ LSLS r4,r4,r1 + 0x000013a8: 4323 #C ORRS r3,r3,r4 + 0x000013aa: b2dc .. UXTB r4,r3 + 0x000013ac: 4603 .F MOV r3,r0 + 0x000013ae: 33ab .3 ADDS r3,r3,#0xab + 0x000013b0: 195b [. ADDS r3,r3,r5 + 0x000013b2: 701c .p STRB r4,[r3,#0] + 0x000013b4: bf00 .. NOP + 0x000013b6: bf00 .. NOP + 0x000013b8: e744 D. B 0x1244 ; GPIO_SetWakeup + 8 gpioGetBit - 0x000014ae: b5f0 .. PUSH {r4-r7,lr} - 0x000014b0: 4602 .F MOV r2,r0 - 0x000014b2: 2400 .$ MOVS r4,#0 - 0x000014b4: 2300 .# MOVS r3,#0 - 0x000014b6: 2500 .% MOVS r5,#0 - 0x000014b8: 0754 T. LSLS r4,r2,#29 - 0x000014ba: 0f64 d. LSRS r4,r4,#29 - 0x000014bc: 06d0 .. LSLS r0,r2,#27 - 0x000014be: 0f83 .. LSRS r3,r0,#30 - 0x000014c0: 4863 cH LDR r0,[pc,#396] ; [0x1650] = 0x10004fe0 - 0x000014c2: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x000014c4: 2000 . MOVS r0,#0 - 0x000014c6: 18ce .. ADDS r6,r1,r3 - 0x000014c8: 2701 .' MOVS r7,#1 - 0x000014ca: 073f ?. LSLS r7,r7,#28 - 0x000014cc: 433e >C ORRS r6,r6,r7 - 0x000014ce: 7836 6x LDRB r6,[r6,#0] - 0x000014d0: 4300 .C ORRS r0,r0,r0 - 0x000014d2: 18ce .. ADDS r6,r1,r3 - 0x000014d4: 433e >C ORRS r6,r6,r7 - 0x000014d6: 7836 6x LDRB r6,[r6,#0] - 0x000014d8: 4330 0C ORRS r0,r0,r6 - 0x000014da: 4605 .F MOV r5,r0 - 0x000014dc: 2001 . MOVS r0,#1 - 0x000014de: 40a0 .@ LSLS r0,r0,r4 - 0x000014e0: 4028 (@ ANDS r0,r0,r5 - 0x000014e2: bdf0 .. POP {r4-r7,pc} + 0x000013ba: b5f0 .. PUSH {r4-r7,lr} + 0x000013bc: 4602 .F MOV r2,r0 + 0x000013be: 2400 .$ MOVS r4,#0 + 0x000013c0: 2300 .# MOVS r3,#0 + 0x000013c2: 2500 .% MOVS r5,#0 + 0x000013c4: 0754 T. LSLS r4,r2,#29 + 0x000013c6: 0f64 d. LSRS r4,r4,#29 + 0x000013c8: 06d0 .. LSLS r0,r2,#27 + 0x000013ca: 0f83 .. LSRS r3,r0,#30 + 0x000013cc: 4863 cH LDR r0,[pc,#396] ; [0x155c] = 0x10004fe0 + 0x000013ce: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x000013d0: 2000 . MOVS r0,#0 + 0x000013d2: 18ce .. ADDS r6,r1,r3 + 0x000013d4: 2701 .' MOVS r7,#1 + 0x000013d6: 073f ?. LSLS r7,r7,#28 + 0x000013d8: 433e >C ORRS r6,r6,r7 + 0x000013da: 7836 6x LDRB r6,[r6,#0] + 0x000013dc: 4300 .C ORRS r0,r0,r0 + 0x000013de: 18ce .. ADDS r6,r1,r3 + 0x000013e0: 433e >C ORRS r6,r6,r7 + 0x000013e2: 7836 6x LDRB r6,[r6,#0] + 0x000013e4: 4330 0C ORRS r0,r0,r6 + 0x000013e6: 4605 .F MOV r5,r0 + 0x000013e8: 2001 . MOVS r0,#1 + 0x000013ea: 40a0 .@ LSLS r0,r0,r4 + 0x000013ec: 4028 (@ ANDS r0,r0,r5 + 0x000013ee: bdf0 .. POP {r4-r7,pc} GPIO_GetInputStatus - 0x000014e4: b510 .. PUSH {r4,lr} - 0x000014e6: 4604 .F MOV r4,r0 - 0x000014e8: 2c28 (, CMP r4,#0x28 - 0x000014ea: d101 .. BNE 0x14f0 ; GPIO_GetInputStatus + 12 - 0x000014ec: bf00 .. NOP - 0x000014ee: e7fe .. B 0x14ee ; GPIO_GetInputStatus + 10 - 0x000014f0: 2080 . MOVS r0,#0x80 - 0x000014f2: 4020 @ ANDS r0,r0,r4 - 0x000014f4: 2800 .( CMP r0,#0 - 0x000014f6: d005 .. BEQ 0x1504 ; GPIO_GetInputStatus + 32 - 0x000014f8: 06e0 .. LSLS r0,r4,#27 - 0x000014fa: 0ec0 .. LSRS r0,r0,#27 - 0x000014fc: 4955 UI LDR r1,[pc,#340] ; [0x1654] = 0x831c - 0x000014fe: f7ffffd6 .... BL gpioGetBit ; 0x14ae - 0x00001502: bd10 .. POP {r4,pc} - 0x00001504: 06e0 .. LSLS r0,r4,#27 - 0x00001506: 0ec0 .. LSRS r0,r0,#27 - 0x00001508: 4952 RI LDR r1,[pc,#328] ; [0x1654] = 0x831c - 0x0000150a: f7ffffd0 .... BL gpioGetBit ; 0x14ae - 0x0000150e: 2800 .( CMP r0,#0 - 0x00001510: d101 .. BNE 0x1516 ; GPIO_GetInputStatus + 50 - 0x00001512: 2001 . MOVS r0,#1 - 0x00001514: e7f5 .. B 0x1502 ; GPIO_GetInputStatus + 30 - 0x00001516: 2000 . MOVS r0,#0 - 0x00001518: e7f3 .. B 0x1502 ; GPIO_GetInputStatus + 30 + 0x000013f0: b510 .. PUSH {r4,lr} + 0x000013f2: 4604 .F MOV r4,r0 + 0x000013f4: 2c28 (, CMP r4,#0x28 + 0x000013f6: d101 .. BNE 0x13fc ; GPIO_GetInputStatus + 12 + 0x000013f8: bf00 .. NOP + 0x000013fa: e7fe .. B 0x13fa ; GPIO_GetInputStatus + 10 + 0x000013fc: 2080 . MOVS r0,#0x80 + 0x000013fe: 4020 @ ANDS r0,r0,r4 + 0x00001400: 2800 .( CMP r0,#0 + 0x00001402: d005 .. BEQ 0x1410 ; GPIO_GetInputStatus + 32 + 0x00001404: 06e0 .. LSLS r0,r4,#27 + 0x00001406: 0ec0 .. LSRS r0,r0,#27 + 0x00001408: 4955 UI LDR r1,[pc,#340] ; [0x1560] = 0x831c + 0x0000140a: f7ffffd6 .... BL gpioGetBit ; 0x13ba + 0x0000140e: bd10 .. POP {r4,pc} + 0x00001410: 06e0 .. LSLS r0,r4,#27 + 0x00001412: 0ec0 .. LSRS r0,r0,#27 + 0x00001414: 4952 RI LDR r1,[pc,#328] ; [0x1560] = 0x831c + 0x00001416: f7ffffd0 .... BL gpioGetBit ; 0x13ba + 0x0000141a: 2800 .( CMP r0,#0 + 0x0000141c: d101 .. BNE 0x1422 ; GPIO_GetInputStatus + 50 + 0x0000141e: 2001 . MOVS r0,#1 + 0x00001420: e7f5 .. B 0x140e ; GPIO_GetInputStatus + 30 + 0x00001422: 2000 . MOVS r0,#0 + 0x00001424: e7f3 .. B 0x140e ; GPIO_GetInputStatus + 30 GPIO_SetWakeupByCurrentState - 0x0000151a: b530 0. PUSH {r4,r5,lr} - 0x0000151c: 4604 .F MOV r4,r0 - 0x0000151e: 2180 .! MOVS r1,#0x80 - 0x00001520: 4321 !C ORRS r1,r1,r4 - 0x00001522: 4608 .F MOV r0,r1 - 0x00001524: f7ffffde .... BL GPIO_GetInputStatus ; 0x14e4 - 0x00001528: 4605 .F MOV r5,r0 - 0x0000152a: 2d00 .- CMP r5,#0 - 0x0000152c: d004 .. BEQ 0x1538 ; GPIO_SetWakeupByCurrentState + 30 - 0x0000152e: 06e0 .. LSLS r0,r4,#27 - 0x00001530: 0ec0 .. LSRS r0,r0,#27 - 0x00001532: f7fffefd .... BL GPIO_SetWakeup ; 0x1330 - 0x00001536: e004 .. B 0x1542 ; GPIO_SetWakeupByCurrentState + 40 - 0x00001538: 2180 .! MOVS r1,#0x80 - 0x0000153a: 4321 !C ORRS r1,r1,r4 - 0x0000153c: 4608 .F MOV r0,r1 - 0x0000153e: f7fffef7 .... BL GPIO_SetWakeup ; 0x1330 - 0x00001542: bd30 0. POP {r4,r5,pc} + 0x00001426: b530 0. PUSH {r4,r5,lr} + 0x00001428: 4604 .F MOV r4,r0 + 0x0000142a: 2180 .! MOVS r1,#0x80 + 0x0000142c: 4321 !C ORRS r1,r1,r4 + 0x0000142e: 4608 .F MOV r0,r1 + 0x00001430: f7ffffde .... BL GPIO_GetInputStatus ; 0x13f0 + 0x00001434: 4605 .F MOV r5,r0 + 0x00001436: 2d00 .- CMP r5,#0 + 0x00001438: d004 .. BEQ 0x1444 ; GPIO_SetWakeupByCurrentState + 30 + 0x0000143a: 06e0 .. LSLS r0,r4,#27 + 0x0000143c: 0ec0 .. LSRS r0,r0,#27 + 0x0000143e: f7fffefd .... BL GPIO_SetWakeup ; 0x123c + 0x00001442: e004 .. B 0x144e ; GPIO_SetWakeupByCurrentState + 40 + 0x00001444: 2180 .! MOVS r1,#0x80 + 0x00001446: 4321 !C ORRS r1,r1,r4 + 0x00001448: 4608 .F MOV r0,r1 + 0x0000144a: f7fffef7 .... BL GPIO_SetWakeup ; 0x123c + 0x0000144e: bd30 0. POP {r4,r5,pc} GPIO_ClearWakeup - 0x00001544: b530 0. PUSH {r4,r5,lr} - 0x00001546: 4602 .F MOV r2,r0 - 0x00001548: 2a28 (* CMP r2,#0x28 - 0x0000154a: d100 .. BNE 0x154e ; GPIO_ClearWakeup + 10 - 0x0000154c: bd30 0. POP {r4,r5,pc} - 0x0000154e: 06d3 .. LSLS r3,r2,#27 - 0x00001550: 0f98 .. LSRS r0,r3,#30 - 0x00001552: 0751 Q. LSLS r1,r2,#29 - 0x00001554: 0f49 I. LSRS r1,r1,#29 - 0x00001556: bf00 .. NOP - 0x00001558: 4b3d =K LDR r3,[pc,#244] ; [0x1650] = 0x10004fe0 - 0x0000155a: 7fdb .. LDRB r3,[r3,#0x1f] - 0x0000155c: 2300 .# MOVS r3,#0 - 0x0000155e: 4604 .F MOV r4,r0 - 0x00001560: 34ab .4 ADDS r4,r4,#0xab - 0x00001562: 2501 .% MOVS r5,#1 - 0x00001564: 072d -. LSLS r5,r5,#28 - 0x00001566: 1964 d. ADDS r4,r4,r5 - 0x00001568: 7824 $x LDRB r4,[r4,#0] - 0x0000156a: 431b .C ORRS r3,r3,r3 - 0x0000156c: 4604 .F MOV r4,r0 - 0x0000156e: 34ab .4 ADDS r4,r4,#0xab - 0x00001570: 1964 d. ADDS r4,r4,r5 - 0x00001572: 7824 $x LDRB r4,[r4,#0] - 0x00001574: 4323 #C ORRS r3,r3,r4 - 0x00001576: 2401 .$ MOVS r4,#1 - 0x00001578: 408c .@ LSLS r4,r4,r1 - 0x0000157a: 43a3 .C BICS r3,r3,r4 - 0x0000157c: 4604 .F MOV r4,r0 - 0x0000157e: 34ab .4 ADDS r4,r4,#0xab - 0x00001580: 1964 d. ADDS r4,r4,r5 - 0x00001582: 7023 #p STRB r3,[r4,#0] - 0x00001584: 4b32 2K LDR r3,[pc,#200] ; [0x1650] = 0x10004fe0 - 0x00001586: 7fdb .. LDRB r3,[r3,#0x1f] - 0x00001588: 2300 .# MOVS r3,#0 - 0x0000158a: 4604 .F MOV r4,r0 - 0x0000158c: 34ab .4 ADDS r4,r4,#0xab - 0x0000158e: 1964 d. ADDS r4,r4,r5 - 0x00001590: 7824 $x LDRB r4,[r4,#0] - 0x00001592: 431b .C ORRS r3,r3,r3 - 0x00001594: 4604 .F MOV r4,r0 - 0x00001596: 34ab .4 ADDS r4,r4,#0xab - 0x00001598: 1964 d. ADDS r4,r4,r5 - 0x0000159a: 7824 $x LDRB r4,[r4,#0] - 0x0000159c: 4323 #C ORRS r3,r3,r4 - 0x0000159e: 2401 .$ MOVS r4,#1 - 0x000015a0: 408c .@ LSLS r4,r4,r1 - 0x000015a2: 43a3 .C BICS r3,r3,r4 - 0x000015a4: 4604 .F MOV r4,r0 - 0x000015a6: 34ab .4 ADDS r4,r4,#0xab - 0x000015a8: 1964 d. ADDS r4,r4,r5 - 0x000015aa: 7023 #p STRB r3,[r4,#0] - 0x000015ac: bf00 .. NOP - 0x000015ae: bf00 .. NOP - 0x000015b0: 4b27 'K LDR r3,[pc,#156] ; [0x1650] = 0x10004fe0 - 0x000015b2: 7fdb .. LDRB r3,[r3,#0x1f] - 0x000015b4: 2300 .# MOVS r3,#0 - 0x000015b6: 4604 .F MOV r4,r0 - 0x000015b8: 34b0 .4 ADDS r4,r4,#0xb0 - 0x000015ba: 1964 d. ADDS r4,r4,r5 - 0x000015bc: 7824 $x LDRB r4,[r4,#0] - 0x000015be: 431b .C ORRS r3,r3,r3 - 0x000015c0: 4604 .F MOV r4,r0 - 0x000015c2: 34b0 .4 ADDS r4,r4,#0xb0 - 0x000015c4: 1964 d. ADDS r4,r4,r5 - 0x000015c6: 7824 $x LDRB r4,[r4,#0] - 0x000015c8: 4323 #C ORRS r3,r3,r4 - 0x000015ca: 2401 .$ MOVS r4,#1 - 0x000015cc: 408c .@ LSLS r4,r4,r1 - 0x000015ce: 43a3 .C BICS r3,r3,r4 - 0x000015d0: 4604 .F MOV r4,r0 - 0x000015d2: 34b0 .4 ADDS r4,r4,#0xb0 - 0x000015d4: 1964 d. ADDS r4,r4,r5 - 0x000015d6: 7023 #p STRB r3,[r4,#0] - 0x000015d8: 4b1d .K LDR r3,[pc,#116] ; [0x1650] = 0x10004fe0 - 0x000015da: 7fdb .. LDRB r3,[r3,#0x1f] - 0x000015dc: 2300 .# MOVS r3,#0 - 0x000015de: 4604 .F MOV r4,r0 - 0x000015e0: 34b0 .4 ADDS r4,r4,#0xb0 - 0x000015e2: 1964 d. ADDS r4,r4,r5 - 0x000015e4: 7824 $x LDRB r4,[r4,#0] - 0x000015e6: 431b .C ORRS r3,r3,r3 - 0x000015e8: 4604 .F MOV r4,r0 - 0x000015ea: 34b0 .4 ADDS r4,r4,#0xb0 - 0x000015ec: 1964 d. ADDS r4,r4,r5 - 0x000015ee: 7824 $x LDRB r4,[r4,#0] - 0x000015f0: 4323 #C ORRS r3,r3,r4 - 0x000015f2: 2401 .$ MOVS r4,#1 - 0x000015f4: 408c .@ LSLS r4,r4,r1 - 0x000015f6: 43a3 .C BICS r3,r3,r4 - 0x000015f8: 4604 .F MOV r4,r0 - 0x000015fa: 34b0 .4 ADDS r4,r4,#0xb0 - 0x000015fc: 1964 d. ADDS r4,r4,r5 - 0x000015fe: 7023 #p STRB r3,[r4,#0] - 0x00001600: bf00 .. NOP - 0x00001602: bf00 .. NOP - 0x00001604: e7a2 .. B 0x154c ; GPIO_ClearWakeup + 8 + 0x00001450: b530 0. PUSH {r4,r5,lr} + 0x00001452: 4602 .F MOV r2,r0 + 0x00001454: 2a28 (* CMP r2,#0x28 + 0x00001456: d100 .. BNE 0x145a ; GPIO_ClearWakeup + 10 + 0x00001458: bd30 0. POP {r4,r5,pc} + 0x0000145a: 06d3 .. LSLS r3,r2,#27 + 0x0000145c: 0f98 .. LSRS r0,r3,#30 + 0x0000145e: 0751 Q. LSLS r1,r2,#29 + 0x00001460: 0f49 I. LSRS r1,r1,#29 + 0x00001462: bf00 .. NOP + 0x00001464: 4b3d =K LDR r3,[pc,#244] ; [0x155c] = 0x10004fe0 + 0x00001466: 7fdb .. LDRB r3,[r3,#0x1f] + 0x00001468: 2300 .# MOVS r3,#0 + 0x0000146a: 4604 .F MOV r4,r0 + 0x0000146c: 34ab .4 ADDS r4,r4,#0xab + 0x0000146e: 2501 .% MOVS r5,#1 + 0x00001470: 072d -. LSLS r5,r5,#28 + 0x00001472: 1964 d. ADDS r4,r4,r5 + 0x00001474: 7824 $x LDRB r4,[r4,#0] + 0x00001476: 431b .C ORRS r3,r3,r3 + 0x00001478: 4604 .F MOV r4,r0 + 0x0000147a: 34ab .4 ADDS r4,r4,#0xab + 0x0000147c: 1964 d. ADDS r4,r4,r5 + 0x0000147e: 7824 $x LDRB r4,[r4,#0] + 0x00001480: 4323 #C ORRS r3,r3,r4 + 0x00001482: 2401 .$ MOVS r4,#1 + 0x00001484: 408c .@ LSLS r4,r4,r1 + 0x00001486: 43a3 .C BICS r3,r3,r4 + 0x00001488: 4604 .F MOV r4,r0 + 0x0000148a: 34ab .4 ADDS r4,r4,#0xab + 0x0000148c: 1964 d. ADDS r4,r4,r5 + 0x0000148e: 7023 #p STRB r3,[r4,#0] + 0x00001490: 4b32 2K LDR r3,[pc,#200] ; [0x155c] = 0x10004fe0 + 0x00001492: 7fdb .. LDRB r3,[r3,#0x1f] + 0x00001494: 2300 .# MOVS r3,#0 + 0x00001496: 4604 .F MOV r4,r0 + 0x00001498: 34ab .4 ADDS r4,r4,#0xab + 0x0000149a: 1964 d. ADDS r4,r4,r5 + 0x0000149c: 7824 $x LDRB r4,[r4,#0] + 0x0000149e: 431b .C ORRS r3,r3,r3 + 0x000014a0: 4604 .F MOV r4,r0 + 0x000014a2: 34ab .4 ADDS r4,r4,#0xab + 0x000014a4: 1964 d. ADDS r4,r4,r5 + 0x000014a6: 7824 $x LDRB r4,[r4,#0] + 0x000014a8: 4323 #C ORRS r3,r3,r4 + 0x000014aa: 2401 .$ MOVS r4,#1 + 0x000014ac: 408c .@ LSLS r4,r4,r1 + 0x000014ae: 43a3 .C BICS r3,r3,r4 + 0x000014b0: 4604 .F MOV r4,r0 + 0x000014b2: 34ab .4 ADDS r4,r4,#0xab + 0x000014b4: 1964 d. ADDS r4,r4,r5 + 0x000014b6: 7023 #p STRB r3,[r4,#0] + 0x000014b8: bf00 .. NOP + 0x000014ba: bf00 .. NOP + 0x000014bc: 4b27 'K LDR r3,[pc,#156] ; [0x155c] = 0x10004fe0 + 0x000014be: 7fdb .. LDRB r3,[r3,#0x1f] + 0x000014c0: 2300 .# MOVS r3,#0 + 0x000014c2: 4604 .F MOV r4,r0 + 0x000014c4: 34b0 .4 ADDS r4,r4,#0xb0 + 0x000014c6: 1964 d. ADDS r4,r4,r5 + 0x000014c8: 7824 $x LDRB r4,[r4,#0] + 0x000014ca: 431b .C ORRS r3,r3,r3 + 0x000014cc: 4604 .F MOV r4,r0 + 0x000014ce: 34b0 .4 ADDS r4,r4,#0xb0 + 0x000014d0: 1964 d. ADDS r4,r4,r5 + 0x000014d2: 7824 $x LDRB r4,[r4,#0] + 0x000014d4: 4323 #C ORRS r3,r3,r4 + 0x000014d6: 2401 .$ MOVS r4,#1 + 0x000014d8: 408c .@ LSLS r4,r4,r1 + 0x000014da: 43a3 .C BICS r3,r3,r4 + 0x000014dc: 4604 .F MOV r4,r0 + 0x000014de: 34b0 .4 ADDS r4,r4,#0xb0 + 0x000014e0: 1964 d. ADDS r4,r4,r5 + 0x000014e2: 7023 #p STRB r3,[r4,#0] + 0x000014e4: 4b1d .K LDR r3,[pc,#116] ; [0x155c] = 0x10004fe0 + 0x000014e6: 7fdb .. LDRB r3,[r3,#0x1f] + 0x000014e8: 2300 .# MOVS r3,#0 + 0x000014ea: 4604 .F MOV r4,r0 + 0x000014ec: 34b0 .4 ADDS r4,r4,#0xb0 + 0x000014ee: 1964 d. ADDS r4,r4,r5 + 0x000014f0: 7824 $x LDRB r4,[r4,#0] + 0x000014f2: 431b .C ORRS r3,r3,r3 + 0x000014f4: 4604 .F MOV r4,r0 + 0x000014f6: 34b0 .4 ADDS r4,r4,#0xb0 + 0x000014f8: 1964 d. ADDS r4,r4,r5 + 0x000014fa: 7824 $x LDRB r4,[r4,#0] + 0x000014fc: 4323 #C ORRS r3,r3,r4 + 0x000014fe: 2401 .$ MOVS r4,#1 + 0x00001500: 408c .@ LSLS r4,r4,r1 + 0x00001502: 43a3 .C BICS r3,r3,r4 + 0x00001504: 4604 .F MOV r4,r0 + 0x00001506: 34b0 .4 ADDS r4,r4,#0xb0 + 0x00001508: 1964 d. ADDS r4,r4,r5 + 0x0000150a: 7023 #p STRB r3,[r4,#0] + 0x0000150c: bf00 .. NOP + 0x0000150e: bf00 .. NOP + 0x00001510: e7a2 .. B 0x1458 ; GPIO_ClearWakeup + 8 GPIO_SetGpioMultFunction - 0x00001606: bf00 .. NOP - 0x00001608: 0682 .. LSLS r2,r0,#26 - 0x0000160a: 0e92 .. LSRS r2,r2,#26 - 0x0000160c: 4b0f .K LDR r3,[pc,#60] ; [0x164c] = 0x8080 - 0x0000160e: 18d2 .. ADDS r2,r2,r3 - 0x00001610: 055b [. LSLS r3,r3,#21 - 0x00001612: 18d2 .. ADDS r2,r2,r3 - 0x00001614: 7011 .p STRB r1,[r2,#0] - 0x00001616: 0682 .. LSLS r2,r0,#26 - 0x00001618: 0e92 .. LSRS r2,r2,#26 - 0x0000161a: 4b0c .K LDR r3,[pc,#48] ; [0x164c] = 0x8080 - 0x0000161c: 18d2 .. ADDS r2,r2,r3 - 0x0000161e: 055b [. LSLS r3,r3,#21 - 0x00001620: 18d2 .. ADDS r2,r2,r3 - 0x00001622: 7011 .p STRB r1,[r2,#0] - 0x00001624: bf00 .. NOP - 0x00001626: 4770 pG BX lr + 0x00001512: bf00 .. NOP + 0x00001514: 0682 .. LSLS r2,r0,#26 + 0x00001516: 0e92 .. LSRS r2,r2,#26 + 0x00001518: 4b0f .K LDR r3,[pc,#60] ; [0x1558] = 0x8080 + 0x0000151a: 18d2 .. ADDS r2,r2,r3 + 0x0000151c: 055b [. LSLS r3,r3,#21 + 0x0000151e: 18d2 .. ADDS r2,r2,r3 + 0x00001520: 7011 .p STRB r1,[r2,#0] + 0x00001522: 0682 .. LSLS r2,r0,#26 + 0x00001524: 0e92 .. LSRS r2,r2,#26 + 0x00001526: 4b0c .K LDR r3,[pc,#48] ; [0x1558] = 0x8080 + 0x00001528: 18d2 .. ADDS r2,r2,r3 + 0x0000152a: 055b [. LSLS r3,r3,#21 + 0x0000152c: 18d2 .. ADDS r2,r2,r3 + 0x0000152e: 7011 .p STRB r1,[r2,#0] + 0x00001530: bf00 .. NOP + 0x00001532: 4770 pG BX lr GPIO_GetInputStatusWithJitter - 0x00001628: b5f8 .. PUSH {r3-r7,lr} - 0x0000162a: 4607 .F MOV r7,r0 - 0x0000162c: bf00 .. NOP - 0x0000162e: 4638 8F MOV r0,r7 - 0x00001630: f7ffff58 ..X. BL GPIO_GetInputStatus ; 0x14e4 - 0x00001634: 4606 .F MOV r6,r0 - 0x00001636: 200a . MOVS r0,#0xa - 0x00001638: f000fdb8 .... BL SYS_delay_ms ; 0x21ac - 0x0000163c: 4638 8F MOV r0,r7 - 0x0000163e: f7ffff51 ..Q. BL GPIO_GetInputStatus ; 0x14e4 - 0x00001642: 4604 .F MOV r4,r0 - 0x00001644: 42a6 .B CMP r6,r4 - 0x00001646: d007 .. BEQ 0x1658 ; GPIO_GetInputStatusWithJitter + 48 - 0x00001648: e00e .. B 0x1668 ; GPIO_GetInputStatusWithJitter + 64 + 0x00001534: b5f8 .. PUSH {r3-r7,lr} + 0x00001536: 4607 .F MOV r7,r0 + 0x00001538: bf00 .. NOP + 0x0000153a: 4638 8F MOV r0,r7 + 0x0000153c: f7ffff58 ..X. BL GPIO_GetInputStatus ; 0x13f0 + 0x00001540: 4606 .F MOV r6,r0 + 0x00001542: 200a . MOVS r0,#0xa + 0x00001544: f000fdb8 .... BL SYS_delay_ms ; 0x20b8 + 0x00001548: 4638 8F MOV r0,r7 + 0x0000154a: f7ffff51 ..Q. BL GPIO_GetInputStatus ; 0x13f0 + 0x0000154e: 4604 .F MOV r4,r0 + 0x00001550: 42a6 .B CMP r6,r4 + 0x00001552: d007 .. BEQ 0x1564 ; GPIO_GetInputStatusWithJitter + 48 + 0x00001554: e00e .. B 0x1574 ; GPIO_GetInputStatusWithJitter + 64 $d - 0x0000164a: 0000 .. DCW 0 - 0x0000164c: 00008080 .... DCD 32896 - 0x00001650: 10004fe0 .O.. DCD 268455904 - 0x00001654: 0000831c .... DCD 33564 + 0x00001556: 0000 .. DCW 0 + 0x00001558: 00008080 .... DCD 32896 + 0x0000155c: 10004fe0 .O.. DCD 268455904 + 0x00001560: 0000831c .... DCD 33564 $t - 0x00001658: 200a . MOVS r0,#0xa - 0x0000165a: f000fda7 .... BL SYS_delay_ms ; 0x21ac - 0x0000165e: 4638 8F MOV r0,r7 - 0x00001660: f7ffff40 ..@. BL GPIO_GetInputStatus ; 0x14e4 - 0x00001664: 4605 .F MOV r5,r0 - 0x00001666: bf00 .. NOP - 0x00001668: 42ac .B CMP r4,r5 - 0x0000166a: d1e0 .. BNE 0x162e ; GPIO_GetInputStatusWithJitter + 6 - 0x0000166c: 2001 . MOVS r0,#1 - 0x0000166e: bdf8 .. POP {r3-r7,pc} + 0x00001564: 200a . MOVS r0,#0xa + 0x00001566: f000fda7 .... BL SYS_delay_ms ; 0x20b8 + 0x0000156a: 4638 8F MOV r0,r7 + 0x0000156c: f7ffff40 ..@. BL GPIO_GetInputStatus ; 0x13f0 + 0x00001570: 4605 .F MOV r5,r0 + 0x00001572: bf00 .. NOP + 0x00001574: 42ac .B CMP r4,r5 + 0x00001576: d1e0 .. BNE 0x153a ; GPIO_GetInputStatusWithJitter + 6 + 0x00001578: 2001 . MOVS r0,#1 + 0x0000157a: bdf8 .. POP {r3-r7,pc} GPIO_CheckGpioIsInputFunction - 0x00001670: 4601 .F MOV r1,r0 - 0x00001672: 48fd .H LDR r0,[pc,#1012] ; [0x1a68] = 0x10004fe0 - 0x00001674: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00001676: 2000 . MOVS r0,#0 - 0x00001678: 068a .. LSLS r2,r1,#26 - 0x0000167a: 0e92 .. LSRS r2,r2,#26 - 0x0000167c: 4bfb .K LDR r3,[pc,#1004] ; [0x1a6c] = 0x8080 - 0x0000167e: 18d2 .. ADDS r2,r2,r3 - 0x00001680: 055b [. LSLS r3,r3,#21 - 0x00001682: 18d2 .. ADDS r2,r2,r3 - 0x00001684: 7812 .x LDRB r2,[r2,#0] - 0x00001686: 4300 .C ORRS r0,r0,r0 - 0x00001688: 068a .. LSLS r2,r1,#26 - 0x0000168a: 0e92 .. LSRS r2,r2,#26 - 0x0000168c: 4bf7 .K LDR r3,[pc,#988] ; [0x1a6c] = 0x8080 - 0x0000168e: 18d2 .. ADDS r2,r2,r3 - 0x00001690: 055b [. LSLS r3,r3,#21 - 0x00001692: 18d2 .. ADDS r2,r2,r3 - 0x00001694: 7812 .x LDRB r2,[r2,#0] - 0x00001696: 4310 .C ORRS r0,r0,r2 - 0x00001698: 0680 .. LSLS r0,r0,#26 - 0x0000169a: 0e80 .. LSRS r0,r0,#26 - 0x0000169c: 2800 .( CMP r0,#0 - 0x0000169e: d101 .. BNE 0x16a4 ; GPIO_CheckGpioIsInputFunction + 52 - 0x000016a0: 2001 . MOVS r0,#1 - 0x000016a2: 4770 pG BX lr - 0x000016a4: 2000 . MOVS r0,#0 - 0x000016a6: e7fc .. B 0x16a2 ; GPIO_CheckGpioIsInputFunction + 50 + 0x0000157c: 4601 .F MOV r1,r0 + 0x0000157e: 48fd .H LDR r0,[pc,#1012] ; [0x1974] = 0x10004fe0 + 0x00001580: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x00001582: 2000 . MOVS r0,#0 + 0x00001584: 068a .. LSLS r2,r1,#26 + 0x00001586: 0e92 .. LSRS r2,r2,#26 + 0x00001588: 4bfb .K LDR r3,[pc,#1004] ; [0x1978] = 0x8080 + 0x0000158a: 18d2 .. ADDS r2,r2,r3 + 0x0000158c: 055b [. LSLS r3,r3,#21 + 0x0000158e: 18d2 .. ADDS r2,r2,r3 + 0x00001590: 7812 .x LDRB r2,[r2,#0] + 0x00001592: 4300 .C ORRS r0,r0,r0 + 0x00001594: 068a .. LSLS r2,r1,#26 + 0x00001596: 0e92 .. LSRS r2,r2,#26 + 0x00001598: 4bf7 .K LDR r3,[pc,#988] ; [0x1978] = 0x8080 + 0x0000159a: 18d2 .. ADDS r2,r2,r3 + 0x0000159c: 055b [. LSLS r3,r3,#21 + 0x0000159e: 18d2 .. ADDS r2,r2,r3 + 0x000015a0: 7812 .x LDRB r2,[r2,#0] + 0x000015a2: 4310 .C ORRS r0,r0,r2 + 0x000015a4: 0680 .. LSLS r0,r0,#26 + 0x000015a6: 0e80 .. LSRS r0,r0,#26 + 0x000015a8: 2800 .( CMP r0,#0 + 0x000015aa: d101 .. BNE 0x15b0 ; GPIO_CheckGpioIsInputFunction + 52 + 0x000015ac: 2001 . MOVS r0,#1 + 0x000015ae: 4770 pG BX lr + 0x000015b0: 2000 . MOVS r0,#0 + 0x000015b2: e7fc .. B 0x15ae ; GPIO_CheckGpioIsInputFunction + 50 GPIO_Set_High_Interrupt - 0x000016a8: b570 p. PUSH {r4-r6,lr} - 0x000016aa: 4605 .F MOV r5,r0 - 0x000016ac: 2400 .$ MOVS r4,#0 - 0x000016ae: 2600 .& MOVS r6,#0 - 0x000016b0: 2080 . MOVS r0,#0x80 - 0x000016b2: 4028 (@ ANDS r0,r0,r5 - 0x000016b4: 2800 .( CMP r0,#0 - 0x000016b6: d07d }. BEQ 0x17b4 ; GPIO_Set_High_Interrupt + 268 - 0x000016b8: 2180 .! MOVS r1,#0x80 - 0x000016ba: 4628 (F MOV r0,r5 - 0x000016bc: 4388 .C BICS r0,r0,r1 - 0x000016be: 4605 .F MOV r5,r0 - 0x000016c0: 2d1f .- CMP r5,#0x1f - 0x000016c2: dc53 S. BGT 0x176c ; GPIO_Set_High_Interrupt + 196 - 0x000016c4: 48e8 .H LDR r0,[pc,#928] ; [0x1a68] = 0x10004fe0 - 0x000016c6: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x000016c8: 2000 . MOVS r0,#0 - 0x000016ca: 49e9 .I LDR r1,[pc,#932] ; [0x1a70] = 0x10008340 - 0x000016cc: 7989 .y LDRB r1,[r1,#6] - 0x000016ce: 4300 .C ORRS r0,r0,r0 - 0x000016d0: 49e7 .I LDR r1,[pc,#924] ; [0x1a70] = 0x10008340 - 0x000016d2: 7989 .y LDRB r1,[r1,#6] - 0x000016d4: 4308 .C ORRS r0,r0,r1 - 0x000016d6: 49e4 .I LDR r1,[pc,#912] ; [0x1a68] = 0x10004fe0 - 0x000016d8: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x000016da: 2100 .! MOVS r1,#0 - 0x000016dc: 4ae4 .J LDR r2,[pc,#912] ; [0x1a70] = 0x10008340 - 0x000016de: 79d2 .y LDRB r2,[r2,#7] - 0x000016e0: 4309 .C ORRS r1,r1,r1 - 0x000016e2: 4ae3 .J LDR r2,[pc,#908] ; [0x1a70] = 0x10008340 - 0x000016e4: 79d2 .y LDRB r2,[r2,#7] - 0x000016e6: 4311 .C ORRS r1,r1,r2 - 0x000016e8: 0209 .. LSLS r1,r1,#8 - 0x000016ea: 4308 .C ORRS r0,r0,r1 - 0x000016ec: 49de .I LDR r1,[pc,#888] ; [0x1a68] = 0x10004fe0 - 0x000016ee: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x000016f0: 2100 .! MOVS r1,#0 - 0x000016f2: 4adf .J LDR r2,[pc,#892] ; [0x1a70] = 0x10008340 - 0x000016f4: 7a12 .z LDRB r2,[r2,#8] - 0x000016f6: 4309 .C ORRS r1,r1,r1 - 0x000016f8: 4add .J LDR r2,[pc,#884] ; [0x1a70] = 0x10008340 - 0x000016fa: 7a12 .z LDRB r2,[r2,#8] - 0x000016fc: 4311 .C ORRS r1,r1,r2 - 0x000016fe: 0409 .. LSLS r1,r1,#16 - 0x00001700: 4308 .C ORRS r0,r0,r1 - 0x00001702: 49d9 .I LDR r1,[pc,#868] ; [0x1a68] = 0x10004fe0 - 0x00001704: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00001706: 2100 .! MOVS r1,#0 - 0x00001708: 4ad9 .J LDR r2,[pc,#868] ; [0x1a70] = 0x10008340 - 0x0000170a: 7a52 Rz LDRB r2,[r2,#9] - 0x0000170c: 4309 .C ORRS r1,r1,r1 - 0x0000170e: 4ad8 .J LDR r2,[pc,#864] ; [0x1a70] = 0x10008340 - 0x00001710: 7a52 Rz LDRB r2,[r2,#9] - 0x00001712: 4311 .C ORRS r1,r1,r2 - 0x00001714: 0609 .. LSLS r1,r1,#24 - 0x00001716: 4308 .C ORRS r0,r0,r1 - 0x00001718: 4604 .F MOV r4,r0 - 0x0000171a: 2001 . MOVS r0,#1 - 0x0000171c: 40a8 .@ LSLS r0,r0,r5 - 0x0000171e: 4304 .C ORRS r4,r4,r0 - 0x00001720: bf00 .. NOP - 0x00001722: bf00 .. NOP - 0x00001724: 49d3 .I LDR r1,[pc,#844] ; [0x1a74] = 0x10008040 - 0x00001726: 730c .s STRB r4,[r1,#0xc] - 0x00001728: 730c .s STRB r4,[r1,#0xc] - 0x0000172a: bf00 .. NOP - 0x0000172c: bf00 .. NOP - 0x0000172e: 0420 . LSLS r0,r4,#16 - 0x00001730: 0e00 .. LSRS r0,r0,#24 - 0x00001732: 7348 Hs STRB r0,[r1,#0xd] - 0x00001734: 0420 . LSLS r0,r4,#16 - 0x00001736: 0e00 .. LSRS r0,r0,#24 - 0x00001738: 7348 Hs STRB r0,[r1,#0xd] - 0x0000173a: bf00 .. NOP - 0x0000173c: bf00 .. NOP - 0x0000173e: 0220 . LSLS r0,r4,#8 - 0x00001740: 0e00 .. LSRS r0,r0,#24 - 0x00001742: 7388 .s STRB r0,[r1,#0xe] - 0x00001744: 0220 . LSLS r0,r4,#8 - 0x00001746: 0e00 .. LSRS r0,r0,#24 - 0x00001748: 7388 .s STRB r0,[r1,#0xe] - 0x0000174a: bf00 .. NOP - 0x0000174c: bf00 .. NOP - 0x0000174e: 0e20 . LSRS r0,r4,#24 - 0x00001750: 73c8 .s STRB r0,[r1,#0xf] - 0x00001752: 0e20 . LSRS r0,r4,#24 - 0x00001754: 73c8 .s STRB r0,[r1,#0xf] - 0x00001756: bf00 .. NOP - 0x00001758: bf00 .. NOP - 0x0000175a: bf00 .. NOP - 0x0000175c: 2008 . MOVS r0,#8 - 0x0000175e: 49c5 .I LDR r1,[pc,#788] ; [0x1a74] = 0x10008040 - 0x00001760: 3940 @9 SUBS r1,r1,#0x40 - 0x00001762: 7148 Hq STRB r0,[r1,#5] - 0x00001764: bf00 .. NOP - 0x00001766: 2064 d MOVS r0,#0x64 - 0x00001768: f001fa4b ..K. BL whileDelay ; 0x2c02 - 0x0000176c: 2d1f .- CMP r5,#0x1f - 0x0000176e: dd4b K. BLE 0x1808 ; GPIO_Set_High_Interrupt + 352 - 0x00001770: 2d28 (- CMP r5,#0x28 - 0x00001772: da49 I. BGE 0x1808 ; GPIO_Set_High_Interrupt + 352 - 0x00001774: bf00 .. NOP - 0x00001776: 2088 . MOVS r0,#0x88 - 0x00001778: 49be .I LDR r1,[pc,#760] ; [0x1a74] = 0x10008040 - 0x0000177a: 7308 .s STRB r0,[r1,#0xc] - 0x0000177c: 7308 .s STRB r0,[r1,#0xc] - 0x0000177e: bf00 .. NOP - 0x00001780: 48b9 .H LDR r0,[pc,#740] ; [0x1a68] = 0x10004fe0 - 0x00001782: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00001784: 2000 . MOVS r0,#0 - 0x00001786: 49ba .I LDR r1,[pc,#744] ; [0x1a70] = 0x10008340 - 0x00001788: 7a89 .z LDRB r1,[r1,#0xa] - 0x0000178a: 4300 .C ORRS r0,r0,r0 - 0x0000178c: 49b8 .I LDR r1,[pc,#736] ; [0x1a70] = 0x10008340 - 0x0000178e: 7a89 .z LDRB r1,[r1,#0xa] - 0x00001790: 4308 .C ORRS r0,r0,r1 - 0x00001792: 49b5 .I LDR r1,[pc,#724] ; [0x1a68] = 0x10004fe0 - 0x00001794: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00001796: 4ab6 .J LDR r2,[pc,#728] ; [0x1a70] = 0x10008340 - 0x00001798: 7ad2 .z LDRB r2,[r2,#0xb] - 0x0000179a: 4311 .C ORRS r1,r1,r2 - 0x0000179c: 4ab4 .J LDR r2,[pc,#720] ; [0x1a70] = 0x10008340 - 0x0000179e: 7ad2 .z LDRB r2,[r2,#0xb] - 0x000017a0: 4311 .C ORRS r1,r1,r2 - 0x000017a2: 0209 .. LSLS r1,r1,#8 - 0x000017a4: 4308 .C ORRS r0,r0,r1 - 0x000017a6: 49b0 .I LDR r1,[pc,#704] ; [0x1a68] = 0x10004fe0 - 0x000017a8: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x000017aa: 4ab1 .J LDR r2,[pc,#708] ; [0x1a70] = 0x10008340 - 0x000017ac: 7b12 .{ LDRB r2,[r2,#0xc] - 0x000017ae: 4311 .C ORRS r1,r1,r2 - 0x000017b0: 4aaf .J LDR r2,[pc,#700] ; [0x1a70] = 0x10008340 - 0x000017b2: e000 .. B 0x17b6 ; GPIO_Set_High_Interrupt + 270 - 0x000017b4: e028 (. B 0x1808 ; GPIO_Set_High_Interrupt + 352 - 0x000017b6: 7b12 .{ LDRB r2,[r2,#0xc] - 0x000017b8: 4311 .C ORRS r1,r1,r2 - 0x000017ba: 0409 .. LSLS r1,r1,#16 - 0x000017bc: 4308 .C ORRS r0,r0,r1 - 0x000017be: 49aa .I LDR r1,[pc,#680] ; [0x1a68] = 0x10004fe0 - 0x000017c0: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x000017c2: 4aab .J LDR r2,[pc,#684] ; [0x1a70] = 0x10008340 - 0x000017c4: 7b52 R{ LDRB r2,[r2,#0xd] - 0x000017c6: 4311 .C ORRS r1,r1,r2 - 0x000017c8: 4aa9 .J LDR r2,[pc,#676] ; [0x1a70] = 0x10008340 - 0x000017ca: 7b52 R{ LDRB r2,[r2,#0xd] - 0x000017cc: 4311 .C ORRS r1,r1,r2 - 0x000017ce: 0609 .. LSLS r1,r1,#24 - 0x000017d0: 4308 .C ORRS r0,r0,r1 - 0x000017d2: b2c6 .. UXTB r6,r0 - 0x000017d4: 4629 )F MOV r1,r5 - 0x000017d6: 3920 9 SUBS r1,r1,#0x20 - 0x000017d8: 2001 . MOVS r0,#1 - 0x000017da: 4088 .@ LSLS r0,r0,r1 - 0x000017dc: 4330 0C ORRS r0,r0,r6 - 0x000017de: b2c6 .. UXTB r6,r0 - 0x000017e0: bf00 .. NOP - 0x000017e2: 48a4 .H LDR r0,[pc,#656] ; [0x1a74] = 0x10008040 - 0x000017e4: 7346 Fs STRB r6,[r0,#0xd] - 0x000017e6: 7346 Fs STRB r6,[r0,#0xd] - 0x000017e8: bf00 .. NOP - 0x000017ea: bf00 .. NOP - 0x000017ec: 2000 . MOVS r0,#0 - 0x000017ee: 49a1 .I LDR r1,[pc,#644] ; [0x1a74] = 0x10008040 - 0x000017f0: 7388 .s STRB r0,[r1,#0xe] - 0x000017f2: 7388 .s STRB r0,[r1,#0xe] - 0x000017f4: bf00 .. NOP - 0x000017f6: bf00 .. NOP - 0x000017f8: 2008 . MOVS r0,#8 - 0x000017fa: 499e .I LDR r1,[pc,#632] ; [0x1a74] = 0x10008040 - 0x000017fc: 3940 @9 SUBS r1,r1,#0x40 - 0x000017fe: 7648 Hv STRB r0,[r1,#0x19] - 0x00001800: bf00 .. NOP - 0x00001802: 2064 d MOVS r0,#0x64 - 0x00001804: f001f9fd .... BL whileDelay ; 0x2c02 - 0x00001808: bd70 p. POP {r4-r6,pc} + 0x000015b4: b570 p. PUSH {r4-r6,lr} + 0x000015b6: 4605 .F MOV r5,r0 + 0x000015b8: 2400 .$ MOVS r4,#0 + 0x000015ba: 2600 .& MOVS r6,#0 + 0x000015bc: 2080 . MOVS r0,#0x80 + 0x000015be: 4028 (@ ANDS r0,r0,r5 + 0x000015c0: 2800 .( CMP r0,#0 + 0x000015c2: d07d }. BEQ 0x16c0 ; GPIO_Set_High_Interrupt + 268 + 0x000015c4: 2180 .! MOVS r1,#0x80 + 0x000015c6: 4628 (F MOV r0,r5 + 0x000015c8: 4388 .C BICS r0,r0,r1 + 0x000015ca: 4605 .F MOV r5,r0 + 0x000015cc: 2d1f .- CMP r5,#0x1f + 0x000015ce: dc53 S. BGT 0x1678 ; GPIO_Set_High_Interrupt + 196 + 0x000015d0: 48e8 .H LDR r0,[pc,#928] ; [0x1974] = 0x10004fe0 + 0x000015d2: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x000015d4: 2000 . MOVS r0,#0 + 0x000015d6: 49e9 .I LDR r1,[pc,#932] ; [0x197c] = 0x10008340 + 0x000015d8: 7989 .y LDRB r1,[r1,#6] + 0x000015da: 4300 .C ORRS r0,r0,r0 + 0x000015dc: 49e7 .I LDR r1,[pc,#924] ; [0x197c] = 0x10008340 + 0x000015de: 7989 .y LDRB r1,[r1,#6] + 0x000015e0: 4308 .C ORRS r0,r0,r1 + 0x000015e2: 49e4 .I LDR r1,[pc,#912] ; [0x1974] = 0x10004fe0 + 0x000015e4: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x000015e6: 2100 .! MOVS r1,#0 + 0x000015e8: 4ae4 .J LDR r2,[pc,#912] ; [0x197c] = 0x10008340 + 0x000015ea: 79d2 .y LDRB r2,[r2,#7] + 0x000015ec: 4309 .C ORRS r1,r1,r1 + 0x000015ee: 4ae3 .J LDR r2,[pc,#908] ; [0x197c] = 0x10008340 + 0x000015f0: 79d2 .y LDRB r2,[r2,#7] + 0x000015f2: 4311 .C ORRS r1,r1,r2 + 0x000015f4: 0209 .. LSLS r1,r1,#8 + 0x000015f6: 4308 .C ORRS r0,r0,r1 + 0x000015f8: 49de .I LDR r1,[pc,#888] ; [0x1974] = 0x10004fe0 + 0x000015fa: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x000015fc: 2100 .! MOVS r1,#0 + 0x000015fe: 4adf .J LDR r2,[pc,#892] ; [0x197c] = 0x10008340 + 0x00001600: 7a12 .z LDRB r2,[r2,#8] + 0x00001602: 4309 .C ORRS r1,r1,r1 + 0x00001604: 4add .J LDR r2,[pc,#884] ; [0x197c] = 0x10008340 + 0x00001606: 7a12 .z LDRB r2,[r2,#8] + 0x00001608: 4311 .C ORRS r1,r1,r2 + 0x0000160a: 0409 .. LSLS r1,r1,#16 + 0x0000160c: 4308 .C ORRS r0,r0,r1 + 0x0000160e: 49d9 .I LDR r1,[pc,#868] ; [0x1974] = 0x10004fe0 + 0x00001610: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x00001612: 2100 .! MOVS r1,#0 + 0x00001614: 4ad9 .J LDR r2,[pc,#868] ; [0x197c] = 0x10008340 + 0x00001616: 7a52 Rz LDRB r2,[r2,#9] + 0x00001618: 4309 .C ORRS r1,r1,r1 + 0x0000161a: 4ad8 .J LDR r2,[pc,#864] ; [0x197c] = 0x10008340 + 0x0000161c: 7a52 Rz LDRB r2,[r2,#9] + 0x0000161e: 4311 .C ORRS r1,r1,r2 + 0x00001620: 0609 .. LSLS r1,r1,#24 + 0x00001622: 4308 .C ORRS r0,r0,r1 + 0x00001624: 4604 .F MOV r4,r0 + 0x00001626: 2001 . MOVS r0,#1 + 0x00001628: 40a8 .@ LSLS r0,r0,r5 + 0x0000162a: 4304 .C ORRS r4,r4,r0 + 0x0000162c: bf00 .. NOP + 0x0000162e: bf00 .. NOP + 0x00001630: 49d3 .I LDR r1,[pc,#844] ; [0x1980] = 0x10008040 + 0x00001632: 730c .s STRB r4,[r1,#0xc] + 0x00001634: 730c .s STRB r4,[r1,#0xc] + 0x00001636: bf00 .. NOP + 0x00001638: bf00 .. NOP + 0x0000163a: 0420 . LSLS r0,r4,#16 + 0x0000163c: 0e00 .. LSRS r0,r0,#24 + 0x0000163e: 7348 Hs STRB r0,[r1,#0xd] + 0x00001640: 0420 . LSLS r0,r4,#16 + 0x00001642: 0e00 .. LSRS r0,r0,#24 + 0x00001644: 7348 Hs STRB r0,[r1,#0xd] + 0x00001646: bf00 .. NOP + 0x00001648: bf00 .. NOP + 0x0000164a: 0220 . LSLS r0,r4,#8 + 0x0000164c: 0e00 .. LSRS r0,r0,#24 + 0x0000164e: 7388 .s STRB r0,[r1,#0xe] + 0x00001650: 0220 . LSLS r0,r4,#8 + 0x00001652: 0e00 .. LSRS r0,r0,#24 + 0x00001654: 7388 .s STRB r0,[r1,#0xe] + 0x00001656: bf00 .. NOP + 0x00001658: bf00 .. NOP + 0x0000165a: 0e20 . LSRS r0,r4,#24 + 0x0000165c: 73c8 .s STRB r0,[r1,#0xf] + 0x0000165e: 0e20 . LSRS r0,r4,#24 + 0x00001660: 73c8 .s STRB r0,[r1,#0xf] + 0x00001662: bf00 .. NOP + 0x00001664: bf00 .. NOP + 0x00001666: bf00 .. NOP + 0x00001668: 2008 . MOVS r0,#8 + 0x0000166a: 49c5 .I LDR r1,[pc,#788] ; [0x1980] = 0x10008040 + 0x0000166c: 3940 @9 SUBS r1,r1,#0x40 + 0x0000166e: 7148 Hq STRB r0,[r1,#5] + 0x00001670: bf00 .. NOP + 0x00001672: 2064 d MOVS r0,#0x64 + 0x00001674: f001fb5b ..[. BL whileDelay ; 0x2d2e + 0x00001678: 2d1f .- CMP r5,#0x1f + 0x0000167a: dd4b K. BLE 0x1714 ; GPIO_Set_High_Interrupt + 352 + 0x0000167c: 2d28 (- CMP r5,#0x28 + 0x0000167e: da49 I. BGE 0x1714 ; GPIO_Set_High_Interrupt + 352 + 0x00001680: bf00 .. NOP + 0x00001682: 2088 . MOVS r0,#0x88 + 0x00001684: 49be .I LDR r1,[pc,#760] ; [0x1980] = 0x10008040 + 0x00001686: 7308 .s STRB r0,[r1,#0xc] + 0x00001688: 7308 .s STRB r0,[r1,#0xc] + 0x0000168a: bf00 .. NOP + 0x0000168c: 48b9 .H LDR r0,[pc,#740] ; [0x1974] = 0x10004fe0 + 0x0000168e: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x00001690: 2000 . MOVS r0,#0 + 0x00001692: 49ba .I LDR r1,[pc,#744] ; [0x197c] = 0x10008340 + 0x00001694: 7a89 .z LDRB r1,[r1,#0xa] + 0x00001696: 4300 .C ORRS r0,r0,r0 + 0x00001698: 49b8 .I LDR r1,[pc,#736] ; [0x197c] = 0x10008340 + 0x0000169a: 7a89 .z LDRB r1,[r1,#0xa] + 0x0000169c: 4308 .C ORRS r0,r0,r1 + 0x0000169e: 49b5 .I LDR r1,[pc,#724] ; [0x1974] = 0x10004fe0 + 0x000016a0: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x000016a2: 4ab6 .J LDR r2,[pc,#728] ; [0x197c] = 0x10008340 + 0x000016a4: 7ad2 .z LDRB r2,[r2,#0xb] + 0x000016a6: 4311 .C ORRS r1,r1,r2 + 0x000016a8: 4ab4 .J LDR r2,[pc,#720] ; [0x197c] = 0x10008340 + 0x000016aa: 7ad2 .z LDRB r2,[r2,#0xb] + 0x000016ac: 4311 .C ORRS r1,r1,r2 + 0x000016ae: 0209 .. LSLS r1,r1,#8 + 0x000016b0: 4308 .C ORRS r0,r0,r1 + 0x000016b2: 49b0 .I LDR r1,[pc,#704] ; [0x1974] = 0x10004fe0 + 0x000016b4: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x000016b6: 4ab1 .J LDR r2,[pc,#708] ; [0x197c] = 0x10008340 + 0x000016b8: 7b12 .{ LDRB r2,[r2,#0xc] + 0x000016ba: 4311 .C ORRS r1,r1,r2 + 0x000016bc: 4aaf .J LDR r2,[pc,#700] ; [0x197c] = 0x10008340 + 0x000016be: e000 .. B 0x16c2 ; GPIO_Set_High_Interrupt + 270 + 0x000016c0: e028 (. B 0x1714 ; GPIO_Set_High_Interrupt + 352 + 0x000016c2: 7b12 .{ LDRB r2,[r2,#0xc] + 0x000016c4: 4311 .C ORRS r1,r1,r2 + 0x000016c6: 0409 .. LSLS r1,r1,#16 + 0x000016c8: 4308 .C ORRS r0,r0,r1 + 0x000016ca: 49aa .I LDR r1,[pc,#680] ; [0x1974] = 0x10004fe0 + 0x000016cc: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x000016ce: 4aab .J LDR r2,[pc,#684] ; [0x197c] = 0x10008340 + 0x000016d0: 7b52 R{ LDRB r2,[r2,#0xd] + 0x000016d2: 4311 .C ORRS r1,r1,r2 + 0x000016d4: 4aa9 .J LDR r2,[pc,#676] ; [0x197c] = 0x10008340 + 0x000016d6: 7b52 R{ LDRB r2,[r2,#0xd] + 0x000016d8: 4311 .C ORRS r1,r1,r2 + 0x000016da: 0609 .. LSLS r1,r1,#24 + 0x000016dc: 4308 .C ORRS r0,r0,r1 + 0x000016de: b2c6 .. UXTB r6,r0 + 0x000016e0: 4629 )F MOV r1,r5 + 0x000016e2: 3920 9 SUBS r1,r1,#0x20 + 0x000016e4: 2001 . MOVS r0,#1 + 0x000016e6: 4088 .@ LSLS r0,r0,r1 + 0x000016e8: 4330 0C ORRS r0,r0,r6 + 0x000016ea: b2c6 .. UXTB r6,r0 + 0x000016ec: bf00 .. NOP + 0x000016ee: 48a4 .H LDR r0,[pc,#656] ; [0x1980] = 0x10008040 + 0x000016f0: 7346 Fs STRB r6,[r0,#0xd] + 0x000016f2: 7346 Fs STRB r6,[r0,#0xd] + 0x000016f4: bf00 .. NOP + 0x000016f6: bf00 .. NOP + 0x000016f8: 2000 . MOVS r0,#0 + 0x000016fa: 49a1 .I LDR r1,[pc,#644] ; [0x1980] = 0x10008040 + 0x000016fc: 7388 .s STRB r0,[r1,#0xe] + 0x000016fe: 7388 .s STRB r0,[r1,#0xe] + 0x00001700: bf00 .. NOP + 0x00001702: bf00 .. NOP + 0x00001704: 2008 . MOVS r0,#8 + 0x00001706: 499e .I LDR r1,[pc,#632] ; [0x1980] = 0x10008040 + 0x00001708: 3940 @9 SUBS r1,r1,#0x40 + 0x0000170a: 7648 Hv STRB r0,[r1,#0x19] + 0x0000170c: bf00 .. NOP + 0x0000170e: 2064 d MOVS r0,#0x64 + 0x00001710: f001fb0d .... BL whileDelay ; 0x2d2e + 0x00001714: bd70 p. POP {r4-r6,pc} GPIO_Set_Low_Interrupt - 0x0000180a: b570 p. PUSH {r4-r6,lr} - 0x0000180c: 4605 .F MOV r5,r0 - 0x0000180e: 2400 .$ MOVS r4,#0 - 0x00001810: 2600 .& MOVS r6,#0 - 0x00001812: 2080 . MOVS r0,#0x80 - 0x00001814: 4028 (@ ANDS r0,r0,r5 - 0x00001816: 2800 .( CMP r0,#0 - 0x00001818: d07e ~. BEQ 0x1918 ; GPIO_Set_Low_Interrupt + 270 - 0x0000181a: 2180 .! MOVS r1,#0x80 - 0x0000181c: 4628 (F MOV r0,r5 - 0x0000181e: 4388 .C BICS r0,r0,r1 - 0x00001820: 4605 .F MOV r5,r0 - 0x00001822: 2d1f .- CMP r5,#0x1f - 0x00001824: dc53 S. BGT 0x18ce ; GPIO_Set_Low_Interrupt + 196 - 0x00001826: 4890 .H LDR r0,[pc,#576] ; [0x1a68] = 0x10004fe0 - 0x00001828: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x0000182a: 2000 . MOVS r0,#0 - 0x0000182c: 4990 .I LDR r1,[pc,#576] ; [0x1a70] = 0x10008340 - 0x0000182e: 7889 .x LDRB r1,[r1,#2] - 0x00001830: 4300 .C ORRS r0,r0,r0 - 0x00001832: 498f .I LDR r1,[pc,#572] ; [0x1a70] = 0x10008340 - 0x00001834: 7889 .x LDRB r1,[r1,#2] - 0x00001836: 4308 .C ORRS r0,r0,r1 - 0x00001838: 498b .I LDR r1,[pc,#556] ; [0x1a68] = 0x10004fe0 - 0x0000183a: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x0000183c: 2100 .! MOVS r1,#0 - 0x0000183e: 4a8c .J LDR r2,[pc,#560] ; [0x1a70] = 0x10008340 - 0x00001840: 78d2 .x LDRB r2,[r2,#3] - 0x00001842: 4309 .C ORRS r1,r1,r1 - 0x00001844: 4a8a .J LDR r2,[pc,#552] ; [0x1a70] = 0x10008340 - 0x00001846: 78d2 .x LDRB r2,[r2,#3] - 0x00001848: 4311 .C ORRS r1,r1,r2 - 0x0000184a: 0209 .. LSLS r1,r1,#8 - 0x0000184c: 4308 .C ORRS r0,r0,r1 - 0x0000184e: 4986 .I LDR r1,[pc,#536] ; [0x1a68] = 0x10004fe0 - 0x00001850: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00001852: 2100 .! MOVS r1,#0 - 0x00001854: 4a86 .J LDR r2,[pc,#536] ; [0x1a70] = 0x10008340 - 0x00001856: 7912 .y LDRB r2,[r2,#4] - 0x00001858: 4309 .C ORRS r1,r1,r1 - 0x0000185a: 4a85 .J LDR r2,[pc,#532] ; [0x1a70] = 0x10008340 - 0x0000185c: 7912 .y LDRB r2,[r2,#4] - 0x0000185e: 4311 .C ORRS r1,r1,r2 - 0x00001860: 0409 .. LSLS r1,r1,#16 - 0x00001862: 4308 .C ORRS r0,r0,r1 - 0x00001864: 4980 .I LDR r1,[pc,#512] ; [0x1a68] = 0x10004fe0 - 0x00001866: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00001868: 2100 .! MOVS r1,#0 - 0x0000186a: 4a81 .J LDR r2,[pc,#516] ; [0x1a70] = 0x10008340 - 0x0000186c: 7952 Ry LDRB r2,[r2,#5] - 0x0000186e: 4309 .C ORRS r1,r1,r1 - 0x00001870: 4a7f .J LDR r2,[pc,#508] ; [0x1a70] = 0x10008340 - 0x00001872: 7952 Ry LDRB r2,[r2,#5] - 0x00001874: 4311 .C ORRS r1,r1,r2 - 0x00001876: 0609 .. LSLS r1,r1,#24 - 0x00001878: 4308 .C ORRS r0,r0,r1 - 0x0000187a: 4604 .F MOV r4,r0 - 0x0000187c: 2001 . MOVS r0,#1 - 0x0000187e: 40a8 .@ LSLS r0,r0,r5 - 0x00001880: 4304 .C ORRS r4,r4,r0 - 0x00001882: bf00 .. NOP - 0x00001884: bf00 .. NOP - 0x00001886: 497b {I LDR r1,[pc,#492] ; [0x1a74] = 0x10008040 - 0x00001888: 730c .s STRB r4,[r1,#0xc] - 0x0000188a: 730c .s STRB r4,[r1,#0xc] - 0x0000188c: bf00 .. NOP - 0x0000188e: bf00 .. NOP - 0x00001890: 0420 . LSLS r0,r4,#16 - 0x00001892: 0e00 .. LSRS r0,r0,#24 - 0x00001894: 7348 Hs STRB r0,[r1,#0xd] - 0x00001896: 0420 . LSLS r0,r4,#16 - 0x00001898: 0e00 .. LSRS r0,r0,#24 - 0x0000189a: 7348 Hs STRB r0,[r1,#0xd] - 0x0000189c: bf00 .. NOP - 0x0000189e: bf00 .. NOP - 0x000018a0: 0220 . LSLS r0,r4,#8 - 0x000018a2: 0e00 .. LSRS r0,r0,#24 - 0x000018a4: 7388 .s STRB r0,[r1,#0xe] - 0x000018a6: 0220 . LSLS r0,r4,#8 - 0x000018a8: 0e00 .. LSRS r0,r0,#24 - 0x000018aa: 7388 .s STRB r0,[r1,#0xe] - 0x000018ac: bf00 .. NOP - 0x000018ae: bf00 .. NOP - 0x000018b0: 0e20 . LSRS r0,r4,#24 - 0x000018b2: 73c8 .s STRB r0,[r1,#0xf] - 0x000018b4: 0e20 . LSRS r0,r4,#24 - 0x000018b6: 73c8 .s STRB r0,[r1,#0xf] - 0x000018b8: bf00 .. NOP - 0x000018ba: bf00 .. NOP - 0x000018bc: bf00 .. NOP - 0x000018be: 2004 . MOVS r0,#4 - 0x000018c0: 496c lI LDR r1,[pc,#432] ; [0x1a74] = 0x10008040 - 0x000018c2: 3940 @9 SUBS r1,r1,#0x40 - 0x000018c4: 7148 Hq STRB r0,[r1,#5] - 0x000018c6: bf00 .. NOP - 0x000018c8: 2064 d MOVS r0,#0x64 - 0x000018ca: f001f99a .... BL whileDelay ; 0x2c02 - 0x000018ce: 2d1f .- CMP r5,#0x1f - 0x000018d0: dd4a J. BLE 0x1968 ; GPIO_Set_Low_Interrupt + 350 - 0x000018d2: 2d28 (- CMP r5,#0x28 - 0x000018d4: da48 H. BGE 0x1968 ; GPIO_Set_Low_Interrupt + 350 - 0x000018d6: bf00 .. NOP - 0x000018d8: 2088 . MOVS r0,#0x88 - 0x000018da: 4966 fI LDR r1,[pc,#408] ; [0x1a74] = 0x10008040 - 0x000018dc: 7308 .s STRB r0,[r1,#0xc] - 0x000018de: 7308 .s STRB r0,[r1,#0xc] - 0x000018e0: bf00 .. NOP - 0x000018e2: bf00 .. NOP - 0x000018e4: 2000 . MOVS r0,#0 - 0x000018e6: 7348 Hs STRB r0,[r1,#0xd] - 0x000018e8: 7348 Hs STRB r0,[r1,#0xd] - 0x000018ea: bf00 .. NOP - 0x000018ec: 485e ^H LDR r0,[pc,#376] ; [0x1a68] = 0x10004fe0 - 0x000018ee: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x000018f0: 2000 . MOVS r0,#0 - 0x000018f2: 495f _I LDR r1,[pc,#380] ; [0x1a70] = 0x10008340 - 0x000018f4: 7989 .y LDRB r1,[r1,#6] - 0x000018f6: 4300 .C ORRS r0,r0,r0 - 0x000018f8: 495d ]I LDR r1,[pc,#372] ; [0x1a70] = 0x10008340 - 0x000018fa: 7989 .y LDRB r1,[r1,#6] - 0x000018fc: 4308 .C ORRS r0,r0,r1 - 0x000018fe: 495a ZI LDR r1,[pc,#360] ; [0x1a68] = 0x10004fe0 - 0x00001900: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00001902: 4a5b [J LDR r2,[pc,#364] ; [0x1a70] = 0x10008340 - 0x00001904: 79d2 .y LDRB r2,[r2,#7] - 0x00001906: 4311 .C ORRS r1,r1,r2 - 0x00001908: 4a59 YJ LDR r2,[pc,#356] ; [0x1a70] = 0x10008340 - 0x0000190a: 79d2 .y LDRB r2,[r2,#7] - 0x0000190c: 4311 .C ORRS r1,r1,r2 - 0x0000190e: 0209 .. LSLS r1,r1,#8 - 0x00001910: 4308 .C ORRS r0,r0,r1 - 0x00001912: 4955 UI LDR r1,[pc,#340] ; [0x1a68] = 0x10004fe0 - 0x00001914: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00001916: e000 .. B 0x191a ; GPIO_Set_Low_Interrupt + 272 - 0x00001918: e026 &. B 0x1968 ; GPIO_Set_Low_Interrupt + 350 - 0x0000191a: 4a55 UJ LDR r2,[pc,#340] ; [0x1a70] = 0x10008340 - 0x0000191c: 7a12 .z LDRB r2,[r2,#8] - 0x0000191e: 4311 .C ORRS r1,r1,r2 - 0x00001920: 4a53 SJ LDR r2,[pc,#332] ; [0x1a70] = 0x10008340 - 0x00001922: 7a12 .z LDRB r2,[r2,#8] - 0x00001924: 4311 .C ORRS r1,r1,r2 - 0x00001926: 0409 .. LSLS r1,r1,#16 - 0x00001928: 4308 .C ORRS r0,r0,r1 - 0x0000192a: 494f OI LDR r1,[pc,#316] ; [0x1a68] = 0x10004fe0 - 0x0000192c: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x0000192e: 4a50 PJ LDR r2,[pc,#320] ; [0x1a70] = 0x10008340 - 0x00001930: 7a52 Rz LDRB r2,[r2,#9] - 0x00001932: 4311 .C ORRS r1,r1,r2 - 0x00001934: 4a4e NJ LDR r2,[pc,#312] ; [0x1a70] = 0x10008340 - 0x00001936: 7a52 Rz LDRB r2,[r2,#9] - 0x00001938: 4311 .C ORRS r1,r1,r2 - 0x0000193a: 0609 .. LSLS r1,r1,#24 - 0x0000193c: 4308 .C ORRS r0,r0,r1 - 0x0000193e: b2c6 .. UXTB r6,r0 - 0x00001940: 4629 )F MOV r1,r5 - 0x00001942: 3920 9 SUBS r1,r1,#0x20 - 0x00001944: 2001 . MOVS r0,#1 - 0x00001946: 4088 .@ LSLS r0,r0,r1 - 0x00001948: 4330 0C ORRS r0,r0,r6 - 0x0000194a: b2c6 .. UXTB r6,r0 - 0x0000194c: bf00 .. NOP - 0x0000194e: 4849 IH LDR r0,[pc,#292] ; [0x1a74] = 0x10008040 - 0x00001950: 7386 .s STRB r6,[r0,#0xe] - 0x00001952: 7386 .s STRB r6,[r0,#0xe] - 0x00001954: bf00 .. NOP - 0x00001956: bf00 .. NOP - 0x00001958: 2008 . MOVS r0,#8 - 0x0000195a: 4946 FI LDR r1,[pc,#280] ; [0x1a74] = 0x10008040 - 0x0000195c: 3940 @9 SUBS r1,r1,#0x40 - 0x0000195e: 7648 Hv STRB r0,[r1,#0x19] - 0x00001960: bf00 .. NOP - 0x00001962: 2064 d MOVS r0,#0x64 - 0x00001964: f001f94d ..M. BL whileDelay ; 0x2c02 - 0x00001968: bd70 p. POP {r4-r6,pc} + 0x00001716: b570 p. PUSH {r4-r6,lr} + 0x00001718: 4605 .F MOV r5,r0 + 0x0000171a: 2400 .$ MOVS r4,#0 + 0x0000171c: 2600 .& MOVS r6,#0 + 0x0000171e: 2080 . MOVS r0,#0x80 + 0x00001720: 4028 (@ ANDS r0,r0,r5 + 0x00001722: 2800 .( CMP r0,#0 + 0x00001724: d07e ~. BEQ 0x1824 ; GPIO_Set_Low_Interrupt + 270 + 0x00001726: 2180 .! MOVS r1,#0x80 + 0x00001728: 4628 (F MOV r0,r5 + 0x0000172a: 4388 .C BICS r0,r0,r1 + 0x0000172c: 4605 .F MOV r5,r0 + 0x0000172e: 2d1f .- CMP r5,#0x1f + 0x00001730: dc53 S. BGT 0x17da ; GPIO_Set_Low_Interrupt + 196 + 0x00001732: 4890 .H LDR r0,[pc,#576] ; [0x1974] = 0x10004fe0 + 0x00001734: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x00001736: 2000 . MOVS r0,#0 + 0x00001738: 4990 .I LDR r1,[pc,#576] ; [0x197c] = 0x10008340 + 0x0000173a: 7889 .x LDRB r1,[r1,#2] + 0x0000173c: 4300 .C ORRS r0,r0,r0 + 0x0000173e: 498f .I LDR r1,[pc,#572] ; [0x197c] = 0x10008340 + 0x00001740: 7889 .x LDRB r1,[r1,#2] + 0x00001742: 4308 .C ORRS r0,r0,r1 + 0x00001744: 498b .I LDR r1,[pc,#556] ; [0x1974] = 0x10004fe0 + 0x00001746: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x00001748: 2100 .! MOVS r1,#0 + 0x0000174a: 4a8c .J LDR r2,[pc,#560] ; [0x197c] = 0x10008340 + 0x0000174c: 78d2 .x LDRB r2,[r2,#3] + 0x0000174e: 4309 .C ORRS r1,r1,r1 + 0x00001750: 4a8a .J LDR r2,[pc,#552] ; [0x197c] = 0x10008340 + 0x00001752: 78d2 .x LDRB r2,[r2,#3] + 0x00001754: 4311 .C ORRS r1,r1,r2 + 0x00001756: 0209 .. LSLS r1,r1,#8 + 0x00001758: 4308 .C ORRS r0,r0,r1 + 0x0000175a: 4986 .I LDR r1,[pc,#536] ; [0x1974] = 0x10004fe0 + 0x0000175c: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x0000175e: 2100 .! MOVS r1,#0 + 0x00001760: 4a86 .J LDR r2,[pc,#536] ; [0x197c] = 0x10008340 + 0x00001762: 7912 .y LDRB r2,[r2,#4] + 0x00001764: 4309 .C ORRS r1,r1,r1 + 0x00001766: 4a85 .J LDR r2,[pc,#532] ; [0x197c] = 0x10008340 + 0x00001768: 7912 .y LDRB r2,[r2,#4] + 0x0000176a: 4311 .C ORRS r1,r1,r2 + 0x0000176c: 0409 .. LSLS r1,r1,#16 + 0x0000176e: 4308 .C ORRS r0,r0,r1 + 0x00001770: 4980 .I LDR r1,[pc,#512] ; [0x1974] = 0x10004fe0 + 0x00001772: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x00001774: 2100 .! MOVS r1,#0 + 0x00001776: 4a81 .J LDR r2,[pc,#516] ; [0x197c] = 0x10008340 + 0x00001778: 7952 Ry LDRB r2,[r2,#5] + 0x0000177a: 4309 .C ORRS r1,r1,r1 + 0x0000177c: 4a7f .J LDR r2,[pc,#508] ; [0x197c] = 0x10008340 + 0x0000177e: 7952 Ry LDRB r2,[r2,#5] + 0x00001780: 4311 .C ORRS r1,r1,r2 + 0x00001782: 0609 .. LSLS r1,r1,#24 + 0x00001784: 4308 .C ORRS r0,r0,r1 + 0x00001786: 4604 .F MOV r4,r0 + 0x00001788: 2001 . MOVS r0,#1 + 0x0000178a: 40a8 .@ LSLS r0,r0,r5 + 0x0000178c: 4304 .C ORRS r4,r4,r0 + 0x0000178e: bf00 .. NOP + 0x00001790: bf00 .. NOP + 0x00001792: 497b {I LDR r1,[pc,#492] ; [0x1980] = 0x10008040 + 0x00001794: 730c .s STRB r4,[r1,#0xc] + 0x00001796: 730c .s STRB r4,[r1,#0xc] + 0x00001798: bf00 .. NOP + 0x0000179a: bf00 .. NOP + 0x0000179c: 0420 . LSLS r0,r4,#16 + 0x0000179e: 0e00 .. LSRS r0,r0,#24 + 0x000017a0: 7348 Hs STRB r0,[r1,#0xd] + 0x000017a2: 0420 . LSLS r0,r4,#16 + 0x000017a4: 0e00 .. LSRS r0,r0,#24 + 0x000017a6: 7348 Hs STRB r0,[r1,#0xd] + 0x000017a8: bf00 .. NOP + 0x000017aa: bf00 .. NOP + 0x000017ac: 0220 . LSLS r0,r4,#8 + 0x000017ae: 0e00 .. LSRS r0,r0,#24 + 0x000017b0: 7388 .s STRB r0,[r1,#0xe] + 0x000017b2: 0220 . LSLS r0,r4,#8 + 0x000017b4: 0e00 .. LSRS r0,r0,#24 + 0x000017b6: 7388 .s STRB r0,[r1,#0xe] + 0x000017b8: bf00 .. NOP + 0x000017ba: bf00 .. NOP + 0x000017bc: 0e20 . LSRS r0,r4,#24 + 0x000017be: 73c8 .s STRB r0,[r1,#0xf] + 0x000017c0: 0e20 . LSRS r0,r4,#24 + 0x000017c2: 73c8 .s STRB r0,[r1,#0xf] + 0x000017c4: bf00 .. NOP + 0x000017c6: bf00 .. NOP + 0x000017c8: bf00 .. NOP + 0x000017ca: 2004 . MOVS r0,#4 + 0x000017cc: 496c lI LDR r1,[pc,#432] ; [0x1980] = 0x10008040 + 0x000017ce: 3940 @9 SUBS r1,r1,#0x40 + 0x000017d0: 7148 Hq STRB r0,[r1,#5] + 0x000017d2: bf00 .. NOP + 0x000017d4: 2064 d MOVS r0,#0x64 + 0x000017d6: f001faaa .... BL whileDelay ; 0x2d2e + 0x000017da: 2d1f .- CMP r5,#0x1f + 0x000017dc: dd4a J. BLE 0x1874 ; GPIO_Set_Low_Interrupt + 350 + 0x000017de: 2d28 (- CMP r5,#0x28 + 0x000017e0: da48 H. BGE 0x1874 ; GPIO_Set_Low_Interrupt + 350 + 0x000017e2: bf00 .. NOP + 0x000017e4: 2088 . MOVS r0,#0x88 + 0x000017e6: 4966 fI LDR r1,[pc,#408] ; [0x1980] = 0x10008040 + 0x000017e8: 7308 .s STRB r0,[r1,#0xc] + 0x000017ea: 7308 .s STRB r0,[r1,#0xc] + 0x000017ec: bf00 .. NOP + 0x000017ee: bf00 .. NOP + 0x000017f0: 2000 . MOVS r0,#0 + 0x000017f2: 7348 Hs STRB r0,[r1,#0xd] + 0x000017f4: 7348 Hs STRB r0,[r1,#0xd] + 0x000017f6: bf00 .. NOP + 0x000017f8: 485e ^H LDR r0,[pc,#376] ; [0x1974] = 0x10004fe0 + 0x000017fa: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x000017fc: 2000 . MOVS r0,#0 + 0x000017fe: 495f _I LDR r1,[pc,#380] ; [0x197c] = 0x10008340 + 0x00001800: 7989 .y LDRB r1,[r1,#6] + 0x00001802: 4300 .C ORRS r0,r0,r0 + 0x00001804: 495d ]I LDR r1,[pc,#372] ; [0x197c] = 0x10008340 + 0x00001806: 7989 .y LDRB r1,[r1,#6] + 0x00001808: 4308 .C ORRS r0,r0,r1 + 0x0000180a: 495a ZI LDR r1,[pc,#360] ; [0x1974] = 0x10004fe0 + 0x0000180c: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x0000180e: 4a5b [J LDR r2,[pc,#364] ; [0x197c] = 0x10008340 + 0x00001810: 79d2 .y LDRB r2,[r2,#7] + 0x00001812: 4311 .C ORRS r1,r1,r2 + 0x00001814: 4a59 YJ LDR r2,[pc,#356] ; [0x197c] = 0x10008340 + 0x00001816: 79d2 .y LDRB r2,[r2,#7] + 0x00001818: 4311 .C ORRS r1,r1,r2 + 0x0000181a: 0209 .. LSLS r1,r1,#8 + 0x0000181c: 4308 .C ORRS r0,r0,r1 + 0x0000181e: 4955 UI LDR r1,[pc,#340] ; [0x1974] = 0x10004fe0 + 0x00001820: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x00001822: e000 .. B 0x1826 ; GPIO_Set_Low_Interrupt + 272 + 0x00001824: e026 &. B 0x1874 ; GPIO_Set_Low_Interrupt + 350 + 0x00001826: 4a55 UJ LDR r2,[pc,#340] ; [0x197c] = 0x10008340 + 0x00001828: 7a12 .z LDRB r2,[r2,#8] + 0x0000182a: 4311 .C ORRS r1,r1,r2 + 0x0000182c: 4a53 SJ LDR r2,[pc,#332] ; [0x197c] = 0x10008340 + 0x0000182e: 7a12 .z LDRB r2,[r2,#8] + 0x00001830: 4311 .C ORRS r1,r1,r2 + 0x00001832: 0409 .. LSLS r1,r1,#16 + 0x00001834: 4308 .C ORRS r0,r0,r1 + 0x00001836: 494f OI LDR r1,[pc,#316] ; [0x1974] = 0x10004fe0 + 0x00001838: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x0000183a: 4a50 PJ LDR r2,[pc,#320] ; [0x197c] = 0x10008340 + 0x0000183c: 7a52 Rz LDRB r2,[r2,#9] + 0x0000183e: 4311 .C ORRS r1,r1,r2 + 0x00001840: 4a4e NJ LDR r2,[pc,#312] ; [0x197c] = 0x10008340 + 0x00001842: 7a52 Rz LDRB r2,[r2,#9] + 0x00001844: 4311 .C ORRS r1,r1,r2 + 0x00001846: 0609 .. LSLS r1,r1,#24 + 0x00001848: 4308 .C ORRS r0,r0,r1 + 0x0000184a: b2c6 .. UXTB r6,r0 + 0x0000184c: 4629 )F MOV r1,r5 + 0x0000184e: 3920 9 SUBS r1,r1,#0x20 + 0x00001850: 2001 . MOVS r0,#1 + 0x00001852: 4088 .@ LSLS r0,r0,r1 + 0x00001854: 4330 0C ORRS r0,r0,r6 + 0x00001856: b2c6 .. UXTB r6,r0 + 0x00001858: bf00 .. NOP + 0x0000185a: 4849 IH LDR r0,[pc,#292] ; [0x1980] = 0x10008040 + 0x0000185c: 7386 .s STRB r6,[r0,#0xe] + 0x0000185e: 7386 .s STRB r6,[r0,#0xe] + 0x00001860: bf00 .. NOP + 0x00001862: bf00 .. NOP + 0x00001864: 2008 . MOVS r0,#8 + 0x00001866: 4946 FI LDR r1,[pc,#280] ; [0x1980] = 0x10008040 + 0x00001868: 3940 @9 SUBS r1,r1,#0x40 + 0x0000186a: 7648 Hv STRB r0,[r1,#0x19] + 0x0000186c: bf00 .. NOP + 0x0000186e: 2064 d MOVS r0,#0x64 + 0x00001870: f001fa5d ..]. BL whileDelay ; 0x2d2e + 0x00001874: bd70 p. POP {r4-r6,pc} GPIO_Clear_High_Interrupt - 0x0000196a: b570 p. PUSH {r4-r6,lr} - 0x0000196c: 4605 .F MOV r5,r0 - 0x0000196e: 2400 .$ MOVS r4,#0 - 0x00001970: 2600 .& MOVS r6,#0 - 0x00001972: 2080 . MOVS r0,#0x80 - 0x00001974: 4028 (@ ANDS r0,r0,r5 - 0x00001976: 2800 .( CMP r0,#0 - 0x00001978: d07e ~. BEQ 0x1a78 ; GPIO_Clear_High_Interrupt + 270 - 0x0000197a: 2180 .! MOVS r1,#0x80 - 0x0000197c: 4628 (F MOV r0,r5 - 0x0000197e: 4388 .C BICS r0,r0,r1 - 0x00001980: 4605 .F MOV r5,r0 - 0x00001982: 2d1f .- CMP r5,#0x1f - 0x00001984: dc55 U. BGT 0x1a32 ; GPIO_Clear_High_Interrupt + 200 - 0x00001986: 4838 8H LDR r0,[pc,#224] ; [0x1a68] = 0x10004fe0 - 0x00001988: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x0000198a: 2000 . MOVS r0,#0 - 0x0000198c: 4938 8I LDR r1,[pc,#224] ; [0x1a70] = 0x10008340 - 0x0000198e: 79c9 .y LDRB r1,[r1,#7] - 0x00001990: 4300 .C ORRS r0,r0,r0 - 0x00001992: 4937 7I LDR r1,[pc,#220] ; [0x1a70] = 0x10008340 - 0x00001994: 79c9 .y LDRB r1,[r1,#7] - 0x00001996: 4308 .C ORRS r0,r0,r1 - 0x00001998: 4933 3I LDR r1,[pc,#204] ; [0x1a68] = 0x10004fe0 - 0x0000199a: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x0000199c: 2100 .! MOVS r1,#0 - 0x0000199e: 4a34 4J LDR r2,[pc,#208] ; [0x1a70] = 0x10008340 - 0x000019a0: 7a12 .z LDRB r2,[r2,#8] - 0x000019a2: 4309 .C ORRS r1,r1,r1 - 0x000019a4: 4a32 2J LDR r2,[pc,#200] ; [0x1a70] = 0x10008340 - 0x000019a6: 7a12 .z LDRB r2,[r2,#8] - 0x000019a8: 4311 .C ORRS r1,r1,r2 - 0x000019aa: 0209 .. LSLS r1,r1,#8 - 0x000019ac: 4308 .C ORRS r0,r0,r1 - 0x000019ae: 492e .I LDR r1,[pc,#184] ; [0x1a68] = 0x10004fe0 - 0x000019b0: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x000019b2: 2100 .! MOVS r1,#0 - 0x000019b4: 4a2e .J LDR r2,[pc,#184] ; [0x1a70] = 0x10008340 - 0x000019b6: 7a52 Rz LDRB r2,[r2,#9] - 0x000019b8: 4309 .C ORRS r1,r1,r1 - 0x000019ba: 4a2d -J LDR r2,[pc,#180] ; [0x1a70] = 0x10008340 - 0x000019bc: 7a52 Rz LDRB r2,[r2,#9] - 0x000019be: 4311 .C ORRS r1,r1,r2 - 0x000019c0: 0409 .. LSLS r1,r1,#16 - 0x000019c2: 4308 .C ORRS r0,r0,r1 - 0x000019c4: 4928 (I LDR r1,[pc,#160] ; [0x1a68] = 0x10004fe0 - 0x000019c6: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x000019c8: 2100 .! MOVS r1,#0 - 0x000019ca: 4a29 )J LDR r2,[pc,#164] ; [0x1a70] = 0x10008340 - 0x000019cc: 7a92 .z LDRB r2,[r2,#0xa] - 0x000019ce: 4309 .C ORRS r1,r1,r1 - 0x000019d0: 4a27 'J LDR r2,[pc,#156] ; [0x1a70] = 0x10008340 - 0x000019d2: 7a92 .z LDRB r2,[r2,#0xa] - 0x000019d4: 4311 .C ORRS r1,r1,r2 - 0x000019d6: 0609 .. LSLS r1,r1,#24 - 0x000019d8: 4308 .C ORRS r0,r0,r1 - 0x000019da: 4604 .F MOV r4,r0 - 0x000019dc: 2001 . MOVS r0,#1 - 0x000019de: 40a8 .@ LSLS r0,r0,r5 - 0x000019e0: 4621 !F MOV r1,r4 - 0x000019e2: 4381 .C BICS r1,r1,r0 - 0x000019e4: 460c .F MOV r4,r1 - 0x000019e6: bf00 .. NOP - 0x000019e8: bf00 .. NOP - 0x000019ea: 4922 "I LDR r1,[pc,#136] ; [0x1a74] = 0x10008040 - 0x000019ec: 730c .s STRB r4,[r1,#0xc] - 0x000019ee: 730c .s STRB r4,[r1,#0xc] - 0x000019f0: bf00 .. NOP - 0x000019f2: bf00 .. NOP - 0x000019f4: 0420 . LSLS r0,r4,#16 - 0x000019f6: 0e00 .. LSRS r0,r0,#24 - 0x000019f8: 7348 Hs STRB r0,[r1,#0xd] - 0x000019fa: 0420 . LSLS r0,r4,#16 - 0x000019fc: 0e00 .. LSRS r0,r0,#24 - 0x000019fe: 7348 Hs STRB r0,[r1,#0xd] - 0x00001a00: bf00 .. NOP - 0x00001a02: bf00 .. NOP - 0x00001a04: 0220 . LSLS r0,r4,#8 - 0x00001a06: 0e00 .. LSRS r0,r0,#24 - 0x00001a08: 7388 .s STRB r0,[r1,#0xe] - 0x00001a0a: 0220 . LSLS r0,r4,#8 - 0x00001a0c: 0e00 .. LSRS r0,r0,#24 - 0x00001a0e: 7388 .s STRB r0,[r1,#0xe] - 0x00001a10: bf00 .. NOP - 0x00001a12: bf00 .. NOP - 0x00001a14: 0e20 . LSRS r0,r4,#24 - 0x00001a16: 73c8 .s STRB r0,[r1,#0xf] - 0x00001a18: 0e20 . LSRS r0,r4,#24 - 0x00001a1a: 73c8 .s STRB r0,[r1,#0xf] - 0x00001a1c: bf00 .. NOP - 0x00001a1e: bf00 .. NOP - 0x00001a20: bf00 .. NOP - 0x00001a22: 2008 . MOVS r0,#8 - 0x00001a24: 4913 .I LDR r1,[pc,#76] ; [0x1a74] = 0x10008040 - 0x00001a26: 3940 @9 SUBS r1,r1,#0x40 - 0x00001a28: 7148 Hq STRB r0,[r1,#5] - 0x00001a2a: bf00 .. NOP - 0x00001a2c: 2064 d MOVS r0,#0x64 - 0x00001a2e: f001f8e8 .... BL whileDelay ; 0x2c02 - 0x00001a32: 2d1f .- CMP r5,#0x1f - 0x00001a34: dd54 T. BLE 0x1ae0 ; GPIO_Clear_High_Interrupt + 374 - 0x00001a36: 2d28 (- CMP r5,#0x28 - 0x00001a38: da52 R. BGE 0x1ae0 ; GPIO_Clear_High_Interrupt + 374 - 0x00001a3a: bf00 .. NOP - 0x00001a3c: 2088 . MOVS r0,#0x88 - 0x00001a3e: 490d .I LDR r1,[pc,#52] ; [0x1a74] = 0x10008040 - 0x00001a40: 7308 .s STRB r0,[r1,#0xc] - 0x00001a42: 7308 .s STRB r0,[r1,#0xc] - 0x00001a44: bf00 .. NOP - 0x00001a46: 4808 .H LDR r0,[pc,#32] ; [0x1a68] = 0x10004fe0 - 0x00001a48: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00001a4a: 2000 . MOVS r0,#0 - 0x00001a4c: 4908 .I LDR r1,[pc,#32] ; [0x1a70] = 0x10008340 - 0x00001a4e: 7ac9 .z LDRB r1,[r1,#0xb] - 0x00001a50: 4300 .C ORRS r0,r0,r0 - 0x00001a52: 4907 .I LDR r1,[pc,#28] ; [0x1a70] = 0x10008340 - 0x00001a54: 7ac9 .z LDRB r1,[r1,#0xb] - 0x00001a56: 4308 .C ORRS r0,r0,r1 - 0x00001a58: 4903 .I LDR r1,[pc,#12] ; [0x1a68] = 0x10004fe0 - 0x00001a5a: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00001a5c: 4a04 .J LDR r2,[pc,#16] ; [0x1a70] = 0x10008340 - 0x00001a5e: 7b12 .{ LDRB r2,[r2,#0xc] - 0x00001a60: 4311 .C ORRS r1,r1,r2 - 0x00001a62: 4a03 .J LDR r2,[pc,#12] ; [0x1a70] = 0x10008340 - 0x00001a64: 7b12 .{ LDRB r2,[r2,#0xc] - 0x00001a66: e008 .. B 0x1a7a ; GPIO_Clear_High_Interrupt + 272 + 0x00001876: b570 p. PUSH {r4-r6,lr} + 0x00001878: 4605 .F MOV r5,r0 + 0x0000187a: 2400 .$ MOVS r4,#0 + 0x0000187c: 2600 .& MOVS r6,#0 + 0x0000187e: 2080 . MOVS r0,#0x80 + 0x00001880: 4028 (@ ANDS r0,r0,r5 + 0x00001882: 2800 .( CMP r0,#0 + 0x00001884: d07e ~. BEQ 0x1984 ; GPIO_Clear_High_Interrupt + 270 + 0x00001886: 2180 .! MOVS r1,#0x80 + 0x00001888: 4628 (F MOV r0,r5 + 0x0000188a: 4388 .C BICS r0,r0,r1 + 0x0000188c: 4605 .F MOV r5,r0 + 0x0000188e: 2d1f .- CMP r5,#0x1f + 0x00001890: dc55 U. BGT 0x193e ; GPIO_Clear_High_Interrupt + 200 + 0x00001892: 4838 8H LDR r0,[pc,#224] ; [0x1974] = 0x10004fe0 + 0x00001894: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x00001896: 2000 . MOVS r0,#0 + 0x00001898: 4938 8I LDR r1,[pc,#224] ; [0x197c] = 0x10008340 + 0x0000189a: 79c9 .y LDRB r1,[r1,#7] + 0x0000189c: 4300 .C ORRS r0,r0,r0 + 0x0000189e: 4937 7I LDR r1,[pc,#220] ; [0x197c] = 0x10008340 + 0x000018a0: 79c9 .y LDRB r1,[r1,#7] + 0x000018a2: 4308 .C ORRS r0,r0,r1 + 0x000018a4: 4933 3I LDR r1,[pc,#204] ; [0x1974] = 0x10004fe0 + 0x000018a6: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x000018a8: 2100 .! MOVS r1,#0 + 0x000018aa: 4a34 4J LDR r2,[pc,#208] ; [0x197c] = 0x10008340 + 0x000018ac: 7a12 .z LDRB r2,[r2,#8] + 0x000018ae: 4309 .C ORRS r1,r1,r1 + 0x000018b0: 4a32 2J LDR r2,[pc,#200] ; [0x197c] = 0x10008340 + 0x000018b2: 7a12 .z LDRB r2,[r2,#8] + 0x000018b4: 4311 .C ORRS r1,r1,r2 + 0x000018b6: 0209 .. LSLS r1,r1,#8 + 0x000018b8: 4308 .C ORRS r0,r0,r1 + 0x000018ba: 492e .I LDR r1,[pc,#184] ; [0x1974] = 0x10004fe0 + 0x000018bc: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x000018be: 2100 .! MOVS r1,#0 + 0x000018c0: 4a2e .J LDR r2,[pc,#184] ; [0x197c] = 0x10008340 + 0x000018c2: 7a52 Rz LDRB r2,[r2,#9] + 0x000018c4: 4309 .C ORRS r1,r1,r1 + 0x000018c6: 4a2d -J LDR r2,[pc,#180] ; [0x197c] = 0x10008340 + 0x000018c8: 7a52 Rz LDRB r2,[r2,#9] + 0x000018ca: 4311 .C ORRS r1,r1,r2 + 0x000018cc: 0409 .. LSLS r1,r1,#16 + 0x000018ce: 4308 .C ORRS r0,r0,r1 + 0x000018d0: 4928 (I LDR r1,[pc,#160] ; [0x1974] = 0x10004fe0 + 0x000018d2: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x000018d4: 2100 .! MOVS r1,#0 + 0x000018d6: 4a29 )J LDR r2,[pc,#164] ; [0x197c] = 0x10008340 + 0x000018d8: 7a92 .z LDRB r2,[r2,#0xa] + 0x000018da: 4309 .C ORRS r1,r1,r1 + 0x000018dc: 4a27 'J LDR r2,[pc,#156] ; [0x197c] = 0x10008340 + 0x000018de: 7a92 .z LDRB r2,[r2,#0xa] + 0x000018e0: 4311 .C ORRS r1,r1,r2 + 0x000018e2: 0609 .. LSLS r1,r1,#24 + 0x000018e4: 4308 .C ORRS r0,r0,r1 + 0x000018e6: 4604 .F MOV r4,r0 + 0x000018e8: 2001 . MOVS r0,#1 + 0x000018ea: 40a8 .@ LSLS r0,r0,r5 + 0x000018ec: 4621 !F MOV r1,r4 + 0x000018ee: 4381 .C BICS r1,r1,r0 + 0x000018f0: 460c .F MOV r4,r1 + 0x000018f2: bf00 .. NOP + 0x000018f4: bf00 .. NOP + 0x000018f6: 4922 "I LDR r1,[pc,#136] ; [0x1980] = 0x10008040 + 0x000018f8: 730c .s STRB r4,[r1,#0xc] + 0x000018fa: 730c .s STRB r4,[r1,#0xc] + 0x000018fc: bf00 .. NOP + 0x000018fe: bf00 .. NOP + 0x00001900: 0420 . LSLS r0,r4,#16 + 0x00001902: 0e00 .. LSRS r0,r0,#24 + 0x00001904: 7348 Hs STRB r0,[r1,#0xd] + 0x00001906: 0420 . LSLS r0,r4,#16 + 0x00001908: 0e00 .. LSRS r0,r0,#24 + 0x0000190a: 7348 Hs STRB r0,[r1,#0xd] + 0x0000190c: bf00 .. NOP + 0x0000190e: bf00 .. NOP + 0x00001910: 0220 . LSLS r0,r4,#8 + 0x00001912: 0e00 .. LSRS r0,r0,#24 + 0x00001914: 7388 .s STRB r0,[r1,#0xe] + 0x00001916: 0220 . LSLS r0,r4,#8 + 0x00001918: 0e00 .. LSRS r0,r0,#24 + 0x0000191a: 7388 .s STRB r0,[r1,#0xe] + 0x0000191c: bf00 .. NOP + 0x0000191e: bf00 .. NOP + 0x00001920: 0e20 . LSRS r0,r4,#24 + 0x00001922: 73c8 .s STRB r0,[r1,#0xf] + 0x00001924: 0e20 . LSRS r0,r4,#24 + 0x00001926: 73c8 .s STRB r0,[r1,#0xf] + 0x00001928: bf00 .. NOP + 0x0000192a: bf00 .. NOP + 0x0000192c: bf00 .. NOP + 0x0000192e: 2008 . MOVS r0,#8 + 0x00001930: 4913 .I LDR r1,[pc,#76] ; [0x1980] = 0x10008040 + 0x00001932: 3940 @9 SUBS r1,r1,#0x40 + 0x00001934: 7148 Hq STRB r0,[r1,#5] + 0x00001936: bf00 .. NOP + 0x00001938: 2064 d MOVS r0,#0x64 + 0x0000193a: f001f9f8 .... BL whileDelay ; 0x2d2e + 0x0000193e: 2d1f .- CMP r5,#0x1f + 0x00001940: dd54 T. BLE 0x19ec ; GPIO_Clear_High_Interrupt + 374 + 0x00001942: 2d28 (- CMP r5,#0x28 + 0x00001944: da52 R. BGE 0x19ec ; GPIO_Clear_High_Interrupt + 374 + 0x00001946: bf00 .. NOP + 0x00001948: 2088 . MOVS r0,#0x88 + 0x0000194a: 490d .I LDR r1,[pc,#52] ; [0x1980] = 0x10008040 + 0x0000194c: 7308 .s STRB r0,[r1,#0xc] + 0x0000194e: 7308 .s STRB r0,[r1,#0xc] + 0x00001950: bf00 .. NOP + 0x00001952: 4808 .H LDR r0,[pc,#32] ; [0x1974] = 0x10004fe0 + 0x00001954: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x00001956: 2000 . MOVS r0,#0 + 0x00001958: 4908 .I LDR r1,[pc,#32] ; [0x197c] = 0x10008340 + 0x0000195a: 7ac9 .z LDRB r1,[r1,#0xb] + 0x0000195c: 4300 .C ORRS r0,r0,r0 + 0x0000195e: 4907 .I LDR r1,[pc,#28] ; [0x197c] = 0x10008340 + 0x00001960: 7ac9 .z LDRB r1,[r1,#0xb] + 0x00001962: 4308 .C ORRS r0,r0,r1 + 0x00001964: 4903 .I LDR r1,[pc,#12] ; [0x1974] = 0x10004fe0 + 0x00001966: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x00001968: 4a04 .J LDR r2,[pc,#16] ; [0x197c] = 0x10008340 + 0x0000196a: 7b12 .{ LDRB r2,[r2,#0xc] + 0x0000196c: 4311 .C ORRS r1,r1,r2 + 0x0000196e: 4a03 .J LDR r2,[pc,#12] ; [0x197c] = 0x10008340 + 0x00001970: 7b12 .{ LDRB r2,[r2,#0xc] + 0x00001972: e008 .. B 0x1986 ; GPIO_Clear_High_Interrupt + 272 $d - 0x00001a68: 10004fe0 .O.. DCD 268455904 - 0x00001a6c: 00008080 .... DCD 32896 - 0x00001a70: 10008340 @... DCD 268469056 - 0x00001a74: 10008040 @... DCD 268468288 + 0x00001974: 10004fe0 .O.. DCD 268455904 + 0x00001978: 00008080 .... DCD 32896 + 0x0000197c: 10008340 @... DCD 268469056 + 0x00001980: 10008040 @... DCD 268468288 $t - 0x00001a78: e032 2. B 0x1ae0 ; GPIO_Clear_High_Interrupt + 374 - 0x00001a7a: 4311 .C ORRS r1,r1,r2 - 0x00001a7c: 0209 .. LSLS r1,r1,#8 - 0x00001a7e: 4308 .C ORRS r0,r0,r1 - 0x00001a80: 4999 .I LDR r1,[pc,#612] ; [0x1ce8] = 0x10004fe0 - 0x00001a82: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00001a84: 4a99 .J LDR r2,[pc,#612] ; [0x1cec] = 0x10008340 - 0x00001a86: 7b52 R{ LDRB r2,[r2,#0xd] - 0x00001a88: 4311 .C ORRS r1,r1,r2 - 0x00001a8a: 4a98 .J LDR r2,[pc,#608] ; [0x1cec] = 0x10008340 - 0x00001a8c: 7b52 R{ LDRB r2,[r2,#0xd] - 0x00001a8e: 4311 .C ORRS r1,r1,r2 - 0x00001a90: 0409 .. LSLS r1,r1,#16 - 0x00001a92: 4308 .C ORRS r0,r0,r1 - 0x00001a94: 4994 .I LDR r1,[pc,#592] ; [0x1ce8] = 0x10004fe0 - 0x00001a96: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00001a98: 4a94 .J LDR r2,[pc,#592] ; [0x1cec] = 0x10008340 - 0x00001a9a: 7b92 .{ LDRB r2,[r2,#0xe] - 0x00001a9c: 4311 .C ORRS r1,r1,r2 - 0x00001a9e: 4a93 .J LDR r2,[pc,#588] ; [0x1cec] = 0x10008340 - 0x00001aa0: 7b92 .{ LDRB r2,[r2,#0xe] - 0x00001aa2: 4311 .C ORRS r1,r1,r2 - 0x00001aa4: 0609 .. LSLS r1,r1,#24 - 0x00001aa6: 4308 .C ORRS r0,r0,r1 - 0x00001aa8: b2c6 .. UXTB r6,r0 - 0x00001aaa: 4629 )F MOV r1,r5 - 0x00001aac: 3920 9 SUBS r1,r1,#0x20 - 0x00001aae: 2001 . MOVS r0,#1 - 0x00001ab0: 4088 .@ LSLS r0,r0,r1 - 0x00001ab2: 4631 1F MOV r1,r6 - 0x00001ab4: 4381 .C BICS r1,r1,r0 - 0x00001ab6: 460e .F MOV r6,r1 - 0x00001ab8: bf00 .. NOP - 0x00001aba: 488d .H LDR r0,[pc,#564] ; [0x1cf0] = 0x10008040 - 0x00001abc: 7346 Fs STRB r6,[r0,#0xd] - 0x00001abe: 7346 Fs STRB r6,[r0,#0xd] - 0x00001ac0: bf00 .. NOP - 0x00001ac2: bf00 .. NOP - 0x00001ac4: 2000 . MOVS r0,#0 - 0x00001ac6: 498a .I LDR r1,[pc,#552] ; [0x1cf0] = 0x10008040 - 0x00001ac8: 7388 .s STRB r0,[r1,#0xe] - 0x00001aca: 7388 .s STRB r0,[r1,#0xe] - 0x00001acc: bf00 .. NOP - 0x00001ace: bf00 .. NOP - 0x00001ad0: 2008 . MOVS r0,#8 - 0x00001ad2: 4987 .I LDR r1,[pc,#540] ; [0x1cf0] = 0x10008040 - 0x00001ad4: 3940 @9 SUBS r1,r1,#0x40 - 0x00001ad6: 7648 Hv STRB r0,[r1,#0x19] - 0x00001ad8: bf00 .. NOP - 0x00001ada: 2064 d MOVS r0,#0x64 - 0x00001adc: f001f891 .... BL whileDelay ; 0x2c02 - 0x00001ae0: bd70 p. POP {r4-r6,pc} + 0x00001984: e032 2. B 0x19ec ; GPIO_Clear_High_Interrupt + 374 + 0x00001986: 4311 .C ORRS r1,r1,r2 + 0x00001988: 0209 .. LSLS r1,r1,#8 + 0x0000198a: 4308 .C ORRS r0,r0,r1 + 0x0000198c: 4999 .I LDR r1,[pc,#612] ; [0x1bf4] = 0x10004fe0 + 0x0000198e: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x00001990: 4a99 .J LDR r2,[pc,#612] ; [0x1bf8] = 0x10008340 + 0x00001992: 7b52 R{ LDRB r2,[r2,#0xd] + 0x00001994: 4311 .C ORRS r1,r1,r2 + 0x00001996: 4a98 .J LDR r2,[pc,#608] ; [0x1bf8] = 0x10008340 + 0x00001998: 7b52 R{ LDRB r2,[r2,#0xd] + 0x0000199a: 4311 .C ORRS r1,r1,r2 + 0x0000199c: 0409 .. LSLS r1,r1,#16 + 0x0000199e: 4308 .C ORRS r0,r0,r1 + 0x000019a0: 4994 .I LDR r1,[pc,#592] ; [0x1bf4] = 0x10004fe0 + 0x000019a2: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x000019a4: 4a94 .J LDR r2,[pc,#592] ; [0x1bf8] = 0x10008340 + 0x000019a6: 7b92 .{ LDRB r2,[r2,#0xe] + 0x000019a8: 4311 .C ORRS r1,r1,r2 + 0x000019aa: 4a93 .J LDR r2,[pc,#588] ; [0x1bf8] = 0x10008340 + 0x000019ac: 7b92 .{ LDRB r2,[r2,#0xe] + 0x000019ae: 4311 .C ORRS r1,r1,r2 + 0x000019b0: 0609 .. LSLS r1,r1,#24 + 0x000019b2: 4308 .C ORRS r0,r0,r1 + 0x000019b4: b2c6 .. UXTB r6,r0 + 0x000019b6: 4629 )F MOV r1,r5 + 0x000019b8: 3920 9 SUBS r1,r1,#0x20 + 0x000019ba: 2001 . MOVS r0,#1 + 0x000019bc: 4088 .@ LSLS r0,r0,r1 + 0x000019be: 4631 1F MOV r1,r6 + 0x000019c0: 4381 .C BICS r1,r1,r0 + 0x000019c2: 460e .F MOV r6,r1 + 0x000019c4: bf00 .. NOP + 0x000019c6: 488d .H LDR r0,[pc,#564] ; [0x1bfc] = 0x10008040 + 0x000019c8: 7346 Fs STRB r6,[r0,#0xd] + 0x000019ca: 7346 Fs STRB r6,[r0,#0xd] + 0x000019cc: bf00 .. NOP + 0x000019ce: bf00 .. NOP + 0x000019d0: 2000 . MOVS r0,#0 + 0x000019d2: 498a .I LDR r1,[pc,#552] ; [0x1bfc] = 0x10008040 + 0x000019d4: 7388 .s STRB r0,[r1,#0xe] + 0x000019d6: 7388 .s STRB r0,[r1,#0xe] + 0x000019d8: bf00 .. NOP + 0x000019da: bf00 .. NOP + 0x000019dc: 2008 . MOVS r0,#8 + 0x000019de: 4987 .I LDR r1,[pc,#540] ; [0x1bfc] = 0x10008040 + 0x000019e0: 3940 @9 SUBS r1,r1,#0x40 + 0x000019e2: 7648 Hv STRB r0,[r1,#0x19] + 0x000019e4: bf00 .. NOP + 0x000019e6: 2064 d MOVS r0,#0x64 + 0x000019e8: f001f9a1 .... BL whileDelay ; 0x2d2e + 0x000019ec: bd70 p. POP {r4-r6,pc} GPIO_Clear_Low_Interrupt - 0x00001ae2: b570 p. PUSH {r4-r6,lr} - 0x00001ae4: 4605 .F MOV r5,r0 - 0x00001ae6: 2400 .$ MOVS r4,#0 - 0x00001ae8: 2600 .& MOVS r6,#0 - 0x00001aea: 2080 . MOVS r0,#0x80 - 0x00001aec: 4028 (@ ANDS r0,r0,r5 - 0x00001aee: 2800 .( CMP r0,#0 - 0x00001af0: d07e ~. BEQ 0x1bf0 ; GPIO_Clear_Low_Interrupt + 270 - 0x00001af2: 2180 .! MOVS r1,#0x80 - 0x00001af4: 4628 (F MOV r0,r5 - 0x00001af6: 4388 .C BICS r0,r0,r1 - 0x00001af8: 4605 .F MOV r5,r0 - 0x00001afa: 2d1f .- CMP r5,#0x1f - 0x00001afc: dc55 U. BGT 0x1baa ; GPIO_Clear_Low_Interrupt + 200 - 0x00001afe: 487a zH LDR r0,[pc,#488] ; [0x1ce8] = 0x10004fe0 - 0x00001b00: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00001b02: 2000 . MOVS r0,#0 - 0x00001b04: 4979 yI LDR r1,[pc,#484] ; [0x1cec] = 0x10008340 - 0x00001b06: 7889 .x LDRB r1,[r1,#2] - 0x00001b08: 4300 .C ORRS r0,r0,r0 - 0x00001b0a: 4978 xI LDR r1,[pc,#480] ; [0x1cec] = 0x10008340 - 0x00001b0c: 7889 .x LDRB r1,[r1,#2] - 0x00001b0e: 4308 .C ORRS r0,r0,r1 - 0x00001b10: 4975 uI LDR r1,[pc,#468] ; [0x1ce8] = 0x10004fe0 - 0x00001b12: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00001b14: 2100 .! MOVS r1,#0 - 0x00001b16: 4a75 uJ LDR r2,[pc,#468] ; [0x1cec] = 0x10008340 - 0x00001b18: 78d2 .x LDRB r2,[r2,#3] - 0x00001b1a: 4309 .C ORRS r1,r1,r1 - 0x00001b1c: 4a73 sJ LDR r2,[pc,#460] ; [0x1cec] = 0x10008340 - 0x00001b1e: 78d2 .x LDRB r2,[r2,#3] + 0x000019ee: b570 p. PUSH {r4-r6,lr} + 0x000019f0: 4605 .F MOV r5,r0 + 0x000019f2: 2400 .$ MOVS r4,#0 + 0x000019f4: 2600 .& MOVS r6,#0 + 0x000019f6: 2080 . MOVS r0,#0x80 + 0x000019f8: 4028 (@ ANDS r0,r0,r5 + 0x000019fa: 2800 .( CMP r0,#0 + 0x000019fc: d07e ~. BEQ 0x1afc ; GPIO_Clear_Low_Interrupt + 270 + 0x000019fe: 2180 .! MOVS r1,#0x80 + 0x00001a00: 4628 (F MOV r0,r5 + 0x00001a02: 4388 .C BICS r0,r0,r1 + 0x00001a04: 4605 .F MOV r5,r0 + 0x00001a06: 2d1f .- CMP r5,#0x1f + 0x00001a08: dc55 U. BGT 0x1ab6 ; GPIO_Clear_Low_Interrupt + 200 + 0x00001a0a: 487a zH LDR r0,[pc,#488] ; [0x1bf4] = 0x10004fe0 + 0x00001a0c: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x00001a0e: 2000 . MOVS r0,#0 + 0x00001a10: 4979 yI LDR r1,[pc,#484] ; [0x1bf8] = 0x10008340 + 0x00001a12: 7889 .x LDRB r1,[r1,#2] + 0x00001a14: 4300 .C ORRS r0,r0,r0 + 0x00001a16: 4978 xI LDR r1,[pc,#480] ; [0x1bf8] = 0x10008340 + 0x00001a18: 7889 .x LDRB r1,[r1,#2] + 0x00001a1a: 4308 .C ORRS r0,r0,r1 + 0x00001a1c: 4975 uI LDR r1,[pc,#468] ; [0x1bf4] = 0x10004fe0 + 0x00001a1e: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x00001a20: 2100 .! MOVS r1,#0 + 0x00001a22: 4a75 uJ LDR r2,[pc,#468] ; [0x1bf8] = 0x10008340 + 0x00001a24: 78d2 .x LDRB r2,[r2,#3] + 0x00001a26: 4309 .C ORRS r1,r1,r1 + 0x00001a28: 4a73 sJ LDR r2,[pc,#460] ; [0x1bf8] = 0x10008340 + 0x00001a2a: 78d2 .x LDRB r2,[r2,#3] + 0x00001a2c: 4311 .C ORRS r1,r1,r2 + 0x00001a2e: 0209 .. LSLS r1,r1,#8 + 0x00001a30: 4308 .C ORRS r0,r0,r1 + 0x00001a32: 4970 pI LDR r1,[pc,#448] ; [0x1bf4] = 0x10004fe0 + 0x00001a34: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x00001a36: 2100 .! MOVS r1,#0 + 0x00001a38: 4a6f oJ LDR r2,[pc,#444] ; [0x1bf8] = 0x10008340 + 0x00001a3a: 7912 .y LDRB r2,[r2,#4] + 0x00001a3c: 4309 .C ORRS r1,r1,r1 + 0x00001a3e: 4a6e nJ LDR r2,[pc,#440] ; [0x1bf8] = 0x10008340 + 0x00001a40: 7912 .y LDRB r2,[r2,#4] + 0x00001a42: 4311 .C ORRS r1,r1,r2 + 0x00001a44: 0409 .. LSLS r1,r1,#16 + 0x00001a46: 4308 .C ORRS r0,r0,r1 + 0x00001a48: 496a jI LDR r1,[pc,#424] ; [0x1bf4] = 0x10004fe0 + 0x00001a4a: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x00001a4c: 2100 .! MOVS r1,#0 + 0x00001a4e: 4a6a jJ LDR r2,[pc,#424] ; [0x1bf8] = 0x10008340 + 0x00001a50: 7952 Ry LDRB r2,[r2,#5] + 0x00001a52: 4309 .C ORRS r1,r1,r1 + 0x00001a54: 4a68 hJ LDR r2,[pc,#416] ; [0x1bf8] = 0x10008340 + 0x00001a56: 7952 Ry LDRB r2,[r2,#5] + 0x00001a58: 4311 .C ORRS r1,r1,r2 + 0x00001a5a: 0609 .. LSLS r1,r1,#24 + 0x00001a5c: 4308 .C ORRS r0,r0,r1 + 0x00001a5e: 4604 .F MOV r4,r0 + 0x00001a60: 2001 . MOVS r0,#1 + 0x00001a62: 40a8 .@ LSLS r0,r0,r5 + 0x00001a64: 4621 !F MOV r1,r4 + 0x00001a66: 4381 .C BICS r1,r1,r0 + 0x00001a68: 460c .F MOV r4,r1 + 0x00001a6a: bf00 .. NOP + 0x00001a6c: bf00 .. NOP + 0x00001a6e: 4963 cI LDR r1,[pc,#396] ; [0x1bfc] = 0x10008040 + 0x00001a70: 730c .s STRB r4,[r1,#0xc] + 0x00001a72: 730c .s STRB r4,[r1,#0xc] + 0x00001a74: bf00 .. NOP + 0x00001a76: bf00 .. NOP + 0x00001a78: 0420 . LSLS r0,r4,#16 + 0x00001a7a: 0e00 .. LSRS r0,r0,#24 + 0x00001a7c: 7348 Hs STRB r0,[r1,#0xd] + 0x00001a7e: 0420 . LSLS r0,r4,#16 + 0x00001a80: 0e00 .. LSRS r0,r0,#24 + 0x00001a82: 7348 Hs STRB r0,[r1,#0xd] + 0x00001a84: bf00 .. NOP + 0x00001a86: bf00 .. NOP + 0x00001a88: 0220 . LSLS r0,r4,#8 + 0x00001a8a: 0e00 .. LSRS r0,r0,#24 + 0x00001a8c: 7388 .s STRB r0,[r1,#0xe] + 0x00001a8e: 0220 . LSLS r0,r4,#8 + 0x00001a90: 0e00 .. LSRS r0,r0,#24 + 0x00001a92: 7388 .s STRB r0,[r1,#0xe] + 0x00001a94: bf00 .. NOP + 0x00001a96: bf00 .. NOP + 0x00001a98: 0e20 . LSRS r0,r4,#24 + 0x00001a9a: 73c8 .s STRB r0,[r1,#0xf] + 0x00001a9c: 0e20 . LSRS r0,r4,#24 + 0x00001a9e: 73c8 .s STRB r0,[r1,#0xf] + 0x00001aa0: bf00 .. NOP + 0x00001aa2: bf00 .. NOP + 0x00001aa4: bf00 .. NOP + 0x00001aa6: 2004 . MOVS r0,#4 + 0x00001aa8: 4954 TI LDR r1,[pc,#336] ; [0x1bfc] = 0x10008040 + 0x00001aaa: 3940 @9 SUBS r1,r1,#0x40 + 0x00001aac: 7148 Hq STRB r0,[r1,#5] + 0x00001aae: bf00 .. NOP + 0x00001ab0: 2064 d MOVS r0,#0x64 + 0x00001ab2: f001f93c ..<. BL whileDelay ; 0x2d2e + 0x00001ab6: 2d1f .- CMP r5,#0x1f + 0x00001ab8: dd4b K. BLE 0x1b52 ; GPIO_Clear_Low_Interrupt + 356 + 0x00001aba: 2d28 (- CMP r5,#0x28 + 0x00001abc: da49 I. BGE 0x1b52 ; GPIO_Clear_Low_Interrupt + 356 + 0x00001abe: bf00 .. NOP + 0x00001ac0: 2088 . MOVS r0,#0x88 + 0x00001ac2: 494e NI LDR r1,[pc,#312] ; [0x1bfc] = 0x10008040 + 0x00001ac4: 7308 .s STRB r0,[r1,#0xc] + 0x00001ac6: 7308 .s STRB r0,[r1,#0xc] + 0x00001ac8: bf00 .. NOP + 0x00001aca: bf00 .. NOP + 0x00001acc: 2000 . MOVS r0,#0 + 0x00001ace: 7348 Hs STRB r0,[r1,#0xd] + 0x00001ad0: 7348 Hs STRB r0,[r1,#0xd] + 0x00001ad2: bf00 .. NOP + 0x00001ad4: 4847 GH LDR r0,[pc,#284] ; [0x1bf4] = 0x10004fe0 + 0x00001ad6: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x00001ad8: 2000 . MOVS r0,#0 + 0x00001ada: 4947 GI LDR r1,[pc,#284] ; [0x1bf8] = 0x10008340 + 0x00001adc: 7989 .y LDRB r1,[r1,#6] + 0x00001ade: 4300 .C ORRS r0,r0,r0 + 0x00001ae0: 4945 EI LDR r1,[pc,#276] ; [0x1bf8] = 0x10008340 + 0x00001ae2: 7989 .y LDRB r1,[r1,#6] + 0x00001ae4: 4308 .C ORRS r0,r0,r1 + 0x00001ae6: 4943 CI LDR r1,[pc,#268] ; [0x1bf4] = 0x10004fe0 + 0x00001ae8: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x00001aea: 4a43 CJ LDR r2,[pc,#268] ; [0x1bf8] = 0x10008340 + 0x00001aec: 79d2 .y LDRB r2,[r2,#7] + 0x00001aee: 4311 .C ORRS r1,r1,r2 + 0x00001af0: 4a41 AJ LDR r2,[pc,#260] ; [0x1bf8] = 0x10008340 + 0x00001af2: 79d2 .y LDRB r2,[r2,#7] + 0x00001af4: 4311 .C ORRS r1,r1,r2 + 0x00001af6: 0209 .. LSLS r1,r1,#8 + 0x00001af8: 4308 .C ORRS r0,r0,r1 + 0x00001afa: e000 .. B 0x1afe ; GPIO_Clear_Low_Interrupt + 272 + 0x00001afc: e029 ). B 0x1b52 ; GPIO_Clear_Low_Interrupt + 356 + 0x00001afe: 493d =I LDR r1,[pc,#244] ; [0x1bf4] = 0x10004fe0 + 0x00001b00: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x00001b02: 4a3d =J LDR r2,[pc,#244] ; [0x1bf8] = 0x10008340 + 0x00001b04: 7a12 .z LDRB r2,[r2,#8] + 0x00001b06: 4311 .C ORRS r1,r1,r2 + 0x00001b08: 4a3b ;J LDR r2,[pc,#236] ; [0x1bf8] = 0x10008340 + 0x00001b0a: 7a12 .z LDRB r2,[r2,#8] + 0x00001b0c: 4311 .C ORRS r1,r1,r2 + 0x00001b0e: 0409 .. LSLS r1,r1,#16 + 0x00001b10: 4308 .C ORRS r0,r0,r1 + 0x00001b12: 4938 8I LDR r1,[pc,#224] ; [0x1bf4] = 0x10004fe0 + 0x00001b14: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x00001b16: 4a38 8J LDR r2,[pc,#224] ; [0x1bf8] = 0x10008340 + 0x00001b18: 7a52 Rz LDRB r2,[r2,#9] + 0x00001b1a: 4311 .C ORRS r1,r1,r2 + 0x00001b1c: 4a36 6J LDR r2,[pc,#216] ; [0x1bf8] = 0x10008340 + 0x00001b1e: 7a52 Rz LDRB r2,[r2,#9] 0x00001b20: 4311 .C ORRS r1,r1,r2 - 0x00001b22: 0209 .. LSLS r1,r1,#8 + 0x00001b22: 0609 .. LSLS r1,r1,#24 0x00001b24: 4308 .C ORRS r0,r0,r1 - 0x00001b26: 4970 pI LDR r1,[pc,#448] ; [0x1ce8] = 0x10004fe0 - 0x00001b28: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00001b2a: 2100 .! MOVS r1,#0 - 0x00001b2c: 4a6f oJ LDR r2,[pc,#444] ; [0x1cec] = 0x10008340 - 0x00001b2e: 7912 .y LDRB r2,[r2,#4] - 0x00001b30: 4309 .C ORRS r1,r1,r1 - 0x00001b32: 4a6e nJ LDR r2,[pc,#440] ; [0x1cec] = 0x10008340 - 0x00001b34: 7912 .y LDRB r2,[r2,#4] - 0x00001b36: 4311 .C ORRS r1,r1,r2 - 0x00001b38: 0409 .. LSLS r1,r1,#16 - 0x00001b3a: 4308 .C ORRS r0,r0,r1 - 0x00001b3c: 496a jI LDR r1,[pc,#424] ; [0x1ce8] = 0x10004fe0 - 0x00001b3e: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00001b40: 2100 .! MOVS r1,#0 - 0x00001b42: 4a6a jJ LDR r2,[pc,#424] ; [0x1cec] = 0x10008340 - 0x00001b44: 7952 Ry LDRB r2,[r2,#5] - 0x00001b46: 4309 .C ORRS r1,r1,r1 - 0x00001b48: 4a68 hJ LDR r2,[pc,#416] ; [0x1cec] = 0x10008340 - 0x00001b4a: 7952 Ry LDRB r2,[r2,#5] - 0x00001b4c: 4311 .C ORRS r1,r1,r2 - 0x00001b4e: 0609 .. LSLS r1,r1,#24 - 0x00001b50: 4308 .C ORRS r0,r0,r1 - 0x00001b52: 4604 .F MOV r4,r0 - 0x00001b54: 2001 . MOVS r0,#1 - 0x00001b56: 40a8 .@ LSLS r0,r0,r5 - 0x00001b58: 4621 !F MOV r1,r4 - 0x00001b5a: 4381 .C BICS r1,r1,r0 - 0x00001b5c: 460c .F MOV r4,r1 - 0x00001b5e: bf00 .. NOP - 0x00001b60: bf00 .. NOP - 0x00001b62: 4963 cI LDR r1,[pc,#396] ; [0x1cf0] = 0x10008040 - 0x00001b64: 730c .s STRB r4,[r1,#0xc] - 0x00001b66: 730c .s STRB r4,[r1,#0xc] - 0x00001b68: bf00 .. NOP - 0x00001b6a: bf00 .. NOP + 0x00001b26: b2c6 .. UXTB r6,r0 + 0x00001b28: 4629 )F MOV r1,r5 + 0x00001b2a: 3920 9 SUBS r1,r1,#0x20 + 0x00001b2c: 2001 . MOVS r0,#1 + 0x00001b2e: 4088 .@ LSLS r0,r0,r1 + 0x00001b30: 4631 1F MOV r1,r6 + 0x00001b32: 4381 .C BICS r1,r1,r0 + 0x00001b34: 460e .F MOV r6,r1 + 0x00001b36: bf00 .. NOP + 0x00001b38: 4830 0H LDR r0,[pc,#192] ; [0x1bfc] = 0x10008040 + 0x00001b3a: 7386 .s STRB r6,[r0,#0xe] + 0x00001b3c: 7386 .s STRB r6,[r0,#0xe] + 0x00001b3e: bf00 .. NOP + 0x00001b40: bf00 .. NOP + 0x00001b42: 2008 . MOVS r0,#8 + 0x00001b44: 492d -I LDR r1,[pc,#180] ; [0x1bfc] = 0x10008040 + 0x00001b46: 3940 @9 SUBS r1,r1,#0x40 + 0x00001b48: 7648 Hv STRB r0,[r1,#0x19] + 0x00001b4a: bf00 .. NOP + 0x00001b4c: 2064 d MOVS r0,#0x64 + 0x00001b4e: f001f8ee .... BL whileDelay ; 0x2d2e + 0x00001b52: bd70 p. POP {r4-r6,pc} + GPIO_Clear_All_Interrupt + 0x00001b54: b510 .. PUSH {r4,lr} + 0x00001b56: 2400 .$ MOVS r4,#0 + 0x00001b58: bf00 .. NOP + 0x00001b5a: bf00 .. NOP + 0x00001b5c: 4927 'I LDR r1,[pc,#156] ; [0x1bfc] = 0x10008040 + 0x00001b5e: 730c .s STRB r4,[r1,#0xc] + 0x00001b60: 730c .s STRB r4,[r1,#0xc] + 0x00001b62: bf00 .. NOP + 0x00001b64: bf00 .. NOP + 0x00001b66: 0420 . LSLS r0,r4,#16 + 0x00001b68: 0e00 .. LSRS r0,r0,#24 + 0x00001b6a: 7348 Hs STRB r0,[r1,#0xd] 0x00001b6c: 0420 . LSLS r0,r4,#16 0x00001b6e: 0e00 .. LSRS r0,r0,#24 0x00001b70: 7348 Hs STRB r0,[r1,#0xd] - 0x00001b72: 0420 . LSLS r0,r4,#16 - 0x00001b74: 0e00 .. LSRS r0,r0,#24 - 0x00001b76: 7348 Hs STRB r0,[r1,#0xd] - 0x00001b78: bf00 .. NOP - 0x00001b7a: bf00 .. NOP + 0x00001b72: bf00 .. NOP + 0x00001b74: bf00 .. NOP + 0x00001b76: 0220 . LSLS r0,r4,#8 + 0x00001b78: 0e00 .. LSRS r0,r0,#24 + 0x00001b7a: 7388 .s STRB r0,[r1,#0xe] 0x00001b7c: 0220 . LSLS r0,r4,#8 0x00001b7e: 0e00 .. LSRS r0,r0,#24 0x00001b80: 7388 .s STRB r0,[r1,#0xe] - 0x00001b82: 0220 . LSLS r0,r4,#8 - 0x00001b84: 0e00 .. LSRS r0,r0,#24 - 0x00001b86: 7388 .s STRB r0,[r1,#0xe] - 0x00001b88: bf00 .. NOP - 0x00001b8a: bf00 .. NOP - 0x00001b8c: 0e20 . LSRS r0,r4,#24 - 0x00001b8e: 73c8 .s STRB r0,[r1,#0xf] - 0x00001b90: 0e20 . LSRS r0,r4,#24 - 0x00001b92: 73c8 .s STRB r0,[r1,#0xf] - 0x00001b94: bf00 .. NOP - 0x00001b96: bf00 .. NOP - 0x00001b98: bf00 .. NOP - 0x00001b9a: 2004 . MOVS r0,#4 - 0x00001b9c: 4954 TI LDR r1,[pc,#336] ; [0x1cf0] = 0x10008040 - 0x00001b9e: 3940 @9 SUBS r1,r1,#0x40 - 0x00001ba0: 7148 Hq STRB r0,[r1,#5] - 0x00001ba2: bf00 .. NOP - 0x00001ba4: 2064 d MOVS r0,#0x64 - 0x00001ba6: f001f82c ..,. BL whileDelay ; 0x2c02 - 0x00001baa: 2d1f .- CMP r5,#0x1f - 0x00001bac: dd4b K. BLE 0x1c46 ; GPIO_Clear_Low_Interrupt + 356 - 0x00001bae: 2d28 (- CMP r5,#0x28 - 0x00001bb0: da49 I. BGE 0x1c46 ; GPIO_Clear_Low_Interrupt + 356 - 0x00001bb2: bf00 .. NOP - 0x00001bb4: 2088 . MOVS r0,#0x88 - 0x00001bb6: 494e NI LDR r1,[pc,#312] ; [0x1cf0] = 0x10008040 - 0x00001bb8: 7308 .s STRB r0,[r1,#0xc] - 0x00001bba: 7308 .s STRB r0,[r1,#0xc] - 0x00001bbc: bf00 .. NOP - 0x00001bbe: bf00 .. NOP - 0x00001bc0: 2000 . MOVS r0,#0 - 0x00001bc2: 7348 Hs STRB r0,[r1,#0xd] - 0x00001bc4: 7348 Hs STRB r0,[r1,#0xd] - 0x00001bc6: bf00 .. NOP - 0x00001bc8: 4847 GH LDR r0,[pc,#284] ; [0x1ce8] = 0x10004fe0 - 0x00001bca: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00001bcc: 2000 . MOVS r0,#0 - 0x00001bce: 4947 GI LDR r1,[pc,#284] ; [0x1cec] = 0x10008340 - 0x00001bd0: 7989 .y LDRB r1,[r1,#6] - 0x00001bd2: 4300 .C ORRS r0,r0,r0 - 0x00001bd4: 4945 EI LDR r1,[pc,#276] ; [0x1cec] = 0x10008340 - 0x00001bd6: 7989 .y LDRB r1,[r1,#6] - 0x00001bd8: 4308 .C ORRS r0,r0,r1 - 0x00001bda: 4943 CI LDR r1,[pc,#268] ; [0x1ce8] = 0x10004fe0 - 0x00001bdc: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00001bde: 4a43 CJ LDR r2,[pc,#268] ; [0x1cec] = 0x10008340 - 0x00001be0: 79d2 .y LDRB r2,[r2,#7] - 0x00001be2: 4311 .C ORRS r1,r1,r2 - 0x00001be4: 4a41 AJ LDR r2,[pc,#260] ; [0x1cec] = 0x10008340 - 0x00001be6: 79d2 .y LDRB r2,[r2,#7] - 0x00001be8: 4311 .C ORRS r1,r1,r2 - 0x00001bea: 0209 .. LSLS r1,r1,#8 - 0x00001bec: 4308 .C ORRS r0,r0,r1 - 0x00001bee: e000 .. B 0x1bf2 ; GPIO_Clear_Low_Interrupt + 272 - 0x00001bf0: e029 ). B 0x1c46 ; GPIO_Clear_Low_Interrupt + 356 - 0x00001bf2: 493d =I LDR r1,[pc,#244] ; [0x1ce8] = 0x10004fe0 - 0x00001bf4: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00001bf6: 4a3d =J LDR r2,[pc,#244] ; [0x1cec] = 0x10008340 - 0x00001bf8: 7a12 .z LDRB r2,[r2,#8] - 0x00001bfa: 4311 .C ORRS r1,r1,r2 - 0x00001bfc: 4a3b ;J LDR r2,[pc,#236] ; [0x1cec] = 0x10008340 - 0x00001bfe: 7a12 .z LDRB r2,[r2,#8] - 0x00001c00: 4311 .C ORRS r1,r1,r2 - 0x00001c02: 0409 .. LSLS r1,r1,#16 - 0x00001c04: 4308 .C ORRS r0,r0,r1 - 0x00001c06: 4938 8I LDR r1,[pc,#224] ; [0x1ce8] = 0x10004fe0 - 0x00001c08: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00001c0a: 4a38 8J LDR r2,[pc,#224] ; [0x1cec] = 0x10008340 - 0x00001c0c: 7a52 Rz LDRB r2,[r2,#9] - 0x00001c0e: 4311 .C ORRS r1,r1,r2 - 0x00001c10: 4a36 6J LDR r2,[pc,#216] ; [0x1cec] = 0x10008340 - 0x00001c12: 7a52 Rz LDRB r2,[r2,#9] - 0x00001c14: 4311 .C ORRS r1,r1,r2 - 0x00001c16: 0609 .. LSLS r1,r1,#24 - 0x00001c18: 4308 .C ORRS r0,r0,r1 - 0x00001c1a: b2c6 .. UXTB r6,r0 - 0x00001c1c: 4629 )F MOV r1,r5 - 0x00001c1e: 3920 9 SUBS r1,r1,#0x20 - 0x00001c20: 2001 . MOVS r0,#1 - 0x00001c22: 4088 .@ LSLS r0,r0,r1 - 0x00001c24: 4631 1F MOV r1,r6 - 0x00001c26: 4381 .C BICS r1,r1,r0 - 0x00001c28: 460e .F MOV r6,r1 - 0x00001c2a: bf00 .. NOP - 0x00001c2c: 4830 0H LDR r0,[pc,#192] ; [0x1cf0] = 0x10008040 - 0x00001c2e: 7386 .s STRB r6,[r0,#0xe] - 0x00001c30: 7386 .s STRB r6,[r0,#0xe] - 0x00001c32: bf00 .. NOP - 0x00001c34: bf00 .. NOP - 0x00001c36: 2008 . MOVS r0,#8 - 0x00001c38: 492d -I LDR r1,[pc,#180] ; [0x1cf0] = 0x10008040 - 0x00001c3a: 3940 @9 SUBS r1,r1,#0x40 - 0x00001c3c: 7648 Hv STRB r0,[r1,#0x19] - 0x00001c3e: bf00 .. NOP - 0x00001c40: 2064 d MOVS r0,#0x64 - 0x00001c42: f000ffde .... BL whileDelay ; 0x2c02 - 0x00001c46: bd70 p. POP {r4-r6,pc} - GPIO_Clear_All_Interrupt - 0x00001c48: b510 .. PUSH {r4,lr} - 0x00001c4a: 2400 .$ MOVS r4,#0 - 0x00001c4c: bf00 .. NOP - 0x00001c4e: bf00 .. NOP - 0x00001c50: 4927 'I LDR r1,[pc,#156] ; [0x1cf0] = 0x10008040 - 0x00001c52: 730c .s STRB r4,[r1,#0xc] - 0x00001c54: 730c .s STRB r4,[r1,#0xc] - 0x00001c56: bf00 .. NOP - 0x00001c58: bf00 .. NOP - 0x00001c5a: 0420 . LSLS r0,r4,#16 - 0x00001c5c: 0e00 .. LSRS r0,r0,#24 - 0x00001c5e: 7348 Hs STRB r0,[r1,#0xd] - 0x00001c60: 0420 . LSLS r0,r4,#16 - 0x00001c62: 0e00 .. LSRS r0,r0,#24 - 0x00001c64: 7348 Hs STRB r0,[r1,#0xd] - 0x00001c66: bf00 .. NOP - 0x00001c68: bf00 .. NOP - 0x00001c6a: 0220 . LSLS r0,r4,#8 - 0x00001c6c: 0e00 .. LSRS r0,r0,#24 - 0x00001c6e: 7388 .s STRB r0,[r1,#0xe] - 0x00001c70: 0220 . LSLS r0,r4,#8 - 0x00001c72: 0e00 .. LSRS r0,r0,#24 - 0x00001c74: 7388 .s STRB r0,[r1,#0xe] - 0x00001c76: bf00 .. NOP - 0x00001c78: bf00 .. NOP - 0x00001c7a: 0e20 . LSRS r0,r4,#24 - 0x00001c7c: 73c8 .s STRB r0,[r1,#0xf] - 0x00001c7e: 0e20 . LSRS r0,r4,#24 - 0x00001c80: 73c8 .s STRB r0,[r1,#0xf] - 0x00001c82: bf00 .. NOP - 0x00001c84: bf00 .. NOP - 0x00001c86: bf00 .. NOP - 0x00001c88: 2004 . MOVS r0,#4 - 0x00001c8a: 4919 .I LDR r1,[pc,#100] ; [0x1cf0] = 0x10008040 - 0x00001c8c: 3940 @9 SUBS r1,r1,#0x40 - 0x00001c8e: 7148 Hq STRB r0,[r1,#5] - 0x00001c90: bf00 .. NOP - 0x00001c92: 2064 d MOVS r0,#0x64 - 0x00001c94: f000ffb5 .... BL whileDelay ; 0x2c02 - 0x00001c98: bf00 .. NOP - 0x00001c9a: 2008 . MOVS r0,#8 - 0x00001c9c: 4914 .I LDR r1,[pc,#80] ; [0x1cf0] = 0x10008040 - 0x00001c9e: 3940 @9 SUBS r1,r1,#0x40 - 0x00001ca0: 7148 Hq STRB r0,[r1,#5] - 0x00001ca2: bf00 .. NOP - 0x00001ca4: 2064 d MOVS r0,#0x64 - 0x00001ca6: f000ffac .... BL whileDelay ; 0x2c02 - 0x00001caa: bf00 .. NOP - 0x00001cac: 2088 . MOVS r0,#0x88 - 0x00001cae: 4910 .I LDR r1,[pc,#64] ; [0x1cf0] = 0x10008040 - 0x00001cb0: 7308 .s STRB r0,[r1,#0xc] - 0x00001cb2: 7308 .s STRB r0,[r1,#0xc] - 0x00001cb4: bf00 .. NOP - 0x00001cb6: bf00 .. NOP - 0x00001cb8: 2000 . MOVS r0,#0 - 0x00001cba: 7348 Hs STRB r0,[r1,#0xd] - 0x00001cbc: 7348 Hs STRB r0,[r1,#0xd] - 0x00001cbe: bf00 .. NOP - 0x00001cc0: bf00 .. NOP - 0x00001cc2: 7388 .s STRB r0,[r1,#0xe] - 0x00001cc4: 7388 .s STRB r0,[r1,#0xe] - 0x00001cc6: bf00 .. NOP - 0x00001cc8: bf00 .. NOP - 0x00001cca: 2008 . MOVS r0,#8 - 0x00001ccc: 4908 .I LDR r1,[pc,#32] ; [0x1cf0] = 0x10008040 - 0x00001cce: 3940 @9 SUBS r1,r1,#0x40 - 0x00001cd0: 7648 Hv STRB r0,[r1,#0x19] - 0x00001cd2: bf00 .. NOP - 0x00001cd4: 2064 d MOVS r0,#0x64 - 0x00001cd6: f000ff94 .... BL whileDelay ; 0x2c02 - 0x00001cda: bd10 .. POP {r4,pc} + 0x00001b82: bf00 .. NOP + 0x00001b84: bf00 .. NOP + 0x00001b86: 0e20 . LSRS r0,r4,#24 + 0x00001b88: 73c8 .s STRB r0,[r1,#0xf] + 0x00001b8a: 0e20 . LSRS r0,r4,#24 + 0x00001b8c: 73c8 .s STRB r0,[r1,#0xf] + 0x00001b8e: bf00 .. NOP + 0x00001b90: bf00 .. NOP + 0x00001b92: bf00 .. NOP + 0x00001b94: 2004 . MOVS r0,#4 + 0x00001b96: 4919 .I LDR r1,[pc,#100] ; [0x1bfc] = 0x10008040 + 0x00001b98: 3940 @9 SUBS r1,r1,#0x40 + 0x00001b9a: 7148 Hq STRB r0,[r1,#5] + 0x00001b9c: bf00 .. NOP + 0x00001b9e: 2064 d MOVS r0,#0x64 + 0x00001ba0: f001f8c5 .... BL whileDelay ; 0x2d2e + 0x00001ba4: bf00 .. NOP + 0x00001ba6: 2008 . MOVS r0,#8 + 0x00001ba8: 4914 .I LDR r1,[pc,#80] ; [0x1bfc] = 0x10008040 + 0x00001baa: 3940 @9 SUBS r1,r1,#0x40 + 0x00001bac: 7148 Hq STRB r0,[r1,#5] + 0x00001bae: bf00 .. NOP + 0x00001bb0: 2064 d MOVS r0,#0x64 + 0x00001bb2: f001f8bc .... BL whileDelay ; 0x2d2e + 0x00001bb6: bf00 .. NOP + 0x00001bb8: 2088 . MOVS r0,#0x88 + 0x00001bba: 4910 .I LDR r1,[pc,#64] ; [0x1bfc] = 0x10008040 + 0x00001bbc: 7308 .s STRB r0,[r1,#0xc] + 0x00001bbe: 7308 .s STRB r0,[r1,#0xc] + 0x00001bc0: bf00 .. NOP + 0x00001bc2: bf00 .. NOP + 0x00001bc4: 2000 . MOVS r0,#0 + 0x00001bc6: 7348 Hs STRB r0,[r1,#0xd] + 0x00001bc8: 7348 Hs STRB r0,[r1,#0xd] + 0x00001bca: bf00 .. NOP + 0x00001bcc: bf00 .. NOP + 0x00001bce: 7388 .s STRB r0,[r1,#0xe] + 0x00001bd0: 7388 .s STRB r0,[r1,#0xe] + 0x00001bd2: bf00 .. NOP + 0x00001bd4: bf00 .. NOP + 0x00001bd6: 2008 . MOVS r0,#8 + 0x00001bd8: 4908 .I LDR r1,[pc,#32] ; [0x1bfc] = 0x10008040 + 0x00001bda: 3940 @9 SUBS r1,r1,#0x40 + 0x00001bdc: 7648 Hv STRB r0,[r1,#0x19] + 0x00001bde: bf00 .. NOP + 0x00001be0: 2064 d MOVS r0,#0x64 + 0x00001be2: f001f8a4 .... BL whileDelay ; 0x2d2e + 0x00001be6: bd10 .. POP {r4,pc} hw_delay - 0x00001cdc: bf00 .. NOP - 0x00001cde: bf00 .. NOP - 0x00001ce0: bf00 .. NOP - 0x00001ce2: bf00 .. NOP - 0x00001ce4: bf00 .. NOP - 0x00001ce6: 4770 pG BX lr + 0x00001be8: bf00 .. NOP + 0x00001bea: bf00 .. NOP + 0x00001bec: bf00 .. NOP + 0x00001bee: bf00 .. NOP + 0x00001bf0: bf00 .. NOP + 0x00001bf2: 4770 pG BX lr $d - 0x00001ce8: 10004fe0 .O.. DCD 268455904 - 0x00001cec: 10008340 @... DCD 268469056 - 0x00001cf0: 10008040 @... DCD 268468288 + 0x00001bf4: 10004fe0 .O.. DCD 268455904 + 0x00001bf8: 10008340 @... DCD 268469056 + 0x00001bfc: 10008040 @... DCD 268468288 $t .text SYS_TimerExpireDefaultHandle - 0x00001cf4: bf00 .. NOP - 0x00001cf6: bf00 .. NOP - 0x00001cf8: 4770 pG BX lr + 0x00001c00: bf00 .. NOP + 0x00001c02: bf00 .. NOP + 0x00001c04: 4770 pG BX lr SYS_TimerGet1usTicks - 0x00001cfa: b510 .. PUSH {r4,lr} - 0x00001cfc: 4bfc .K LDR r3,[pc,#1008] ; [0x20f0] = 0x10004fe0 - 0x00001cfe: 7fdb .. LDRB r3,[r3,#0x1f] - 0x00001d00: 2300 .# MOVS r3,#0 - 0x00001d02: 4cfc .L LDR r4,[pc,#1008] ; [0x20f4] = 0x10008040 - 0x00001d04: 78e4 .x LDRB r4,[r4,#3] - 0x00001d06: 431b .C ORRS r3,r3,r3 - 0x00001d08: 4cfa .L LDR r4,[pc,#1000] ; [0x20f4] = 0x10008040 - 0x00001d0a: 78e4 .x LDRB r4,[r4,#3] - 0x00001d0c: 4323 #C ORRS r3,r3,r4 - 0x00001d0e: 4619 .F MOV r1,r3 - 0x00001d10: 074b K. LSLS r3,r1,#29 - 0x00001d12: 0f9a .. LSRS r2,r3,#30 - 0x00001d14: 2000 . MOVS r0,#0 - 0x00001d16: 2a00 .* CMP r2,#0 - 0x00001d18: d006 .. BEQ 0x1d28 ; SYS_TimerGet1usTicks + 46 - 0x00001d1a: 2a01 .* CMP r2,#1 - 0x00001d1c: d006 .. BEQ 0x1d2c ; SYS_TimerGet1usTicks + 50 - 0x00001d1e: 2a02 .* CMP r2,#2 - 0x00001d20: d006 .. BEQ 0x1d30 ; SYS_TimerGet1usTicks + 54 - 0x00001d22: 2a03 .* CMP r2,#3 - 0x00001d24: d108 .. BNE 0x1d38 ; SYS_TimerGet1usTicks + 62 - 0x00001d26: e005 .. B 0x1d34 ; SYS_TimerGet1usTicks + 58 - 0x00001d28: 2030 0 MOVS r0,#0x30 - 0x00001d2a: e006 .. B 0x1d3a ; SYS_TimerGet1usTicks + 64 - 0x00001d2c: 2040 @ MOVS r0,#0x40 - 0x00001d2e: e004 .. B 0x1d3a ; SYS_TimerGet1usTicks + 64 - 0x00001d30: 2060 ` MOVS r0,#0x60 - 0x00001d32: e002 .. B 0x1d3a ; SYS_TimerGet1usTicks + 64 - 0x00001d34: 20c0 . MOVS r0,#0xc0 - 0x00001d36: e000 .. B 0x1d3a ; SYS_TimerGet1usTicks + 64 - 0x00001d38: bf00 .. NOP - 0x00001d3a: bf00 .. NOP - 0x00001d3c: bd10 .. POP {r4,pc} + 0x00001c06: b510 .. PUSH {r4,lr} + 0x00001c08: 4bfc .K LDR r3,[pc,#1008] ; [0x1ffc] = 0x10004fe0 + 0x00001c0a: 7fdb .. LDRB r3,[r3,#0x1f] + 0x00001c0c: 2300 .# MOVS r3,#0 + 0x00001c0e: 4cfc .L LDR r4,[pc,#1008] ; [0x2000] = 0x10008040 + 0x00001c10: 78e4 .x LDRB r4,[r4,#3] + 0x00001c12: 431b .C ORRS r3,r3,r3 + 0x00001c14: 4cfa .L LDR r4,[pc,#1000] ; [0x2000] = 0x10008040 + 0x00001c16: 78e4 .x LDRB r4,[r4,#3] + 0x00001c18: 4323 #C ORRS r3,r3,r4 + 0x00001c1a: 4619 .F MOV r1,r3 + 0x00001c1c: 074b K. LSLS r3,r1,#29 + 0x00001c1e: 0f9a .. LSRS r2,r3,#30 + 0x00001c20: 2000 . MOVS r0,#0 + 0x00001c22: 2a00 .* CMP r2,#0 + 0x00001c24: d006 .. BEQ 0x1c34 ; SYS_TimerGet1usTicks + 46 + 0x00001c26: 2a01 .* CMP r2,#1 + 0x00001c28: d006 .. BEQ 0x1c38 ; SYS_TimerGet1usTicks + 50 + 0x00001c2a: 2a02 .* CMP r2,#2 + 0x00001c2c: d006 .. BEQ 0x1c3c ; SYS_TimerGet1usTicks + 54 + 0x00001c2e: 2a03 .* CMP r2,#3 + 0x00001c30: d108 .. BNE 0x1c44 ; SYS_TimerGet1usTicks + 62 + 0x00001c32: e005 .. B 0x1c40 ; SYS_TimerGet1usTicks + 58 + 0x00001c34: 2030 0 MOVS r0,#0x30 + 0x00001c36: e006 .. B 0x1c46 ; SYS_TimerGet1usTicks + 64 + 0x00001c38: 2040 @ MOVS r0,#0x40 + 0x00001c3a: e004 .. B 0x1c46 ; SYS_TimerGet1usTicks + 64 + 0x00001c3c: 2060 ` MOVS r0,#0x60 + 0x00001c3e: e002 .. B 0x1c46 ; SYS_TimerGet1usTicks + 64 + 0x00001c40: 20c0 . MOVS r0,#0xc0 + 0x00001c42: e000 .. B 0x1c46 ; SYS_TimerGet1usTicks + 64 + 0x00001c44: bf00 .. NOP + 0x00001c46: bf00 .. NOP + 0x00001c48: bd10 .. POP {r4,pc} SYS_ChangeDPLL - 0x00001d3e: b5f8 .. PUSH {r3-r7,lr} - 0x00001d40: 4604 .F MOV r4,r0 - 0x00001d42: 48eb .H LDR r0,[pc,#940] ; [0x20f0] = 0x10004fe0 - 0x00001d44: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00001d46: 2000 . MOVS r0,#0 - 0x00001d48: 49ea .I LDR r1,[pc,#936] ; [0x20f4] = 0x10008040 - 0x00001d4a: 78c9 .x LDRB r1,[r1,#3] - 0x00001d4c: 4300 .C ORRS r0,r0,r0 - 0x00001d4e: 49e9 .I LDR r1,[pc,#932] ; [0x20f4] = 0x10008040 - 0x00001d50: 78c9 .x LDRB r1,[r1,#3] - 0x00001d52: 4308 .C ORRS r0,r0,r1 - 0x00001d54: 4605 .F MOV r5,r0 - 0x00001d56: 2c00 ., CMP r4,#0 - 0x00001d58: d000 .. BEQ 0x1d5c ; SYS_ChangeDPLL + 30 - 0x00001d5a: 2400 .$ MOVS r4,#0 - 0x00001d5c: 4626 &F MOV r6,r4 - 0x00001d5e: 20f9 . MOVS r0,#0xf9 - 0x00001d60: 4005 .@ ANDS r5,r5,r0 - 0x00001d62: 0070 p. LSLS r0,r6,#1 - 0x00001d64: 4328 (C ORRS r0,r0,r5 - 0x00001d66: b2c5 .. UXTB r5,r0 - 0x00001d68: bf00 .. NOP - 0x00001d6a: 48e2 .H LDR r0,[pc,#904] ; [0x20f4] = 0x10008040 - 0x00001d6c: 70c5 .p STRB r5,[r0,#3] - 0x00001d6e: 70c5 .p STRB r5,[r0,#3] - 0x00001d70: bf00 .. NOP - 0x00001d72: f7ffffc2 .... BL SYS_TimerGet1usTicks ; 0x1cfa - 0x00001d76: 49e0 .I LDR r1,[pc,#896] ; [0x20f8] = 0x2710 - 0x00001d78: 4348 HC MULS r0,r1,r0 - 0x00001d7a: 4607 .F MOV r7,r0 - 0x00001d7c: f000fa2e .... BL SysTick_Config ; 0x21dc - 0x00001d80: bdf8 .. POP {r3-r7,pc} + 0x00001c4a: b5f8 .. PUSH {r3-r7,lr} + 0x00001c4c: 4604 .F MOV r4,r0 + 0x00001c4e: 48eb .H LDR r0,[pc,#940] ; [0x1ffc] = 0x10004fe0 + 0x00001c50: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x00001c52: 2000 . MOVS r0,#0 + 0x00001c54: 49ea .I LDR r1,[pc,#936] ; [0x2000] = 0x10008040 + 0x00001c56: 78c9 .x LDRB r1,[r1,#3] + 0x00001c58: 4300 .C ORRS r0,r0,r0 + 0x00001c5a: 49e9 .I LDR r1,[pc,#932] ; [0x2000] = 0x10008040 + 0x00001c5c: 78c9 .x LDRB r1,[r1,#3] + 0x00001c5e: 4308 .C ORRS r0,r0,r1 + 0x00001c60: 4605 .F MOV r5,r0 + 0x00001c62: 2c00 ., CMP r4,#0 + 0x00001c64: d000 .. BEQ 0x1c68 ; SYS_ChangeDPLL + 30 + 0x00001c66: 2400 .$ MOVS r4,#0 + 0x00001c68: 4626 &F MOV r6,r4 + 0x00001c6a: 20f9 . MOVS r0,#0xf9 + 0x00001c6c: 4005 .@ ANDS r5,r5,r0 + 0x00001c6e: 0070 p. LSLS r0,r6,#1 + 0x00001c70: 4328 (C ORRS r0,r0,r5 + 0x00001c72: b2c5 .. UXTB r5,r0 + 0x00001c74: bf00 .. NOP + 0x00001c76: 48e2 .H LDR r0,[pc,#904] ; [0x2000] = 0x10008040 + 0x00001c78: 70c5 .p STRB r5,[r0,#3] + 0x00001c7a: 70c5 .p STRB r5,[r0,#3] + 0x00001c7c: bf00 .. NOP + 0x00001c7e: f7ffffc2 .... BL SYS_TimerGet1usTicks ; 0x1c06 + 0x00001c82: 49e0 .I LDR r1,[pc,#896] ; [0x2004] = 0x2710 + 0x00001c84: 4348 HC MULS r0,r1,r0 + 0x00001c86: 4607 .F MOV r7,r0 + 0x00001c88: f000fa2e .... BL SysTick_Config ; 0x20e8 + 0x00001c8c: bdf8 .. POP {r3-r7,pc} SYS_ChangeToFastDPLL - 0x00001d82: b570 p. PUSH {r4-r6,lr} - 0x00001d84: 2001 . MOVS r0,#1 - 0x00001d86: 49dd .I LDR r1,[pc,#884] ; [0x20fc] = 0x10011011 - 0x00001d88: 7008 .p STRB r0,[r1,#0] - 0x00001d8a: 48d9 .H LDR r0,[pc,#868] ; [0x20f0] = 0x10004fe0 - 0x00001d8c: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00001d8e: 2000 . MOVS r0,#0 - 0x00001d90: 49d8 .I LDR r1,[pc,#864] ; [0x20f4] = 0x10008040 - 0x00001d92: 78c9 .x LDRB r1,[r1,#3] - 0x00001d94: 4300 .C ORRS r0,r0,r0 - 0x00001d96: 49d7 .I LDR r1,[pc,#860] ; [0x20f4] = 0x10008040 - 0x00001d98: 78c9 .x LDRB r1,[r1,#3] - 0x00001d9a: 4308 .C ORRS r0,r0,r1 - 0x00001d9c: 4604 .F MOV r4,r0 - 0x00001d9e: 2503 .% MOVS r5,#3 - 0x00001da0: 20f9 . MOVS r0,#0xf9 - 0x00001da2: 4004 .@ ANDS r4,r4,r0 - 0x00001da4: 0068 h. LSLS r0,r5,#1 - 0x00001da6: 4304 .C ORRS r4,r4,r0 - 0x00001da8: bf00 .. NOP - 0x00001daa: 48d2 .H LDR r0,[pc,#840] ; [0x20f4] = 0x10008040 - 0x00001dac: 70c4 .p STRB r4,[r0,#3] - 0x00001dae: 70c4 .p STRB r4,[r0,#3] - 0x00001db0: bf00 .. NOP - 0x00001db2: f000fa04 .... BL hw_delay ; 0x21be - 0x00001db6: f000fa02 .... BL hw_delay ; 0x21be - 0x00001dba: f000fa00 .... BL hw_delay ; 0x21be - 0x00001dbe: f000f9fe .... BL hw_delay ; 0x21be - 0x00001dc2: f000f9fc .... BL hw_delay ; 0x21be - 0x00001dc6: f000f9fa .... BL hw_delay ; 0x21be - 0x00001dca: f000f9f8 .... BL hw_delay ; 0x21be - 0x00001dce: f000f9f6 .... BL hw_delay ; 0x21be - 0x00001dd2: f000f9f4 .... BL hw_delay ; 0x21be - 0x00001dd6: f000f9f2 .... BL hw_delay ; 0x21be - 0x00001dda: f000f9f0 .... BL hw_delay ; 0x21be - 0x00001dde: f000f9ee .... BL hw_delay ; 0x21be - 0x00001de2: f000f9ec .... BL hw_delay ; 0x21be - 0x00001de6: f000f9ea .... BL hw_delay ; 0x21be - 0x00001dea: f000f9e8 .... BL hw_delay ; 0x21be - 0x00001dee: f000f9e6 .... BL hw_delay ; 0x21be - 0x00001df2: f000f9e4 .... BL hw_delay ; 0x21be - 0x00001df6: f000f9e2 .... BL hw_delay ; 0x21be - 0x00001dfa: f000f9e0 .... BL hw_delay ; 0x21be - 0x00001dfe: f000f9de .... BL hw_delay ; 0x21be - 0x00001e02: bd70 p. POP {r4-r6,pc} + 0x00001c8e: b570 p. PUSH {r4-r6,lr} + 0x00001c90: 2001 . MOVS r0,#1 + 0x00001c92: 49dd .I LDR r1,[pc,#884] ; [0x2008] = 0x1001100d + 0x00001c94: 7008 .p STRB r0,[r1,#0] + 0x00001c96: 48d9 .H LDR r0,[pc,#868] ; [0x1ffc] = 0x10004fe0 + 0x00001c98: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x00001c9a: 2000 . MOVS r0,#0 + 0x00001c9c: 49d8 .I LDR r1,[pc,#864] ; [0x2000] = 0x10008040 + 0x00001c9e: 78c9 .x LDRB r1,[r1,#3] + 0x00001ca0: 4300 .C ORRS r0,r0,r0 + 0x00001ca2: 49d7 .I LDR r1,[pc,#860] ; [0x2000] = 0x10008040 + 0x00001ca4: 78c9 .x LDRB r1,[r1,#3] + 0x00001ca6: 4308 .C ORRS r0,r0,r1 + 0x00001ca8: 4604 .F MOV r4,r0 + 0x00001caa: 2503 .% MOVS r5,#3 + 0x00001cac: 20f9 . MOVS r0,#0xf9 + 0x00001cae: 4004 .@ ANDS r4,r4,r0 + 0x00001cb0: 0068 h. LSLS r0,r5,#1 + 0x00001cb2: 4304 .C ORRS r4,r4,r0 + 0x00001cb4: bf00 .. NOP + 0x00001cb6: 48d2 .H LDR r0,[pc,#840] ; [0x2000] = 0x10008040 + 0x00001cb8: 70c4 .p STRB r4,[r0,#3] + 0x00001cba: 70c4 .p STRB r4,[r0,#3] + 0x00001cbc: bf00 .. NOP + 0x00001cbe: f000fa04 .... BL hw_delay ; 0x20ca + 0x00001cc2: f000fa02 .... BL hw_delay ; 0x20ca + 0x00001cc6: f000fa00 .... BL hw_delay ; 0x20ca + 0x00001cca: f000f9fe .... BL hw_delay ; 0x20ca + 0x00001cce: f000f9fc .... BL hw_delay ; 0x20ca + 0x00001cd2: f000f9fa .... BL hw_delay ; 0x20ca + 0x00001cd6: f000f9f8 .... BL hw_delay ; 0x20ca + 0x00001cda: f000f9f6 .... BL hw_delay ; 0x20ca + 0x00001cde: f000f9f4 .... BL hw_delay ; 0x20ca + 0x00001ce2: f000f9f2 .... BL hw_delay ; 0x20ca + 0x00001ce6: f000f9f0 .... BL hw_delay ; 0x20ca + 0x00001cea: f000f9ee .... BL hw_delay ; 0x20ca + 0x00001cee: f000f9ec .... BL hw_delay ; 0x20ca + 0x00001cf2: f000f9ea .... BL hw_delay ; 0x20ca + 0x00001cf6: f000f9e8 .... BL hw_delay ; 0x20ca + 0x00001cfa: f000f9e6 .... BL hw_delay ; 0x20ca + 0x00001cfe: f000f9e4 .... BL hw_delay ; 0x20ca + 0x00001d02: f000f9e2 .... BL hw_delay ; 0x20ca + 0x00001d06: f000f9e0 .... BL hw_delay ; 0x20ca + 0x00001d0a: f000f9de .... BL hw_delay ; 0x20ca + 0x00001d0e: bd70 p. POP {r4-r6,pc} SYS_ChangeToNormalDPLL - 0x00001e04: b570 p. PUSH {r4-r6,lr} - 0x00001e06: 2000 . MOVS r0,#0 - 0x00001e08: 49bc .I LDR r1,[pc,#752] ; [0x20fc] = 0x10011011 - 0x00001e0a: 7008 .p STRB r0,[r1,#0] - 0x00001e0c: 48b8 .H LDR r0,[pc,#736] ; [0x20f0] = 0x10004fe0 - 0x00001e0e: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00001e10: 2000 . MOVS r0,#0 - 0x00001e12: 49b8 .I LDR r1,[pc,#736] ; [0x20f4] = 0x10008040 - 0x00001e14: 78c9 .x LDRB r1,[r1,#3] - 0x00001e16: 4300 .C ORRS r0,r0,r0 - 0x00001e18: 49b6 .I LDR r1,[pc,#728] ; [0x20f4] = 0x10008040 - 0x00001e1a: 78c9 .x LDRB r1,[r1,#3] - 0x00001e1c: 4308 .C ORRS r0,r0,r1 - 0x00001e1e: 4604 .F MOV r4,r0 - 0x00001e20: 2500 .% MOVS r5,#0 - 0x00001e22: 20f9 . MOVS r0,#0xf9 - 0x00001e24: 4004 .@ ANDS r4,r4,r0 - 0x00001e26: 0068 h. LSLS r0,r5,#1 - 0x00001e28: 4304 .C ORRS r4,r4,r0 - 0x00001e2a: bf00 .. NOP - 0x00001e2c: 48b1 .H LDR r0,[pc,#708] ; [0x20f4] = 0x10008040 - 0x00001e2e: 70c4 .p STRB r4,[r0,#3] - 0x00001e30: 70c4 .p STRB r4,[r0,#3] - 0x00001e32: bf00 .. NOP - 0x00001e34: f000f9c3 .... BL hw_delay ; 0x21be - 0x00001e38: f000f9c1 .... BL hw_delay ; 0x21be - 0x00001e3c: f000f9bf .... BL hw_delay ; 0x21be - 0x00001e40: f000f9bd .... BL hw_delay ; 0x21be - 0x00001e44: f000f9bb .... BL hw_delay ; 0x21be - 0x00001e48: f000f9b9 .... BL hw_delay ; 0x21be - 0x00001e4c: f000f9b7 .... BL hw_delay ; 0x21be - 0x00001e50: f000f9b5 .... BL hw_delay ; 0x21be - 0x00001e54: f000f9b3 .... BL hw_delay ; 0x21be - 0x00001e58: f000f9b1 .... BL hw_delay ; 0x21be - 0x00001e5c: f000f9af .... BL hw_delay ; 0x21be - 0x00001e60: f000f9ad .... BL hw_delay ; 0x21be - 0x00001e64: f000f9ab .... BL hw_delay ; 0x21be - 0x00001e68: f000f9a9 .... BL hw_delay ; 0x21be - 0x00001e6c: f000f9a7 .... BL hw_delay ; 0x21be - 0x00001e70: f000f9a5 .... BL hw_delay ; 0x21be - 0x00001e74: f000f9a3 .... BL hw_delay ; 0x21be - 0x00001e78: f000f9a1 .... BL hw_delay ; 0x21be - 0x00001e7c: f000f99f .... BL hw_delay ; 0x21be - 0x00001e80: f000f99d .... BL hw_delay ; 0x21be - 0x00001e84: bd70 p. POP {r4-r6,pc} + 0x00001d10: b570 p. PUSH {r4-r6,lr} + 0x00001d12: 2000 . MOVS r0,#0 + 0x00001d14: 49bc .I LDR r1,[pc,#752] ; [0x2008] = 0x1001100d + 0x00001d16: 7008 .p STRB r0,[r1,#0] + 0x00001d18: 48b8 .H LDR r0,[pc,#736] ; [0x1ffc] = 0x10004fe0 + 0x00001d1a: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x00001d1c: 2000 . MOVS r0,#0 + 0x00001d1e: 49b8 .I LDR r1,[pc,#736] ; [0x2000] = 0x10008040 + 0x00001d20: 78c9 .x LDRB r1,[r1,#3] + 0x00001d22: 4300 .C ORRS r0,r0,r0 + 0x00001d24: 49b6 .I LDR r1,[pc,#728] ; [0x2000] = 0x10008040 + 0x00001d26: 78c9 .x LDRB r1,[r1,#3] + 0x00001d28: 4308 .C ORRS r0,r0,r1 + 0x00001d2a: 4604 .F MOV r4,r0 + 0x00001d2c: 2500 .% MOVS r5,#0 + 0x00001d2e: 20f9 . MOVS r0,#0xf9 + 0x00001d30: 4004 .@ ANDS r4,r4,r0 + 0x00001d32: 0068 h. LSLS r0,r5,#1 + 0x00001d34: 4304 .C ORRS r4,r4,r0 + 0x00001d36: bf00 .. NOP + 0x00001d38: 48b1 .H LDR r0,[pc,#708] ; [0x2000] = 0x10008040 + 0x00001d3a: 70c4 .p STRB r4,[r0,#3] + 0x00001d3c: 70c4 .p STRB r4,[r0,#3] + 0x00001d3e: bf00 .. NOP + 0x00001d40: f000f9c3 .... BL hw_delay ; 0x20ca + 0x00001d44: f000f9c1 .... BL hw_delay ; 0x20ca + 0x00001d48: f000f9bf .... BL hw_delay ; 0x20ca + 0x00001d4c: f000f9bd .... BL hw_delay ; 0x20ca + 0x00001d50: f000f9bb .... BL hw_delay ; 0x20ca + 0x00001d54: f000f9b9 .... BL hw_delay ; 0x20ca + 0x00001d58: f000f9b7 .... BL hw_delay ; 0x20ca + 0x00001d5c: f000f9b5 .... BL hw_delay ; 0x20ca + 0x00001d60: f000f9b3 .... BL hw_delay ; 0x20ca + 0x00001d64: f000f9b1 .... BL hw_delay ; 0x20ca + 0x00001d68: f000f9af .... BL hw_delay ; 0x20ca + 0x00001d6c: f000f9ad .... BL hw_delay ; 0x20ca + 0x00001d70: f000f9ab .... BL hw_delay ; 0x20ca + 0x00001d74: f000f9a9 .... BL hw_delay ; 0x20ca + 0x00001d78: f000f9a7 .... BL hw_delay ; 0x20ca + 0x00001d7c: f000f9a5 .... BL hw_delay ; 0x20ca + 0x00001d80: f000f9a3 .... BL hw_delay ; 0x20ca + 0x00001d84: f000f9a1 .... BL hw_delay ; 0x20ca + 0x00001d88: f000f99f .... BL hw_delay ; 0x20ca + 0x00001d8c: f000f99d .... BL hw_delay ; 0x20ca + 0x00001d90: bd70 p. POP {r4-r6,pc} SystemCheckInFastSpeed - 0x00001e86: 489d .H LDR r0,[pc,#628] ; [0x20fc] = 0x10011011 - 0x00001e88: 7800 .x LDRB r0,[r0,#0] - 0x00001e8a: 4770 pG BX lr + 0x00001d92: 489d .H LDR r0,[pc,#628] ; [0x2008] = 0x1001100d + 0x00001d94: 7800 .x LDRB r0,[r0,#0] + 0x00001d96: 4770 pG BX lr SYS_ClkTicks - 0x00001e8c: b510 .. PUSH {r4,lr} - 0x00001e8e: f7fffffa .... BL SystemCheckInFastSpeed ; 0x1e86 - 0x00001e92: 2800 .( CMP r0,#0 - 0x00001e94: d000 .. BEQ 0x1e98 ; SYS_ClkTicks + 12 - 0x00001e96: bd10 .. POP {r4,pc} - 0x00001e98: 4895 .H LDR r0,[pc,#596] ; [0x20f0] = 0x10004fe0 - 0x00001e9a: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00001e9c: 2000 . MOVS r0,#0 - 0x00001e9e: 4b98 .K LDR r3,[pc,#608] ; [0x2100] = 0x10008300 - 0x00001ea0: 781b .x LDRB r3,[r3,#0] - 0x00001ea2: 4300 .C ORRS r0,r0,r0 - 0x00001ea4: 4b96 .K LDR r3,[pc,#600] ; [0x2100] = 0x10008300 - 0x00001ea6: 781b .x LDRB r3,[r3,#0] - 0x00001ea8: 4318 .C ORRS r0,r0,r3 - 0x00001eaa: 4b91 .K LDR r3,[pc,#580] ; [0x20f0] = 0x10004fe0 - 0x00001eac: 7fdb .. LDRB r3,[r3,#0x1f] - 0x00001eae: 2300 .# MOVS r3,#0 - 0x00001eb0: 4c93 .L LDR r4,[pc,#588] ; [0x2100] = 0x10008300 - 0x00001eb2: 7864 dx LDRB r4,[r4,#1] - 0x00001eb4: 431b .C ORRS r3,r3,r3 - 0x00001eb6: 4c92 .L LDR r4,[pc,#584] ; [0x2100] = 0x10008300 - 0x00001eb8: 7864 dx LDRB r4,[r4,#1] - 0x00001eba: 4323 #C ORRS r3,r3,r4 - 0x00001ebc: 021b .. LSLS r3,r3,#8 - 0x00001ebe: 4318 .C ORRS r0,r0,r3 - 0x00001ec0: 4b8b .K LDR r3,[pc,#556] ; [0x20f0] = 0x10004fe0 - 0x00001ec2: 7fdb .. LDRB r3,[r3,#0x1f] - 0x00001ec4: 2300 .# MOVS r3,#0 - 0x00001ec6: 4c8e .L LDR r4,[pc,#568] ; [0x2100] = 0x10008300 - 0x00001ec8: 78a4 .x LDRB r4,[r4,#2] - 0x00001eca: 431b .C ORRS r3,r3,r3 - 0x00001ecc: 4c8c .L LDR r4,[pc,#560] ; [0x2100] = 0x10008300 - 0x00001ece: 78a4 .x LDRB r4,[r4,#2] - 0x00001ed0: 4323 #C ORRS r3,r3,r4 - 0x00001ed2: 041b .. LSLS r3,r3,#16 - 0x00001ed4: 4318 .C ORRS r0,r0,r3 - 0x00001ed6: 4b86 .K LDR r3,[pc,#536] ; [0x20f0] = 0x10004fe0 - 0x00001ed8: 7fdb .. LDRB r3,[r3,#0x1f] - 0x00001eda: 2300 .# MOVS r3,#0 - 0x00001edc: 4c88 .L LDR r4,[pc,#544] ; [0x2100] = 0x10008300 - 0x00001ede: 78e4 .x LDRB r4,[r4,#3] - 0x00001ee0: 431b .C ORRS r3,r3,r3 - 0x00001ee2: 4c87 .L LDR r4,[pc,#540] ; [0x2100] = 0x10008300 - 0x00001ee4: 78e4 .x LDRB r4,[r4,#3] - 0x00001ee6: 4323 #C ORRS r3,r3,r4 - 0x00001ee8: 061b .. LSLS r3,r3,#24 - 0x00001eea: 4318 .C ORRS r0,r0,r3 - 0x00001eec: 4601 .F MOV r1,r0 - 0x00001eee: 2200 ." MOVS r2,#0 - 0x00001ef0: 4884 .H LDR r0,[pc,#528] ; [0x2104] = 0x1001100c - 0x00001ef2: 6800 .h LDR r0,[r0,#0] - 0x00001ef4: 2800 .( CMP r0,#0 - 0x00001ef6: d102 .. BNE 0x1efe ; SYS_ClkTicks + 114 - 0x00001ef8: 4882 .H LDR r0,[pc,#520] ; [0x2104] = 0x1001100c - 0x00001efa: 6001 .` STR r1,[r0,#0] - 0x00001efc: e017 .. B 0x1f2e ; SYS_ClkTicks + 162 - 0x00001efe: 4881 .H LDR r0,[pc,#516] ; [0x2104] = 0x1001100c - 0x00001f00: 6800 .h LDR r0,[r0,#0] - 0x00001f02: 4288 .B CMP r0,r1 - 0x00001f04: d902 .. BLS 0x1f0c ; SYS_ClkTicks + 128 - 0x00001f06: 487f .H LDR r0,[pc,#508] ; [0x2104] = 0x1001100c - 0x00001f08: 6001 .` STR r1,[r0,#0] - 0x00001f0a: e7c4 .. B 0x1e96 ; SYS_ClkTicks + 10 - 0x00001f0c: 487d }H LDR r0,[pc,#500] ; [0x2104] = 0x1001100c - 0x00001f0e: 6800 .h LDR r0,[r0,#0] - 0x00001f10: 1a0a .. SUBS r2,r1,r0 - 0x00001f12: e00a .. B 0x1f2a ; SYS_ClkTicks + 158 - 0x00001f14: 487c |H LDR r0,[pc,#496] ; [0x2108] = 0x10011008 - 0x00001f16: 6800 .h LDR r0,[r0,#0] - 0x00001f18: 1c40 @. ADDS r0,r0,#1 - 0x00001f1a: 4b7b {K LDR r3,[pc,#492] ; [0x2108] = 0x10011008 - 0x00001f1c: 6018 .` STR r0,[r3,#0] - 0x00001f1e: 4879 yH LDR r0,[pc,#484] ; [0x2104] = 0x1001100c - 0x00001f20: 6800 .h LDR r0,[r0,#0] - 0x00001f22: 3020 0 ADDS r0,r0,#0x20 - 0x00001f24: 4b77 wK LDR r3,[pc,#476] ; [0x2104] = 0x1001100c - 0x00001f26: 6018 .` STR r0,[r3,#0] - 0x00001f28: 3a20 : SUBS r2,r2,#0x20 - 0x00001f2a: 2a20 * CMP r2,#0x20 - 0x00001f2c: d2f2 .. BCS 0x1f14 ; SYS_ClkTicks + 136 - 0x00001f2e: bf00 .. NOP - 0x00001f30: e7b1 .. B 0x1e96 ; SYS_ClkTicks + 10 + 0x00001d98: b510 .. PUSH {r4,lr} + 0x00001d9a: f7fffffa .... BL SystemCheckInFastSpeed ; 0x1d92 + 0x00001d9e: 2800 .( CMP r0,#0 + 0x00001da0: d000 .. BEQ 0x1da4 ; SYS_ClkTicks + 12 + 0x00001da2: bd10 .. POP {r4,pc} + 0x00001da4: 4895 .H LDR r0,[pc,#596] ; [0x1ffc] = 0x10004fe0 + 0x00001da6: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x00001da8: 2000 . MOVS r0,#0 + 0x00001daa: 4b98 .K LDR r3,[pc,#608] ; [0x200c] = 0x10008300 + 0x00001dac: 781b .x LDRB r3,[r3,#0] + 0x00001dae: 4300 .C ORRS r0,r0,r0 + 0x00001db0: 4b96 .K LDR r3,[pc,#600] ; [0x200c] = 0x10008300 + 0x00001db2: 781b .x LDRB r3,[r3,#0] + 0x00001db4: 4318 .C ORRS r0,r0,r3 + 0x00001db6: 4b91 .K LDR r3,[pc,#580] ; [0x1ffc] = 0x10004fe0 + 0x00001db8: 7fdb .. LDRB r3,[r3,#0x1f] + 0x00001dba: 2300 .# MOVS r3,#0 + 0x00001dbc: 4c93 .L LDR r4,[pc,#588] ; [0x200c] = 0x10008300 + 0x00001dbe: 7864 dx LDRB r4,[r4,#1] + 0x00001dc0: 431b .C ORRS r3,r3,r3 + 0x00001dc2: 4c92 .L LDR r4,[pc,#584] ; [0x200c] = 0x10008300 + 0x00001dc4: 7864 dx LDRB r4,[r4,#1] + 0x00001dc6: 4323 #C ORRS r3,r3,r4 + 0x00001dc8: 021b .. LSLS r3,r3,#8 + 0x00001dca: 4318 .C ORRS r0,r0,r3 + 0x00001dcc: 4b8b .K LDR r3,[pc,#556] ; [0x1ffc] = 0x10004fe0 + 0x00001dce: 7fdb .. LDRB r3,[r3,#0x1f] + 0x00001dd0: 2300 .# MOVS r3,#0 + 0x00001dd2: 4c8e .L LDR r4,[pc,#568] ; [0x200c] = 0x10008300 + 0x00001dd4: 78a4 .x LDRB r4,[r4,#2] + 0x00001dd6: 431b .C ORRS r3,r3,r3 + 0x00001dd8: 4c8c .L LDR r4,[pc,#560] ; [0x200c] = 0x10008300 + 0x00001dda: 78a4 .x LDRB r4,[r4,#2] + 0x00001ddc: 4323 #C ORRS r3,r3,r4 + 0x00001dde: 041b .. LSLS r3,r3,#16 + 0x00001de0: 4318 .C ORRS r0,r0,r3 + 0x00001de2: 4b86 .K LDR r3,[pc,#536] ; [0x1ffc] = 0x10004fe0 + 0x00001de4: 7fdb .. LDRB r3,[r3,#0x1f] + 0x00001de6: 2300 .# MOVS r3,#0 + 0x00001de8: 4c88 .L LDR r4,[pc,#544] ; [0x200c] = 0x10008300 + 0x00001dea: 78e4 .x LDRB r4,[r4,#3] + 0x00001dec: 431b .C ORRS r3,r3,r3 + 0x00001dee: 4c87 .L LDR r4,[pc,#540] ; [0x200c] = 0x10008300 + 0x00001df0: 78e4 .x LDRB r4,[r4,#3] + 0x00001df2: 4323 #C ORRS r3,r3,r4 + 0x00001df4: 061b .. LSLS r3,r3,#24 + 0x00001df6: 4318 .C ORRS r0,r0,r3 + 0x00001df8: 4601 .F MOV r1,r0 + 0x00001dfa: 2200 ." MOVS r2,#0 + 0x00001dfc: 4884 .H LDR r0,[pc,#528] ; [0x2010] = 0x10011008 + 0x00001dfe: 6800 .h LDR r0,[r0,#0] + 0x00001e00: 2800 .( CMP r0,#0 + 0x00001e02: d102 .. BNE 0x1e0a ; SYS_ClkTicks + 114 + 0x00001e04: 4882 .H LDR r0,[pc,#520] ; [0x2010] = 0x10011008 + 0x00001e06: 6001 .` STR r1,[r0,#0] + 0x00001e08: e017 .. B 0x1e3a ; SYS_ClkTicks + 162 + 0x00001e0a: 4881 .H LDR r0,[pc,#516] ; [0x2010] = 0x10011008 + 0x00001e0c: 6800 .h LDR r0,[r0,#0] + 0x00001e0e: 4288 .B CMP r0,r1 + 0x00001e10: d902 .. BLS 0x1e18 ; SYS_ClkTicks + 128 + 0x00001e12: 487f .H LDR r0,[pc,#508] ; [0x2010] = 0x10011008 + 0x00001e14: 6001 .` STR r1,[r0,#0] + 0x00001e16: e7c4 .. B 0x1da2 ; SYS_ClkTicks + 10 + 0x00001e18: 487d }H LDR r0,[pc,#500] ; [0x2010] = 0x10011008 + 0x00001e1a: 6800 .h LDR r0,[r0,#0] + 0x00001e1c: 1a0a .. SUBS r2,r1,r0 + 0x00001e1e: e00a .. B 0x1e36 ; SYS_ClkTicks + 158 + 0x00001e20: 487c |H LDR r0,[pc,#496] ; [0x2014] = 0x10011004 + 0x00001e22: 6800 .h LDR r0,[r0,#0] + 0x00001e24: 1c40 @. ADDS r0,r0,#1 + 0x00001e26: 4b7b {K LDR r3,[pc,#492] ; [0x2014] = 0x10011004 + 0x00001e28: 6018 .` STR r0,[r3,#0] + 0x00001e2a: 4879 yH LDR r0,[pc,#484] ; [0x2010] = 0x10011008 + 0x00001e2c: 6800 .h LDR r0,[r0,#0] + 0x00001e2e: 3020 0 ADDS r0,r0,#0x20 + 0x00001e30: 4b77 wK LDR r3,[pc,#476] ; [0x2010] = 0x10011008 + 0x00001e32: 6018 .` STR r0,[r3,#0] + 0x00001e34: 3a20 : SUBS r2,r2,#0x20 + 0x00001e36: 2a20 * CMP r2,#0x20 + 0x00001e38: d2f2 .. BCS 0x1e20 ; SYS_ClkTicks + 136 + 0x00001e3a: bf00 .. NOP + 0x00001e3c: e7b1 .. B 0x1da2 ; SYS_ClkTicks + 10 SYS_TimerStartTickTimer - 0x00001f32: b510 .. PUSH {r4,lr} - 0x00001f34: 4604 .F MOV r4,r0 - 0x00001f36: f7ffffa9 .... BL SYS_ClkTicks ; 0x1e8c - 0x00001f3a: 4620 F MOV r0,r4 - 0x00001f3c: f7fffeff .... BL SYS_ChangeDPLL ; 0x1d3e - 0x00001f40: bd10 .. POP {r4,pc} + 0x00001e3e: b510 .. PUSH {r4,lr} + 0x00001e40: 4604 .F MOV r4,r0 + 0x00001e42: f7ffffa9 .... BL SYS_ClkTicks ; 0x1d98 + 0x00001e46: 4620 F MOV r0,r4 + 0x00001e48: f7fffeff .... BL SYS_ChangeDPLL ; 0x1c4a + 0x00001e4c: bd10 .. POP {r4,pc} SYS_TimerInit - 0x00001f42: b510 .. PUSH {r4,lr} - 0x00001f44: 4604 .F MOV r4,r0 - 0x00001f46: 4871 qH LDR r0,[pc,#452] ; [0x210c] = 0x1001102c - 0x00001f48: 4971 qI LDR r1,[pc,#452] ; [0x2110] = 0x10011004 - 0x00001f4a: 6008 .` STR r0,[r1,#0] - 0x00001f4c: 2000 . MOVS r0,#0 - 0x00001f4e: 6809 .h LDR r1,[r1,#0] - 0x00001f50: 60c8 .` STR r0,[r1,#0xc] - 0x00001f52: 4870 pH LDR r0,[pc,#448] ; [0x2114] = 0x1cf5 - 0x00001f54: 496e nI LDR r1,[pc,#440] ; [0x2110] = 0x10011004 - 0x00001f56: 6809 .h LDR r1,[r1,#0] - 0x00001f58: 6088 .` STR r0,[r1,#8] - 0x00001f5a: 2001 . MOVS r0,#1 - 0x00001f5c: 496c lI LDR r1,[pc,#432] ; [0x2110] = 0x10011004 - 0x00001f5e: 6809 .h LDR r1,[r1,#0] - 0x00001f60: 7508 .u STRB r0,[r1,#0x14] - 0x00001f62: 2000 . MOVS r0,#0 - 0x00001f64: 496a jI LDR r1,[pc,#424] ; [0x2110] = 0x10011004 - 0x00001f66: 6809 .h LDR r1,[r1,#0] - 0x00001f68: 6008 .` STR r0,[r1,#0] - 0x00001f6a: 4966 fI LDR r1,[pc,#408] ; [0x2104] = 0x1001100c - 0x00001f6c: 6008 .` STR r0,[r1,#0] - 0x00001f6e: 4620 F MOV r0,r4 - 0x00001f70: f7ffffdf .... BL SYS_TimerStartTickTimer ; 0x1f32 - 0x00001f74: bd10 .. POP {r4,pc} + 0x00001e4e: b510 .. PUSH {r4,lr} + 0x00001e50: 4604 .F MOV r4,r0 + 0x00001e52: 4871 qH LDR r0,[pc,#452] ; [0x2018] = 0x1001101c + 0x00001e54: 4971 qI LDR r1,[pc,#452] ; [0x201c] = 0x10011000 + 0x00001e56: 6008 .` STR r0,[r1,#0] + 0x00001e58: 2000 . MOVS r0,#0 + 0x00001e5a: 6809 .h LDR r1,[r1,#0] + 0x00001e5c: 60c8 .` STR r0,[r1,#0xc] + 0x00001e5e: 4870 pH LDR r0,[pc,#448] ; [0x2020] = 0x1c01 + 0x00001e60: 496e nI LDR r1,[pc,#440] ; [0x201c] = 0x10011000 + 0x00001e62: 6809 .h LDR r1,[r1,#0] + 0x00001e64: 6088 .` STR r0,[r1,#8] + 0x00001e66: 2001 . MOVS r0,#1 + 0x00001e68: 496c lI LDR r1,[pc,#432] ; [0x201c] = 0x10011000 + 0x00001e6a: 6809 .h LDR r1,[r1,#0] + 0x00001e6c: 7508 .u STRB r0,[r1,#0x14] + 0x00001e6e: 2000 . MOVS r0,#0 + 0x00001e70: 496a jI LDR r1,[pc,#424] ; [0x201c] = 0x10011000 + 0x00001e72: 6809 .h LDR r1,[r1,#0] + 0x00001e74: 6008 .` STR r0,[r1,#0] + 0x00001e76: 4966 fI LDR r1,[pc,#408] ; [0x2010] = 0x10011008 + 0x00001e78: 6008 .` STR r0,[r1,#0] + 0x00001e7a: 4620 F MOV r0,r4 + 0x00001e7c: f7ffffdf .... BL SYS_TimerStartTickTimer ; 0x1e3e + 0x00001e80: bd10 .. POP {r4,pc} SYS_TimerisExist - 0x00001f76: 4602 .F MOV r2,r0 - 0x00001f78: 4865 eH LDR r0,[pc,#404] ; [0x2110] = 0x10011004 - 0x00001f7a: 6800 .h LDR r0,[r0,#0] - 0x00001f7c: 2800 .( CMP r0,#0 - 0x00001f7e: d100 .. BNE 0x1f82 ; SYS_TimerisExist + 12 - 0x00001f80: 4770 pG BX lr - 0x00001f82: 2a00 .* CMP r2,#0 - 0x00001f84: d101 .. BNE 0x1f8a ; SYS_TimerisExist + 20 - 0x00001f86: 2000 . MOVS r0,#0 - 0x00001f88: e7fa .. B 0x1f80 ; SYS_TimerisExist + 10 - 0x00001f8a: 4861 aH LDR r0,[pc,#388] ; [0x2110] = 0x10011004 - 0x00001f8c: 6801 .h LDR r1,[r0,#0] - 0x00001f8e: e004 .. B 0x1f9a ; SYS_TimerisExist + 36 - 0x00001f90: 428a .B CMP r2,r1 - 0x00001f92: d101 .. BNE 0x1f98 ; SYS_TimerisExist + 34 - 0x00001f94: 2001 . MOVS r0,#1 - 0x00001f96: e7f3 .. B 0x1f80 ; SYS_TimerisExist + 10 - 0x00001f98: 68c9 .h LDR r1,[r1,#0xc] - 0x00001f9a: 68c8 .h LDR r0,[r1,#0xc] - 0x00001f9c: 2800 .( CMP r0,#0 - 0x00001f9e: d1f7 .. BNE 0x1f90 ; SYS_TimerisExist + 26 - 0x00001fa0: bf00 .. NOP - 0x00001fa2: e7ed .. B 0x1f80 ; SYS_TimerisExist + 10 + 0x00001e82: 4602 .F MOV r2,r0 + 0x00001e84: 4865 eH LDR r0,[pc,#404] ; [0x201c] = 0x10011000 + 0x00001e86: 6800 .h LDR r0,[r0,#0] + 0x00001e88: 2800 .( CMP r0,#0 + 0x00001e8a: d100 .. BNE 0x1e8e ; SYS_TimerisExist + 12 + 0x00001e8c: 4770 pG BX lr + 0x00001e8e: 2a00 .* CMP r2,#0 + 0x00001e90: d101 .. BNE 0x1e96 ; SYS_TimerisExist + 20 + 0x00001e92: 2000 . MOVS r0,#0 + 0x00001e94: e7fa .. B 0x1e8c ; SYS_TimerisExist + 10 + 0x00001e96: 4861 aH LDR r0,[pc,#388] ; [0x201c] = 0x10011000 + 0x00001e98: 6801 .h LDR r1,[r0,#0] + 0x00001e9a: e004 .. B 0x1ea6 ; SYS_TimerisExist + 36 + 0x00001e9c: 428a .B CMP r2,r1 + 0x00001e9e: d101 .. BNE 0x1ea4 ; SYS_TimerisExist + 34 + 0x00001ea0: 2001 . MOVS r0,#1 + 0x00001ea2: e7f3 .. B 0x1e8c ; SYS_TimerisExist + 10 + 0x00001ea4: 68c9 .h LDR r1,[r1,#0xc] + 0x00001ea6: 68c8 .h LDR r0,[r1,#0xc] + 0x00001ea8: 2800 .( CMP r0,#0 + 0x00001eaa: d1f7 .. BNE 0x1e9c ; SYS_TimerisExist + 26 + 0x00001eac: bf00 .. NOP + 0x00001eae: e7ed .. B 0x1e8c ; SYS_TimerisExist + 10 SYS_SetTimer - 0x00001fa4: b5f0 .. PUSH {r4-r7,lr} - 0x00001fa6: 4604 .F MOV r4,r0 - 0x00001fa8: 460d .F MOV r5,r1 - 0x00001faa: 4616 .F MOV r6,r2 - 0x00001fac: 4858 XH LDR r0,[pc,#352] ; [0x2110] = 0x10011004 - 0x00001fae: 6800 .h LDR r0,[r0,#0] - 0x00001fb0: 2800 .( CMP r0,#0 - 0x00001fb2: d100 .. BNE 0x1fb6 ; SYS_SetTimer + 18 - 0x00001fb4: bdf0 .. POP {r4-r7,pc} - 0x00001fb6: 2c00 ., CMP r4,#0 - 0x00001fb8: d101 .. BNE 0x1fbe ; SYS_SetTimer + 26 - 0x00001fba: 2000 . MOVS r0,#0 - 0x00001fbc: e7fa .. B 0x1fb4 ; SYS_SetTimer + 16 - 0x00001fbe: 2b00 .+ CMP r3,#0 - 0x00001fc0: d102 .. BNE 0x1fc8 ; SYS_SetTimer + 36 - 0x00001fc2: 4854 TH LDR r0,[pc,#336] ; [0x2114] = 0x1cf5 - 0x00001fc4: 60a0 .` STR r0,[r4,#8] - 0x00001fc6: e000 .. B 0x1fca ; SYS_SetTimer + 38 - 0x00001fc8: 60a3 .` STR r3,[r4,#8] - 0x00001fca: b672 r. CPSID i - 0x00001fcc: 484e NH LDR r0,[pc,#312] ; [0x2108] = 0x10011008 - 0x00001fce: 6800 .h LDR r0,[r0,#0] - 0x00001fd0: 1940 @. ADDS r0,r0,r5 - 0x00001fd2: 6020 ` STR r0,[r4,#0] - 0x00001fd4: 6065 e` STR r5,[r4,#4] - 0x00001fd6: 2001 . MOVS r0,#1 - 0x00001fd8: 7520 u STRB r0,[r4,#0x14] - 0x00001fda: 06b0 .. LSLS r0,r6,#26 - 0x00001fdc: 0e80 .. LSRS r0,r0,#26 - 0x00001fde: 7560 `u STRB r0,[r4,#0x15] - 0x00001fe0: 4620 F MOV r0,r4 - 0x00001fe2: f7ffffc8 .... BL SYS_TimerisExist ; 0x1f76 - 0x00001fe6: 2800 .( CMP r0,#0 - 0x00001fe8: d002 .. BEQ 0x1ff0 ; SYS_SetTimer + 76 - 0x00001fea: b662 b. CPSIE i - 0x00001fec: 2001 . MOVS r0,#1 - 0x00001fee: e7e1 .. B 0x1fb4 ; SYS_SetTimer + 16 - 0x00001ff0: 4847 GH LDR r0,[pc,#284] ; [0x2110] = 0x10011004 - 0x00001ff2: 6807 .h LDR r7,[r0,#0] - 0x00001ff4: 6004 .` STR r4,[r0,#0] - 0x00001ff6: 6800 .h LDR r0,[r0,#0] - 0x00001ff8: 60c7 .` STR r7,[r0,#0xc] - 0x00001ffa: b662 b. CPSIE i - 0x00001ffc: 2001 . MOVS r0,#1 - 0x00001ffe: e7d9 .. B 0x1fb4 ; SYS_SetTimer + 16 + 0x00001eb0: b5f0 .. PUSH {r4-r7,lr} + 0x00001eb2: 4604 .F MOV r4,r0 + 0x00001eb4: 460d .F MOV r5,r1 + 0x00001eb6: 4616 .F MOV r6,r2 + 0x00001eb8: 4858 XH LDR r0,[pc,#352] ; [0x201c] = 0x10011000 + 0x00001eba: 6800 .h LDR r0,[r0,#0] + 0x00001ebc: 2800 .( CMP r0,#0 + 0x00001ebe: d100 .. BNE 0x1ec2 ; SYS_SetTimer + 18 + 0x00001ec0: bdf0 .. POP {r4-r7,pc} + 0x00001ec2: 2c00 ., CMP r4,#0 + 0x00001ec4: d101 .. BNE 0x1eca ; SYS_SetTimer + 26 + 0x00001ec6: 2000 . MOVS r0,#0 + 0x00001ec8: e7fa .. B 0x1ec0 ; SYS_SetTimer + 16 + 0x00001eca: 2b00 .+ CMP r3,#0 + 0x00001ecc: d102 .. BNE 0x1ed4 ; SYS_SetTimer + 36 + 0x00001ece: 4854 TH LDR r0,[pc,#336] ; [0x2020] = 0x1c01 + 0x00001ed0: 60a0 .` STR r0,[r4,#8] + 0x00001ed2: e000 .. B 0x1ed6 ; SYS_SetTimer + 38 + 0x00001ed4: 60a3 .` STR r3,[r4,#8] + 0x00001ed6: b672 r. CPSID i + 0x00001ed8: 484e NH LDR r0,[pc,#312] ; [0x2014] = 0x10011004 + 0x00001eda: 6800 .h LDR r0,[r0,#0] + 0x00001edc: 1940 @. ADDS r0,r0,r5 + 0x00001ede: 6020 ` STR r0,[r4,#0] + 0x00001ee0: 6065 e` STR r5,[r4,#4] + 0x00001ee2: 2001 . MOVS r0,#1 + 0x00001ee4: 7520 u STRB r0,[r4,#0x14] + 0x00001ee6: 06b0 .. LSLS r0,r6,#26 + 0x00001ee8: 0e80 .. LSRS r0,r0,#26 + 0x00001eea: 7560 `u STRB r0,[r4,#0x15] + 0x00001eec: 4620 F MOV r0,r4 + 0x00001eee: f7ffffc8 .... BL SYS_TimerisExist ; 0x1e82 + 0x00001ef2: 2800 .( CMP r0,#0 + 0x00001ef4: d002 .. BEQ 0x1efc ; SYS_SetTimer + 76 + 0x00001ef6: b662 b. CPSIE i + 0x00001ef8: 2001 . MOVS r0,#1 + 0x00001efa: e7e1 .. B 0x1ec0 ; SYS_SetTimer + 16 + 0x00001efc: 4847 GH LDR r0,[pc,#284] ; [0x201c] = 0x10011000 + 0x00001efe: 6807 .h LDR r7,[r0,#0] + 0x00001f00: 6004 .` STR r4,[r0,#0] + 0x00001f02: 6800 .h LDR r0,[r0,#0] + 0x00001f04: 60c7 .` STR r7,[r0,#0xc] + 0x00001f06: b662 b. CPSIE i + 0x00001f08: 2001 . MOVS r0,#1 + 0x00001f0a: e7d9 .. B 0x1ec0 ; SYS_SetTimer + 16 SYS_ResetTimer - 0x00002000: 4601 .F MOV r1,r0 - 0x00002002: 4843 CH LDR r0,[pc,#268] ; [0x2110] = 0x10011004 - 0x00002004: 6800 .h LDR r0,[r0,#0] - 0x00002006: 2800 .( CMP r0,#0 - 0x00002008: d100 .. BNE 0x200c ; SYS_ResetTimer + 12 - 0x0000200a: 4770 pG BX lr - 0x0000200c: 2900 .) CMP r1,#0 - 0x0000200e: d101 .. BNE 0x2014 ; SYS_ResetTimer + 20 - 0x00002010: 2000 . MOVS r0,#0 - 0x00002012: e7fa .. B 0x200a ; SYS_ResetTimer + 10 - 0x00002014: 483e >H LDR r0,[pc,#248] ; [0x2110] = 0x10011004 - 0x00002016: 6802 .h LDR r2,[r0,#0] - 0x00002018: e009 .. B 0x202e ; SYS_ResetTimer + 46 - 0x0000201a: 4291 .B CMP r1,r2 - 0x0000201c: d106 .. BNE 0x202c ; SYS_ResetTimer + 44 - 0x0000201e: 4b3a :K LDR r3,[pc,#232] ; [0x2108] = 0x10011008 - 0x00002020: 6848 Hh LDR r0,[r1,#4] - 0x00002022: 681b .h LDR r3,[r3,#0] - 0x00002024: 18c0 .. ADDS r0,r0,r3 - 0x00002026: 6008 .` STR r0,[r1,#0] - 0x00002028: 2001 . MOVS r0,#1 - 0x0000202a: e7ee .. B 0x200a ; SYS_ResetTimer + 10 - 0x0000202c: 68d2 .h LDR r2,[r2,#0xc] - 0x0000202e: 68d0 .h LDR r0,[r2,#0xc] - 0x00002030: 2800 .( CMP r0,#0 - 0x00002032: d1f2 .. BNE 0x201a ; SYS_ResetTimer + 26 - 0x00002034: bf00 .. NOP - 0x00002036: e7e8 .. B 0x200a ; SYS_ResetTimer + 10 + 0x00001f0c: 4601 .F MOV r1,r0 + 0x00001f0e: 4843 CH LDR r0,[pc,#268] ; [0x201c] = 0x10011000 + 0x00001f10: 6800 .h LDR r0,[r0,#0] + 0x00001f12: 2800 .( CMP r0,#0 + 0x00001f14: d100 .. BNE 0x1f18 ; SYS_ResetTimer + 12 + 0x00001f16: 4770 pG BX lr + 0x00001f18: 2900 .) CMP r1,#0 + 0x00001f1a: d101 .. BNE 0x1f20 ; SYS_ResetTimer + 20 + 0x00001f1c: 2000 . MOVS r0,#0 + 0x00001f1e: e7fa .. B 0x1f16 ; SYS_ResetTimer + 10 + 0x00001f20: 483e >H LDR r0,[pc,#248] ; [0x201c] = 0x10011000 + 0x00001f22: 6802 .h LDR r2,[r0,#0] + 0x00001f24: e009 .. B 0x1f3a ; SYS_ResetTimer + 46 + 0x00001f26: 4291 .B CMP r1,r2 + 0x00001f28: d106 .. BNE 0x1f38 ; SYS_ResetTimer + 44 + 0x00001f2a: 4b3a :K LDR r3,[pc,#232] ; [0x2014] = 0x10011004 + 0x00001f2c: 6848 Hh LDR r0,[r1,#4] + 0x00001f2e: 681b .h LDR r3,[r3,#0] + 0x00001f30: 18c0 .. ADDS r0,r0,r3 + 0x00001f32: 6008 .` STR r0,[r1,#0] + 0x00001f34: 2001 . MOVS r0,#1 + 0x00001f36: e7ee .. B 0x1f16 ; SYS_ResetTimer + 10 + 0x00001f38: 68d2 .h LDR r2,[r2,#0xc] + 0x00001f3a: 68d0 .h LDR r0,[r2,#0xc] + 0x00001f3c: 2800 .( CMP r0,#0 + 0x00001f3e: d1f2 .. BNE 0x1f26 ; SYS_ResetTimer + 26 + 0x00001f40: bf00 .. NOP + 0x00001f42: e7e8 .. B 0x1f16 ; SYS_ResetTimer + 10 SYS_TimerTest - 0x00002038: 2100 .! MOVS r1,#0 - 0x0000203a: 4a35 5J LDR r2,[pc,#212] ; [0x2110] = 0x10011004 - 0x0000203c: 6810 .h LDR r0,[r2,#0] - 0x0000203e: e001 .. B 0x2044 ; SYS_TimerTest + 12 - 0x00002040: 1c49 I. ADDS r1,r1,#1 - 0x00002042: 68c0 .h LDR r0,[r0,#0xc] - 0x00002044: 68c2 .h LDR r2,[r0,#0xc] - 0x00002046: 2a00 .* CMP r2,#0 - 0x00002048: d1fa .. BNE 0x2040 ; SYS_TimerTest + 8 - 0x0000204a: 4770 pG BX lr + 0x00001f44: 2100 .! MOVS r1,#0 + 0x00001f46: 4a35 5J LDR r2,[pc,#212] ; [0x201c] = 0x10011000 + 0x00001f48: 6810 .h LDR r0,[r2,#0] + 0x00001f4a: e001 .. B 0x1f50 ; SYS_TimerTest + 12 + 0x00001f4c: 1c49 I. ADDS r1,r1,#1 + 0x00001f4e: 68c0 .h LDR r0,[r0,#0xc] + 0x00001f50: 68c2 .h LDR r2,[r0,#0xc] + 0x00001f52: 2a00 .* CMP r2,#0 + 0x00001f54: d1fa .. BNE 0x1f4c ; SYS_TimerTest + 8 + 0x00001f56: 4770 pG BX lr SYS_ReleaseTimer - 0x0000204c: b510 .. PUSH {r4,lr} - 0x0000204e: 4602 .F MOV r2,r0 - 0x00002050: 482f /H LDR r0,[pc,#188] ; [0x2110] = 0x10011004 - 0x00002052: 6800 .h LDR r0,[r0,#0] - 0x00002054: 2800 .( CMP r0,#0 - 0x00002056: d100 .. BNE 0x205a ; SYS_ReleaseTimer + 14 - 0x00002058: bd10 .. POP {r4,pc} - 0x0000205a: 2a00 .* CMP r2,#0 - 0x0000205c: d101 .. BNE 0x2062 ; SYS_ReleaseTimer + 22 - 0x0000205e: 2000 . MOVS r0,#0 - 0x00002060: e7fa .. B 0x2058 ; SYS_ReleaseTimer + 12 - 0x00002062: 482a *H LDR r0,[pc,#168] ; [0x210c] = 0x1001102c - 0x00002064: 4282 .B CMP r2,r0 - 0x00002066: d101 .. BNE 0x206c ; SYS_ReleaseTimer + 32 - 0x00002068: 2000 . MOVS r0,#0 - 0x0000206a: e7f5 .. B 0x2058 ; SYS_ReleaseTimer + 12 - 0x0000206c: 4828 (H LDR r0,[pc,#160] ; [0x2110] = 0x10011004 - 0x0000206e: 6801 .h LDR r1,[r0,#0] - 0x00002070: 460b .F MOV r3,r1 - 0x00002072: e00f .. B 0x2094 ; SYS_ReleaseTimer + 72 - 0x00002074: 428a .B CMP r2,r1 - 0x00002076: d10b .. BNE 0x2090 ; SYS_ReleaseTimer + 68 - 0x00002078: 2000 . MOVS r0,#0 - 0x0000207a: 7508 .u STRB r0,[r1,#0x14] - 0x0000207c: 428b .B CMP r3,r1 - 0x0000207e: d103 .. BNE 0x2088 ; SYS_ReleaseTimer + 60 - 0x00002080: 4c23 #L LDR r4,[pc,#140] ; [0x2110] = 0x10011004 - 0x00002082: 68c8 .h LDR r0,[r1,#0xc] - 0x00002084: 6020 ` STR r0,[r4,#0] - 0x00002086: e001 .. B 0x208c ; SYS_ReleaseTimer + 64 - 0x00002088: 68c8 .h LDR r0,[r1,#0xc] - 0x0000208a: 60d8 .` STR r0,[r3,#0xc] - 0x0000208c: 2001 . MOVS r0,#1 - 0x0000208e: e7e3 .. B 0x2058 ; SYS_ReleaseTimer + 12 - 0x00002090: 460b .F MOV r3,r1 - 0x00002092: 68c9 .h LDR r1,[r1,#0xc] - 0x00002094: 68c8 .h LDR r0,[r1,#0xc] - 0x00002096: 2800 .( CMP r0,#0 - 0x00002098: d1ec .. BNE 0x2074 ; SYS_ReleaseTimer + 40 - 0x0000209a: bf00 .. NOP - 0x0000209c: e7dc .. B 0x2058 ; SYS_ReleaseTimer + 12 + 0x00001f58: b510 .. PUSH {r4,lr} + 0x00001f5a: 4602 .F MOV r2,r0 + 0x00001f5c: 482f /H LDR r0,[pc,#188] ; [0x201c] = 0x10011000 + 0x00001f5e: 6800 .h LDR r0,[r0,#0] + 0x00001f60: 2800 .( CMP r0,#0 + 0x00001f62: d100 .. BNE 0x1f66 ; SYS_ReleaseTimer + 14 + 0x00001f64: bd10 .. POP {r4,pc} + 0x00001f66: 2a00 .* CMP r2,#0 + 0x00001f68: d101 .. BNE 0x1f6e ; SYS_ReleaseTimer + 22 + 0x00001f6a: 2000 . MOVS r0,#0 + 0x00001f6c: e7fa .. B 0x1f64 ; SYS_ReleaseTimer + 12 + 0x00001f6e: 482a *H LDR r0,[pc,#168] ; [0x2018] = 0x1001101c + 0x00001f70: 4282 .B CMP r2,r0 + 0x00001f72: d101 .. BNE 0x1f78 ; SYS_ReleaseTimer + 32 + 0x00001f74: 2000 . MOVS r0,#0 + 0x00001f76: e7f5 .. B 0x1f64 ; SYS_ReleaseTimer + 12 + 0x00001f78: 4828 (H LDR r0,[pc,#160] ; [0x201c] = 0x10011000 + 0x00001f7a: 6801 .h LDR r1,[r0,#0] + 0x00001f7c: 460b .F MOV r3,r1 + 0x00001f7e: e00f .. B 0x1fa0 ; SYS_ReleaseTimer + 72 + 0x00001f80: 428a .B CMP r2,r1 + 0x00001f82: d10b .. BNE 0x1f9c ; SYS_ReleaseTimer + 68 + 0x00001f84: 2000 . MOVS r0,#0 + 0x00001f86: 7508 .u STRB r0,[r1,#0x14] + 0x00001f88: 428b .B CMP r3,r1 + 0x00001f8a: d103 .. BNE 0x1f94 ; SYS_ReleaseTimer + 60 + 0x00001f8c: 4c23 #L LDR r4,[pc,#140] ; [0x201c] = 0x10011000 + 0x00001f8e: 68c8 .h LDR r0,[r1,#0xc] + 0x00001f90: 6020 ` STR r0,[r4,#0] + 0x00001f92: e001 .. B 0x1f98 ; SYS_ReleaseTimer + 64 + 0x00001f94: 68c8 .h LDR r0,[r1,#0xc] + 0x00001f96: 60d8 .` STR r0,[r3,#0xc] + 0x00001f98: 2001 . MOVS r0,#1 + 0x00001f9a: e7e3 .. B 0x1f64 ; SYS_ReleaseTimer + 12 + 0x00001f9c: 460b .F MOV r3,r1 + 0x00001f9e: 68c9 .h LDR r1,[r1,#0xc] + 0x00001fa0: 68c8 .h LDR r0,[r1,#0xc] + 0x00001fa2: 2800 .( CMP r0,#0 + 0x00001fa4: d1ec .. BNE 0x1f80 ; SYS_ReleaseTimer + 40 + 0x00001fa6: bf00 .. NOP + 0x00001fa8: e7dc .. B 0x1f64 ; SYS_ReleaseTimer + 12 SYS_timerPolling - 0x0000209e: b510 .. PUSH {r4,lr} - 0x000020a0: 481d .H LDR r0,[pc,#116] ; [0x2118] = 0x10011010 - 0x000020a2: 7800 .x LDRB r0,[r0,#0] - 0x000020a4: 2800 .( CMP r0,#0 - 0x000020a6: d022 ". BEQ 0x20ee ; SYS_timerPolling + 80 - 0x000020a8: 2000 . MOVS r0,#0 - 0x000020aa: 491b .I LDR r1,[pc,#108] ; [0x2118] = 0x10011010 - 0x000020ac: 7008 .p STRB r0,[r1,#0] - 0x000020ae: f7ffffc3 .... BL SYS_TimerTest ; 0x2038 - 0x000020b2: 4817 .H LDR r0,[pc,#92] ; [0x2110] = 0x10011004 - 0x000020b4: 6804 .h LDR r4,[r0,#0] - 0x000020b6: e017 .. B 0x20e8 ; SYS_timerPolling + 74 - 0x000020b8: 7d20 } LDRB r0,[r4,#0x14] - 0x000020ba: 2801 .( CMP r0,#1 - 0x000020bc: d113 .. BNE 0x20e6 ; SYS_timerPolling + 72 - 0x000020be: 4912 .I LDR r1,[pc,#72] ; [0x2108] = 0x10011008 - 0x000020c0: 6820 h LDR r0,[r4,#0] - 0x000020c2: 6809 .h LDR r1,[r1,#0] - 0x000020c4: 4288 .B CMP r0,r1 - 0x000020c6: d80e .. BHI 0x20e6 ; SYS_timerPolling + 72 - 0x000020c8: 7d60 `} LDRB r0,[r4,#0x15] - 0x000020ca: 2800 .( CMP r0,#0 - 0x000020cc: d103 .. BNE 0x20d6 ; SYS_timerPolling + 56 - 0x000020ce: 4620 F MOV r0,r4 - 0x000020d0: f7ffffbc .... BL SYS_ReleaseTimer ; 0x204c - 0x000020d4: e004 .. B 0x20e0 ; SYS_timerPolling + 66 - 0x000020d6: 490c .I LDR r1,[pc,#48] ; [0x2108] = 0x10011008 - 0x000020d8: 6860 `h LDR r0,[r4,#4] - 0x000020da: 6809 .h LDR r1,[r1,#0] - 0x000020dc: 1840 @. ADDS r0,r0,r1 - 0x000020de: 6020 ` STR r0,[r4,#0] - 0x000020e0: 68a1 .h LDR r1,[r4,#8] - 0x000020e2: 6920 i LDR r0,[r4,#0x10] - 0x000020e4: 4788 .G BLX r1 - 0x000020e6: 68e4 .h LDR r4,[r4,#0xc] - 0x000020e8: 68e0 .h LDR r0,[r4,#0xc] - 0x000020ea: 2800 .( CMP r0,#0 - 0x000020ec: d1e4 .. BNE 0x20b8 ; SYS_timerPolling + 26 - 0x000020ee: bd10 .. POP {r4,pc} + 0x00001faa: b510 .. PUSH {r4,lr} + 0x00001fac: 481d .H LDR r0,[pc,#116] ; [0x2024] = 0x1001100c + 0x00001fae: 7800 .x LDRB r0,[r0,#0] + 0x00001fb0: 2800 .( CMP r0,#0 + 0x00001fb2: d022 ". BEQ 0x1ffa ; SYS_timerPolling + 80 + 0x00001fb4: 2000 . MOVS r0,#0 + 0x00001fb6: 491b .I LDR r1,[pc,#108] ; [0x2024] = 0x1001100c + 0x00001fb8: 7008 .p STRB r0,[r1,#0] + 0x00001fba: f7ffffc3 .... BL SYS_TimerTest ; 0x1f44 + 0x00001fbe: 4817 .H LDR r0,[pc,#92] ; [0x201c] = 0x10011000 + 0x00001fc0: 6804 .h LDR r4,[r0,#0] + 0x00001fc2: e017 .. B 0x1ff4 ; SYS_timerPolling + 74 + 0x00001fc4: 7d20 } LDRB r0,[r4,#0x14] + 0x00001fc6: 2801 .( CMP r0,#1 + 0x00001fc8: d113 .. BNE 0x1ff2 ; SYS_timerPolling + 72 + 0x00001fca: 4912 .I LDR r1,[pc,#72] ; [0x2014] = 0x10011004 + 0x00001fcc: 6820 h LDR r0,[r4,#0] + 0x00001fce: 6809 .h LDR r1,[r1,#0] + 0x00001fd0: 4288 .B CMP r0,r1 + 0x00001fd2: d80e .. BHI 0x1ff2 ; SYS_timerPolling + 72 + 0x00001fd4: 7d60 `} LDRB r0,[r4,#0x15] + 0x00001fd6: 2800 .( CMP r0,#0 + 0x00001fd8: d103 .. BNE 0x1fe2 ; SYS_timerPolling + 56 + 0x00001fda: 4620 F MOV r0,r4 + 0x00001fdc: f7ffffbc .... BL SYS_ReleaseTimer ; 0x1f58 + 0x00001fe0: e004 .. B 0x1fec ; SYS_timerPolling + 66 + 0x00001fe2: 490c .I LDR r1,[pc,#48] ; [0x2014] = 0x10011004 + 0x00001fe4: 6860 `h LDR r0,[r4,#4] + 0x00001fe6: 6809 .h LDR r1,[r1,#0] + 0x00001fe8: 1840 @. ADDS r0,r0,r1 + 0x00001fea: 6020 ` STR r0,[r4,#0] + 0x00001fec: 68a1 .h LDR r1,[r4,#8] + 0x00001fee: 6920 i LDR r0,[r4,#0x10] + 0x00001ff0: 4788 .G BLX r1 + 0x00001ff2: 68e4 .h LDR r4,[r4,#0xc] + 0x00001ff4: 68e0 .h LDR r0,[r4,#0xc] + 0x00001ff6: 2800 .( CMP r0,#0 + 0x00001ff8: d1e4 .. BNE 0x1fc4 ; SYS_timerPolling + 26 + 0x00001ffa: bd10 .. POP {r4,pc} $d - 0x000020f0: 10004fe0 .O.. DCD 268455904 - 0x000020f4: 10008040 @... DCD 268468288 - 0x000020f8: 00002710 .'.. DCD 10000 - 0x000020fc: 10011011 .... DCD 268505105 - 0x00002100: 10008300 .... DCD 268468992 - 0x00002104: 1001100c .... DCD 268505100 - 0x00002108: 10011008 .... DCD 268505096 - 0x0000210c: 1001102c ,... DCD 268505132 - 0x00002110: 10011004 .... DCD 268505092 - 0x00002114: 00001cf5 .... DCD 7413 - 0x00002118: 10011010 .... DCD 268505104 + 0x00001ffc: 10004fe0 .O.. DCD 268455904 + 0x00002000: 10008040 @... DCD 268468288 + 0x00002004: 00002710 .'.. DCD 10000 + 0x00002008: 1001100d .... DCD 268505101 + 0x0000200c: 10008300 .... DCD 268468992 + 0x00002010: 10011008 .... DCD 268505096 + 0x00002014: 10011004 .... DCD 268505092 + 0x00002018: 1001101c .... DCD 268505116 + 0x0000201c: 10011000 .... DCD 268505088 + 0x00002020: 00001c01 .... DCD 7169 + 0x00002024: 1001100c .... DCD 268505100 $t SYS_ReleaseAllTimer - 0x0000211c: 492b +I LDR r1,[pc,#172] ; [0x21cc] = 0x10011004 - 0x0000211e: 6809 .h LDR r1,[r1,#0] - 0x00002120: 2900 .) CMP r1,#0 - 0x00002122: d100 .. BNE 0x2126 ; SYS_ReleaseAllTimer + 10 - 0x00002124: 4770 pG BX lr - 0x00002126: 4929 )I LDR r1,[pc,#164] ; [0x21cc] = 0x10011004 - 0x00002128: 6808 .h LDR r0,[r1,#0] - 0x0000212a: e002 .. B 0x2132 ; SYS_ReleaseAllTimer + 22 - 0x0000212c: 2100 .! MOVS r1,#0 - 0x0000212e: 7501 .u STRB r1,[r0,#0x14] - 0x00002130: 68c0 .h LDR r0,[r0,#0xc] - 0x00002132: 68c1 .h LDR r1,[r0,#0xc] - 0x00002134: 2900 .) CMP r1,#0 - 0x00002136: d1f9 .. BNE 0x212c ; SYS_ReleaseAllTimer + 16 - 0x00002138: 4925 %I LDR r1,[pc,#148] ; [0x21d0] = 0x1001102c - 0x0000213a: 4a24 $J LDR r2,[pc,#144] ; [0x21cc] = 0x10011004 - 0x0000213c: 6011 .` STR r1,[r2,#0] - 0x0000213e: bf00 .. NOP - 0x00002140: e7f0 .. B 0x2124 ; SYS_ReleaseAllTimer + 8 + 0x00002028: 492b +I LDR r1,[pc,#172] ; [0x20d8] = 0x10011000 + 0x0000202a: 6809 .h LDR r1,[r1,#0] + 0x0000202c: 2900 .) CMP r1,#0 + 0x0000202e: d100 .. BNE 0x2032 ; SYS_ReleaseAllTimer + 10 + 0x00002030: 4770 pG BX lr + 0x00002032: 4929 )I LDR r1,[pc,#164] ; [0x20d8] = 0x10011000 + 0x00002034: 6808 .h LDR r0,[r1,#0] + 0x00002036: e002 .. B 0x203e ; SYS_ReleaseAllTimer + 22 + 0x00002038: 2100 .! MOVS r1,#0 + 0x0000203a: 7501 .u STRB r1,[r0,#0x14] + 0x0000203c: 68c0 .h LDR r0,[r0,#0xc] + 0x0000203e: 68c1 .h LDR r1,[r0,#0xc] + 0x00002040: 2900 .) CMP r1,#0 + 0x00002042: d1f9 .. BNE 0x2038 ; SYS_ReleaseAllTimer + 16 + 0x00002044: 4925 %I LDR r1,[pc,#148] ; [0x20dc] = 0x1001101c + 0x00002046: 4a24 $J LDR r2,[pc,#144] ; [0x20d8] = 0x10011000 + 0x00002048: 6011 .` STR r1,[r2,#0] + 0x0000204a: bf00 .. NOP + 0x0000204c: e7f0 .. B 0x2030 ; SYS_ReleaseAllTimer + 8 SYStick_handle - 0x00002142: b500 .. PUSH {lr} - 0x00002144: f7fffea2 .... BL SYS_ClkTicks ; 0x1e8c - 0x00002148: 2001 . MOVS r0,#1 - 0x0000214a: 4922 "I LDR r1,[pc,#136] ; [0x21d4] = 0x10011010 - 0x0000214c: 7008 .p STRB r0,[r1,#0] - 0x0000214e: bd00 .. POP {pc} + 0x0000204e: b500 .. PUSH {lr} + 0x00002050: f7fffea2 .... BL SYS_ClkTicks ; 0x1d98 + 0x00002054: 2001 . MOVS r0,#1 + 0x00002056: 4922 "I LDR r1,[pc,#136] ; [0x20e0] = 0x1001100c + 0x00002058: 7008 .p STRB r0,[r1,#0] + 0x0000205a: bd00 .. POP {pc} Bt_100ms_timer - 0x00002150: b510 .. PUSH {r4,lr} - 0x00002152: 4604 .F MOV r4,r0 - 0x00002154: f7fffe9a .... BL SYS_ClkTicks ; 0x1e8c - 0x00002158: 2001 . MOVS r0,#1 - 0x0000215a: 491e .I LDR r1,[pc,#120] ; [0x21d4] = 0x10011010 - 0x0000215c: 7008 .p STRB r0,[r1,#0] - 0x0000215e: bd10 .. POP {r4,pc} + 0x0000205c: b510 .. PUSH {r4,lr} + 0x0000205e: 4604 .F MOV r4,r0 + 0x00002060: f7fffe9a .... BL SYS_ClkTicks ; 0x1d98 + 0x00002064: 2001 . MOVS r0,#1 + 0x00002066: 491e .I LDR r1,[pc,#120] ; [0x20e0] = 0x1001100c + 0x00002068: 7008 .p STRB r0,[r1,#0] + 0x0000206a: bd10 .. POP {r4,pc} SYS_delay_us - 0x00002160: b5fc .. PUSH {r2-r7,lr} - 0x00002162: 4607 .F MOV r7,r0 - 0x00002164: 2000 . MOVS r0,#0 - 0x00002166: 9001 .. STR r0,[sp,#4] - 0x00002168: 2500 .% MOVS r5,#0 - 0x0000216a: 2400 .$ MOVS r4,#0 - 0x0000216c: 2600 .& MOVS r6,#0 - 0x0000216e: f7fffdc4 .... BL SYS_TimerGet1usTicks ; 0x1cfa - 0x00002172: 4378 xC MULS r0,r7,r0 - 0x00002174: 9001 .. STR r0,[sp,#4] - 0x00002176: 4818 .H LDR r0,[pc,#96] ; [0x21d8] = 0xe000e000 - 0x00002178: 6940 @i LDR r0,[r0,#0x14] - 0x0000217a: 9000 .. STR r0,[sp,#0] - 0x0000217c: 4816 .H LDR r0,[pc,#88] ; [0x21d8] = 0xe000e000 - 0x0000217e: 6985 .i LDR r5,[r0,#0x18] - 0x00002180: e011 .. B 0x21a6 ; SYS_delay_us + 70 - 0x00002182: 4815 .H LDR r0,[pc,#84] ; [0x21d8] = 0xe000e000 - 0x00002184: 6984 .i LDR r4,[r0,#0x18] - 0x00002186: 42ac .B CMP r4,r5 - 0x00002188: d00d .. BEQ 0x21a6 ; SYS_delay_us + 70 - 0x0000218a: 42ac .B CMP r4,r5 - 0x0000218c: d202 .. BCS 0x2194 ; SYS_delay_us + 52 - 0x0000218e: 1b28 (. SUBS r0,r5,r4 - 0x00002190: 1986 .. ADDS r6,r0,r6 - 0x00002192: e003 .. B 0x219c ; SYS_delay_us + 60 - 0x00002194: 9800 .. LDR r0,[sp,#0] - 0x00002196: 1b00 .. SUBS r0,r0,r4 - 0x00002198: 1940 @. ADDS r0,r0,r5 - 0x0000219a: 1986 .. ADDS r6,r0,r6 - 0x0000219c: 4625 %F MOV r5,r4 - 0x0000219e: 9801 .. LDR r0,[sp,#4] - 0x000021a0: 4286 .B CMP r6,r0 - 0x000021a2: d300 .. BCC 0x21a6 ; SYS_delay_us + 70 - 0x000021a4: e000 .. B 0x21a8 ; SYS_delay_us + 72 - 0x000021a6: e7ec .. B 0x2182 ; SYS_delay_us + 34 - 0x000021a8: bf00 .. NOP - 0x000021aa: bdfc .. POP {r2-r7,pc} + 0x0000206c: b5fc .. PUSH {r2-r7,lr} + 0x0000206e: 4607 .F MOV r7,r0 + 0x00002070: 2000 . MOVS r0,#0 + 0x00002072: 9001 .. STR r0,[sp,#4] + 0x00002074: 2500 .% MOVS r5,#0 + 0x00002076: 2400 .$ MOVS r4,#0 + 0x00002078: 2600 .& MOVS r6,#0 + 0x0000207a: f7fffdc4 .... BL SYS_TimerGet1usTicks ; 0x1c06 + 0x0000207e: 4378 xC MULS r0,r7,r0 + 0x00002080: 9001 .. STR r0,[sp,#4] + 0x00002082: 4818 .H LDR r0,[pc,#96] ; [0x20e4] = 0xe000e000 + 0x00002084: 6940 @i LDR r0,[r0,#0x14] + 0x00002086: 9000 .. STR r0,[sp,#0] + 0x00002088: 4816 .H LDR r0,[pc,#88] ; [0x20e4] = 0xe000e000 + 0x0000208a: 6985 .i LDR r5,[r0,#0x18] + 0x0000208c: e011 .. B 0x20b2 ; SYS_delay_us + 70 + 0x0000208e: 4815 .H LDR r0,[pc,#84] ; [0x20e4] = 0xe000e000 + 0x00002090: 6984 .i LDR r4,[r0,#0x18] + 0x00002092: 42ac .B CMP r4,r5 + 0x00002094: d00d .. BEQ 0x20b2 ; SYS_delay_us + 70 + 0x00002096: 42ac .B CMP r4,r5 + 0x00002098: d202 .. BCS 0x20a0 ; SYS_delay_us + 52 + 0x0000209a: 1b28 (. SUBS r0,r5,r4 + 0x0000209c: 1986 .. ADDS r6,r0,r6 + 0x0000209e: e003 .. B 0x20a8 ; SYS_delay_us + 60 + 0x000020a0: 9800 .. LDR r0,[sp,#0] + 0x000020a2: 1b00 .. SUBS r0,r0,r4 + 0x000020a4: 1940 @. ADDS r0,r0,r5 + 0x000020a6: 1986 .. ADDS r6,r0,r6 + 0x000020a8: 4625 %F MOV r5,r4 + 0x000020aa: 9801 .. LDR r0,[sp,#4] + 0x000020ac: 4286 .B CMP r6,r0 + 0x000020ae: d300 .. BCC 0x20b2 ; SYS_delay_us + 70 + 0x000020b0: e000 .. B 0x20b4 ; SYS_delay_us + 72 + 0x000020b2: e7ec .. B 0x208e ; SYS_delay_us + 34 + 0x000020b4: bf00 .. NOP + 0x000020b6: bdfc .. POP {r2-r7,pc} SYS_delay_ms - 0x000021ac: b510 .. PUSH {r4,lr} - 0x000021ae: 4604 .F MOV r4,r0 - 0x000021b0: 217d }! MOVS r1,#0x7d - 0x000021b2: 00c9 .. LSLS r1,r1,#3 - 0x000021b4: 4361 aC MULS r1,r4,r1 - 0x000021b6: 4608 .F MOV r0,r1 - 0x000021b8: f7ffffd2 .... BL SYS_delay_us ; 0x2160 - 0x000021bc: bd10 .. POP {r4,pc} + 0x000020b8: b510 .. PUSH {r4,lr} + 0x000020ba: 4604 .F MOV r4,r0 + 0x000020bc: 217d }! MOVS r1,#0x7d + 0x000020be: 00c9 .. LSLS r1,r1,#3 + 0x000020c0: 4361 aC MULS r1,r4,r1 + 0x000020c2: 4608 .F MOV r0,r1 + 0x000020c4: f7ffffd2 .... BL SYS_delay_us ; 0x206c + 0x000020c8: bd10 .. POP {r4,pc} hw_delay - 0x000021be: bf00 .. NOP - 0x000021c0: bf00 .. NOP - 0x000021c2: bf00 .. NOP - 0x000021c4: bf00 .. NOP - 0x000021c6: bf00 .. NOP - 0x000021c8: 4770 pG BX lr + 0x000020ca: bf00 .. NOP + 0x000020cc: bf00 .. NOP + 0x000020ce: bf00 .. NOP + 0x000020d0: bf00 .. NOP + 0x000020d2: bf00 .. NOP + 0x000020d4: 4770 pG BX lr $d - 0x000021ca: 0000 .. DCW 0 - 0x000021cc: 10011004 .... DCD 268505092 - 0x000021d0: 1001102c ,... DCD 268505132 - 0x000021d4: 10011010 .... DCD 268505104 - 0x000021d8: e000e000 .... DCD 3758153728 + 0x000020d6: 0000 .. DCW 0 + 0x000020d8: 10011000 .... DCD 268505088 + 0x000020dc: 1001101c .... DCD 268505116 + 0x000020e0: 1001100c .... DCD 268505100 + 0x000020e4: e000e000 .... DCD 3758153728 $t .text SysTick_Config - 0x000021dc: 4601 .F MOV r1,r0 - 0x000021de: 1e49 I. SUBS r1,r1,#1 - 0x000021e0: 2900 .) CMP r1,#0 - 0x000021e2: d002 .. BEQ 0x21ea ; SysTick_Config + 14 - 0x000021e4: 4810 .H LDR r0,[pc,#64] ; [0x2228] = 0xffffff - 0x000021e6: 4281 .B CMP r1,r0 - 0x000021e8: d901 .. BLS 0x21ee ; SysTick_Config + 18 - 0x000021ea: 2001 . MOVS r0,#1 - 0x000021ec: 4770 pG BX lr - 0x000021ee: 480f .H LDR r0,[pc,#60] ; [0x222c] = 0xe000e000 - 0x000021f0: 6900 .i LDR r0,[r0,#0x10] - 0x000021f2: 0840 @. LSRS r0,r0,#1 - 0x000021f4: 0040 @. LSLS r0,r0,#1 - 0x000021f6: 4a0d .J LDR r2,[pc,#52] ; [0x222c] = 0xe000e000 - 0x000021f8: 6110 .a STR r0,[r2,#0x10] - 0x000021fa: 4610 .F MOV r0,r2 - 0x000021fc: 6141 Aa STR r1,[r0,#0x14] - 0x000021fe: 2000 . MOVS r0,#0 - 0x00002200: 6190 .a STR r0,[r2,#0x18] - 0x00002202: 4a0b .J LDR r2,[pc,#44] ; [0x2230] = 0x10011014 - 0x00002204: 6010 .` STR r0,[r2,#0] - 0x00002206: 4809 .H LDR r0,[pc,#36] ; [0x222c] = 0xe000e000 - 0x00002208: 6900 .i LDR r0,[r0,#0x10] - 0x0000220a: 2207 ." MOVS r2,#7 - 0x0000220c: 4310 .C ORRS r0,r0,r2 - 0x0000220e: 4a07 .J LDR r2,[pc,#28] ; [0x222c] = 0xe000e000 - 0x00002210: 6110 .a STR r0,[r2,#0x10] - 0x00002212: 2000 . MOVS r0,#0 - 0x00002214: e7ea .. B 0x21ec ; SysTick_Config + 16 + 0x000020e8: 4601 .F MOV r1,r0 + 0x000020ea: 1e49 I. SUBS r1,r1,#1 + 0x000020ec: 2900 .) CMP r1,#0 + 0x000020ee: d002 .. BEQ 0x20f6 ; SysTick_Config + 14 + 0x000020f0: 4810 .H LDR r0,[pc,#64] ; [0x2134] = 0xffffff + 0x000020f2: 4281 .B CMP r1,r0 + 0x000020f4: d901 .. BLS 0x20fa ; SysTick_Config + 18 + 0x000020f6: 2001 . MOVS r0,#1 + 0x000020f8: 4770 pG BX lr + 0x000020fa: 480f .H LDR r0,[pc,#60] ; [0x2138] = 0xe000e000 + 0x000020fc: 6900 .i LDR r0,[r0,#0x10] + 0x000020fe: 0840 @. LSRS r0,r0,#1 + 0x00002100: 0040 @. LSLS r0,r0,#1 + 0x00002102: 4a0d .J LDR r2,[pc,#52] ; [0x2138] = 0xe000e000 + 0x00002104: 6110 .a STR r0,[r2,#0x10] + 0x00002106: 4610 .F MOV r0,r2 + 0x00002108: 6141 Aa STR r1,[r0,#0x14] + 0x0000210a: 2000 . MOVS r0,#0 + 0x0000210c: 6190 .a STR r0,[r2,#0x18] + 0x0000210e: 4a0b .J LDR r2,[pc,#44] ; [0x213c] = 0x10011010 + 0x00002110: 6010 .` STR r0,[r2,#0] + 0x00002112: 4809 .H LDR r0,[pc,#36] ; [0x2138] = 0xe000e000 + 0x00002114: 6900 .i LDR r0,[r0,#0x10] + 0x00002116: 2207 ." MOVS r2,#7 + 0x00002118: 4310 .C ORRS r0,r0,r2 + 0x0000211a: 4a07 .J LDR r2,[pc,#28] ; [0x2138] = 0xe000e000 + 0x0000211c: 6110 .a STR r0,[r2,#0x10] + 0x0000211e: 2000 . MOVS r0,#0 + 0x00002120: e7ea .. B 0x20f8 ; SysTick_Config + 16 SysTick_GetTick - 0x00002216: 4806 .H LDR r0,[pc,#24] ; [0x2230] = 0x10011014 - 0x00002218: 6800 .h LDR r0,[r0,#0] - 0x0000221a: 4770 pG BX lr + 0x00002122: 4806 .H LDR r0,[pc,#24] ; [0x213c] = 0x10011010 + 0x00002124: 6800 .h LDR r0,[r0,#0] + 0x00002126: 4770 pG BX lr SysTick_IsTimeOut - 0x0000221c: 4602 .F MOV r2,r0 - 0x0000221e: 2000 . MOVS r0,#0 - 0x00002220: 4770 pG BX lr + 0x00002128: 4602 .F MOV r2,r0 + 0x0000212a: 2000 . MOVS r0,#0 + 0x0000212c: 4770 pG BX lr SysTick_GetRelativeTime - 0x00002222: 4601 .F MOV r1,r0 - 0x00002224: 2000 . MOVS r0,#0 - 0x00002226: 4770 pG BX lr + 0x0000212e: 4601 .F MOV r1,r0 + 0x00002130: 2000 . MOVS r0,#0 + 0x00002132: 4770 pG BX lr $d - 0x00002228: 00ffffff .... DCD 16777215 - 0x0000222c: e000e000 .... DCD 3758153728 - 0x00002230: 10011014 .... DCD 268505108 + 0x00002134: 00ffffff .... DCD 16777215 + 0x00002138: e000e000 .... DCD 3758153728 + 0x0000213c: 10011010 .... DCD 268505104 $t .text - USART_Init - 0x00002234: b5fe .. PUSH {r1-r7,lr} - 0x00002236: 4605 .F MOV r5,r0 - 0x00002238: 460c .F MOV r4,r1 - 0x0000223a: 2000 . MOVS r0,#0 - 0x0000223c: 9001 .. STR r0,[sp,#4] - 0x0000223e: 2600 .& MOVS r6,#0 - 0x00002240: 2700 .' MOVS r7,#0 - 0x00002242: 9000 .. STR r0,[sp,#0] - 0x00002244: bf00 .. NOP - 0x00002246: 2001 . MOVS r0,#1 - 0x00002248: 49fa .I LDR r1,[pc,#1000] ; [0x2634] = 0x10008040 - 0x0000224a: 70c8 .p STRB r0,[r1,#3] - 0x0000224c: 70c8 .p STRB r0,[r1,#3] - 0x0000224e: bf00 .. NOP - 0x00002250: bf00 .. NOP - 0x00002252: 48f9 .H LDR r0,[pc,#996] ; [0x2638] = 0x10004fe0 - 0x00002254: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00002256: 2000 . MOVS r0,#0 - 0x00002258: 7c49 I| LDRB r1,[r1,#0x11] - 0x0000225a: 4300 .C ORRS r0,r0,r0 - 0x0000225c: 49f5 .I LDR r1,[pc,#980] ; [0x2634] = 0x10008040 - 0x0000225e: 7c49 I| LDRB r1,[r1,#0x11] - 0x00002260: 4308 .C ORRS r0,r0,r1 - 0x00002262: 2180 .! MOVS r1,#0x80 - 0x00002264: 4388 .C BICS r0,r0,r1 - 0x00002266: 49f3 .I LDR r1,[pc,#972] ; [0x2634] = 0x10008040 - 0x00002268: 7448 Ht STRB r0,[r1,#0x11] - 0x0000226a: 48f3 .H LDR r0,[pc,#972] ; [0x2638] = 0x10004fe0 - 0x0000226c: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x0000226e: 2000 . MOVS r0,#0 - 0x00002270: 7c49 I| LDRB r1,[r1,#0x11] - 0x00002272: 4300 .C ORRS r0,r0,r0 - 0x00002274: 49ef .I LDR r1,[pc,#956] ; [0x2634] = 0x10008040 - 0x00002276: 7c49 I| LDRB r1,[r1,#0x11] - 0x00002278: 4308 .C ORRS r0,r0,r1 - 0x0000227a: 2180 .! MOVS r1,#0x80 - 0x0000227c: 4388 .C BICS r0,r0,r1 - 0x0000227e: 49ed .I LDR r1,[pc,#948] ; [0x2634] = 0x10008040 - 0x00002280: 7448 Ht STRB r0,[r1,#0x11] - 0x00002282: bf00 .. NOP - 0x00002284: 2c00 ., CMP r4,#0 - 0x00002286: d104 .. BNE 0x2292 ; USART_Init + 94 - 0x00002288: 4aec .J LDR r2,[pc,#944] ; [0x263c] = 0x77aa - 0x0000228a: 215b [! MOVS r1,#0x5b - 0x0000228c: a0ec .. ADR r0,{pc}+0x3b4 ; 0x2640 - 0x0000228e: f7feffbe .... BL _assert_handler ; 0x120e - 0x00002292: 2d00 .- CMP r5,#0 - 0x00002294: d006 .. BEQ 0x22a4 ; USART_Init + 112 - 0x00002296: 2d01 .- CMP r5,#1 - 0x00002298: d004 .. BEQ 0x22a4 ; USART_Init + 112 - 0x0000229a: 4ae8 .J LDR r2,[pc,#928] ; [0x263c] = 0x77aa - 0x0000229c: 215c \! MOVS r1,#0x5c - 0x0000229e: a0e8 .. ADR r0,{pc}+0x3a2 ; 0x2640 - 0x000022a0: f7feffb5 .... BL _assert_handler ; 0x120e - 0x000022a4: 6820 h LDR r0,[r4,#0] - 0x000022a6: 2800 .( CMP r0,#0 - 0x000022a8: d003 .. BEQ 0x22b2 ; USART_Init + 126 - 0x000022aa: 49f3 .I LDR r1,[pc,#972] ; [0x2678] = 0xce20 - 0x000022ac: 6820 h LDR r0,[r4,#0] - 0x000022ae: 4288 .B CMP r0,r1 - 0x000022b0: d304 .. BCC 0x22bc ; USART_Init + 136 - 0x000022b2: 4ae2 .J LDR r2,[pc,#904] ; [0x263c] = 0x77aa - 0x000022b4: 215e ^! MOVS r1,#0x5e - 0x000022b6: a0e2 .. ADR r0,{pc}+0x38a ; 0x2640 - 0x000022b8: f7feffa9 .... BL _assert_handler ; 0x120e - 0x000022bc: 88a0 .. LDRH r0,[r4,#4] - 0x000022be: 2800 .( CMP r0,#0 - 0x000022c0: d007 .. BEQ 0x22d2 ; USART_Init + 158 - 0x000022c2: 88a0 .. LDRH r0,[r4,#4] - 0x000022c4: 2804 .( CMP r0,#4 - 0x000022c6: d004 .. BEQ 0x22d2 ; USART_Init + 158 - 0x000022c8: 4adc .J LDR r2,[pc,#880] ; [0x263c] = 0x77aa - 0x000022ca: 215f _! MOVS r1,#0x5f - 0x000022cc: a0dc .. ADR r0,{pc}+0x374 ; 0x2640 - 0x000022ce: f7feff9e .... BL _assert_handler ; 0x120e - 0x000022d2: 88e0 .. LDRH r0,[r4,#6] - 0x000022d4: 2800 .( CMP r0,#0 - 0x000022d6: d007 .. BEQ 0x22e8 ; USART_Init + 180 - 0x000022d8: 88e0 .. LDRH r0,[r4,#6] - 0x000022da: 2808 .( CMP r0,#8 - 0x000022dc: d004 .. BEQ 0x22e8 ; USART_Init + 180 - 0x000022de: 4ad7 .J LDR r2,[pc,#860] ; [0x263c] = 0x77aa - 0x000022e0: 2160 `! MOVS r1,#0x60 - 0x000022e2: a0d7 .. ADR r0,{pc}+0x35e ; 0x2640 - 0x000022e4: f7feff93 .... BL _assert_handler ; 0x120e - 0x000022e8: 8920 . LDRH r0,[r4,#8] - 0x000022ea: 2800 .( CMP r0,#0 - 0x000022ec: d007 .. BEQ 0x22fe ; USART_Init + 202 - 0x000022ee: 8920 . LDRH r0,[r4,#8] - 0x000022f0: 2802 .( CMP r0,#2 - 0x000022f2: d004 .. BEQ 0x22fe ; USART_Init + 202 - 0x000022f4: 4ad1 .J LDR r2,[pc,#836] ; [0x263c] = 0x77aa - 0x000022f6: 2161 a! MOVS r1,#0x61 - 0x000022f8: a0d1 .. ADR r0,{pc}+0x348 ; 0x2640 - 0x000022fa: f7feff88 .... BL _assert_handler ; 0x120e - 0x000022fe: 8960 `. LDRH r0,[r4,#0xa] - 0x00002300: 2840 @( CMP r0,#0x40 - 0x00002302: d007 .. BEQ 0x2314 ; USART_Init + 224 - 0x00002304: 8960 `. LDRH r0,[r4,#0xa] - 0x00002306: 2800 .( CMP r0,#0 - 0x00002308: d004 .. BEQ 0x2314 ; USART_Init + 224 - 0x0000230a: 4acc .J LDR r2,[pc,#816] ; [0x263c] = 0x77aa - 0x0000230c: 2162 b! MOVS r1,#0x62 - 0x0000230e: a0cc .. ADR r0,{pc}+0x332 ; 0x2640 - 0x00002310: f7feff7d ..}. BL _assert_handler ; 0x120e - 0x00002314: 89a0 .. LDRH r0,[r4,#0xc] - 0x00002316: 2800 .( CMP r0,#0 - 0x00002318: d007 .. BEQ 0x232a ; USART_Init + 246 - 0x0000231a: 89a0 .. LDRH r0,[r4,#0xc] - 0x0000231c: 2810 .( CMP r0,#0x10 - 0x0000231e: d004 .. BEQ 0x232a ; USART_Init + 246 - 0x00002320: 4ac6 .J LDR r2,[pc,#792] ; [0x263c] = 0x77aa - 0x00002322: 2163 c! MOVS r1,#0x63 - 0x00002324: a0c6 .. ADR r0,{pc}+0x31c ; 0x2640 - 0x00002326: f7feff72 ..r. BL _assert_handler ; 0x120e - 0x0000232a: 89e0 .. LDRH r0,[r4,#0xe] - 0x0000232c: 2800 .( CMP r0,#0 - 0x0000232e: dd03 .. BLE 0x2338 ; USART_Init + 260 - 0x00002330: 89e0 .. LDRH r0,[r4,#0xe] - 0x00002332: 49d2 .I LDR r1,[pc,#840] ; [0x267c] = 0x1001 - 0x00002334: 4288 .B CMP r0,r1 - 0x00002336: dd04 .. BLE 0x2342 ; USART_Init + 270 - 0x00002338: 4ac0 .J LDR r2,[pc,#768] ; [0x263c] = 0x77aa - 0x0000233a: 2164 d! MOVS r1,#0x64 - 0x0000233c: a0c0 .. ADR r0,{pc}+0x304 ; 0x2640 - 0x0000233e: f7feff66 ..f. BL _assert_handler ; 0x120e - 0x00002342: 8a20 . LDRH r0,[r4,#0x10] - 0x00002344: 2800 .( CMP r0,#0 - 0x00002346: dd03 .. BLE 0x2350 ; USART_Init + 284 - 0x00002348: 8a20 . LDRH r0,[r4,#0x10] - 0x0000234a: 49cc .I LDR r1,[pc,#816] ; [0x267c] = 0x1001 - 0x0000234c: 4288 .B CMP r0,r1 - 0x0000234e: dd04 .. BLE 0x235a ; USART_Init + 294 - 0x00002350: 4aba .J LDR r2,[pc,#744] ; [0x263c] = 0x77aa - 0x00002352: 2165 e! MOVS r1,#0x65 - 0x00002354: a0ba .. ADR r0,{pc}+0x2ec ; 0x2640 - 0x00002356: f7feff5a ..Z. BL _assert_handler ; 0x120e - 0x0000235a: 8820 . LDRH r0,[r4,#0] - 0x0000235c: 0129 ). LSLS r1,r5,#4 - 0x0000235e: 4ac8 .J LDR r2,[pc,#800] ; [0x2680] = 0x10011044 - 0x00002360: 5250 PR STRH r0,[r2,r1] - 0x00002362: 2d00 .- CMP r5,#0 - 0x00002364: d112 .. BNE 0x238c ; USART_Init + 344 - 0x00002366: 4ec7 .N LDR r6,[pc,#796] ; [0x2684] = 0x10011064 - 0x00002368: 0129 ). LSLS r1,r5,#4 - 0x0000236a: 1889 .. ADDS r1,r1,r2 - 0x0000236c: 810e .. STRH r6,[r1,#8] - 0x0000236e: 89e0 .. LDRH r0,[r4,#0xe] - 0x00002370: 1980 .. ADDS r0,r0,r6 - 0x00002372: 0129 ). LSLS r1,r5,#4 - 0x00002374: 1889 .. ADDS r1,r1,r2 - 0x00002376: 8148 H. STRH r0,[r1,#0xa] - 0x00002378: 4ec3 .N LDR r6,[pc,#780] ; [0x2688] = 0x10012065 - 0x0000237a: 0129 ). LSLS r1,r5,#4 - 0x0000237c: 1889 .. ADDS r1,r1,r2 - 0x0000237e: 804e N. STRH r6,[r1,#2] - 0x00002380: 8a20 . LDRH r0,[r4,#0x10] - 0x00002382: 1980 .. ADDS r0,r0,r6 - 0x00002384: 0129 ). LSLS r1,r5,#4 - 0x00002386: 1889 .. ADDS r1,r1,r2 - 0x00002388: 8088 .. STRH r0,[r1,#4] - 0x0000238a: e012 .. B 0x23b2 ; USART_Init + 382 - 0x0000238c: 4ebf .N LDR r6,[pc,#764] ; [0x268c] = 0x1001101c - 0x0000238e: 0129 ). LSLS r1,r5,#4 - 0x00002390: 4abb .J LDR r2,[pc,#748] ; [0x2680] = 0x10011044 - 0x00002392: 1889 .. ADDS r1,r1,r2 - 0x00002394: 810e .. STRH r6,[r1,#8] - 0x00002396: 89e0 .. LDRH r0,[r4,#0xe] - 0x00002398: 1980 .. ADDS r0,r0,r6 - 0x0000239a: 0129 ). LSLS r1,r5,#4 - 0x0000239c: 1889 .. ADDS r1,r1,r2 - 0x0000239e: 8148 H. STRH r0,[r1,#0xa] - 0x000023a0: 4ebb .N LDR r6,[pc,#748] ; [0x2690] = 0x1001101e - 0x000023a2: 0129 ). LSLS r1,r5,#4 - 0x000023a4: 1889 .. ADDS r1,r1,r2 - 0x000023a6: 804e N. STRH r6,[r1,#2] - 0x000023a8: 8a20 . LDRH r0,[r4,#0x10] - 0x000023aa: 1980 .. ADDS r0,r0,r6 - 0x000023ac: 0129 ). LSLS r1,r5,#4 - 0x000023ae: 1889 .. ADDS r1,r1,r2 - 0x000023b0: 8088 .. STRH r0,[r1,#4] - 0x000023b2: 7aa0 .z LDRB r0,[r4,#0xa] - 0x000023b4: 7b21 !{ LDRB r1,[r4,#0xc] - 0x000023b6: 4308 .C ORRS r0,r0,r1 - 0x000023b8: 7a21 !z LDRB r1,[r4,#8] - 0x000023ba: 4308 .C ORRS r0,r0,r1 - 0x000023bc: 79a1 .y LDRB r1,[r4,#6] + IpcDefaultCallBack + 0x00002140: 4afe .J LDR r2,[pc,#1016] ; [0x253c] = 0x10011018 + 0x00002142: 7812 .x LDRB r2,[r2,#0] + 0x00002144: 1c52 R. ADDS r2,r2,#1 + 0x00002146: 4bfd .K LDR r3,[pc,#1012] ; [0x253c] = 0x10011018 + 0x00002148: 701a .p STRB r2,[r3,#0] + 0x0000214a: 4770 pG BX lr + IPC_Initialize + 0x0000214c: b510 .. PUSH {r4,lr} + 0x0000214e: 4604 .F MOV r4,r0 + 0x00002150: 2228 (" MOVS r2,#0x28 + 0x00002152: 4621 !F MOV r1,r4 + 0x00002154: 48fa .H LDR r0,[pc,#1000] ; [0x2540] = 0x10011034 + 0x00002156: f000fe69 ..i. BL __aeabi_memcpy ; 0x2e2c + 0x0000215a: bd10 .. POP {r4,pc} + IPC_init + 0x0000215c: 49f9 .I LDR r1,[pc,#996] ; [0x2544] = 0x10011014 + 0x0000215e: 6008 .` STR r0,[r1,#0] + 0x00002160: 4770 pG BX lr + ipcRx + 0x00002162: b570 p. PUSH {r4-r6,lr} + 0x00002164: 4605 .F MOV r5,r0 + 0x00002166: 460e .F MOV r6,r1 + 0x00002168: 49f7 .I LDR r1,[pc,#988] ; [0x2548] = 0x10004fe0 + 0x0000216a: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x0000216c: 2100 .! MOVS r1,#0 + 0x0000216e: 4af7 .J LDR r2,[pc,#988] ; [0x254c] = 0x10004400 + 0x00002170: 78d2 .x LDRB r2,[r2,#3] + 0x00002172: 4309 .C ORRS r1,r1,r1 + 0x00002174: 4af5 .J LDR r2,[pc,#980] ; [0x254c] = 0x10004400 + 0x00002176: 78d2 .x LDRB r2,[r2,#3] + 0x00002178: 4311 .C ORRS r1,r1,r2 + 0x0000217a: 4af3 .J LDR r2,[pc,#972] ; [0x2548] = 0x10004fe0 + 0x0000217c: 7fd2 .. LDRB r2,[r2,#0x1f] + 0x0000217e: 2200 ." MOVS r2,#0 + 0x00002180: 4bf2 .K LDR r3,[pc,#968] ; [0x254c] = 0x10004400 + 0x00002182: 791b .y LDRB r3,[r3,#4] + 0x00002184: 4312 .C ORRS r2,r2,r2 + 0x00002186: 4bf1 .K LDR r3,[pc,#964] ; [0x254c] = 0x10004400 + 0x00002188: 791b .y LDRB r3,[r3,#4] + 0x0000218a: 431a .C ORRS r2,r2,r3 + 0x0000218c: 0212 .. LSLS r2,r2,#8 + 0x0000218e: 4311 .C ORRS r1,r1,r2 + 0x00002190: 4aed .J LDR r2,[pc,#948] ; [0x2548] = 0x10004fe0 + 0x00002192: 7fd2 .. LDRB r2,[r2,#0x1f] + 0x00002194: 2200 ." MOVS r2,#0 + 0x00002196: 4bed .K LDR r3,[pc,#948] ; [0x254c] = 0x10004400 + 0x00002198: 795b [y LDRB r3,[r3,#5] + 0x0000219a: 4312 .C ORRS r2,r2,r2 + 0x0000219c: 4beb .K LDR r3,[pc,#940] ; [0x254c] = 0x10004400 + 0x0000219e: 795b [y LDRB r3,[r3,#5] + 0x000021a0: 431a .C ORRS r2,r2,r3 + 0x000021a2: 0412 .. LSLS r2,r2,#16 + 0x000021a4: 4311 .C ORRS r1,r1,r2 + 0x000021a6: 2201 ." MOVS r2,#1 + 0x000021a8: 0712 .. LSLS r2,r2,#28 + 0x000021aa: 1888 .. ADDS r0,r1,r2 + 0x000021ac: f000fd57 ..W. BL HR_REG_24BIT ; 0x2c5e + 0x000021b0: 4604 .F MOV r4,r0 + 0x000021b2: 2000 . MOVS r0,#0 + 0x000021b4: e052 R. B 0x225c ; ipcRx + 250 + 0x000021b6: 49e4 .I LDR r1,[pc,#912] ; [0x2548] = 0x10004fe0 + 0x000021b8: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x000021ba: 2100 .! MOVS r1,#0 + 0x000021bc: 2201 ." MOVS r2,#1 + 0x000021be: 0712 .. LSLS r2,r2,#28 + 0x000021c0: 4322 "C ORRS r2,r2,r4 + 0x000021c2: 7812 .x LDRB r2,[r2,#0] + 0x000021c4: 4309 .C ORRS r1,r1,r1 + 0x000021c6: 2201 ." MOVS r2,#1 + 0x000021c8: 0712 .. LSLS r2,r2,#28 + 0x000021ca: 4322 "C ORRS r2,r2,r4 + 0x000021cc: 7812 .x LDRB r2,[r2,#0] + 0x000021ce: 4311 .C ORRS r1,r1,r2 + 0x000021d0: 5429 )T STRB r1,[r5,r0] + 0x000021d2: 49dd .I LDR r1,[pc,#884] ; [0x2548] = 0x10004fe0 + 0x000021d4: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x000021d6: 2100 .! MOVS r1,#0 + 0x000021d8: 4adc .J LDR r2,[pc,#880] ; [0x254c] = 0x10004400 + 0x000021da: 7a52 Rz LDRB r2,[r2,#9] + 0x000021dc: 4309 .C ORRS r1,r1,r1 + 0x000021de: 4adb .J LDR r2,[pc,#876] ; [0x254c] = 0x10004400 + 0x000021e0: 7a52 Rz LDRB r2,[r2,#9] + 0x000021e2: 4311 .C ORRS r1,r1,r2 + 0x000021e4: 4ad8 .J LDR r2,[pc,#864] ; [0x2548] = 0x10004fe0 + 0x000021e6: 7fd2 .. LDRB r2,[r2,#0x1f] + 0x000021e8: 2200 ." MOVS r2,#0 + 0x000021ea: 4bd8 .K LDR r3,[pc,#864] ; [0x254c] = 0x10004400 + 0x000021ec: 7a9b .z LDRB r3,[r3,#0xa] + 0x000021ee: 4312 .C ORRS r2,r2,r2 + 0x000021f0: 4bd6 .K LDR r3,[pc,#856] ; [0x254c] = 0x10004400 + 0x000021f2: 7a9b .z LDRB r3,[r3,#0xa] + 0x000021f4: 431a .C ORRS r2,r2,r3 + 0x000021f6: 0212 .. LSLS r2,r2,#8 + 0x000021f8: 4311 .C ORRS r1,r1,r2 + 0x000021fa: 4ad3 .J LDR r2,[pc,#844] ; [0x2548] = 0x10004fe0 + 0x000021fc: 7fd2 .. LDRB r2,[r2,#0x1f] + 0x000021fe: 2200 ." MOVS r2,#0 + 0x00002200: 4bd2 .K LDR r3,[pc,#840] ; [0x254c] = 0x10004400 + 0x00002202: 7adb .z LDRB r3,[r3,#0xb] + 0x00002204: 4312 .C ORRS r2,r2,r2 + 0x00002206: 4bd1 .K LDR r3,[pc,#836] ; [0x254c] = 0x10004400 + 0x00002208: 7adb .z LDRB r3,[r3,#0xb] + 0x0000220a: 431a .C ORRS r2,r2,r3 + 0x0000220c: 0412 .. LSLS r2,r2,#16 + 0x0000220e: 4311 .C ORRS r1,r1,r2 + 0x00002210: 1c62 b. ADDS r2,r4,#1 + 0x00002212: 4614 .F MOV r4,r2 + 0x00002214: 4291 .B CMP r1,r2 + 0x00002216: d81f .. BHI 0x2258 ; ipcRx + 246 + 0x00002218: 49cb .I LDR r1,[pc,#812] ; [0x2548] = 0x10004fe0 + 0x0000221a: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x0000221c: 2100 .! MOVS r1,#0 + 0x0000221e: 4acb .J LDR r2,[pc,#812] ; [0x254c] = 0x10004400 + 0x00002220: 7992 .y LDRB r2,[r2,#6] + 0x00002222: 4309 .C ORRS r1,r1,r1 + 0x00002224: 4ac9 .J LDR r2,[pc,#804] ; [0x254c] = 0x10004400 + 0x00002226: 7992 .y LDRB r2,[r2,#6] + 0x00002228: 4311 .C ORRS r1,r1,r2 + 0x0000222a: 4ac7 .J LDR r2,[pc,#796] ; [0x2548] = 0x10004fe0 + 0x0000222c: 7fd2 .. LDRB r2,[r2,#0x1f] + 0x0000222e: 2200 ." MOVS r2,#0 + 0x00002230: 4bc6 .K LDR r3,[pc,#792] ; [0x254c] = 0x10004400 + 0x00002232: 79db .y LDRB r3,[r3,#7] + 0x00002234: 4312 .C ORRS r2,r2,r2 + 0x00002236: 4bc5 .K LDR r3,[pc,#788] ; [0x254c] = 0x10004400 + 0x00002238: 79db .y LDRB r3,[r3,#7] + 0x0000223a: 431a .C ORRS r2,r2,r3 + 0x0000223c: 0212 .. LSLS r2,r2,#8 + 0x0000223e: 4311 .C ORRS r1,r1,r2 + 0x00002240: 4ac1 .J LDR r2,[pc,#772] ; [0x2548] = 0x10004fe0 + 0x00002242: 7fd2 .. LDRB r2,[r2,#0x1f] + 0x00002244: 2200 ." MOVS r2,#0 + 0x00002246: 4bc1 .K LDR r3,[pc,#772] ; [0x254c] = 0x10004400 + 0x00002248: 7a1b .z LDRB r3,[r3,#8] + 0x0000224a: 4312 .C ORRS r2,r2,r2 + 0x0000224c: 4bbf .K LDR r3,[pc,#764] ; [0x254c] = 0x10004400 + 0x0000224e: 7a1b .z LDRB r3,[r3,#8] + 0x00002250: 431a .C ORRS r2,r2,r3 + 0x00002252: 0412 .. LSLS r2,r2,#16 + 0x00002254: 4311 .C ORRS r1,r1,r2 + 0x00002256: 460c .F MOV r4,r1 + 0x00002258: 1c41 A. ADDS r1,r0,#1 + 0x0000225a: b288 .. UXTH r0,r1 + 0x0000225c: 42b0 .B CMP r0,r6 + 0x0000225e: dbaa .. BLT 0x21b6 ; ipcRx + 84 + 0x00002260: bf00 .. NOP + 0x00002262: bf00 .. NOP + 0x00002264: b2e2 .. UXTB r2,r4 + 0x00002266: 48b8 .H LDR r0,[pc,#736] ; [0x2548] = 0x10004fe0 + 0x00002268: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x0000226a: 2100 .! MOVS r1,#0 + 0x0000226c: 48b7 .H LDR r0,[pc,#732] ; [0x254c] = 0x10004400 + 0x0000226e: 78c0 .x LDRB r0,[r0,#3] + 0x00002270: 4309 .C ORRS r1,r1,r1 + 0x00002272: 48b6 .H LDR r0,[pc,#728] ; [0x254c] = 0x10004400 + 0x00002274: 78c0 .x LDRB r0,[r0,#3] + 0x00002276: 4301 .C ORRS r1,r1,r0 + 0x00002278: 48b3 .H LDR r0,[pc,#716] ; [0x2548] = 0x10004fe0 + 0x0000227a: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x0000227c: 2000 . MOVS r0,#0 + 0x0000227e: 4bb3 .K LDR r3,[pc,#716] ; [0x254c] = 0x10004400 + 0x00002280: 791b .y LDRB r3,[r3,#4] + 0x00002282: 4300 .C ORRS r0,r0,r0 + 0x00002284: 4bb1 .K LDR r3,[pc,#708] ; [0x254c] = 0x10004400 + 0x00002286: 791b .y LDRB r3,[r3,#4] + 0x00002288: 4318 .C ORRS r0,r0,r3 + 0x0000228a: 0200 .. LSLS r0,r0,#8 + 0x0000228c: 4308 .C ORRS r0,r0,r1 + 0x0000228e: 49ae .I LDR r1,[pc,#696] ; [0x2548] = 0x10004fe0 + 0x00002290: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x00002292: 2100 .! MOVS r1,#0 + 0x00002294: 4bad .K LDR r3,[pc,#692] ; [0x254c] = 0x10004400 + 0x00002296: 795b [y LDRB r3,[r3,#5] + 0x00002298: 4309 .C ORRS r1,r1,r1 + 0x0000229a: 4bac .K LDR r3,[pc,#688] ; [0x254c] = 0x10004400 + 0x0000229c: 795b [y LDRB r3,[r3,#5] + 0x0000229e: 4319 .C ORRS r1,r1,r3 + 0x000022a0: 0409 .. LSLS r1,r1,#16 + 0x000022a2: 4308 .C ORRS r0,r0,r1 + 0x000022a4: 2101 .! MOVS r1,#1 + 0x000022a6: 0709 .. LSLS r1,r1,#28 + 0x000022a8: 1840 @. ADDS r0,r0,r1 + 0x000022aa: 7002 .p STRB r2,[r0,#0] + 0x000022ac: b2e2 .. UXTB r2,r4 + 0x000022ae: 48a6 .H LDR r0,[pc,#664] ; [0x2548] = 0x10004fe0 + 0x000022b0: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x000022b2: 2000 . MOVS r0,#0 + 0x000022b4: 49a5 .I LDR r1,[pc,#660] ; [0x254c] = 0x10004400 + 0x000022b6: 78c9 .x LDRB r1,[r1,#3] + 0x000022b8: 4300 .C ORRS r0,r0,r0 + 0x000022ba: 49a4 .I LDR r1,[pc,#656] ; [0x254c] = 0x10004400 + 0x000022bc: 78c9 .x LDRB r1,[r1,#3] + 0x000022be: 4308 .C ORRS r0,r0,r1 + 0x000022c0: 49a1 .I LDR r1,[pc,#644] ; [0x2548] = 0x10004fe0 + 0x000022c2: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x000022c4: 2100 .! MOVS r1,#0 + 0x000022c6: 4ba1 .K LDR r3,[pc,#644] ; [0x254c] = 0x10004400 + 0x000022c8: 791b .y LDRB r3,[r3,#4] + 0x000022ca: 4309 .C ORRS r1,r1,r1 + 0x000022cc: 4b9f .K LDR r3,[pc,#636] ; [0x254c] = 0x10004400 + 0x000022ce: 791b .y LDRB r3,[r3,#4] + 0x000022d0: 4319 .C ORRS r1,r1,r3 + 0x000022d2: 0209 .. LSLS r1,r1,#8 + 0x000022d4: 4308 .C ORRS r0,r0,r1 + 0x000022d6: 499c .I LDR r1,[pc,#624] ; [0x2548] = 0x10004fe0 + 0x000022d8: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x000022da: 2100 .! MOVS r1,#0 + 0x000022dc: 4b9b .K LDR r3,[pc,#620] ; [0x254c] = 0x10004400 + 0x000022de: 795b [y LDRB r3,[r3,#5] + 0x000022e0: 4309 .C ORRS r1,r1,r1 + 0x000022e2: 4b9a .K LDR r3,[pc,#616] ; [0x254c] = 0x10004400 + 0x000022e4: 795b [y LDRB r3,[r3,#5] + 0x000022e6: 4319 .C ORRS r1,r1,r3 + 0x000022e8: 0409 .. LSLS r1,r1,#16 + 0x000022ea: 4308 .C ORRS r0,r0,r1 + 0x000022ec: 2101 .! MOVS r1,#1 + 0x000022ee: 0709 .. LSLS r1,r1,#28 + 0x000022f0: 1840 @. ADDS r0,r0,r1 + 0x000022f2: 7002 .p STRB r2,[r0,#0] + 0x000022f4: bf00 .. NOP + 0x000022f6: bf00 .. NOP + 0x000022f8: 0420 . LSLS r0,r4,#16 + 0x000022fa: 0e02 .. LSRS r2,r0,#24 + 0x000022fc: 4892 .H LDR r0,[pc,#584] ; [0x2548] = 0x10004fe0 + 0x000022fe: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x00002300: 2000 . MOVS r0,#0 + 0x00002302: 4992 .I LDR r1,[pc,#584] ; [0x254c] = 0x10004400 + 0x00002304: 78c9 .x LDRB r1,[r1,#3] + 0x00002306: 4300 .C ORRS r0,r0,r0 + 0x00002308: 4990 .I LDR r1,[pc,#576] ; [0x254c] = 0x10004400 + 0x0000230a: 78c9 .x LDRB r1,[r1,#3] + 0x0000230c: 4308 .C ORRS r0,r0,r1 + 0x0000230e: 498e .I LDR r1,[pc,#568] ; [0x2548] = 0x10004fe0 + 0x00002310: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x00002312: 2100 .! MOVS r1,#0 + 0x00002314: 4b8d .K LDR r3,[pc,#564] ; [0x254c] = 0x10004400 + 0x00002316: 791b .y LDRB r3,[r3,#4] + 0x00002318: 4309 .C ORRS r1,r1,r1 + 0x0000231a: 4b8c .K LDR r3,[pc,#560] ; [0x254c] = 0x10004400 + 0x0000231c: 791b .y LDRB r3,[r3,#4] + 0x0000231e: 4319 .C ORRS r1,r1,r3 + 0x00002320: 0209 .. LSLS r1,r1,#8 + 0x00002322: 4308 .C ORRS r0,r0,r1 + 0x00002324: 4988 .I LDR r1,[pc,#544] ; [0x2548] = 0x10004fe0 + 0x00002326: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x00002328: 2100 .! MOVS r1,#0 + 0x0000232a: 4b88 .K LDR r3,[pc,#544] ; [0x254c] = 0x10004400 + 0x0000232c: 795b [y LDRB r3,[r3,#5] + 0x0000232e: 4309 .C ORRS r1,r1,r1 + 0x00002330: 4b86 .K LDR r3,[pc,#536] ; [0x254c] = 0x10004400 + 0x00002332: 795b [y LDRB r3,[r3,#5] + 0x00002334: 4319 .C ORRS r1,r1,r3 + 0x00002336: 0409 .. LSLS r1,r1,#16 + 0x00002338: 4308 .C ORRS r0,r0,r1 + 0x0000233a: 1c40 @. ADDS r0,r0,#1 + 0x0000233c: 2101 .! MOVS r1,#1 + 0x0000233e: 0709 .. LSLS r1,r1,#28 + 0x00002340: 1840 @. ADDS r0,r0,r1 + 0x00002342: 7002 .p STRB r2,[r0,#0] + 0x00002344: 0420 . LSLS r0,r4,#16 + 0x00002346: 0e02 .. LSRS r2,r0,#24 + 0x00002348: 487f .H LDR r0,[pc,#508] ; [0x2548] = 0x10004fe0 + 0x0000234a: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x0000234c: 2100 .! MOVS r1,#0 + 0x0000234e: 487f .H LDR r0,[pc,#508] ; [0x254c] = 0x10004400 + 0x00002350: 78c0 .x LDRB r0,[r0,#3] + 0x00002352: 4309 .C ORRS r1,r1,r1 + 0x00002354: 487d }H LDR r0,[pc,#500] ; [0x254c] = 0x10004400 + 0x00002356: 78c0 .x LDRB r0,[r0,#3] + 0x00002358: 4301 .C ORRS r1,r1,r0 + 0x0000235a: 487b {H LDR r0,[pc,#492] ; [0x2548] = 0x10004fe0 + 0x0000235c: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x0000235e: 2000 . MOVS r0,#0 + 0x00002360: 4b7a zK LDR r3,[pc,#488] ; [0x254c] = 0x10004400 + 0x00002362: 791b .y LDRB r3,[r3,#4] + 0x00002364: 4300 .C ORRS r0,r0,r0 + 0x00002366: 4b79 yK LDR r3,[pc,#484] ; [0x254c] = 0x10004400 + 0x00002368: 791b .y LDRB r3,[r3,#4] + 0x0000236a: 4318 .C ORRS r0,r0,r3 + 0x0000236c: 0200 .. LSLS r0,r0,#8 + 0x0000236e: 4308 .C ORRS r0,r0,r1 + 0x00002370: 4975 uI LDR r1,[pc,#468] ; [0x2548] = 0x10004fe0 + 0x00002372: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x00002374: 2100 .! MOVS r1,#0 + 0x00002376: 4b75 uK LDR r3,[pc,#468] ; [0x254c] = 0x10004400 + 0x00002378: 795b [y LDRB r3,[r3,#5] + 0x0000237a: 4309 .C ORRS r1,r1,r1 + 0x0000237c: 4b73 sK LDR r3,[pc,#460] ; [0x254c] = 0x10004400 + 0x0000237e: 795b [y LDRB r3,[r3,#5] + 0x00002380: 4319 .C ORRS r1,r1,r3 + 0x00002382: 0409 .. LSLS r1,r1,#16 + 0x00002384: 4308 .C ORRS r0,r0,r1 + 0x00002386: 1c40 @. ADDS r0,r0,#1 + 0x00002388: 2101 .! MOVS r1,#1 + 0x0000238a: 0709 .. LSLS r1,r1,#28 + 0x0000238c: 1840 @. ADDS r0,r0,r1 + 0x0000238e: 7002 .p STRB r2,[r0,#0] + 0x00002390: bf00 .. NOP + 0x00002392: bf00 .. NOP + 0x00002394: 0220 . LSLS r0,r4,#8 + 0x00002396: 0e02 .. LSRS r2,r0,#24 + 0x00002398: 486b kH LDR r0,[pc,#428] ; [0x2548] = 0x10004fe0 + 0x0000239a: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x0000239c: 2100 .! MOVS r1,#0 + 0x0000239e: 486b kH LDR r0,[pc,#428] ; [0x254c] = 0x10004400 + 0x000023a0: 78c0 .x LDRB r0,[r0,#3] + 0x000023a2: 4309 .C ORRS r1,r1,r1 + 0x000023a4: 4869 iH LDR r0,[pc,#420] ; [0x254c] = 0x10004400 + 0x000023a6: 78c0 .x LDRB r0,[r0,#3] + 0x000023a8: 4301 .C ORRS r1,r1,r0 + 0x000023aa: 4867 gH LDR r0,[pc,#412] ; [0x2548] = 0x10004fe0 + 0x000023ac: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x000023ae: 2000 . MOVS r0,#0 + 0x000023b0: 4b66 fK LDR r3,[pc,#408] ; [0x254c] = 0x10004400 + 0x000023b2: 791b .y LDRB r3,[r3,#4] + 0x000023b4: 4300 .C ORRS r0,r0,r0 + 0x000023b6: 4b65 eK LDR r3,[pc,#404] ; [0x254c] = 0x10004400 + 0x000023b8: 791b .y LDRB r3,[r3,#4] + 0x000023ba: 4318 .C ORRS r0,r0,r3 + 0x000023bc: 0200 .. LSLS r0,r0,#8 0x000023be: 4308 .C ORRS r0,r0,r1 - 0x000023c0: 7921 !y LDRB r1,[r4,#4] - 0x000023c2: 4308 .C ORRS r0,r0,r1 - 0x000023c4: 2181 .! MOVS r1,#0x81 - 0x000023c6: 4308 .C ORRS r0,r0,r1 - 0x000023c8: b2c0 .. UXTB r0,r0 - 0x000023ca: 9001 .. STR r0,[sp,#4] - 0x000023cc: 0129 ). LSLS r1,r5,#4 - 0x000023ce: 4aac .J LDR r2,[pc,#688] ; [0x2680] = 0x10011044 - 0x000023d0: 1889 .. ADDS r1,r1,r2 - 0x000023d2: 9801 .. LDR r0,[sp,#4] - 0x000023d4: 7388 .s STRB r0,[r1,#0xe] - 0x000023d6: 2d00 .- CMP r5,#0 - 0x000023d8: d104 .. BNE 0x23e4 ; USART_Init + 432 - 0x000023da: 4fae .O LDR r7,[pc,#696] ; [0x2694] = 0x8060 - 0x000023dc: 4895 .H LDR r0,[pc,#596] ; [0x2634] = 0x10008040 - 0x000023de: 3012 .0 ADDS r0,r0,#0x12 - 0x000023e0: 9000 .. STR r0,[sp,#0] - 0x000023e2: e004 .. B 0x23ee ; USART_Init + 442 - 0x000023e4: 4fab .O LDR r7,[pc,#684] ; [0x2694] = 0x8060 - 0x000023e6: 3711 .7 ADDS r7,r7,#0x11 - 0x000023e8: 4892 .H LDR r0,[pc,#584] ; [0x2634] = 0x10008040 - 0x000023ea: 3032 20 ADDS r0,r0,#0x32 - 0x000023ec: 9000 .. STR r0,[sp,#0] - 0x000023ee: bf00 .. NOP - 0x000023f0: 4891 .H LDR r0,[pc,#580] ; [0x2638] = 0x10004fe0 - 0x000023f2: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x000023f4: 2000 . MOVS r0,#0 - 0x000023f6: 2101 .! MOVS r1,#1 - 0x000023f8: 0709 .. LSLS r1,r1,#28 - 0x000023fa: 1879 y. ADDS r1,r7,r1 - 0x000023fc: 7809 .x LDRB r1,[r1,#0] - 0x000023fe: 4300 .C ORRS r0,r0,r0 - 0x00002400: 2101 .! MOVS r1,#1 - 0x00002402: 0709 .. LSLS r1,r1,#28 - 0x00002404: 1879 y. ADDS r1,r7,r1 - 0x00002406: 7809 .x LDRB r1,[r1,#0] - 0x00002408: 4308 .C ORRS r0,r0,r1 - 0x0000240a: 0840 @. LSRS r0,r0,#1 - 0x0000240c: 0040 @. LSLS r0,r0,#1 - 0x0000240e: 2101 .! MOVS r1,#1 - 0x00002410: 0709 .. LSLS r1,r1,#28 - 0x00002412: 1879 y. ADDS r1,r7,r1 - 0x00002414: 7008 .p STRB r0,[r1,#0] - 0x00002416: 4888 .H LDR r0,[pc,#544] ; [0x2638] = 0x10004fe0 - 0x00002418: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x0000241a: 2000 . MOVS r0,#0 - 0x0000241c: 2101 .! MOVS r1,#1 - 0x0000241e: 0709 .. LSLS r1,r1,#28 - 0x00002420: 1879 y. ADDS r1,r7,r1 - 0x00002422: 7809 .x LDRB r1,[r1,#0] - 0x00002424: 4300 .C ORRS r0,r0,r0 - 0x00002426: 2101 .! MOVS r1,#1 - 0x00002428: 0709 .. LSLS r1,r1,#28 - 0x0000242a: 1879 y. ADDS r1,r7,r1 - 0x0000242c: 7809 .x LDRB r1,[r1,#0] - 0x0000242e: 4308 .C ORRS r0,r0,r1 - 0x00002430: 0840 @. LSRS r0,r0,#1 - 0x00002432: 0040 @. LSLS r0,r0,#1 - 0x00002434: 2101 .! MOVS r1,#1 - 0x00002436: 0709 .. LSLS r1,r1,#28 - 0x00002438: 1879 y. ADDS r1,r7,r1 - 0x0000243a: 7008 .p STRB r0,[r1,#0] - 0x0000243c: bf00 .. NOP - 0x0000243e: 0128 (. LSLS r0,r5,#4 - 0x00002440: 4a8f .J LDR r2,[pc,#572] ; [0x2680] = 0x10011044 - 0x00002442: 5a11 .Z LDRH r1,[r2,r0] - 0x00002444: 9800 .. LDR r0,[sp,#0] - 0x00002446: f000fb5a ..Z. BL HW_REG_16BIT ; 0x2afe - 0x0000244a: 0128 (. LSLS r0,r5,#4 - 0x0000244c: 4a8c .J LDR r2,[pc,#560] ; [0x2680] = 0x10011044 - 0x0000244e: 1880 .. ADDS r0,r0,r2 - 0x00002450: 8901 .. LDRH r1,[r0,#8] - 0x00002452: 9800 .. LDR r0,[sp,#0] - 0x00002454: 3008 .0 ADDS r0,r0,#8 - 0x00002456: f000fb52 ..R. BL HW_REG_16BIT ; 0x2afe - 0x0000245a: 0128 (. LSLS r0,r5,#4 - 0x0000245c: 4a88 .J LDR r2,[pc,#544] ; [0x2680] = 0x10011044 - 0x0000245e: 1880 .. ADDS r0,r0,r2 - 0x00002460: 8941 A. LDRH r1,[r0,#0xa] - 0x00002462: 9800 .. LDR r0,[sp,#0] - 0x00002464: 300a .0 ADDS r0,r0,#0xa - 0x00002466: f000fb4a ..J. BL HW_REG_16BIT ; 0x2afe - 0x0000246a: 0128 (. LSLS r0,r5,#4 - 0x0000246c: 4a84 .J LDR r2,[pc,#528] ; [0x2680] = 0x10011044 - 0x0000246e: 1880 .. ADDS r0,r0,r2 - 0x00002470: 8901 .. LDRH r1,[r0,#8] - 0x00002472: 9800 .. LDR r0,[sp,#0] - 0x00002474: 300c .0 ADDS r0,r0,#0xc - 0x00002476: f000fb42 ..B. BL HW_REG_16BIT ; 0x2afe - 0x0000247a: 0128 (. LSLS r0,r5,#4 - 0x0000247c: 4a80 .J LDR r2,[pc,#512] ; [0x2680] = 0x10011044 - 0x0000247e: 1880 .. ADDS r0,r0,r2 - 0x00002480: 8841 A. LDRH r1,[r0,#2] - 0x00002482: 9800 .. LDR r0,[sp,#0] - 0x00002484: 1c80 .. ADDS r0,r0,#2 - 0x00002486: f000fb3a ..:. BL HW_REG_16BIT ; 0x2afe - 0x0000248a: 0128 (. LSLS r0,r5,#4 - 0x0000248c: 4a7c |J LDR r2,[pc,#496] ; [0x2680] = 0x10011044 - 0x0000248e: 1880 .. ADDS r0,r0,r2 - 0x00002490: 8881 .. LDRH r1,[r0,#4] - 0x00002492: 9800 .. LDR r0,[sp,#0] - 0x00002494: 1d00 .. ADDS r0,r0,#4 - 0x00002496: f000fb32 ..2. BL HW_REG_16BIT ; 0x2afe - 0x0000249a: 0128 (. LSLS r0,r5,#4 - 0x0000249c: 4a78 xJ LDR r2,[pc,#480] ; [0x2680] = 0x10011044 - 0x0000249e: 1880 .. ADDS r0,r0,r2 - 0x000024a0: 8841 A. LDRH r1,[r0,#2] - 0x000024a2: 9800 .. LDR r0,[sp,#0] - 0x000024a4: 1d80 .. ADDS r0,r0,#6 - 0x000024a6: f000fb2a ..*. BL HW_REG_16BIT ; 0x2afe - 0x000024aa: bf00 .. NOP - 0x000024ac: 0128 (. LSLS r0,r5,#4 - 0x000024ae: 4974 tI LDR r1,[pc,#464] ; [0x2680] = 0x10011044 - 0x000024b0: 1840 @. ADDS r0,r0,r1 - 0x000024b2: 7b80 .{ LDRB r0,[r0,#0xe] - 0x000024b4: 2101 .! MOVS r1,#1 - 0x000024b6: 0709 .. LSLS r1,r1,#28 - 0x000024b8: 1879 y. ADDS r1,r7,r1 - 0x000024ba: 7008 .p STRB r0,[r1,#0] - 0x000024bc: 0128 (. LSLS r0,r5,#4 - 0x000024be: 4970 pI LDR r1,[pc,#448] ; [0x2680] = 0x10011044 - 0x000024c0: 1840 @. ADDS r0,r0,r1 - 0x000024c2: 7b80 .{ LDRB r0,[r0,#0xe] - 0x000024c4: 2101 .! MOVS r1,#1 - 0x000024c6: 0709 .. LSLS r1,r1,#28 - 0x000024c8: 1879 y. ADDS r1,r7,r1 - 0x000024ca: 7008 .p STRB r0,[r1,#0] - 0x000024cc: bf00 .. NOP - 0x000024ce: bdfe .. POP {r1-r7,pc} - UARTx_Configuration - 0x000024d0: b530 0. PUSH {r4,r5,lr} - 0x000024d2: b085 .. SUB sp,sp,#0x14 - 0x000024d4: 4604 .F MOV r4,r0 - 0x000024d6: 460d .F MOV r5,r1 - 0x000024d8: 9500 .. STR r5,[sp,#0] - 0x000024da: 2100 .! MOVS r1,#0 - 0x000024dc: 4668 hF MOV r0,sp - 0x000024de: 8181 .. STRH r1,[r0,#0xc] - 0x000024e0: 8081 .. STRH r1,[r0,#4] - 0x000024e2: 80c1 .. STRH r1,[r0,#6] - 0x000024e4: 8141 A. STRH r1,[r0,#0xa] - 0x000024e6: 8101 .. STRH r1,[r0,#8] - 0x000024e8: 2101 .! MOVS r1,#1 - 0x000024ea: 0289 .. LSLS r1,r1,#10 - 0x000024ec: 81c1 .. STRH r1,[r0,#0xe] - 0x000024ee: 8201 .. STRH r1,[r0,#0x10] - 0x000024f0: 2c00 ., CMP r4,#0 - 0x000024f2: d10a .. BNE 0x250a ; UARTx_Configuration + 58 - 0x000024f4: 4968 hI LDR r1,[pc,#416] ; [0x2698] = 0x10011018 - 0x000024f6: 7848 Hx LDRB r0,[r1,#1] - 0x000024f8: 2108 .! MOVS r1,#8 - 0x000024fa: f7fff884 .... BL GPIO_SetGpioMultFunction ; 0x1606 - 0x000024fe: 4966 fI LDR r1,[pc,#408] ; [0x2698] = 0x10011018 - 0x00002500: 7808 .x LDRB r0,[r1,#0] - 0x00002502: 2109 .! MOVS r1,#9 - 0x00002504: f7fff87f .... BL GPIO_SetGpioMultFunction ; 0x1606 - 0x00002508: e00b .. B 0x2522 ; UARTx_Configuration + 82 - 0x0000250a: 2c01 ., CMP r4,#1 - 0x0000250c: d109 .. BNE 0x2522 ; UARTx_Configuration + 82 - 0x0000250e: 4962 bI LDR r1,[pc,#392] ; [0x2698] = 0x10011018 - 0x00002510: 78c8 .x LDRB r0,[r1,#3] - 0x00002512: 210c .! MOVS r1,#0xc - 0x00002514: f7fff877 ..w. BL GPIO_SetGpioMultFunction ; 0x1606 - 0x00002518: 495f _I LDR r1,[pc,#380] ; [0x2698] = 0x10011018 - 0x0000251a: 7888 .x LDRB r0,[r1,#2] - 0x0000251c: 210d .! MOVS r1,#0xd - 0x0000251e: f7fff872 ..r. BL GPIO_SetGpioMultFunction ; 0x1606 - 0x00002522: 4669 iF MOV r1,sp - 0x00002524: 4620 F MOV r0,r4 - 0x00002526: f7fffe85 .... BL USART_Init ; 0x2234 - 0x0000252a: b005 .. ADD sp,sp,#0x14 - 0x0000252c: bd30 0. POP {r4,r5,pc} - USART_DeInit - 0x0000252e: b510 .. PUSH {r4,lr} - 0x00002530: 4604 .F MOV r4,r0 - 0x00002532: 2c00 ., CMP r4,#0 - 0x00002534: d006 .. BEQ 0x2544 ; USART_DeInit + 22 - 0x00002536: 2c01 ., CMP r4,#1 - 0x00002538: d004 .. BEQ 0x2544 ; USART_DeInit + 22 - 0x0000253a: 4a58 XJ LDR r2,[pc,#352] ; [0x269c] = 0x77b5 - 0x0000253c: 21a4 .! MOVS r1,#0xa4 - 0x0000253e: a040 @. ADR r0,{pc}+0x102 ; 0x2640 - 0x00002540: f7fefe65 ..e. BL _assert_handler ; 0x120e - 0x00002544: 2c00 ., CMP r4,#0 - 0x00002546: d139 9. BNE 0x25bc ; USART_DeInit + 142 - 0x00002548: bf00 .. NOP - 0x0000254a: 483b ;H LDR r0,[pc,#236] ; [0x2638] = 0x10004fe0 - 0x0000254c: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x0000254e: 2000 . MOVS r0,#0 - 0x00002550: 4938 8I LDR r1,[pc,#224] ; [0x2634] = 0x10008040 - 0x00002552: 3120 1 ADDS r1,r1,#0x20 - 0x00002554: 7809 .x LDRB r1,[r1,#0] - 0x00002556: 4300 .C ORRS r0,r0,r0 - 0x00002558: 4936 6I LDR r1,[pc,#216] ; [0x2634] = 0x10008040 - 0x0000255a: 3120 1 ADDS r1,r1,#0x20 - 0x0000255c: 7809 .x LDRB r1,[r1,#0] - 0x0000255e: 4308 .C ORRS r0,r0,r1 - 0x00002560: 2101 .! MOVS r1,#1 - 0x00002562: 4308 .C ORRS r0,r0,r1 - 0x00002564: 4933 3I LDR r1,[pc,#204] ; [0x2634] = 0x10008040 - 0x00002566: 3120 1 ADDS r1,r1,#0x20 - 0x00002568: 7008 .p STRB r0,[r1,#0] - 0x0000256a: 4833 3H LDR r0,[pc,#204] ; [0x2638] = 0x10004fe0 - 0x0000256c: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x0000256e: 2000 . MOVS r0,#0 - 0x00002570: 7809 .x LDRB r1,[r1,#0] - 0x00002572: 4300 .C ORRS r0,r0,r0 - 0x00002574: 492f /I LDR r1,[pc,#188] ; [0x2634] = 0x10008040 - 0x00002576: 3120 1 ADDS r1,r1,#0x20 - 0x00002578: 7809 .x LDRB r1,[r1,#0] - 0x0000257a: 4308 .C ORRS r0,r0,r1 - 0x0000257c: 2101 .! MOVS r1,#1 - 0x0000257e: 4308 .C ORRS r0,r0,r1 - 0x00002580: 492c ,I LDR r1,[pc,#176] ; [0x2634] = 0x10008040 - 0x00002582: 3120 1 ADDS r1,r1,#0x20 - 0x00002584: 7008 .p STRB r0,[r1,#0] - 0x00002586: bf00 .. NOP - 0x00002588: bf00 .. NOP - 0x0000258a: 482b +H LDR r0,[pc,#172] ; [0x2638] = 0x10004fe0 - 0x0000258c: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x0000258e: 2000 . MOVS r0,#0 - 0x00002590: 7809 .x LDRB r1,[r1,#0] - 0x00002592: 4300 .C ORRS r0,r0,r0 - 0x00002594: 4927 'I LDR r1,[pc,#156] ; [0x2634] = 0x10008040 - 0x00002596: 3120 1 ADDS r1,r1,#0x20 - 0x00002598: 7809 .x LDRB r1,[r1,#0] - 0x0000259a: 4308 .C ORRS r0,r0,r1 - 0x0000259c: 4925 %I LDR r1,[pc,#148] ; [0x2634] = 0x10008040 - 0x0000259e: 3120 1 ADDS r1,r1,#0x20 - 0x000025a0: 7008 .p STRB r0,[r1,#0] - 0x000025a2: 4825 %H LDR r0,[pc,#148] ; [0x2638] = 0x10004fe0 - 0x000025a4: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x000025a6: 2000 . MOVS r0,#0 - 0x000025a8: 7809 .x LDRB r1,[r1,#0] - 0x000025aa: 4300 .C ORRS r0,r0,r0 - 0x000025ac: 4921 !I LDR r1,[pc,#132] ; [0x2634] = 0x10008040 - 0x000025ae: 3120 1 ADDS r1,r1,#0x20 - 0x000025b0: 7809 .x LDRB r1,[r1,#0] - 0x000025b2: 4308 .C ORRS r0,r0,r1 - 0x000025b4: 491f .I LDR r1,[pc,#124] ; [0x2634] = 0x10008040 - 0x000025b6: 3120 1 ADDS r1,r1,#0x20 - 0x000025b8: 7008 .p STRB r0,[r1,#0] - 0x000025ba: e039 9. B 0x2630 ; USART_DeInit + 258 - 0x000025bc: bf00 .. NOP - 0x000025be: 481e .H LDR r0,[pc,#120] ; [0x2638] = 0x10004fe0 - 0x000025c0: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x000025c2: 2000 . MOVS r0,#0 - 0x000025c4: 491b .I LDR r1,[pc,#108] ; [0x2634] = 0x10008040 - 0x000025c6: 3120 1 ADDS r1,r1,#0x20 - 0x000025c8: 7c49 I| LDRB r1,[r1,#0x11] - 0x000025ca: 4300 .C ORRS r0,r0,r0 - 0x000025cc: 4919 .I LDR r1,[pc,#100] ; [0x2634] = 0x10008040 - 0x000025ce: 3120 1 ADDS r1,r1,#0x20 - 0x000025d0: 7c49 I| LDRB r1,[r1,#0x11] - 0x000025d2: 4308 .C ORRS r0,r0,r1 - 0x000025d4: 2101 .! MOVS r1,#1 - 0x000025d6: 4308 .C ORRS r0,r0,r1 - 0x000025d8: 4916 .I LDR r1,[pc,#88] ; [0x2634] = 0x10008040 - 0x000025da: 3120 1 ADDS r1,r1,#0x20 - 0x000025dc: 7448 Ht STRB r0,[r1,#0x11] - 0x000025de: 4816 .H LDR r0,[pc,#88] ; [0x2638] = 0x10004fe0 - 0x000025e0: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x000025e2: 2000 . MOVS r0,#0 - 0x000025e4: 7c49 I| LDRB r1,[r1,#0x11] - 0x000025e6: 4300 .C ORRS r0,r0,r0 - 0x000025e8: 4912 .I LDR r1,[pc,#72] ; [0x2634] = 0x10008040 - 0x000025ea: 3120 1 ADDS r1,r1,#0x20 - 0x000025ec: 7c49 I| LDRB r1,[r1,#0x11] - 0x000025ee: 4308 .C ORRS r0,r0,r1 - 0x000025f0: 2101 .! MOVS r1,#1 - 0x000025f2: 4308 .C ORRS r0,r0,r1 - 0x000025f4: 490f .I LDR r1,[pc,#60] ; [0x2634] = 0x10008040 - 0x000025f6: 3120 1 ADDS r1,r1,#0x20 - 0x000025f8: 7448 Ht STRB r0,[r1,#0x11] - 0x000025fa: bf00 .. NOP - 0x000025fc: bf00 .. NOP - 0x000025fe: 480e .H LDR r0,[pc,#56] ; [0x2638] = 0x10004fe0 - 0x00002600: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00002602: 2000 . MOVS r0,#0 - 0x00002604: 7c49 I| LDRB r1,[r1,#0x11] - 0x00002606: 4300 .C ORRS r0,r0,r0 - 0x00002608: 490a .I LDR r1,[pc,#40] ; [0x2634] = 0x10008040 - 0x0000260a: 3120 1 ADDS r1,r1,#0x20 - 0x0000260c: 7c49 I| LDRB r1,[r1,#0x11] - 0x0000260e: 4308 .C ORRS r0,r0,r1 - 0x00002610: 4908 .I LDR r1,[pc,#32] ; [0x2634] = 0x10008040 - 0x00002612: 3120 1 ADDS r1,r1,#0x20 - 0x00002614: 7448 Ht STRB r0,[r1,#0x11] - 0x00002616: 4808 .H LDR r0,[pc,#32] ; [0x2638] = 0x10004fe0 - 0x00002618: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x0000261a: 2000 . MOVS r0,#0 - 0x0000261c: 7c49 I| LDRB r1,[r1,#0x11] - 0x0000261e: 4300 .C ORRS r0,r0,r0 - 0x00002620: 4904 .I LDR r1,[pc,#16] ; [0x2634] = 0x10008040 - 0x00002622: 3120 1 ADDS r1,r1,#0x20 - 0x00002624: 7c49 I| LDRB r1,[r1,#0x11] - 0x00002626: 4308 .C ORRS r0,r0,r1 - 0x00002628: 4902 .I LDR r1,[pc,#8] ; [0x2634] = 0x10008040 - 0x0000262a: 3120 1 ADDS r1,r1,#0x20 - 0x0000262c: 7448 Ht STRB r0,[r1,#0x11] - 0x0000262e: bf00 .. NOP - 0x00002630: bd10 .. POP {r4,pc} + 0x000023c0: 4961 aI LDR r1,[pc,#388] ; [0x2548] = 0x10004fe0 + 0x000023c2: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x000023c4: 2100 .! MOVS r1,#0 + 0x000023c6: 4b61 aK LDR r3,[pc,#388] ; [0x254c] = 0x10004400 + 0x000023c8: 795b [y LDRB r3,[r3,#5] + 0x000023ca: 4309 .C ORRS r1,r1,r1 + 0x000023cc: 4b5f _K LDR r3,[pc,#380] ; [0x254c] = 0x10004400 + 0x000023ce: 795b [y LDRB r3,[r3,#5] + 0x000023d0: 4319 .C ORRS r1,r1,r3 + 0x000023d2: 0409 .. LSLS r1,r1,#16 + 0x000023d4: 4308 .C ORRS r0,r0,r1 + 0x000023d6: 1c80 .. ADDS r0,r0,#2 + 0x000023d8: 2101 .! MOVS r1,#1 + 0x000023da: 0709 .. LSLS r1,r1,#28 + 0x000023dc: 1840 @. ADDS r0,r0,r1 + 0x000023de: 7002 .p STRB r2,[r0,#0] + 0x000023e0: 0220 . LSLS r0,r4,#8 + 0x000023e2: 0e02 .. LSRS r2,r0,#24 + 0x000023e4: 4858 XH LDR r0,[pc,#352] ; [0x2548] = 0x10004fe0 + 0x000023e6: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x000023e8: 2000 . MOVS r0,#0 + 0x000023ea: 4958 XI LDR r1,[pc,#352] ; [0x254c] = 0x10004400 + 0x000023ec: 78c9 .x LDRB r1,[r1,#3] + 0x000023ee: 4300 .C ORRS r0,r0,r0 + 0x000023f0: 4956 VI LDR r1,[pc,#344] ; [0x254c] = 0x10004400 + 0x000023f2: 78c9 .x LDRB r1,[r1,#3] + 0x000023f4: 4308 .C ORRS r0,r0,r1 + 0x000023f6: 4954 TI LDR r1,[pc,#336] ; [0x2548] = 0x10004fe0 + 0x000023f8: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x000023fa: 2100 .! MOVS r1,#0 + 0x000023fc: 4b53 SK LDR r3,[pc,#332] ; [0x254c] = 0x10004400 + 0x000023fe: 791b .y LDRB r3,[r3,#4] + 0x00002400: 4309 .C ORRS r1,r1,r1 + 0x00002402: 4b52 RK LDR r3,[pc,#328] ; [0x254c] = 0x10004400 + 0x00002404: 791b .y LDRB r3,[r3,#4] + 0x00002406: 4319 .C ORRS r1,r1,r3 + 0x00002408: 0209 .. LSLS r1,r1,#8 + 0x0000240a: 4301 .C ORRS r1,r1,r0 + 0x0000240c: 484e NH LDR r0,[pc,#312] ; [0x2548] = 0x10004fe0 + 0x0000240e: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x00002410: 2000 . MOVS r0,#0 + 0x00002412: 4b4e NK LDR r3,[pc,#312] ; [0x254c] = 0x10004400 + 0x00002414: 795b [y LDRB r3,[r3,#5] + 0x00002416: 4300 .C ORRS r0,r0,r0 + 0x00002418: 4b4c LK LDR r3,[pc,#304] ; [0x254c] = 0x10004400 + 0x0000241a: 795b [y LDRB r3,[r3,#5] + 0x0000241c: 4318 .C ORRS r0,r0,r3 + 0x0000241e: 0400 .. LSLS r0,r0,#16 + 0x00002420: 4301 .C ORRS r1,r1,r0 + 0x00002422: 1c89 .. ADDS r1,r1,#2 + 0x00002424: 2001 . MOVS r0,#1 + 0x00002426: 0700 .. LSLS r0,r0,#28 + 0x00002428: 1808 .. ADDS r0,r1,r0 + 0x0000242a: 7002 .p STRB r2,[r0,#0] + 0x0000242c: bf00 .. NOP + 0x0000242e: bf00 .. NOP + 0x00002430: bd70 p. POP {r4-r6,pc} + ipcTx + 0x00002432: b5f8 .. PUSH {r3-r7,lr} + 0x00002434: 4605 .F MOV r5,r0 + 0x00002436: 460e .F MOV r6,r1 + 0x00002438: 4943 CI LDR r1,[pc,#268] ; [0x2548] = 0x10004fe0 + 0x0000243a: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x0000243c: 2100 .! MOVS r1,#0 + 0x0000243e: 4a43 CJ LDR r2,[pc,#268] ; [0x254c] = 0x10004400 + 0x00002440: 3a20 : SUBS r2,r2,#0x20 + 0x00002442: 7e92 .~ LDRB r2,[r2,#0x1a] + 0x00002444: 4309 .C ORRS r1,r1,r1 + 0x00002446: 4a41 AJ LDR r2,[pc,#260] ; [0x254c] = 0x10004400 + 0x00002448: 3a20 : SUBS r2,r2,#0x20 + 0x0000244a: 7e92 .~ LDRB r2,[r2,#0x1a] + 0x0000244c: 4311 .C ORRS r1,r1,r2 + 0x0000244e: 4a3e >J LDR r2,[pc,#248] ; [0x2548] = 0x10004fe0 + 0x00002450: 7fd2 .. LDRB r2,[r2,#0x1f] + 0x00002452: 2200 ." MOVS r2,#0 + 0x00002454: 4b3d =K LDR r3,[pc,#244] ; [0x254c] = 0x10004400 + 0x00002456: 3b20 ; SUBS r3,r3,#0x20 + 0x00002458: 7edb .~ LDRB r3,[r3,#0x1b] + 0x0000245a: 4312 .C ORRS r2,r2,r2 + 0x0000245c: 4b3b ;K LDR r3,[pc,#236] ; [0x254c] = 0x10004400 + 0x0000245e: 3b20 ; SUBS r3,r3,#0x20 + 0x00002460: 7edb .~ LDRB r3,[r3,#0x1b] + 0x00002462: 431a .C ORRS r2,r2,r3 + 0x00002464: 0212 .. LSLS r2,r2,#8 + 0x00002466: 4311 .C ORRS r1,r1,r2 + 0x00002468: 4a37 7J LDR r2,[pc,#220] ; [0x2548] = 0x10004fe0 + 0x0000246a: 7fd2 .. LDRB r2,[r2,#0x1f] + 0x0000246c: 2200 ." MOVS r2,#0 + 0x0000246e: 4b37 7K LDR r3,[pc,#220] ; [0x254c] = 0x10004400 + 0x00002470: 3b20 ; SUBS r3,r3,#0x20 + 0x00002472: 7f1b .. LDRB r3,[r3,#0x1c] + 0x00002474: 4312 .C ORRS r2,r2,r2 + 0x00002476: 4b35 5K LDR r3,[pc,#212] ; [0x254c] = 0x10004400 + 0x00002478: 3b20 ; SUBS r3,r3,#0x20 + 0x0000247a: 7f1b .. LDRB r3,[r3,#0x1c] + 0x0000247c: 431a .C ORRS r2,r2,r3 + 0x0000247e: 0412 .. LSLS r2,r2,#16 + 0x00002480: 4311 .C ORRS r1,r1,r2 + 0x00002482: 2201 ." MOVS r2,#1 + 0x00002484: 0712 .. LSLS r2,r2,#28 + 0x00002486: 1888 .. ADDS r0,r1,r2 + 0x00002488: f000fbe9 .... BL HR_REG_24BIT ; 0x2c5e + 0x0000248c: 4604 .F MOV r4,r0 + 0x0000248e: 2000 . MOVS r0,#0 + 0x00002490: e06d m. B 0x256e ; ipcTx + 316 + 0x00002492: bf00 .. NOP + 0x00002494: 5c2a *\ LDRB r2,[r5,r0] + 0x00002496: 2101 .! MOVS r1,#1 + 0x00002498: 0709 .. LSLS r1,r1,#28 + 0x0000249a: 4321 !C ORRS r1,r1,r4 + 0x0000249c: 700a .p STRB r2,[r1,#0] + 0x0000249e: 5c2a *\ LDRB r2,[r5,r0] + 0x000024a0: 2101 .! MOVS r1,#1 + 0x000024a2: 0709 .. LSLS r1,r1,#28 + 0x000024a4: 4321 !C ORRS r1,r1,r4 + 0x000024a6: 700a .p STRB r2,[r1,#0] + 0x000024a8: bf00 .. NOP + 0x000024aa: 4927 'I LDR r1,[pc,#156] ; [0x2548] = 0x10004fe0 + 0x000024ac: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x000024ae: 2100 .! MOVS r1,#0 + 0x000024b0: 4a26 &J LDR r2,[pc,#152] ; [0x254c] = 0x10004400 + 0x000024b2: 3a20 : SUBS r2,r2,#0x20 + 0x000024b4: 7dd2 .} LDRB r2,[r2,#0x17] + 0x000024b6: 4309 .C ORRS r1,r1,r1 + 0x000024b8: 4a24 $J LDR r2,[pc,#144] ; [0x254c] = 0x10004400 + 0x000024ba: 3a20 : SUBS r2,r2,#0x20 + 0x000024bc: 7dd2 .} LDRB r2,[r2,#0x17] + 0x000024be: 4311 .C ORRS r1,r1,r2 + 0x000024c0: 4a21 !J LDR r2,[pc,#132] ; [0x2548] = 0x10004fe0 + 0x000024c2: 7fd2 .. LDRB r2,[r2,#0x1f] + 0x000024c4: 2200 ." MOVS r2,#0 + 0x000024c6: 4b21 !K LDR r3,[pc,#132] ; [0x254c] = 0x10004400 + 0x000024c8: 3b20 ; SUBS r3,r3,#0x20 + 0x000024ca: 7e1b .~ LDRB r3,[r3,#0x18] + 0x000024cc: 4312 .C ORRS r2,r2,r2 + 0x000024ce: 4b1f .K LDR r3,[pc,#124] ; [0x254c] = 0x10004400 + 0x000024d0: 3b20 ; SUBS r3,r3,#0x20 + 0x000024d2: 7e1b .~ LDRB r3,[r3,#0x18] + 0x000024d4: 431a .C ORRS r2,r2,r3 + 0x000024d6: 0212 .. LSLS r2,r2,#8 + 0x000024d8: 4311 .C ORRS r1,r1,r2 + 0x000024da: 4a1b .J LDR r2,[pc,#108] ; [0x2548] = 0x10004fe0 + 0x000024dc: 7fd2 .. LDRB r2,[r2,#0x1f] + 0x000024de: 2200 ." MOVS r2,#0 + 0x000024e0: 4b1a .K LDR r3,[pc,#104] ; [0x254c] = 0x10004400 + 0x000024e2: 3b20 ; SUBS r3,r3,#0x20 + 0x000024e4: 7e5b [~ LDRB r3,[r3,#0x19] + 0x000024e6: 4312 .C ORRS r2,r2,r2 + 0x000024e8: 4b18 .K LDR r3,[pc,#96] ; [0x254c] = 0x10004400 + 0x000024ea: 3b20 ; SUBS r3,r3,#0x20 + 0x000024ec: 7e5b [~ LDRB r3,[r3,#0x19] + 0x000024ee: 431a .C ORRS r2,r2,r3 + 0x000024f0: 0412 .. LSLS r2,r2,#16 + 0x000024f2: 4311 .C ORRS r1,r1,r2 + 0x000024f4: 1c62 b. ADDS r2,r4,#1 + 0x000024f6: 4614 .F MOV r4,r2 + 0x000024f8: 4291 .B CMP r1,r2 + 0x000024fa: d830 0. BHI 0x255e ; ipcTx + 300 + 0x000024fc: 4912 .I LDR r1,[pc,#72] ; [0x2548] = 0x10004fe0 + 0x000024fe: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x00002500: 2100 .! MOVS r1,#0 + 0x00002502: 4a12 .J LDR r2,[pc,#72] ; [0x254c] = 0x10004400 + 0x00002504: 3a20 : SUBS r2,r2,#0x20 + 0x00002506: 7d12 .} LDRB r2,[r2,#0x14] + 0x00002508: 4309 .C ORRS r1,r1,r1 + 0x0000250a: 4a10 .J LDR r2,[pc,#64] ; [0x254c] = 0x10004400 + 0x0000250c: 3a20 : SUBS r2,r2,#0x20 + 0x0000250e: 7d12 .} LDRB r2,[r2,#0x14] + 0x00002510: 4311 .C ORRS r1,r1,r2 + 0x00002512: 4a0d .J LDR r2,[pc,#52] ; [0x2548] = 0x10004fe0 + 0x00002514: 7fd2 .. LDRB r2,[r2,#0x1f] + 0x00002516: 2200 ." MOVS r2,#0 + 0x00002518: 4b0c .K LDR r3,[pc,#48] ; [0x254c] = 0x10004400 + 0x0000251a: 3b20 ; SUBS r3,r3,#0x20 + 0x0000251c: 7d5b [} LDRB r3,[r3,#0x15] + 0x0000251e: 4312 .C ORRS r2,r2,r2 + 0x00002520: 4b0a .K LDR r3,[pc,#40] ; [0x254c] = 0x10004400 + 0x00002522: 3b20 ; SUBS r3,r3,#0x20 + 0x00002524: 7d5b [} LDRB r3,[r3,#0x15] + 0x00002526: 431a .C ORRS r2,r2,r3 + 0x00002528: 0212 .. LSLS r2,r2,#8 + 0x0000252a: 4311 .C ORRS r1,r1,r2 + 0x0000252c: 4a06 .J LDR r2,[pc,#24] ; [0x2548] = 0x10004fe0 + 0x0000252e: 7fd2 .. LDRB r2,[r2,#0x1f] + 0x00002530: 2200 ." MOVS r2,#0 + 0x00002532: 4b06 .K LDR r3,[pc,#24] ; [0x254c] = 0x10004400 + 0x00002534: 3b20 ; SUBS r3,r3,#0x20 + 0x00002536: 7d9b .} LDRB r3,[r3,#0x16] + 0x00002538: 4312 .C ORRS r2,r2,r2 + 0x0000253a: e009 .. B 0x2550 ; ipcTx + 286 $d - 0x00002632: 0000 .. DCW 0 - 0x00002634: 10008040 @... DCD 268468288 - 0x00002638: 10004fe0 .O.. DCD 268455904 - 0x0000263c: 000077aa .w.. DCD 30634 - 0x00002640: 2e5c2e2e ..\. DCD 777793070 - 0x00002644: 2e2e5c2e .\.. DCD 774790190 - 0x00002648: 5c2e2e5c \..\ DCD 1546530396 - 0x0000264c: 2e5c2e2e ..\. DCD 777793070 - 0x00002650: 694c5c2e .\Li DCD 1766612014 - 0x00002654: 72617262 brar DCD 1918988898 - 0x00002658: 5c726569 ier\ DCD 1551000937 - 0x0000265c: 76697264 driv DCD 1986622052 - 0x00002660: 5c737265 ers\ DCD 1551069797 - 0x00002664: 74726175 uart DCD 1953653109 - 0x00002668: 3163795c \yc1 DCD 828602716 - 0x0000266c: 5f787831 1xx_ DCD 1601730609 - 0x00002670: 74726175 uart DCD 1953653109 - 0x00002674: 0000632e .c.. DCD 25390 - 0x00002678: 0000ce20 ... DCD 52768 - 0x0000267c: 00001001 .... DCD 4097 - 0x00002680: 10011044 D... DCD 268505156 - 0x00002684: 10011064 d... DCD 268505188 - 0x00002688: 10012065 e .. DCD 268509285 - 0x0000268c: 1001101c .... DCD 268505116 - 0x00002690: 1001101e .... DCD 268505118 - 0x00002694: 00008060 `... DCD 32864 - 0x00002698: 10011018 .... DCD 268505112 - 0x0000269c: 000077b5 .w.. DCD 30645 + 0x0000253c: 10011018 .... DCD 268505112 + 0x00002540: 10011034 4... DCD 268505140 + 0x00002544: 10011014 .... DCD 268505108 + 0x00002548: 10004fe0 .O.. DCD 268455904 + 0x0000254c: 10004400 .D.. DCD 268452864 $t - USART_SendData - 0x000026a0: b5f8 .. PUSH {r3-r7,lr} - 0x000026a2: 4604 .F MOV r4,r0 - 0x000026a4: 460f .F MOV r7,r1 - 0x000026a6: 2500 .% MOVS r5,#0 - 0x000026a8: 2600 .& MOVS r6,#0 - 0x000026aa: 2c00 ., CMP r4,#0 - 0x000026ac: d006 .. BEQ 0x26bc ; USART_SendData + 28 - 0x000026ae: 2c01 ., CMP r4,#1 - 0x000026b0: d004 .. BEQ 0x26bc ; USART_SendData + 28 - 0x000026b2: 4af7 .J LDR r2,[pc,#988] ; [0x2a90] = 0x77c2 - 0x000026b4: 21bb .! MOVS r1,#0xbb - 0x000026b6: 48f7 .H LDR r0,[pc,#988] ; [0x2a94] = 0x2640 - 0x000026b8: f7fefda9 .... BL _assert_handler ; 0x120e - 0x000026bc: 2c00 ., CMP r4,#0 - 0x000026be: d101 .. BNE 0x26c4 ; USART_SendData + 36 - 0x000026c0: 4df5 .M LDR r5,[pc,#980] ; [0x2a98] = 0x10008052 - 0x000026c2: e001 .. B 0x26c8 ; USART_SendData + 40 - 0x000026c4: 4df4 .M LDR r5,[pc,#976] ; [0x2a98] = 0x10008052 - 0x000026c6: 3520 5 ADDS r5,r5,#0x20 - 0x000026c8: 4628 (F MOV r0,r5 - 0x000026ca: 3008 .0 ADDS r0,r0,#8 - 0x000026cc: 2800 .( CMP r0,#0 - 0x000026ce: d104 .. BNE 0x26da ; USART_SendData + 58 - 0x000026d0: 4aef .J LDR r2,[pc,#956] ; [0x2a90] = 0x77c2 - 0x000026d2: 21c2 .! MOVS r1,#0xc2 - 0x000026d4: 48ef .H LDR r0,[pc,#956] ; [0x2a94] = 0x2640 - 0x000026d6: f7fefd9a .... BL _assert_handler ; 0x120e - 0x000026da: 4628 (F MOV r0,r5 - 0x000026dc: 300c .0 ADDS r0,r0,#0xc - 0x000026de: f000fa17 .... BL HR_REG_16BIT ; 0x2b10 - 0x000026e2: 4606 .F MOV r6,r0 - 0x000026e4: 2c00 ., CMP r4,#0 - 0x000026e6: d10c .. BNE 0x2702 ; USART_SendData + 98 - 0x000026e8: bf00 .. NOP - 0x000026ea: 48ec .H LDR r0,[pc,#944] ; [0x2a9c] = 0x10004fe0 - 0x000026ec: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x000026ee: 2000 . MOVS r0,#0 - 0x000026f0: 49eb .I LDR r1,[pc,#940] ; [0x2aa0] = 0x10008300 - 0x000026f2: 7b89 .{ LDRB r1,[r1,#0xe] - 0x000026f4: 4300 .C ORRS r0,r0,r0 - 0x000026f6: 49ea .I LDR r1,[pc,#936] ; [0x2aa0] = 0x10008300 - 0x000026f8: 7b89 .{ LDRB r1,[r1,#0xe] - 0x000026fa: 4308 .C ORRS r0,r0,r1 - 0x000026fc: 2800 .( CMP r0,#0 - 0x000026fe: dcf4 .. BGT 0x26ea ; USART_SendData + 74 - 0x00002700: e00d .. B 0x271e ; USART_SendData + 126 - 0x00002702: bf00 .. NOP - 0x00002704: 48e5 .H LDR r0,[pc,#916] ; [0x2a9c] = 0x10004fe0 - 0x00002706: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00002708: 2000 . MOVS r0,#0 - 0x0000270a: 49e5 .I LDR r1,[pc,#916] ; [0x2aa0] = 0x10008300 - 0x0000270c: 3140 @1 ADDS r1,r1,#0x40 - 0x0000270e: 7d89 .} LDRB r1,[r1,#0x16] - 0x00002710: 4300 .C ORRS r0,r0,r0 - 0x00002712: 49e3 .I LDR r1,[pc,#908] ; [0x2aa0] = 0x10008300 - 0x00002714: 3140 @1 ADDS r1,r1,#0x40 - 0x00002716: 7d89 .} LDRB r1,[r1,#0x16] - 0x00002718: 4308 .C ORRS r0,r0,r1 - 0x0000271a: 2800 .( CMP r0,#0 - 0x0000271c: dcf2 .. BGT 0x2704 ; USART_SendData + 100 - 0x0000271e: 48e1 .H LDR r0,[pc,#900] ; [0x2aa4] = 0x10010000 - 0x00002720: 1830 0. ADDS r0,r6,r0 - 0x00002722: 7007 .p STRB r7,[r0,#0] - 0x00002724: 4628 (F MOV r0,r5 - 0x00002726: 300a .0 ADDS r0,r0,#0xa - 0x00002728: f000f9f2 .... BL HR_REG_16BIT ; 0x2b10 - 0x0000272c: 42b0 .B CMP r0,r6 - 0x0000272e: d105 .. BNE 0x273c ; USART_SendData + 156 - 0x00002730: 4628 (F MOV r0,r5 - 0x00002732: 3008 .0 ADDS r0,r0,#8 - 0x00002734: f000f9ec .... BL HR_REG_16BIT ; 0x2b10 - 0x00002738: 4606 .F MOV r6,r0 - 0x0000273a: e001 .. B 0x2740 ; USART_SendData + 160 - 0x0000273c: 1c70 p. ADDS r0,r6,#1 - 0x0000273e: b286 .. UXTH r6,r0 - 0x00002740: 4631 1F MOV r1,r6 - 0x00002742: 4628 (F MOV r0,r5 - 0x00002744: 300c .0 ADDS r0,r0,#0xc - 0x00002746: f000f9da .... BL HW_REG_16BIT ; 0x2afe - 0x0000274a: 2c00 ., CMP r4,#0 - 0x0000274c: d117 .. BNE 0x277e ; USART_SendData + 222 - 0x0000274e: bf00 .. NOP - 0x00002750: 48d2 .H LDR r0,[pc,#840] ; [0x2a9c] = 0x10004fe0 - 0x00002752: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00002754: 2000 . MOVS r0,#0 - 0x00002756: 49d2 .I LDR r1,[pc,#840] ; [0x2aa0] = 0x10008300 - 0x00002758: 7b89 .{ LDRB r1,[r1,#0xe] - 0x0000275a: 4300 .C ORRS r0,r0,r0 - 0x0000275c: 49d0 .I LDR r1,[pc,#832] ; [0x2aa0] = 0x10008300 - 0x0000275e: 7b89 .{ LDRB r1,[r1,#0xe] + 0x00002550: 4bfe .K LDR r3,[pc,#1016] ; [0x294c] = 0x10004400 + 0x00002552: 3b20 ; SUBS r3,r3,#0x20 + 0x00002554: 7d9b .} LDRB r3,[r3,#0x16] + 0x00002556: 431a .C ORRS r2,r2,r3 + 0x00002558: 0412 .. LSLS r2,r2,#16 + 0x0000255a: 4311 .C ORRS r1,r1,r2 + 0x0000255c: 460c .F MOV r4,r1 + 0x0000255e: 2764 d' MOVS r7,#0x64 + 0x00002560: bf00 .. NOP + 0x00002562: 4639 9F MOV r1,r7 + 0x00002564: 1e7f .. SUBS r7,r7,#1 + 0x00002566: 2900 .) CMP r1,#0 + 0x00002568: d1fb .. BNE 0x2562 ; ipcTx + 304 + 0x0000256a: 1c41 A. ADDS r1,r0,#1 + 0x0000256c: b288 .. UXTH r0,r1 + 0x0000256e: 42b0 .B CMP r0,r6 + 0x00002570: db8f .. BLT 0x2492 ; ipcTx + 96 + 0x00002572: bf00 .. NOP + 0x00002574: bf00 .. NOP + 0x00002576: b2e2 .. UXTB r2,r4 + 0x00002578: 48f5 .H LDR r0,[pc,#980] ; [0x2950] = 0x10004fe0 + 0x0000257a: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x0000257c: 2000 . MOVS r0,#0 + 0x0000257e: 49f3 .I LDR r1,[pc,#972] ; [0x294c] = 0x10004400 + 0x00002580: 3920 9 SUBS r1,r1,#0x20 + 0x00002582: 7e89 .~ LDRB r1,[r1,#0x1a] + 0x00002584: 4300 .C ORRS r0,r0,r0 + 0x00002586: 49f1 .I LDR r1,[pc,#964] ; [0x294c] = 0x10004400 + 0x00002588: 3920 9 SUBS r1,r1,#0x20 + 0x0000258a: 7e89 .~ LDRB r1,[r1,#0x1a] + 0x0000258c: 4308 .C ORRS r0,r0,r1 + 0x0000258e: 49f0 .I LDR r1,[pc,#960] ; [0x2950] = 0x10004fe0 + 0x00002590: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x00002592: 2100 .! MOVS r1,#0 + 0x00002594: 4bed .K LDR r3,[pc,#948] ; [0x294c] = 0x10004400 + 0x00002596: 3b20 ; SUBS r3,r3,#0x20 + 0x00002598: 7edb .~ LDRB r3,[r3,#0x1b] + 0x0000259a: 4309 .C ORRS r1,r1,r1 + 0x0000259c: 4beb .K LDR r3,[pc,#940] ; [0x294c] = 0x10004400 + 0x0000259e: 3b20 ; SUBS r3,r3,#0x20 + 0x000025a0: 7edb .~ LDRB r3,[r3,#0x1b] + 0x000025a2: 4319 .C ORRS r1,r1,r3 + 0x000025a4: 0209 .. LSLS r1,r1,#8 + 0x000025a6: 4308 .C ORRS r0,r0,r1 + 0x000025a8: 49e9 .I LDR r1,[pc,#932] ; [0x2950] = 0x10004fe0 + 0x000025aa: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x000025ac: 2100 .! MOVS r1,#0 + 0x000025ae: 4be7 .K LDR r3,[pc,#924] ; [0x294c] = 0x10004400 + 0x000025b0: 3b20 ; SUBS r3,r3,#0x20 + 0x000025b2: 7f1b .. LDRB r3,[r3,#0x1c] + 0x000025b4: 4309 .C ORRS r1,r1,r1 + 0x000025b6: 4be5 .K LDR r3,[pc,#916] ; [0x294c] = 0x10004400 + 0x000025b8: 3b20 ; SUBS r3,r3,#0x20 + 0x000025ba: 7f1b .. LDRB r3,[r3,#0x1c] + 0x000025bc: 4319 .C ORRS r1,r1,r3 + 0x000025be: 0409 .. LSLS r1,r1,#16 + 0x000025c0: 4308 .C ORRS r0,r0,r1 + 0x000025c2: 2101 .! MOVS r1,#1 + 0x000025c4: 0709 .. LSLS r1,r1,#28 + 0x000025c6: 1840 @. ADDS r0,r0,r1 + 0x000025c8: 7002 .p STRB r2,[r0,#0] + 0x000025ca: b2e2 .. UXTB r2,r4 + 0x000025cc: 48e0 .H LDR r0,[pc,#896] ; [0x2950] = 0x10004fe0 + 0x000025ce: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x000025d0: 2000 . MOVS r0,#0 + 0x000025d2: 49de .I LDR r1,[pc,#888] ; [0x294c] = 0x10004400 + 0x000025d4: 3920 9 SUBS r1,r1,#0x20 + 0x000025d6: 7e89 .~ LDRB r1,[r1,#0x1a] + 0x000025d8: 4300 .C ORRS r0,r0,r0 + 0x000025da: 49dc .I LDR r1,[pc,#880] ; [0x294c] = 0x10004400 + 0x000025dc: 3920 9 SUBS r1,r1,#0x20 + 0x000025de: 7e89 .~ LDRB r1,[r1,#0x1a] + 0x000025e0: 4308 .C ORRS r0,r0,r1 + 0x000025e2: 49db .I LDR r1,[pc,#876] ; [0x2950] = 0x10004fe0 + 0x000025e4: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x000025e6: 2100 .! MOVS r1,#0 + 0x000025e8: 4bd8 .K LDR r3,[pc,#864] ; [0x294c] = 0x10004400 + 0x000025ea: 3b20 ; SUBS r3,r3,#0x20 + 0x000025ec: 7edb .~ LDRB r3,[r3,#0x1b] + 0x000025ee: 4309 .C ORRS r1,r1,r1 + 0x000025f0: 4bd6 .K LDR r3,[pc,#856] ; [0x294c] = 0x10004400 + 0x000025f2: 3b20 ; SUBS r3,r3,#0x20 + 0x000025f4: 7edb .~ LDRB r3,[r3,#0x1b] + 0x000025f6: 4319 .C ORRS r1,r1,r3 + 0x000025f8: 0209 .. LSLS r1,r1,#8 + 0x000025fa: 4308 .C ORRS r0,r0,r1 + 0x000025fc: 49d4 .I LDR r1,[pc,#848] ; [0x2950] = 0x10004fe0 + 0x000025fe: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x00002600: 2100 .! MOVS r1,#0 + 0x00002602: 4bd2 .K LDR r3,[pc,#840] ; [0x294c] = 0x10004400 + 0x00002604: 3b20 ; SUBS r3,r3,#0x20 + 0x00002606: 7f1b .. LDRB r3,[r3,#0x1c] + 0x00002608: 4309 .C ORRS r1,r1,r1 + 0x0000260a: 4bd0 .K LDR r3,[pc,#832] ; [0x294c] = 0x10004400 + 0x0000260c: 3b20 ; SUBS r3,r3,#0x20 + 0x0000260e: 7f1b .. LDRB r3,[r3,#0x1c] + 0x00002610: 4319 .C ORRS r1,r1,r3 + 0x00002612: 0409 .. LSLS r1,r1,#16 + 0x00002614: 4308 .C ORRS r0,r0,r1 + 0x00002616: 2101 .! MOVS r1,#1 + 0x00002618: 0709 .. LSLS r1,r1,#28 + 0x0000261a: 1840 @. ADDS r0,r0,r1 + 0x0000261c: 7002 .p STRB r2,[r0,#0] + 0x0000261e: bf00 .. NOP + 0x00002620: bf00 .. NOP + 0x00002622: 0420 . LSLS r0,r4,#16 + 0x00002624: 0e02 .. LSRS r2,r0,#24 + 0x00002626: 48ca .H LDR r0,[pc,#808] ; [0x2950] = 0x10004fe0 + 0x00002628: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x0000262a: 2000 . MOVS r0,#0 + 0x0000262c: 49c7 .I LDR r1,[pc,#796] ; [0x294c] = 0x10004400 + 0x0000262e: 3920 9 SUBS r1,r1,#0x20 + 0x00002630: 7e89 .~ LDRB r1,[r1,#0x1a] + 0x00002632: 4300 .C ORRS r0,r0,r0 + 0x00002634: 49c5 .I LDR r1,[pc,#788] ; [0x294c] = 0x10004400 + 0x00002636: 3920 9 SUBS r1,r1,#0x20 + 0x00002638: 7e89 .~ LDRB r1,[r1,#0x1a] + 0x0000263a: 4308 .C ORRS r0,r0,r1 + 0x0000263c: 49c4 .I LDR r1,[pc,#784] ; [0x2950] = 0x10004fe0 + 0x0000263e: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x00002640: 2100 .! MOVS r1,#0 + 0x00002642: 4bc2 .K LDR r3,[pc,#776] ; [0x294c] = 0x10004400 + 0x00002644: 3b20 ; SUBS r3,r3,#0x20 + 0x00002646: 7edb .~ LDRB r3,[r3,#0x1b] + 0x00002648: 4309 .C ORRS r1,r1,r1 + 0x0000264a: 4bc0 .K LDR r3,[pc,#768] ; [0x294c] = 0x10004400 + 0x0000264c: 3b20 ; SUBS r3,r3,#0x20 + 0x0000264e: 7edb .~ LDRB r3,[r3,#0x1b] + 0x00002650: 4319 .C ORRS r1,r1,r3 + 0x00002652: 0209 .. LSLS r1,r1,#8 + 0x00002654: 4308 .C ORRS r0,r0,r1 + 0x00002656: 49be .I LDR r1,[pc,#760] ; [0x2950] = 0x10004fe0 + 0x00002658: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x0000265a: 2100 .! MOVS r1,#0 + 0x0000265c: 4bbb .K LDR r3,[pc,#748] ; [0x294c] = 0x10004400 + 0x0000265e: 3b20 ; SUBS r3,r3,#0x20 + 0x00002660: 7f1b .. LDRB r3,[r3,#0x1c] + 0x00002662: 4309 .C ORRS r1,r1,r1 + 0x00002664: 4bb9 .K LDR r3,[pc,#740] ; [0x294c] = 0x10004400 + 0x00002666: 3b20 ; SUBS r3,r3,#0x20 + 0x00002668: 7f1b .. LDRB r3,[r3,#0x1c] + 0x0000266a: 4319 .C ORRS r1,r1,r3 + 0x0000266c: 0409 .. LSLS r1,r1,#16 + 0x0000266e: 4308 .C ORRS r0,r0,r1 + 0x00002670: 1c40 @. ADDS r0,r0,#1 + 0x00002672: 2101 .! MOVS r1,#1 + 0x00002674: 0709 .. LSLS r1,r1,#28 + 0x00002676: 1840 @. ADDS r0,r0,r1 + 0x00002678: 7002 .p STRB r2,[r0,#0] + 0x0000267a: 0420 . LSLS r0,r4,#16 + 0x0000267c: 0e02 .. LSRS r2,r0,#24 + 0x0000267e: 48b4 .H LDR r0,[pc,#720] ; [0x2950] = 0x10004fe0 + 0x00002680: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x00002682: 2000 . MOVS r0,#0 + 0x00002684: 49b1 .I LDR r1,[pc,#708] ; [0x294c] = 0x10004400 + 0x00002686: 3920 9 SUBS r1,r1,#0x20 + 0x00002688: 7e89 .~ LDRB r1,[r1,#0x1a] + 0x0000268a: 4300 .C ORRS r0,r0,r0 + 0x0000268c: 49af .I LDR r1,[pc,#700] ; [0x294c] = 0x10004400 + 0x0000268e: 3920 9 SUBS r1,r1,#0x20 + 0x00002690: 7e89 .~ LDRB r1,[r1,#0x1a] + 0x00002692: 4308 .C ORRS r0,r0,r1 + 0x00002694: 49ae .I LDR r1,[pc,#696] ; [0x2950] = 0x10004fe0 + 0x00002696: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x00002698: 2100 .! MOVS r1,#0 + 0x0000269a: 4bac .K LDR r3,[pc,#688] ; [0x294c] = 0x10004400 + 0x0000269c: 3b20 ; SUBS r3,r3,#0x20 + 0x0000269e: 7edb .~ LDRB r3,[r3,#0x1b] + 0x000026a0: 4309 .C ORRS r1,r1,r1 + 0x000026a2: 4baa .K LDR r3,[pc,#680] ; [0x294c] = 0x10004400 + 0x000026a4: 3b20 ; SUBS r3,r3,#0x20 + 0x000026a6: 7edb .~ LDRB r3,[r3,#0x1b] + 0x000026a8: 4319 .C ORRS r1,r1,r3 + 0x000026aa: 0209 .. LSLS r1,r1,#8 + 0x000026ac: 4308 .C ORRS r0,r0,r1 + 0x000026ae: 49a8 .I LDR r1,[pc,#672] ; [0x2950] = 0x10004fe0 + 0x000026b0: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x000026b2: 2100 .! MOVS r1,#0 + 0x000026b4: 4ba5 .K LDR r3,[pc,#660] ; [0x294c] = 0x10004400 + 0x000026b6: 3b20 ; SUBS r3,r3,#0x20 + 0x000026b8: 7f1b .. LDRB r3,[r3,#0x1c] + 0x000026ba: 4309 .C ORRS r1,r1,r1 + 0x000026bc: 4ba3 .K LDR r3,[pc,#652] ; [0x294c] = 0x10004400 + 0x000026be: 3b20 ; SUBS r3,r3,#0x20 + 0x000026c0: 7f1b .. LDRB r3,[r3,#0x1c] + 0x000026c2: 4319 .C ORRS r1,r1,r3 + 0x000026c4: 0409 .. LSLS r1,r1,#16 + 0x000026c6: 4308 .C ORRS r0,r0,r1 + 0x000026c8: 1c40 @. ADDS r0,r0,#1 + 0x000026ca: 2101 .! MOVS r1,#1 + 0x000026cc: 0709 .. LSLS r1,r1,#28 + 0x000026ce: 1840 @. ADDS r0,r0,r1 + 0x000026d0: 7002 .p STRB r2,[r0,#0] + 0x000026d2: bf00 .. NOP + 0x000026d4: bf00 .. NOP + 0x000026d6: 0220 . LSLS r0,r4,#8 + 0x000026d8: 0e02 .. LSRS r2,r0,#24 + 0x000026da: 489d .H LDR r0,[pc,#628] ; [0x2950] = 0x10004fe0 + 0x000026dc: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x000026de: 2000 . MOVS r0,#0 + 0x000026e0: 499a .I LDR r1,[pc,#616] ; [0x294c] = 0x10004400 + 0x000026e2: 3920 9 SUBS r1,r1,#0x20 + 0x000026e4: 7e89 .~ LDRB r1,[r1,#0x1a] + 0x000026e6: 4300 .C ORRS r0,r0,r0 + 0x000026e8: 4998 .I LDR r1,[pc,#608] ; [0x294c] = 0x10004400 + 0x000026ea: 3920 9 SUBS r1,r1,#0x20 + 0x000026ec: 7e89 .~ LDRB r1,[r1,#0x1a] + 0x000026ee: 4308 .C ORRS r0,r0,r1 + 0x000026f0: 4997 .I LDR r1,[pc,#604] ; [0x2950] = 0x10004fe0 + 0x000026f2: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x000026f4: 2100 .! MOVS r1,#0 + 0x000026f6: 4b95 .K LDR r3,[pc,#596] ; [0x294c] = 0x10004400 + 0x000026f8: 3b20 ; SUBS r3,r3,#0x20 + 0x000026fa: 7edb .~ LDRB r3,[r3,#0x1b] + 0x000026fc: 4309 .C ORRS r1,r1,r1 + 0x000026fe: 4b93 .K LDR r3,[pc,#588] ; [0x294c] = 0x10004400 + 0x00002700: 3b20 ; SUBS r3,r3,#0x20 + 0x00002702: 7edb .~ LDRB r3,[r3,#0x1b] + 0x00002704: 4319 .C ORRS r1,r1,r3 + 0x00002706: 0209 .. LSLS r1,r1,#8 + 0x00002708: 4308 .C ORRS r0,r0,r1 + 0x0000270a: 4991 .I LDR r1,[pc,#580] ; [0x2950] = 0x10004fe0 + 0x0000270c: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x0000270e: 2100 .! MOVS r1,#0 + 0x00002710: 4b8e .K LDR r3,[pc,#568] ; [0x294c] = 0x10004400 + 0x00002712: 3b20 ; SUBS r3,r3,#0x20 + 0x00002714: 7f1b .. LDRB r3,[r3,#0x1c] + 0x00002716: 4309 .C ORRS r1,r1,r1 + 0x00002718: 4b8c .K LDR r3,[pc,#560] ; [0x294c] = 0x10004400 + 0x0000271a: 3b20 ; SUBS r3,r3,#0x20 + 0x0000271c: 7f1b .. LDRB r3,[r3,#0x1c] + 0x0000271e: 4319 .C ORRS r1,r1,r3 + 0x00002720: 0409 .. LSLS r1,r1,#16 + 0x00002722: 4308 .C ORRS r0,r0,r1 + 0x00002724: 1c80 .. ADDS r0,r0,#2 + 0x00002726: 2101 .! MOVS r1,#1 + 0x00002728: 0709 .. LSLS r1,r1,#28 + 0x0000272a: 1840 @. ADDS r0,r0,r1 + 0x0000272c: 7002 .p STRB r2,[r0,#0] + 0x0000272e: 0220 . LSLS r0,r4,#8 + 0x00002730: 0e02 .. LSRS r2,r0,#24 + 0x00002732: 4887 .H LDR r0,[pc,#540] ; [0x2950] = 0x10004fe0 + 0x00002734: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x00002736: 2000 . MOVS r0,#0 + 0x00002738: 4984 .I LDR r1,[pc,#528] ; [0x294c] = 0x10004400 + 0x0000273a: 3920 9 SUBS r1,r1,#0x20 + 0x0000273c: 7e89 .~ LDRB r1,[r1,#0x1a] + 0x0000273e: 4300 .C ORRS r0,r0,r0 + 0x00002740: 4982 .I LDR r1,[pc,#520] ; [0x294c] = 0x10004400 + 0x00002742: 3920 9 SUBS r1,r1,#0x20 + 0x00002744: 7e89 .~ LDRB r1,[r1,#0x1a] + 0x00002746: 4308 .C ORRS r0,r0,r1 + 0x00002748: 4981 .I LDR r1,[pc,#516] ; [0x2950] = 0x10004fe0 + 0x0000274a: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x0000274c: 2100 .! MOVS r1,#0 + 0x0000274e: 4b7f .K LDR r3,[pc,#508] ; [0x294c] = 0x10004400 + 0x00002750: 3b20 ; SUBS r3,r3,#0x20 + 0x00002752: 7edb .~ LDRB r3,[r3,#0x1b] + 0x00002754: 4309 .C ORRS r1,r1,r1 + 0x00002756: 4b7d }K LDR r3,[pc,#500] ; [0x294c] = 0x10004400 + 0x00002758: 3b20 ; SUBS r3,r3,#0x20 + 0x0000275a: 7edb .~ LDRB r3,[r3,#0x1b] + 0x0000275c: 4319 .C ORRS r1,r1,r3 + 0x0000275e: 0209 .. LSLS r1,r1,#8 0x00002760: 4308 .C ORRS r0,r0,r1 - 0x00002762: 49ce .I LDR r1,[pc,#824] ; [0x2a9c] = 0x10004fe0 + 0x00002762: 497b {I LDR r1,[pc,#492] ; [0x2950] = 0x10004fe0 0x00002764: 7fc9 .. LDRB r1,[r1,#0x1f] 0x00002766: 2100 .! MOVS r1,#0 - 0x00002768: 4acd .J LDR r2,[pc,#820] ; [0x2aa0] = 0x10008300 - 0x0000276a: 7bd2 .{ LDRB r2,[r2,#0xf] - 0x0000276c: 4309 .C ORRS r1,r1,r1 - 0x0000276e: 4acc .J LDR r2,[pc,#816] ; [0x2aa0] = 0x10008300 - 0x00002770: 7bd2 .{ LDRB r2,[r2,#0xf] - 0x00002772: 4311 .C ORRS r1,r1,r2 - 0x00002774: 0209 .. LSLS r1,r1,#8 - 0x00002776: 4308 .C ORRS r0,r0,r1 - 0x00002778: 2800 .( CMP r0,#0 - 0x0000277a: d1e9 .. BNE 0x2750 ; USART_SendData + 176 - 0x0000277c: e01a .. B 0x27b4 ; USART_SendData + 276 - 0x0000277e: bf00 .. NOP - 0x00002780: 48c6 .H LDR r0,[pc,#792] ; [0x2a9c] = 0x10004fe0 - 0x00002782: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00002784: 2000 . MOVS r0,#0 - 0x00002786: 49c6 .I LDR r1,[pc,#792] ; [0x2aa0] = 0x10008300 - 0x00002788: 3140 @1 ADDS r1,r1,#0x40 - 0x0000278a: 7d89 .} LDRB r1,[r1,#0x16] - 0x0000278c: 4300 .C ORRS r0,r0,r0 - 0x0000278e: 49c4 .I LDR r1,[pc,#784] ; [0x2aa0] = 0x10008300 - 0x00002790: 3140 @1 ADDS r1,r1,#0x40 - 0x00002792: 7d89 .} LDRB r1,[r1,#0x16] - 0x00002794: 4308 .C ORRS r0,r0,r1 - 0x00002796: 49c1 .I LDR r1,[pc,#772] ; [0x2a9c] = 0x10004fe0 - 0x00002798: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x0000279a: 2100 .! MOVS r1,#0 - 0x0000279c: 4ac0 .J LDR r2,[pc,#768] ; [0x2aa0] = 0x10008300 - 0x0000279e: 3240 @2 ADDS r2,r2,#0x40 - 0x000027a0: 7dd2 .} LDRB r2,[r2,#0x17] - 0x000027a2: 4309 .C ORRS r1,r1,r1 - 0x000027a4: 4abe .J LDR r2,[pc,#760] ; [0x2aa0] = 0x10008300 - 0x000027a6: 3240 @2 ADDS r2,r2,#0x40 - 0x000027a8: 7dd2 .} LDRB r2,[r2,#0x17] - 0x000027aa: 4311 .C ORRS r1,r1,r2 - 0x000027ac: 0209 .. LSLS r1,r1,#8 - 0x000027ae: 4308 .C ORRS r0,r0,r1 - 0x000027b0: 2800 .( CMP r0,#0 - 0x000027b2: d1e5 .. BNE 0x2780 ; USART_SendData + 224 - 0x000027b4: bdf8 .. POP {r3-r7,pc} - USART_ReceiveData - 0x000027b6: b5f8 .. PUSH {r3-r7,lr} - 0x000027b8: 4604 .F MOV r4,r0 - 0x000027ba: 2500 .% MOVS r5,#0 - 0x000027bc: 2600 .& MOVS r6,#0 - 0x000027be: 2700 .' MOVS r7,#0 - 0x000027c0: 2c00 ., CMP r4,#0 - 0x000027c2: d006 .. BEQ 0x27d2 ; USART_ReceiveData + 28 - 0x000027c4: 2c01 ., CMP r4,#1 - 0x000027c6: d004 .. BEQ 0x27d2 ; USART_ReceiveData + 28 - 0x000027c8: 4ab7 .J LDR r2,[pc,#732] ; [0x2aa8] = 0x77d1 - 0x000027ca: 21e7 .! MOVS r1,#0xe7 - 0x000027cc: 48b1 .H LDR r0,[pc,#708] ; [0x2a94] = 0x2640 - 0x000027ce: f7fefd1e .... BL _assert_handler ; 0x120e - 0x000027d2: 2c00 ., CMP r4,#0 - 0x000027d4: d101 .. BNE 0x27da ; USART_ReceiveData + 36 - 0x000027d6: 4db0 .M LDR r5,[pc,#704] ; [0x2a98] = 0x10008052 - 0x000027d8: e001 .. B 0x27de ; USART_ReceiveData + 40 - 0x000027da: 4daf .M LDR r5,[pc,#700] ; [0x2a98] = 0x10008052 - 0x000027dc: 3520 5 ADDS r5,r5,#0x20 - 0x000027de: 1da8 .. ADDS r0,r5,#6 - 0x000027e0: f000f996 .... BL HR_REG_16BIT ; 0x2b10 - 0x000027e4: 4606 .F MOV r6,r0 - 0x000027e6: 48af .H LDR r0,[pc,#700] ; [0x2aa4] = 0x10010000 - 0x000027e8: 1830 0. ADDS r0,r6,r0 - 0x000027ea: f000f991 .... BL HR_REG_16BIT ; 0x2b10 - 0x000027ee: b2c7 .. UXTB r7,r0 - 0x000027f0: 1d28 (. ADDS r0,r5,#4 - 0x000027f2: f000f98d .... BL HR_REG_16BIT ; 0x2b10 - 0x000027f6: 42b0 .B CMP r0,r6 - 0x000027f8: d104 .. BNE 0x2804 ; USART_ReceiveData + 78 - 0x000027fa: 1ca8 .. ADDS r0,r5,#2 - 0x000027fc: f000f988 .... BL HR_REG_16BIT ; 0x2b10 - 0x00002800: 4606 .F MOV r6,r0 - 0x00002802: e001 .. B 0x2808 ; USART_ReceiveData + 82 - 0x00002804: 1c70 p. ADDS r0,r6,#1 - 0x00002806: b286 .. UXTH r6,r0 - 0x00002808: 4631 1F MOV r1,r6 - 0x0000280a: 1da8 .. ADDS r0,r5,#6 - 0x0000280c: f000f977 ..w. BL HW_REG_16BIT ; 0x2afe - 0x00002810: 4638 8F MOV r0,r7 - 0x00002812: bdf8 .. POP {r3-r7,pc} - USART_GetRxCount - 0x00002814: b510 .. PUSH {r4,lr} - 0x00002816: 4604 .F MOV r4,r0 - 0x00002818: 2c00 ., CMP r4,#0 - 0x0000281a: d006 .. BEQ 0x282a ; USART_GetRxCount + 22 - 0x0000281c: 2c01 ., CMP r4,#1 - 0x0000281e: d004 .. BEQ 0x282a ; USART_GetRxCount + 22 - 0x00002820: 4aa2 .J LDR r2,[pc,#648] ; [0x2aac] = 0x77e3 - 0x00002822: 21fd .! MOVS r1,#0xfd - 0x00002824: 489b .H LDR r0,[pc,#620] ; [0x2a94] = 0x2640 - 0x00002826: f7fefcf2 .... BL _assert_handler ; 0x120e - 0x0000282a: 2c00 ., CMP r4,#0 - 0x0000282c: d104 .. BNE 0x2838 ; USART_GetRxCount + 36 - 0x0000282e: 489c .H LDR r0,[pc,#624] ; [0x2aa0] = 0x10008300 - 0x00002830: 3012 .0 ADDS r0,r0,#0x12 - 0x00002832: f000f96d ..m. BL HR_REG_16BIT ; 0x2b10 - 0x00002836: bd10 .. POP {r4,pc} - 0x00002838: 4899 .H LDR r0,[pc,#612] ; [0x2aa0] = 0x10008300 - 0x0000283a: 305a Z0 ADDS r0,r0,#0x5a - 0x0000283c: f000f968 ..h. BL HR_REG_16BIT ; 0x2b10 - 0x00002840: e7f9 .. B 0x2836 ; USART_GetRxCount + 34 - USART_ReadDatatoBuff - 0x00002842: b5f7 .. PUSH {r0-r2,r4-r7,lr} - 0x00002844: b084 .. SUB sp,sp,#0x10 - 0x00002846: 4604 .F MOV r4,r0 - 0x00002848: 4615 .F MOV r5,r2 - 0x0000284a: 2000 . MOVS r0,#0 - 0x0000284c: 9003 .. STR r0,[sp,#0xc] - 0x0000284e: 2600 .& MOVS r6,#0 - 0x00002850: 2700 .' MOVS r7,#0 - 0x00002852: 9002 .. STR r0,[sp,#8] - 0x00002854: 9001 .. STR r0,[sp,#4] - 0x00002856: 2c00 ., CMP r4,#0 - 0x00002858: d007 .. BEQ 0x286a ; USART_ReadDatatoBuff + 40 - 0x0000285a: 2c01 ., CMP r4,#1 - 0x0000285c: d005 .. BEQ 0x286a ; USART_ReadDatatoBuff + 40 - 0x0000285e: 4a94 .J LDR r2,[pc,#592] ; [0x2ab0] = 0x77f4 - 0x00002860: 21ff .! MOVS r1,#0xff - 0x00002862: 3114 .1 ADDS r1,r1,#0x14 - 0x00002864: 488b .H LDR r0,[pc,#556] ; [0x2a94] = 0x2640 - 0x00002866: f7fefcd2 .... BL _assert_handler ; 0x120e - 0x0000286a: 9805 .. LDR r0,[sp,#0x14] - 0x0000286c: 2800 .( CMP r0,#0 - 0x0000286e: d105 .. BNE 0x287c ; USART_ReadDatatoBuff + 58 - 0x00002870: 4a8f .J LDR r2,[pc,#572] ; [0x2ab0] = 0x77f4 - 0x00002872: 21ff .! MOVS r1,#0xff - 0x00002874: 3115 .1 ADDS r1,r1,#0x15 - 0x00002876: 4887 .H LDR r0,[pc,#540] ; [0x2a94] = 0x2640 - 0x00002878: f7fefcc9 .... BL _assert_handler ; 0x120e - 0x0000287c: 2c00 ., CMP r4,#0 - 0x0000287e: d105 .. BNE 0x288c ; USART_ReadDatatoBuff + 74 - 0x00002880: 4885 .H LDR r0,[pc,#532] ; [0x2a98] = 0x10008052 - 0x00002882: 9001 .. STR r0,[sp,#4] - 0x00002884: 4886 .H LDR r0,[pc,#536] ; [0x2aa0] = 0x10008300 - 0x00002886: 3012 .0 ADDS r0,r0,#0x12 - 0x00002888: 9002 .. STR r0,[sp,#8] - 0x0000288a: e005 .. B 0x2898 ; USART_ReadDatatoBuff + 86 - 0x0000288c: 4882 .H LDR r0,[pc,#520] ; [0x2a98] = 0x10008052 - 0x0000288e: 3020 0 ADDS r0,r0,#0x20 - 0x00002890: 9001 .. STR r0,[sp,#4] - 0x00002892: 4883 .H LDR r0,[pc,#524] ; [0x2aa0] = 0x10008300 - 0x00002894: 305a Z0 ADDS r0,r0,#0x5a - 0x00002896: 9002 .. STR r0,[sp,#8] - 0x00002898: 2201 ." MOVS r2,#1 - 0x0000289a: 0712 .. LSLS r2,r2,#28 - 0x0000289c: 9902 .. LDR r1,[sp,#8] - 0x0000289e: 4311 .C ORRS r1,r1,r2 - 0x000028a0: 4608 .F MOV r0,r1 - 0x000028a2: f000f935 ..5. BL HR_REG_16BIT ; 0x2b10 - 0x000028a6: 9003 .. STR r0,[sp,#0xc] - 0x000028a8: 2d00 .- CMP r5,#0 - 0x000028aa: d006 .. BEQ 0x28ba ; USART_ReadDatatoBuff + 120 - 0x000028ac: 9803 .. LDR r0,[sp,#0xc] - 0x000028ae: 42a8 .B CMP r0,r5 - 0x000028b0: da02 .. BGE 0x28b8 ; USART_ReadDatatoBuff + 118 - 0x000028b2: 2000 . MOVS r0,#0 - 0x000028b4: b007 .. ADD sp,sp,#0x1c - 0x000028b6: bdf0 .. POP {r4-r7,pc} - 0x000028b8: 9503 .. STR r5,[sp,#0xc] - 0x000028ba: 9803 .. LDR r0,[sp,#0xc] - 0x000028bc: 2800 .( CMP r0,#0 - 0x000028be: d100 .. BNE 0x28c2 ; USART_ReadDatatoBuff + 128 - 0x000028c0: e7f8 .. B 0x28b4 ; USART_ReadDatatoBuff + 114 - 0x000028c2: 9801 .. LDR r0,[sp,#4] - 0x000028c4: 1d80 .. ADDS r0,r0,#6 - 0x000028c6: f000f923 ..#. BL HR_REG_16BIT ; 0x2b10 - 0x000028ca: 4606 .F MOV r6,r0 - 0x000028cc: 2700 .' MOVS r7,#0 - 0x000028ce: e014 .. B 0x28fa ; USART_ReadDatatoBuff + 184 - 0x000028d0: 4874 tH LDR r0,[pc,#464] ; [0x2aa4] = 0x10010000 - 0x000028d2: 1830 0. ADDS r0,r6,r0 - 0x000028d4: 7801 .x LDRB r1,[r0,#0] - 0x000028d6: 9805 .. LDR r0,[sp,#0x14] - 0x000028d8: 55c1 .U STRB r1,[r0,r7] - 0x000028da: 9801 .. LDR r0,[sp,#4] - 0x000028dc: 1d00 .. ADDS r0,r0,#4 - 0x000028de: f000f917 .... BL HR_REG_16BIT ; 0x2b10 - 0x000028e2: 42b0 .B CMP r0,r6 - 0x000028e4: d105 .. BNE 0x28f2 ; USART_ReadDatatoBuff + 176 - 0x000028e6: 9801 .. LDR r0,[sp,#4] - 0x000028e8: 1c80 .. ADDS r0,r0,#2 - 0x000028ea: f000f911 .... BL HR_REG_16BIT ; 0x2b10 - 0x000028ee: 4606 .F MOV r6,r0 - 0x000028f0: e001 .. B 0x28f6 ; USART_ReadDatatoBuff + 180 - 0x000028f2: 1c70 p. ADDS r0,r6,#1 - 0x000028f4: b286 .. UXTH r6,r0 - 0x000028f6: 1c78 x. ADDS r0,r7,#1 - 0x000028f8: b287 .. UXTH r7,r0 - 0x000028fa: 9803 .. LDR r0,[sp,#0xc] - 0x000028fc: 4287 .B CMP r7,r0 - 0x000028fe: dbe7 .. BLT 0x28d0 ; USART_ReadDatatoBuff + 142 - 0x00002900: 4631 1F MOV r1,r6 - 0x00002902: 9801 .. LDR r0,[sp,#4] - 0x00002904: 1d80 .. ADDS r0,r0,#6 - 0x00002906: f000f8fa .... BL HW_REG_16BIT ; 0x2afe - 0x0000290a: 4638 8F MOV r0,r7 - 0x0000290c: e7d2 .. B 0x28b4 ; USART_ReadDatatoBuff + 114 - USART_SendDataFromBuff - 0x0000290e: b5f7 .. PUSH {r0-r2,r4-r7,lr} - 0x00002910: b082 .. SUB sp,sp,#8 - 0x00002912: 4604 .F MOV r4,r0 - 0x00002914: 2500 .% MOVS r5,#0 - 0x00002916: 2000 . MOVS r0,#0 - 0x00002918: 9001 .. STR r0,[sp,#4] - 0x0000291a: 2700 .' MOVS r7,#0 - 0x0000291c: 2c00 ., CMP r4,#0 - 0x0000291e: d007 .. BEQ 0x2930 ; USART_SendDataFromBuff + 34 - 0x00002920: 2c01 ., CMP r4,#1 - 0x00002922: d005 .. BEQ 0x2930 ; USART_SendDataFromBuff + 34 - 0x00002924: 4a63 cJ LDR r2,[pc,#396] ; [0x2ab4] = 0x7809 - 0x00002926: 21ff .! MOVS r1,#0xff - 0x00002928: 313e >1 ADDS r1,r1,#0x3e - 0x0000292a: 485a ZH LDR r0,[pc,#360] ; [0x2a94] = 0x2640 - 0x0000292c: f7fefc6f ..o. BL _assert_handler ; 0x120e - 0x00002930: 9803 .. LDR r0,[sp,#0xc] - 0x00002932: 2800 .( CMP r0,#0 - 0x00002934: d105 .. BNE 0x2942 ; USART_SendDataFromBuff + 52 - 0x00002936: 4a5f _J LDR r2,[pc,#380] ; [0x2ab4] = 0x7809 - 0x00002938: 21ff .! MOVS r1,#0xff - 0x0000293a: 313f ?1 ADDS r1,r1,#0x3f - 0x0000293c: 4855 UH LDR r0,[pc,#340] ; [0x2a94] = 0x2640 - 0x0000293e: f7fefc66 ..f. BL _assert_handler ; 0x120e - 0x00002942: 9804 .. LDR r0,[sp,#0x10] - 0x00002944: 2800 .( CMP r0,#0 - 0x00002946: dc05 .. BGT 0x2954 ; USART_SendDataFromBuff + 70 - 0x00002948: 4a5a ZJ LDR r2,[pc,#360] ; [0x2ab4] = 0x7809 - 0x0000294a: 21ff .! MOVS r1,#0xff - 0x0000294c: 3140 @1 ADDS r1,r1,#0x40 - 0x0000294e: 4851 QH LDR r0,[pc,#324] ; [0x2a94] = 0x2640 - 0x00002950: f7fefc5d ..]. BL _assert_handler ; 0x120e - 0x00002954: 2c00 ., CMP r4,#0 - 0x00002956: d101 .. BNE 0x295c ; USART_SendDataFromBuff + 78 - 0x00002958: 4f4f OO LDR r7,[pc,#316] ; [0x2a98] = 0x10008052 - 0x0000295a: e001 .. B 0x2960 ; USART_SendDataFromBuff + 82 - 0x0000295c: 4f4e NO LDR r7,[pc,#312] ; [0x2a98] = 0x10008052 - 0x0000295e: 3720 7 ADDS r7,r7,#0x20 - 0x00002960: 4638 8F MOV r0,r7 - 0x00002962: 300c .0 ADDS r0,r0,#0xc - 0x00002964: f000f8d4 .... BL HR_REG_16BIT ; 0x2b10 - 0x00002968: 4605 .F MOV r5,r0 - 0x0000296a: 2600 .& MOVS r6,#0 - 0x0000296c: e018 .. B 0x29a0 ; USART_SendDataFromBuff + 146 - 0x0000296e: 9803 .. LDR r0,[sp,#0xc] - 0x00002970: 5d80 .] LDRB r0,[r0,r6] - 0x00002972: 494c LI LDR r1,[pc,#304] ; [0x2aa4] = 0x10010000 - 0x00002974: 1869 i. ADDS r1,r5,r1 - 0x00002976: 7008 .p STRB r0,[r1,#0] - 0x00002978: 4638 8F MOV r0,r7 - 0x0000297a: 300a .0 ADDS r0,r0,#0xa - 0x0000297c: f000f8c8 .... BL HR_REG_16BIT ; 0x2b10 - 0x00002980: 42a8 .B CMP r0,r5 - 0x00002982: d105 .. BNE 0x2990 ; USART_SendDataFromBuff + 130 - 0x00002984: 4638 8F MOV r0,r7 - 0x00002986: 3008 .0 ADDS r0,r0,#8 - 0x00002988: f000f8c2 .... BL HR_REG_16BIT ; 0x2b10 - 0x0000298c: 4605 .F MOV r5,r0 - 0x0000298e: e001 .. B 0x2994 ; USART_SendDataFromBuff + 134 - 0x00002990: 1c68 h. ADDS r0,r5,#1 - 0x00002992: b285 .. UXTH r5,r0 - 0x00002994: 9801 .. LDR r0,[sp,#4] - 0x00002996: 1c40 @. ADDS r0,r0,#1 - 0x00002998: b280 .. UXTH r0,r0 - 0x0000299a: 9001 .. STR r0,[sp,#4] - 0x0000299c: 1c70 p. ADDS r0,r6,#1 - 0x0000299e: b286 .. UXTH r6,r0 - 0x000029a0: 9804 .. LDR r0,[sp,#0x10] - 0x000029a2: 4286 .B CMP r6,r0 - 0x000029a4: dbe3 .. BLT 0x296e ; USART_SendDataFromBuff + 96 - 0x000029a6: 4629 )F MOV r1,r5 - 0x000029a8: 4638 8F MOV r0,r7 - 0x000029aa: 300c .0 ADDS r0,r0,#0xc - 0x000029ac: f000f8a7 .... BL HW_REG_16BIT ; 0x2afe - 0x000029b0: 2c00 ., CMP r4,#0 - 0x000029b2: d117 .. BNE 0x29e4 ; USART_SendDataFromBuff + 214 - 0x000029b4: bf00 .. NOP - 0x000029b6: 4839 9H LDR r0,[pc,#228] ; [0x2a9c] = 0x10004fe0 - 0x000029b8: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x000029ba: 2000 . MOVS r0,#0 - 0x000029bc: 4938 8I LDR r1,[pc,#224] ; [0x2aa0] = 0x10008300 - 0x000029be: 7b89 .{ LDRB r1,[r1,#0xe] - 0x000029c0: 4300 .C ORRS r0,r0,r0 - 0x000029c2: 4937 7I LDR r1,[pc,#220] ; [0x2aa0] = 0x10008300 - 0x000029c4: 7b89 .{ LDRB r1,[r1,#0xe] - 0x000029c6: 4308 .C ORRS r0,r0,r1 - 0x000029c8: 4934 4I LDR r1,[pc,#208] ; [0x2a9c] = 0x10004fe0 - 0x000029ca: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x000029cc: 2100 .! MOVS r1,#0 - 0x000029ce: 4a34 4J LDR r2,[pc,#208] ; [0x2aa0] = 0x10008300 - 0x000029d0: 7bd2 .{ LDRB r2,[r2,#0xf] - 0x000029d2: 4309 .C ORRS r1,r1,r1 - 0x000029d4: 4a32 2J LDR r2,[pc,#200] ; [0x2aa0] = 0x10008300 - 0x000029d6: 7bd2 .{ LDRB r2,[r2,#0xf] - 0x000029d8: 4311 .C ORRS r1,r1,r2 - 0x000029da: 0209 .. LSLS r1,r1,#8 - 0x000029dc: 4308 .C ORRS r0,r0,r1 - 0x000029de: 2800 .( CMP r0,#0 - 0x000029e0: d1e9 .. BNE 0x29b6 ; USART_SendDataFromBuff + 168 - 0x000029e2: e01a .. B 0x2a1a ; USART_SendDataFromBuff + 268 - 0x000029e4: bf00 .. NOP - 0x000029e6: 482d -H LDR r0,[pc,#180] ; [0x2a9c] = 0x10004fe0 - 0x000029e8: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x000029ea: 2000 . MOVS r0,#0 - 0x000029ec: 492c ,I LDR r1,[pc,#176] ; [0x2aa0] = 0x10008300 - 0x000029ee: 3140 @1 ADDS r1,r1,#0x40 - 0x000029f0: 7d89 .} LDRB r1,[r1,#0x16] - 0x000029f2: 4300 .C ORRS r0,r0,r0 - 0x000029f4: 492a *I LDR r1,[pc,#168] ; [0x2aa0] = 0x10008300 - 0x000029f6: 3140 @1 ADDS r1,r1,#0x40 - 0x000029f8: 7d89 .} LDRB r1,[r1,#0x16] - 0x000029fa: 4308 .C ORRS r0,r0,r1 - 0x000029fc: 4927 'I LDR r1,[pc,#156] ; [0x2a9c] = 0x10004fe0 - 0x000029fe: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00002a00: 2100 .! MOVS r1,#0 - 0x00002a02: 4a27 'J LDR r2,[pc,#156] ; [0x2aa0] = 0x10008300 - 0x00002a04: 3240 @2 ADDS r2,r2,#0x40 - 0x00002a06: 7dd2 .} LDRB r2,[r2,#0x17] - 0x00002a08: 4309 .C ORRS r1,r1,r1 - 0x00002a0a: 4a25 %J LDR r2,[pc,#148] ; [0x2aa0] = 0x10008300 - 0x00002a0c: 3240 @2 ADDS r2,r2,#0x40 - 0x00002a0e: 7dd2 .} LDRB r2,[r2,#0x17] - 0x00002a10: 4311 .C ORRS r1,r1,r2 - 0x00002a12: 0209 .. LSLS r1,r1,#8 - 0x00002a14: 4308 .C ORRS r0,r0,r1 - 0x00002a16: 2800 .( CMP r0,#0 - 0x00002a18: d1e5 .. BNE 0x29e6 ; USART_SendDataFromBuff + 216 - 0x00002a1a: b005 .. ADD sp,sp,#0x14 - 0x00002a1c: bdf0 .. POP {r4-r7,pc} - USART_SetRxITNum - 0x00002a1e: b570 p. PUSH {r4-r6,lr} - 0x00002a20: 4605 .F MOV r5,r0 - 0x00002a22: 460c .F MOV r4,r1 - 0x00002a24: 2d00 .- CMP r5,#0 - 0x00002a26: d007 .. BEQ 0x2a38 ; USART_SetRxITNum + 26 - 0x00002a28: 2d01 .- CMP r5,#1 - 0x00002a2a: d005 .. BEQ 0x2a38 ; USART_SetRxITNum + 26 - 0x00002a2c: 4a22 "J LDR r2,[pc,#136] ; [0x2ab8] = 0x7820 - 0x00002a2e: 21ff .! MOVS r1,#0xff - 0x00002a30: 3161 a1 ADDS r1,r1,#0x61 - 0x00002a32: 4818 .H LDR r0,[pc,#96] ; [0x2a94] = 0x2640 - 0x00002a34: f7fefbeb .... BL _assert_handler ; 0x120e - 0x00002a38: 2d00 .- CMP r5,#0 - 0x00002a3a: d105 .. BNE 0x2a48 ; USART_SetRxITNum + 42 - 0x00002a3c: bf00 .. NOP - 0x00002a3e: 4816 .H LDR r0,[pc,#88] ; [0x2a98] = 0x10008052 - 0x00002a40: 30ce .0 ADDS r0,r0,#0xce - 0x00002a42: 7484 .t STRB r4,[r0,#0x12] - 0x00002a44: 7484 .t STRB r4,[r0,#0x12] - 0x00002a46: e005 .. B 0x2a54 ; USART_SetRxITNum + 54 - 0x00002a48: bf00 .. NOP - 0x00002a4a: 4813 .H LDR r0,[pc,#76] ; [0x2a98] = 0x10008052 - 0x00002a4c: 30ce .0 ADDS r0,r0,#0xce - 0x00002a4e: 7544 Du STRB r4,[r0,#0x15] - 0x00002a50: 7544 Du STRB r4,[r0,#0x15] - 0x00002a52: bf00 .. NOP - 0x00002a54: bd70 p. POP {r4-r6,pc} - USART_SetRxTimeout - 0x00002a56: b570 p. PUSH {r4-r6,lr} - 0x00002a58: 4605 .F MOV r5,r0 - 0x00002a5a: 460c .F MOV r4,r1 - 0x00002a5c: 2d00 .- CMP r5,#0 - 0x00002a5e: d007 .. BEQ 0x2a70 ; USART_SetRxTimeout + 26 - 0x00002a60: 2d01 .- CMP r5,#1 - 0x00002a62: d005 .. BEQ 0x2a70 ; USART_SetRxTimeout + 26 - 0x00002a64: 4a15 .J LDR r2,[pc,#84] ; [0x2abc] = 0x7831 - 0x00002a66: 21ff .! MOVS r1,#0xff - 0x00002a68: 3173 s1 ADDS r1,r1,#0x73 - 0x00002a6a: 480a .H LDR r0,[pc,#40] ; [0x2a94] = 0x2640 - 0x00002a6c: f7fefbcf .... BL _assert_handler ; 0x120e - 0x00002a70: 2d00 .- CMP r5,#0 - 0x00002a72: d125 %. BNE 0x2ac0 ; USART_SetRxTimeout + 106 - 0x00002a74: bf00 .. NOP - 0x00002a76: bf00 .. NOP - 0x00002a78: 4907 .I LDR r1,[pc,#28] ; [0x2a98] = 0x10008052 - 0x00002a7a: 31ce .1 ADDS r1,r1,#0xce - 0x00002a7c: 74cc .t STRB r4,[r1,#0x13] - 0x00002a7e: 74cc .t STRB r4,[r1,#0x13] - 0x00002a80: bf00 .. NOP - 0x00002a82: bf00 .. NOP - 0x00002a84: 1220 . ASRS r0,r4,#8 - 0x00002a86: 7508 .u STRB r0,[r1,#0x14] - 0x00002a88: 1220 . ASRS r0,r4,#8 - 0x00002a8a: 7508 .u STRB r0,[r1,#0x14] - 0x00002a8c: bf00 .. NOP - 0x00002a8e: e024 $. B 0x2ada ; USART_SetRxTimeout + 132 + 0x00002768: 4b78 xK LDR r3,[pc,#480] ; [0x294c] = 0x10004400 + 0x0000276a: 3b20 ; SUBS r3,r3,#0x20 + 0x0000276c: 7f1b .. LDRB r3,[r3,#0x1c] + 0x0000276e: 4309 .C ORRS r1,r1,r1 + 0x00002770: 4b76 vK LDR r3,[pc,#472] ; [0x294c] = 0x10004400 + 0x00002772: 3b20 ; SUBS r3,r3,#0x20 + 0x00002774: 7f1b .. LDRB r3,[r3,#0x1c] + 0x00002776: 4319 .C ORRS r1,r1,r3 + 0x00002778: 0409 .. LSLS r1,r1,#16 + 0x0000277a: 4308 .C ORRS r0,r0,r1 + 0x0000277c: 1c80 .. ADDS r0,r0,#2 + 0x0000277e: 2101 .! MOVS r1,#1 + 0x00002780: 0709 .. LSLS r1,r1,#28 + 0x00002782: 1840 @. ADDS r0,r0,r1 + 0x00002784: 7002 .p STRB r2,[r0,#0] + 0x00002786: bf00 .. NOP + 0x00002788: bf00 .. NOP + 0x0000278a: bdf8 .. POP {r3-r7,pc} + IPC_TxBufferIsEnough + 0x0000278c: b570 p. PUSH {r4-r6,lr} + 0x0000278e: 4604 .F MOV r4,r0 + 0x00002790: 496f oI LDR r1,[pc,#444] ; [0x2950] = 0x10004fe0 + 0x00002792: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x00002794: 2100 .! MOVS r1,#0 + 0x00002796: 4a6d mJ LDR r2,[pc,#436] ; [0x294c] = 0x10004400 + 0x00002798: 3a20 : SUBS r2,r2,#0x20 + 0x0000279a: 7e92 .~ LDRB r2,[r2,#0x1a] + 0x0000279c: 4309 .C ORRS r1,r1,r1 + 0x0000279e: 4a6b kJ LDR r2,[pc,#428] ; [0x294c] = 0x10004400 + 0x000027a0: 3a20 : SUBS r2,r2,#0x20 + 0x000027a2: 7e92 .~ LDRB r2,[r2,#0x1a] + 0x000027a4: 4311 .C ORRS r1,r1,r2 + 0x000027a6: 4a6a jJ LDR r2,[pc,#424] ; [0x2950] = 0x10004fe0 + 0x000027a8: 7fd2 .. LDRB r2,[r2,#0x1f] + 0x000027aa: 2200 ." MOVS r2,#0 + 0x000027ac: 4b67 gK LDR r3,[pc,#412] ; [0x294c] = 0x10004400 + 0x000027ae: 3b20 ; SUBS r3,r3,#0x20 + 0x000027b0: 7edb .~ LDRB r3,[r3,#0x1b] + 0x000027b2: 4312 .C ORRS r2,r2,r2 + 0x000027b4: 4b65 eK LDR r3,[pc,#404] ; [0x294c] = 0x10004400 + 0x000027b6: 3b20 ; SUBS r3,r3,#0x20 + 0x000027b8: 7edb .~ LDRB r3,[r3,#0x1b] + 0x000027ba: 431a .C ORRS r2,r2,r3 + 0x000027bc: 0212 .. LSLS r2,r2,#8 + 0x000027be: 4311 .C ORRS r1,r1,r2 + 0x000027c0: 4a63 cJ LDR r2,[pc,#396] ; [0x2950] = 0x10004fe0 + 0x000027c2: 7fd2 .. LDRB r2,[r2,#0x1f] + 0x000027c4: 2200 ." MOVS r2,#0 + 0x000027c6: 4b61 aK LDR r3,[pc,#388] ; [0x294c] = 0x10004400 + 0x000027c8: 3b20 ; SUBS r3,r3,#0x20 + 0x000027ca: 7f1b .. LDRB r3,[r3,#0x1c] + 0x000027cc: 4312 .C ORRS r2,r2,r2 + 0x000027ce: 4b5f _K LDR r3,[pc,#380] ; [0x294c] = 0x10004400 + 0x000027d0: 3b20 ; SUBS r3,r3,#0x20 + 0x000027d2: 7f1b .. LDRB r3,[r3,#0x1c] + 0x000027d4: 431a .C ORRS r2,r2,r3 + 0x000027d6: 0412 .. LSLS r2,r2,#16 + 0x000027d8: 4311 .C ORRS r1,r1,r2 + 0x000027da: 2201 ." MOVS r2,#1 + 0x000027dc: 0712 .. LSLS r2,r2,#28 + 0x000027de: 1888 .. ADDS r0,r1,r2 + 0x000027e0: f000fa3d ..=. BL HR_REG_24BIT ; 0x2c5e + 0x000027e4: 4605 .F MOV r5,r0 + 0x000027e6: 495a ZI LDR r1,[pc,#360] ; [0x2950] = 0x10004fe0 + 0x000027e8: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x000027ea: 2100 .! MOVS r1,#0 + 0x000027ec: 4a57 WJ LDR r2,[pc,#348] ; [0x294c] = 0x10004400 + 0x000027ee: 3a20 : SUBS r2,r2,#0x20 + 0x000027f0: 7f52 R. LDRB r2,[r2,#0x1d] + 0x000027f2: 4309 .C ORRS r1,r1,r1 + 0x000027f4: 4a55 UJ LDR r2,[pc,#340] ; [0x294c] = 0x10004400 + 0x000027f6: 3a20 : SUBS r2,r2,#0x20 + 0x000027f8: 7f52 R. LDRB r2,[r2,#0x1d] + 0x000027fa: 4311 .C ORRS r1,r1,r2 + 0x000027fc: 4a54 TJ LDR r2,[pc,#336] ; [0x2950] = 0x10004fe0 + 0x000027fe: 7fd2 .. LDRB r2,[r2,#0x1f] + 0x00002800: 2200 ." MOVS r2,#0 + 0x00002802: 4b52 RK LDR r3,[pc,#328] ; [0x294c] = 0x10004400 + 0x00002804: 3b20 ; SUBS r3,r3,#0x20 + 0x00002806: 7f9b .. LDRB r3,[r3,#0x1e] + 0x00002808: 4312 .C ORRS r2,r2,r2 + 0x0000280a: 4b50 PK LDR r3,[pc,#320] ; [0x294c] = 0x10004400 + 0x0000280c: 3b20 ; SUBS r3,r3,#0x20 + 0x0000280e: 7f9b .. LDRB r3,[r3,#0x1e] + 0x00002810: 431a .C ORRS r2,r2,r3 + 0x00002812: 0212 .. LSLS r2,r2,#8 + 0x00002814: 4311 .C ORRS r1,r1,r2 + 0x00002816: 4a4e NJ LDR r2,[pc,#312] ; [0x2950] = 0x10004fe0 + 0x00002818: 7fd2 .. LDRB r2,[r2,#0x1f] + 0x0000281a: 2200 ." MOVS r2,#0 + 0x0000281c: 4b4b KK LDR r3,[pc,#300] ; [0x294c] = 0x10004400 + 0x0000281e: 3b20 ; SUBS r3,r3,#0x20 + 0x00002820: 7fdb .. LDRB r3,[r3,#0x1f] + 0x00002822: 4312 .C ORRS r2,r2,r2 + 0x00002824: 4b49 IK LDR r3,[pc,#292] ; [0x294c] = 0x10004400 + 0x00002826: 3b20 ; SUBS r3,r3,#0x20 + 0x00002828: 7fdb .. LDRB r3,[r3,#0x1f] + 0x0000282a: 431a .C ORRS r2,r2,r3 + 0x0000282c: 0412 .. LSLS r2,r2,#16 + 0x0000282e: 4311 .C ORRS r1,r1,r2 + 0x00002830: 2201 ." MOVS r2,#1 + 0x00002832: 0712 .. LSLS r2,r2,#28 + 0x00002834: 1888 .. ADDS r0,r1,r2 + 0x00002836: f000fa12 .... BL HR_REG_24BIT ; 0x2c5e + 0x0000283a: 4606 .F MOV r6,r0 + 0x0000283c: 2100 .! MOVS r1,#0 + 0x0000283e: e054 T. B 0x28ea ; IPC_TxBufferIsEnough + 350 + 0x00002840: 4843 CH LDR r0,[pc,#268] ; [0x2950] = 0x10004fe0 + 0x00002842: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x00002844: 2000 . MOVS r0,#0 + 0x00002846: 4a41 AJ LDR r2,[pc,#260] ; [0x294c] = 0x10004400 + 0x00002848: 3a20 : SUBS r2,r2,#0x20 + 0x0000284a: 7dd2 .} LDRB r2,[r2,#0x17] + 0x0000284c: 4300 .C ORRS r0,r0,r0 + 0x0000284e: 4a3f ?J LDR r2,[pc,#252] ; [0x294c] = 0x10004400 + 0x00002850: 3a20 : SUBS r2,r2,#0x20 + 0x00002852: 7dd2 .} LDRB r2,[r2,#0x17] + 0x00002854: 4310 .C ORRS r0,r0,r2 + 0x00002856: 4a3e >J LDR r2,[pc,#248] ; [0x2950] = 0x10004fe0 + 0x00002858: 7fd2 .. LDRB r2,[r2,#0x1f] + 0x0000285a: 2200 ." MOVS r2,#0 + 0x0000285c: 4b3b ;K LDR r3,[pc,#236] ; [0x294c] = 0x10004400 + 0x0000285e: 3b20 ; SUBS r3,r3,#0x20 + 0x00002860: 7e1b .~ LDRB r3,[r3,#0x18] + 0x00002862: 4312 .C ORRS r2,r2,r2 + 0x00002864: 4b39 9K LDR r3,[pc,#228] ; [0x294c] = 0x10004400 + 0x00002866: 3b20 ; SUBS r3,r3,#0x20 + 0x00002868: 7e1b .~ LDRB r3,[r3,#0x18] + 0x0000286a: 431a .C ORRS r2,r2,r3 + 0x0000286c: 0212 .. LSLS r2,r2,#8 + 0x0000286e: 4310 .C ORRS r0,r0,r2 + 0x00002870: 4a37 7J LDR r2,[pc,#220] ; [0x2950] = 0x10004fe0 + 0x00002872: 7fd2 .. LDRB r2,[r2,#0x1f] + 0x00002874: 2200 ." MOVS r2,#0 + 0x00002876: 4b35 5K LDR r3,[pc,#212] ; [0x294c] = 0x10004400 + 0x00002878: 3b20 ; SUBS r3,r3,#0x20 + 0x0000287a: 7e5b [~ LDRB r3,[r3,#0x19] + 0x0000287c: 4312 .C ORRS r2,r2,r2 + 0x0000287e: 4b33 3K LDR r3,[pc,#204] ; [0x294c] = 0x10004400 + 0x00002880: 3b20 ; SUBS r3,r3,#0x20 + 0x00002882: 7e5b [~ LDRB r3,[r3,#0x19] + 0x00002884: 431a .C ORRS r2,r2,r3 + 0x00002886: 0412 .. LSLS r2,r2,#16 + 0x00002888: 4310 .C ORRS r0,r0,r2 + 0x0000288a: 1c6a j. ADDS r2,r5,#1 + 0x0000288c: 4615 .F MOV r5,r2 + 0x0000288e: 4290 .B CMP r0,r2 + 0x00002890: d825 %. BHI 0x28de ; IPC_TxBufferIsEnough + 338 + 0x00002892: 482f /H LDR r0,[pc,#188] ; [0x2950] = 0x10004fe0 + 0x00002894: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x00002896: 2000 . MOVS r0,#0 + 0x00002898: 4a2c ,J LDR r2,[pc,#176] ; [0x294c] = 0x10004400 + 0x0000289a: 3a20 : SUBS r2,r2,#0x20 + 0x0000289c: 7d12 .} LDRB r2,[r2,#0x14] + 0x0000289e: 4300 .C ORRS r0,r0,r0 + 0x000028a0: 4a2a *J LDR r2,[pc,#168] ; [0x294c] = 0x10004400 + 0x000028a2: 3a20 : SUBS r2,r2,#0x20 + 0x000028a4: 7d12 .} LDRB r2,[r2,#0x14] + 0x000028a6: 4310 .C ORRS r0,r0,r2 + 0x000028a8: 4a29 )J LDR r2,[pc,#164] ; [0x2950] = 0x10004fe0 + 0x000028aa: 7fd2 .. LDRB r2,[r2,#0x1f] + 0x000028ac: 2200 ." MOVS r2,#0 + 0x000028ae: 4b27 'K LDR r3,[pc,#156] ; [0x294c] = 0x10004400 + 0x000028b0: 3b20 ; SUBS r3,r3,#0x20 + 0x000028b2: 7d5b [} LDRB r3,[r3,#0x15] + 0x000028b4: 4312 .C ORRS r2,r2,r2 + 0x000028b6: 4b25 %K LDR r3,[pc,#148] ; [0x294c] = 0x10004400 + 0x000028b8: 3b20 ; SUBS r3,r3,#0x20 + 0x000028ba: 7d5b [} LDRB r3,[r3,#0x15] + 0x000028bc: 431a .C ORRS r2,r2,r3 + 0x000028be: 0212 .. LSLS r2,r2,#8 + 0x000028c0: 4310 .C ORRS r0,r0,r2 + 0x000028c2: 4a23 #J LDR r2,[pc,#140] ; [0x2950] = 0x10004fe0 + 0x000028c4: 7fd2 .. LDRB r2,[r2,#0x1f] + 0x000028c6: 2200 ." MOVS r2,#0 + 0x000028c8: 4b20 K LDR r3,[pc,#128] ; [0x294c] = 0x10004400 + 0x000028ca: 3b20 ; SUBS r3,r3,#0x20 + 0x000028cc: 7d9b .} LDRB r3,[r3,#0x16] + 0x000028ce: 4312 .C ORRS r2,r2,r2 + 0x000028d0: 4b1e .K LDR r3,[pc,#120] ; [0x294c] = 0x10004400 + 0x000028d2: 3b20 ; SUBS r3,r3,#0x20 + 0x000028d4: 7d9b .} LDRB r3,[r3,#0x16] + 0x000028d6: 431a .C ORRS r2,r2,r3 + 0x000028d8: 0412 .. LSLS r2,r2,#16 + 0x000028da: 4310 .C ORRS r0,r0,r2 + 0x000028dc: 4605 .F MOV r5,r0 + 0x000028de: 42b5 .B CMP r5,r6 + 0x000028e0: d101 .. BNE 0x28e6 ; IPC_TxBufferIsEnough + 346 + 0x000028e2: 2000 . MOVS r0,#0 + 0x000028e4: bd70 p. POP {r4-r6,pc} + 0x000028e6: 1c48 H. ADDS r0,r1,#1 + 0x000028e8: b281 .. UXTH r1,r0 + 0x000028ea: 42a1 .B CMP r1,r4 + 0x000028ec: dba8 .. BLT 0x2840 ; IPC_TxBufferIsEnough + 180 + 0x000028ee: 2001 . MOVS r0,#1 + 0x000028f0: e7f8 .. B 0x28e4 ; IPC_TxBufferIsEnough + 344 + IPC_WaitBufferEnough + 0x000028f2: b570 p. PUSH {r4-r6,lr} + 0x000028f4: 4604 .F MOV r4,r0 + 0x000028f6: e00d .. B 0x2914 ; IPC_WaitBufferEnough + 34 + 0x000028f8: 4620 F MOV r0,r4 + 0x000028fa: f7ffff47 ..G. BL IPC_TxBufferIsEnough ; 0x278c + 0x000028fe: 2800 .( CMP r0,#0 + 0x00002900: d001 .. BEQ 0x2906 ; IPC_WaitBufferEnough + 20 + 0x00002902: 2001 . MOVS r0,#1 + 0x00002904: bd70 p. POP {r4-r6,pc} + 0x00002906: 257d }% MOVS r5,#0x7d + 0x00002908: 00ed .. LSLS r5,r5,#3 + 0x0000290a: bf00 .. NOP + 0x0000290c: 4628 (F MOV r0,r5 + 0x0000290e: 1e6d m. SUBS r5,r5,#1 + 0x00002910: 2800 .( CMP r0,#0 + 0x00002912: d1fb .. BNE 0x290c ; IPC_WaitBufferEnough + 26 + 0x00002914: e7f0 .. B 0x28f8 ; IPC_WaitBufferEnough + 6 + IPC_TxCommon + 0x00002916: b570 p. PUSH {r4-r6,lr} + 0x00002918: 4605 .F MOV r5,r0 + 0x0000291a: 460e .F MOV r6,r1 + 0x0000291c: 4614 .F MOV r4,r2 + 0x0000291e: 480d .H LDR r0,[pc,#52] ; [0x2954] = 0x10011124 + 0x00002920: 7005 .p STRB r5,[r0,#0] + 0x00002922: 2c00 ., CMP r4,#0 + 0x00002924: d100 .. BNE 0x2928 ; IPC_TxCommon + 18 + 0x00002926: bd70 p. POP {r4-r6,pc} + 0x00002928: 4809 .H LDR r0,[pc,#36] ; [0x2950] = 0x10004fe0 + 0x0000292a: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x0000292c: 2000 . MOVS r0,#0 + 0x0000292e: 4907 .I LDR r1,[pc,#28] ; [0x294c] = 0x10004400 + 0x00002930: 3940 @9 SUBS r1,r1,#0x40 + 0x00002932: 7f49 I. LDRB r1,[r1,#0x1d] + 0x00002934: 4300 .C ORRS r0,r0,r0 + 0x00002936: 4905 .I LDR r1,[pc,#20] ; [0x294c] = 0x10004400 + 0x00002938: 3940 @9 SUBS r1,r1,#0x40 + 0x0000293a: 7f49 I. LDRB r1,[r1,#0x1d] + 0x0000293c: 4308 .C ORRS r0,r0,r1 + 0x0000293e: 2802 .( CMP r0,#2 + 0x00002940: d10d .. BNE 0x295e ; IPC_TxCommon + 72 + 0x00002942: bf00 .. NOP + 0x00002944: 2000 . MOVS r0,#0 + 0x00002946: 4901 .I LDR r1,[pc,#4] ; [0x294c] = 0x10004400 + 0x00002948: 3940 @9 SUBS r1,r1,#0x40 + 0x0000294a: e005 .. B 0x2958 ; IPC_TxCommon + 66 $d - 0x00002a90: 000077c2 .w.. DCD 30658 - 0x00002a94: 00002640 @&.. DCD 9792 - 0x00002a98: 10008052 R... DCD 268468306 - 0x00002a9c: 10004fe0 .O.. DCD 268455904 - 0x00002aa0: 10008300 .... DCD 268468992 - 0x00002aa4: 10010000 .... DCD 268500992 - 0x00002aa8: 000077d1 .w.. DCD 30673 - 0x00002aac: 000077e3 .w.. DCD 30691 - 0x00002ab0: 000077f4 .w.. DCD 30708 - 0x00002ab4: 00007809 .x.. DCD 30729 - 0x00002ab8: 00007820 x.. DCD 30752 - 0x00002abc: 00007831 1x.. DCD 30769 + 0x0000294c: 10004400 .D.. DCD 268452864 + 0x00002950: 10004fe0 .O.. DCD 268455904 + 0x00002954: 10011124 $... DCD 268505380 $t - 0x00002ac0: bf00 .. NOP - 0x00002ac2: bf00 .. NOP - 0x00002ac4: 4905 .I LDR r1,[pc,#20] ; [0x2adc] = 0x10008120 - 0x00002ac6: 758c .u STRB r4,[r1,#0x16] - 0x00002ac8: 758c .u STRB r4,[r1,#0x16] - 0x00002aca: bf00 .. NOP - 0x00002acc: bf00 .. NOP - 0x00002ace: 1220 . ASRS r0,r4,#8 - 0x00002ad0: 75c8 .u STRB r0,[r1,#0x17] - 0x00002ad2: 1220 . ASRS r0,r4,#8 - 0x00002ad4: 75c8 .u STRB r0,[r1,#0x17] - 0x00002ad6: bf00 .. NOP - 0x00002ad8: bf00 .. NOP - 0x00002ada: bd70 p. POP {r4-r6,pc} + 0x00002958: 7748 Hw STRB r0,[r1,#0x1d] + 0x0000295a: 7748 Hw STRB r0,[r1,#0x1d] + 0x0000295c: bf00 .. NOP + 0x0000295e: 48a4 .H LDR r0,[pc,#656] ; [0x2bf0] = 0x10011124 + 0x00002960: 7044 Dp STRB r4,[r0,#1] + 0x00002962: 4622 "F MOV r2,r4 + 0x00002964: 4631 1F MOV r1,r6 + 0x00002966: 1c80 .. ADDS r0,r0,#2 + 0x00002968: f000fa60 ..`. BL __aeabi_memcpy ; 0x2e2c + 0x0000296c: 1ca0 .. ADDS r0,r4,#2 + 0x0000296e: b2c1 .. UXTB r1,r0 + 0x00002970: 489f .H LDR r0,[pc,#636] ; [0x2bf0] = 0x10011124 + 0x00002972: f7fffd5e ..^. BL ipcTx ; 0x2432 + 0x00002976: bf00 .. NOP + 0x00002978: e7d5 .. B 0x2926 ; IPC_TxCommon + 16 + IPC_TxPacket + 0x0000297a: b510 .. PUSH {r4,lr} + 0x0000297c: 4604 .F MOV r4,r0 + 0x0000297e: 7860 `x LDRB r0,[r4,#1] + 0x00002980: 2800 .( CMP r0,#0 + 0x00002982: d100 .. BNE 0x2986 ; IPC_TxPacket + 12 + 0x00002984: bd10 .. POP {r4,pc} + 0x00002986: 489b .H LDR r0,[pc,#620] ; [0x2bf4] = 0x10004fe0 + 0x00002988: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x0000298a: 2000 . MOVS r0,#0 + 0x0000298c: 499a .I LDR r1,[pc,#616] ; [0x2bf8] = 0x100043c0 + 0x0000298e: 7f49 I. LDRB r1,[r1,#0x1d] + 0x00002990: 4300 .C ORRS r0,r0,r0 + 0x00002992: 4999 .I LDR r1,[pc,#612] ; [0x2bf8] = 0x100043c0 + 0x00002994: 7f49 I. LDRB r1,[r1,#0x1d] + 0x00002996: 4308 .C ORRS r0,r0,r1 + 0x00002998: 2802 .( CMP r0,#2 + 0x0000299a: d105 .. BNE 0x29a8 ; IPC_TxPacket + 46 + 0x0000299c: bf00 .. NOP + 0x0000299e: 2000 . MOVS r0,#0 + 0x000029a0: 4995 .I LDR r1,[pc,#596] ; [0x2bf8] = 0x100043c0 + 0x000029a2: 7748 Hw STRB r0,[r1,#0x1d] + 0x000029a4: 7748 Hw STRB r0,[r1,#0x1d] + 0x000029a6: bf00 .. NOP + 0x000029a8: 7860 `x LDRB r0,[r4,#1] + 0x000029aa: 1c80 .. ADDS r0,r0,#2 + 0x000029ac: b2c1 .. UXTB r1,r0 + 0x000029ae: 4620 F MOV r0,r4 + 0x000029b0: f7fffd3f ..?. BL ipcTx ; 0x2432 + 0x000029b4: bf00 .. NOP + 0x000029b6: e7e5 .. B 0x2984 ; IPC_TxPacket + 10 + IPC_TxControlCmd + 0x000029b8: b538 8. PUSH {r3-r5,lr} + 0x000029ba: 4604 .F MOV r4,r0 + 0x000029bc: 488f .H LDR r0,[pc,#572] ; [0x2bfc] = 0x2e94 + 0x000029be: 6800 .h LDR r0,[r0,#0] + 0x000029c0: 9000 .. STR r0,[sp,#0] + 0x000029c2: 488c .H LDR r0,[pc,#560] ; [0x2bf4] = 0x10004fe0 + 0x000029c4: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x000029c6: 2000 . MOVS r0,#0 + 0x000029c8: 498b .I LDR r1,[pc,#556] ; [0x2bf8] = 0x100043c0 + 0x000029ca: 7f49 I. LDRB r1,[r1,#0x1d] + 0x000029cc: 4300 .C ORRS r0,r0,r0 + 0x000029ce: 498a .I LDR r1,[pc,#552] ; [0x2bf8] = 0x100043c0 + 0x000029d0: 7f49 I. LDRB r1,[r1,#0x1d] + 0x000029d2: 4308 .C ORRS r0,r0,r1 + 0x000029d4: 2802 .( CMP r0,#2 + 0x000029d6: d105 .. BNE 0x29e4 ; IPC_TxControlCmd + 44 + 0x000029d8: bf00 .. NOP + 0x000029da: 2000 . MOVS r0,#0 + 0x000029dc: 4986 .I LDR r1,[pc,#536] ; [0x2bf8] = 0x100043c0 + 0x000029de: 7748 Hw STRB r0,[r1,#0x1d] + 0x000029e0: 7748 Hw STRB r0,[r1,#0x1d] + 0x000029e2: bf00 .. NOP + 0x000029e4: 4668 hF MOV r0,sp + 0x000029e6: 7084 .p STRB r4,[r0,#2] + 0x000029e8: 2103 .! MOVS r1,#3 + 0x000029ea: f7fffd22 ..". BL ipcTx ; 0x2432 + 0x000029ee: bd38 8. POP {r3-r5,pc} + IPC_GetBBDIsconnectReason + 0x000029f0: 2000 . MOVS r0,#0 + 0x000029f2: 4770 pG BX lr + IPC_CheckServerConenct + 0x000029f4: 2000 . MOVS r0,#0 + 0x000029f6: 4770 pG BX lr + IPC_CheckReconnect + 0x000029f8: 2000 . MOVS r0,#0 + 0x000029fa: 4770 pG BX lr + IPC_WaitLpm + 0x000029fc: b510 .. PUSH {r4,lr} + 0x000029fe: 4c80 .L LDR r4,[pc,#512] ; [0x2c00] = 0x2710 + 0x00002a00: e001 .. B 0x2a06 ; IPC_WaitLpm + 10 + 0x00002a02: f000f8ee .... BL hw_delay ; 0x2be2 + 0x00002a06: 4620 F MOV r0,r4 + 0x00002a08: 1e64 d. SUBS r4,r4,#1 + 0x00002a0a: 2800 .( CMP r0,#0 + 0x00002a0c: d1f9 .. BNE 0x2a02 ; IPC_WaitLpm + 6 + 0x00002a0e: bd10 .. POP {r4,pc} + IPC_AbandonLpm + 0x00002a10: b510 .. PUSH {r4,lr} + 0x00002a12: f000f8e6 .... BL hw_delay ; 0x2be2 + 0x00002a16: bd10 .. POP {r4,pc} + IPC_DisableLpm + 0x00002a18: b510 .. PUSH {r4,lr} + 0x00002a1a: f000f8e2 .... BL hw_delay ; 0x2be2 + 0x00002a1e: bd10 .. POP {r4,pc} + IPC_EnableLpm + 0x00002a20: b510 .. PUSH {r4,lr} + 0x00002a22: f000f8de .... BL hw_delay ; 0x2be2 + 0x00002a26: bd10 .. POP {r4,pc} + IPC_IsTxBuffEmpty + 0x00002a28: b570 p. PUSH {r4-r6,lr} + 0x00002a2a: 4972 rI LDR r1,[pc,#456] ; [0x2bf4] = 0x10004fe0 + 0x00002a2c: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x00002a2e: 2100 .! MOVS r1,#0 + 0x00002a30: 4a71 qJ LDR r2,[pc,#452] ; [0x2bf8] = 0x100043c0 + 0x00002a32: 3220 2 ADDS r2,r2,#0x20 + 0x00002a34: 7f52 R. LDRB r2,[r2,#0x1d] + 0x00002a36: 4309 .C ORRS r1,r1,r1 + 0x00002a38: 4a6f oJ LDR r2,[pc,#444] ; [0x2bf8] = 0x100043c0 + 0x00002a3a: 3220 2 ADDS r2,r2,#0x20 + 0x00002a3c: 7f52 R. LDRB r2,[r2,#0x1d] + 0x00002a3e: 4311 .C ORRS r1,r1,r2 + 0x00002a40: 4a6c lJ LDR r2,[pc,#432] ; [0x2bf4] = 0x10004fe0 + 0x00002a42: 7fd2 .. LDRB r2,[r2,#0x1f] + 0x00002a44: 2200 ." MOVS r2,#0 + 0x00002a46: 4b6c lK LDR r3,[pc,#432] ; [0x2bf8] = 0x100043c0 + 0x00002a48: 3320 3 ADDS r3,r3,#0x20 + 0x00002a4a: 7f9b .. LDRB r3,[r3,#0x1e] + 0x00002a4c: 4312 .C ORRS r2,r2,r2 + 0x00002a4e: 4b6a jK LDR r3,[pc,#424] ; [0x2bf8] = 0x100043c0 + 0x00002a50: 3320 3 ADDS r3,r3,#0x20 + 0x00002a52: 7f9b .. LDRB r3,[r3,#0x1e] + 0x00002a54: 431a .C ORRS r2,r2,r3 + 0x00002a56: 0212 .. LSLS r2,r2,#8 + 0x00002a58: 4311 .C ORRS r1,r1,r2 + 0x00002a5a: 4a66 fJ LDR r2,[pc,#408] ; [0x2bf4] = 0x10004fe0 + 0x00002a5c: 7fd2 .. LDRB r2,[r2,#0x1f] + 0x00002a5e: 2200 ." MOVS r2,#0 + 0x00002a60: 4b65 eK LDR r3,[pc,#404] ; [0x2bf8] = 0x100043c0 + 0x00002a62: 3320 3 ADDS r3,r3,#0x20 + 0x00002a64: 7fdb .. LDRB r3,[r3,#0x1f] + 0x00002a66: 4312 .C ORRS r2,r2,r2 + 0x00002a68: 4b63 cK LDR r3,[pc,#396] ; [0x2bf8] = 0x100043c0 + 0x00002a6a: 3320 3 ADDS r3,r3,#0x20 + 0x00002a6c: 7fdb .. LDRB r3,[r3,#0x1f] + 0x00002a6e: 431a .C ORRS r2,r2,r3 + 0x00002a70: 0412 .. LSLS r2,r2,#16 + 0x00002a72: 4311 .C ORRS r1,r1,r2 + 0x00002a74: 2201 ." MOVS r2,#1 + 0x00002a76: 0712 .. LSLS r2,r2,#28 + 0x00002a78: 1888 .. ADDS r0,r1,r2 + 0x00002a7a: f000f8f0 .... BL HR_REG_24BIT ; 0x2c5e + 0x00002a7e: 4604 .F MOV r4,r0 + 0x00002a80: 495c \I LDR r1,[pc,#368] ; [0x2bf4] = 0x10004fe0 + 0x00002a82: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x00002a84: 2100 .! MOVS r1,#0 + 0x00002a86: 4a5c \J LDR r2,[pc,#368] ; [0x2bf8] = 0x100043c0 + 0x00002a88: 3220 2 ADDS r2,r2,#0x20 + 0x00002a8a: 7e92 .~ LDRB r2,[r2,#0x1a] + 0x00002a8c: 4309 .C ORRS r1,r1,r1 + 0x00002a8e: 4a5a ZJ LDR r2,[pc,#360] ; [0x2bf8] = 0x100043c0 + 0x00002a90: 3220 2 ADDS r2,r2,#0x20 + 0x00002a92: 7e92 .~ LDRB r2,[r2,#0x1a] + 0x00002a94: 4311 .C ORRS r1,r1,r2 + 0x00002a96: 4a57 WJ LDR r2,[pc,#348] ; [0x2bf4] = 0x10004fe0 + 0x00002a98: 7fd2 .. LDRB r2,[r2,#0x1f] + 0x00002a9a: 2200 ." MOVS r2,#0 + 0x00002a9c: 4b56 VK LDR r3,[pc,#344] ; [0x2bf8] = 0x100043c0 + 0x00002a9e: 3320 3 ADDS r3,r3,#0x20 + 0x00002aa0: 7edb .~ LDRB r3,[r3,#0x1b] + 0x00002aa2: 4312 .C ORRS r2,r2,r2 + 0x00002aa4: 4b54 TK LDR r3,[pc,#336] ; [0x2bf8] = 0x100043c0 + 0x00002aa6: 3320 3 ADDS r3,r3,#0x20 + 0x00002aa8: 7edb .~ LDRB r3,[r3,#0x1b] + 0x00002aaa: 431a .C ORRS r2,r2,r3 + 0x00002aac: 0212 .. LSLS r2,r2,#8 + 0x00002aae: 4311 .C ORRS r1,r1,r2 + 0x00002ab0: 4a50 PJ LDR r2,[pc,#320] ; [0x2bf4] = 0x10004fe0 + 0x00002ab2: 7fd2 .. LDRB r2,[r2,#0x1f] + 0x00002ab4: 2200 ." MOVS r2,#0 + 0x00002ab6: 4b50 PK LDR r3,[pc,#320] ; [0x2bf8] = 0x100043c0 + 0x00002ab8: 3320 3 ADDS r3,r3,#0x20 + 0x00002aba: 7f1b .. LDRB r3,[r3,#0x1c] + 0x00002abc: 4312 .C ORRS r2,r2,r2 + 0x00002abe: 4b4e NK LDR r3,[pc,#312] ; [0x2bf8] = 0x100043c0 + 0x00002ac0: 3320 3 ADDS r3,r3,#0x20 + 0x00002ac2: 7f1b .. LDRB r3,[r3,#0x1c] + 0x00002ac4: 431a .C ORRS r2,r2,r3 + 0x00002ac6: 0412 .. LSLS r2,r2,#16 + 0x00002ac8: 4311 .C ORRS r1,r1,r2 + 0x00002aca: 2201 ." MOVS r2,#1 + 0x00002acc: 0712 .. LSLS r2,r2,#28 + 0x00002ace: 1888 .. ADDS r0,r1,r2 + 0x00002ad0: f000f8c5 .... BL HR_REG_24BIT ; 0x2c5e + 0x00002ad4: 4605 .F MOV r5,r0 + 0x00002ad6: 42a5 .B CMP r5,r4 + 0x00002ad8: d101 .. BNE 0x2ade ; IPC_IsTxBuffEmpty + 182 + 0x00002ada: 2001 . MOVS r0,#1 + 0x00002adc: bd70 p. POP {r4-r6,pc} + 0x00002ade: 2000 . MOVS r0,#0 + 0x00002ae0: e7fc .. B 0x2adc ; IPC_IsTxBuffEmpty + 180 + IPC_IsRxBuffEmpty + 0x00002ae2: b570 p. PUSH {r4-r6,lr} + 0x00002ae4: 4943 CI LDR r1,[pc,#268] ; [0x2bf4] = 0x10004fe0 + 0x00002ae6: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x00002ae8: 2100 .! MOVS r1,#0 + 0x00002aea: 4a43 CJ LDR r2,[pc,#268] ; [0x2bf8] = 0x100043c0 + 0x00002aec: 3240 @2 ADDS r2,r2,#0x40 + 0x00002aee: 78d2 .x LDRB r2,[r2,#3] + 0x00002af0: 4309 .C ORRS r1,r1,r1 + 0x00002af2: 4a41 AJ LDR r2,[pc,#260] ; [0x2bf8] = 0x100043c0 + 0x00002af4: 3240 @2 ADDS r2,r2,#0x40 + 0x00002af6: 78d2 .x LDRB r2,[r2,#3] + 0x00002af8: 4311 .C ORRS r1,r1,r2 + 0x00002afa: 4a3e >J LDR r2,[pc,#248] ; [0x2bf4] = 0x10004fe0 + 0x00002afc: 7fd2 .. LDRB r2,[r2,#0x1f] + 0x00002afe: 2200 ." MOVS r2,#0 + 0x00002b00: 4b3d =K LDR r3,[pc,#244] ; [0x2bf8] = 0x100043c0 + 0x00002b02: 3340 @3 ADDS r3,r3,#0x40 + 0x00002b04: 791b .y LDRB r3,[r3,#4] + 0x00002b06: 4312 .C ORRS r2,r2,r2 + 0x00002b08: 4b3b ;K LDR r3,[pc,#236] ; [0x2bf8] = 0x100043c0 + 0x00002b0a: 3340 @3 ADDS r3,r3,#0x40 + 0x00002b0c: 791b .y LDRB r3,[r3,#4] + 0x00002b0e: 431a .C ORRS r2,r2,r3 + 0x00002b10: 0212 .. LSLS r2,r2,#8 + 0x00002b12: 4311 .C ORRS r1,r1,r2 + 0x00002b14: 4a37 7J LDR r2,[pc,#220] ; [0x2bf4] = 0x10004fe0 + 0x00002b16: 7fd2 .. LDRB r2,[r2,#0x1f] + 0x00002b18: 2200 ." MOVS r2,#0 + 0x00002b1a: 4b37 7K LDR r3,[pc,#220] ; [0x2bf8] = 0x100043c0 + 0x00002b1c: 3340 @3 ADDS r3,r3,#0x40 + 0x00002b1e: 795b [y LDRB r3,[r3,#5] + 0x00002b20: 4312 .C ORRS r2,r2,r2 + 0x00002b22: 4b35 5K LDR r3,[pc,#212] ; [0x2bf8] = 0x100043c0 + 0x00002b24: 3340 @3 ADDS r3,r3,#0x40 + 0x00002b26: 795b [y LDRB r3,[r3,#5] + 0x00002b28: 431a .C ORRS r2,r2,r3 + 0x00002b2a: 0412 .. LSLS r2,r2,#16 + 0x00002b2c: 4311 .C ORRS r1,r1,r2 + 0x00002b2e: 2201 ." MOVS r2,#1 + 0x00002b30: 0712 .. LSLS r2,r2,#28 + 0x00002b32: 1888 .. ADDS r0,r1,r2 + 0x00002b34: f000f893 .... BL HR_REG_24BIT ; 0x2c5e + 0x00002b38: 4604 .F MOV r4,r0 + 0x00002b3a: 492e .I LDR r1,[pc,#184] ; [0x2bf4] = 0x10004fe0 + 0x00002b3c: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x00002b3e: 2100 .! MOVS r1,#0 + 0x00002b40: 4a2d -J LDR r2,[pc,#180] ; [0x2bf8] = 0x100043c0 + 0x00002b42: 3240 @2 ADDS r2,r2,#0x40 + 0x00002b44: 7812 .x LDRB r2,[r2,#0] + 0x00002b46: 4309 .C ORRS r1,r1,r1 + 0x00002b48: 4a2b +J LDR r2,[pc,#172] ; [0x2bf8] = 0x100043c0 + 0x00002b4a: 3240 @2 ADDS r2,r2,#0x40 + 0x00002b4c: 7812 .x LDRB r2,[r2,#0] + 0x00002b4e: 4311 .C ORRS r1,r1,r2 + 0x00002b50: 4a28 (J LDR r2,[pc,#160] ; [0x2bf4] = 0x10004fe0 + 0x00002b52: 7fd2 .. LDRB r2,[r2,#0x1f] + 0x00002b54: 2200 ." MOVS r2,#0 + 0x00002b56: 4b28 (K LDR r3,[pc,#160] ; [0x2bf8] = 0x100043c0 + 0x00002b58: 3340 @3 ADDS r3,r3,#0x40 + 0x00002b5a: 785b [x LDRB r3,[r3,#1] + 0x00002b5c: 4312 .C ORRS r2,r2,r2 + 0x00002b5e: 4b26 &K LDR r3,[pc,#152] ; [0x2bf8] = 0x100043c0 + 0x00002b60: 3340 @3 ADDS r3,r3,#0x40 + 0x00002b62: 785b [x LDRB r3,[r3,#1] + 0x00002b64: 431a .C ORRS r2,r2,r3 + 0x00002b66: 0212 .. LSLS r2,r2,#8 + 0x00002b68: 4311 .C ORRS r1,r1,r2 + 0x00002b6a: 4a22 "J LDR r2,[pc,#136] ; [0x2bf4] = 0x10004fe0 + 0x00002b6c: 7fd2 .. LDRB r2,[r2,#0x1f] + 0x00002b6e: 2200 ." MOVS r2,#0 + 0x00002b70: 4b21 !K LDR r3,[pc,#132] ; [0x2bf8] = 0x100043c0 + 0x00002b72: 3340 @3 ADDS r3,r3,#0x40 + 0x00002b74: 789b .x LDRB r3,[r3,#2] + 0x00002b76: 4312 .C ORRS r2,r2,r2 + 0x00002b78: 4b1f .K LDR r3,[pc,#124] ; [0x2bf8] = 0x100043c0 + 0x00002b7a: 3340 @3 ADDS r3,r3,#0x40 + 0x00002b7c: 789b .x LDRB r3,[r3,#2] + 0x00002b7e: 431a .C ORRS r2,r2,r3 + 0x00002b80: 0412 .. LSLS r2,r2,#16 + 0x00002b82: 4311 .C ORRS r1,r1,r2 + 0x00002b84: 2201 ." MOVS r2,#1 + 0x00002b86: 0712 .. LSLS r2,r2,#28 + 0x00002b88: 1888 .. ADDS r0,r1,r2 + 0x00002b8a: f000f868 ..h. BL HR_REG_24BIT ; 0x2c5e + 0x00002b8e: 4605 .F MOV r5,r0 + 0x00002b90: 42ac .B CMP r4,r5 + 0x00002b92: d101 .. BNE 0x2b98 ; IPC_IsRxBuffEmpty + 182 + 0x00002b94: 2001 . MOVS r0,#1 + 0x00002b96: bd70 p. POP {r4-r6,pc} + 0x00002b98: 2000 . MOVS r0,#0 + 0x00002b9a: e7fc .. B 0x2b96 ; IPC_IsRxBuffEmpty + 180 + IPC_HandleRxPacket + 0x00002b9c: b510 .. PUSH {r4,lr} + 0x00002b9e: 4c19 .L LDR r4,[pc,#100] ; [0x2c04] = 0x1001105c + 0x00002ba0: f7ffff9f .... BL IPC_IsRxBuffEmpty ; 0x2ae2 + 0x00002ba4: 2800 .( CMP r0,#0 + 0x00002ba6: d000 .. BEQ 0x2baa ; IPC_HandleRxPacket + 14 + 0x00002ba8: bd10 .. POP {r4,pc} + 0x00002baa: 2102 .! MOVS r1,#2 + 0x00002bac: 4815 .H LDR r0,[pc,#84] ; [0x2c04] = 0x1001105c + 0x00002bae: f7fffad8 .... BL ipcRx ; 0x2162 + 0x00002bb2: 7820 x LDRB r0,[r4,#0] + 0x00002bb4: 2800 .( CMP r0,#0 + 0x00002bb6: dd10 .. BLE 0x2bda ; IPC_HandleRxPacket + 62 + 0x00002bb8: 7820 x LDRB r0,[r4,#0] + 0x00002bba: 280d .( CMP r0,#0xd + 0x00002bbc: da0d .. BGE 0x2bda ; IPC_HandleRxPacket + 62 + 0x00002bbe: 7861 ax LDRB r1,[r4,#1] + 0x00002bc0: 4810 .H LDR r0,[pc,#64] ; [0x2c04] = 0x1001105c + 0x00002bc2: 1c80 .. ADDS r0,r0,#2 + 0x00002bc4: f7fffacd .... BL ipcRx ; 0x2162 + 0x00002bc8: 7860 `x LDRB r0,[r4,#1] + 0x00002bca: 7821 !x LDRB r1,[r4,#0] + 0x00002bcc: 0089 .. LSLS r1,r1,#2 + 0x00002bce: 4b0e .K LDR r3,[pc,#56] ; [0x2c08] = 0x10011014 + 0x00002bd0: 681b .h LDR r3,[r3,#0] + 0x00002bd2: 585a ZX LDR r2,[r3,r1] + 0x00002bd4: 1ca1 .. ADDS r1,r4,#2 + 0x00002bd6: 4790 .G BLX r2 + 0x00002bd8: e001 .. B 0x2bde ; IPC_HandleRxPacket + 66 + 0x00002bda: bf00 .. NOP + 0x00002bdc: e7fe .. B 0x2bdc ; IPC_HandleRxPacket + 64 + 0x00002bde: bf00 .. NOP + 0x00002be0: e7e2 .. B 0x2ba8 ; IPC_HandleRxPacket + 12 + hw_delay + 0x00002be2: bf00 .. NOP + 0x00002be4: bf00 .. NOP + 0x00002be6: bf00 .. NOP + 0x00002be8: bf00 .. NOP + 0x00002bea: bf00 .. NOP + 0x00002bec: 4770 pG BX lr $d - 0x00002adc: 10008120 ... DCD 268468512 + 0x00002bee: 0000 .. DCW 0 + 0x00002bf0: 10011124 $... DCD 268505380 + 0x00002bf4: 10004fe0 .O.. DCD 268455904 + 0x00002bf8: 100043c0 .C.. DCD 268452800 + 0x00002bfc: 00002e94 .... DCD 11924 + 0x00002c00: 00002710 .'.. DCD 10000 + 0x00002c04: 1001105c \... DCD 268505180 + 0x00002c08: 10011014 .... DCD 268505108 $t .text HW_REG_24BIT - 0x00002ae0: b570 p. PUSH {r4-r6,lr} - 0x00002ae2: 4604 .F MOV r4,r0 - 0x00002ae4: 460d .F MOV r5,r1 - 0x00002ae6: 7025 %p STRB r5,[r4,#0] - 0x00002ae8: f000f8fd .... BL hw_delay ; 0x2ce6 - 0x00002aec: 0428 (. LSLS r0,r5,#16 - 0x00002aee: 0e00 .. LSRS r0,r0,#24 - 0x00002af0: 7060 `p STRB r0,[r4,#1] - 0x00002af2: f000f8f8 .... BL hw_delay ; 0x2ce6 - 0x00002af6: 0228 (. LSLS r0,r5,#8 - 0x00002af8: 0e00 .. LSRS r0,r0,#24 - 0x00002afa: 70a0 .p STRB r0,[r4,#2] - 0x00002afc: bd70 p. POP {r4-r6,pc} + 0x00002c0c: b570 p. PUSH {r4-r6,lr} + 0x00002c0e: 4604 .F MOV r4,r0 + 0x00002c10: 460d .F MOV r5,r1 + 0x00002c12: 7025 %p STRB r5,[r4,#0] + 0x00002c14: f000f8fd .... BL hw_delay ; 0x2e12 + 0x00002c18: 0428 (. LSLS r0,r5,#16 + 0x00002c1a: 0e00 .. LSRS r0,r0,#24 + 0x00002c1c: 7060 `p STRB r0,[r4,#1] + 0x00002c1e: f000f8f8 .... BL hw_delay ; 0x2e12 + 0x00002c22: 0228 (. LSLS r0,r5,#8 + 0x00002c24: 0e00 .. LSRS r0,r0,#24 + 0x00002c26: 70a0 .p STRB r0,[r4,#2] + 0x00002c28: bd70 p. POP {r4-r6,pc} HW_REG_16BIT - 0x00002afe: b570 p. PUSH {r4-r6,lr} - 0x00002b00: 4604 .F MOV r4,r0 - 0x00002b02: 460d .F MOV r5,r1 - 0x00002b04: 7025 %p STRB r5,[r4,#0] - 0x00002b06: f000f8ee .... BL hw_delay ; 0x2ce6 - 0x00002b0a: 1228 (. ASRS r0,r5,#8 - 0x00002b0c: 7060 `p STRB r0,[r4,#1] - 0x00002b0e: bd70 p. POP {r4-r6,pc} + 0x00002c2a: b570 p. PUSH {r4-r6,lr} + 0x00002c2c: 4604 .F MOV r4,r0 + 0x00002c2e: 460d .F MOV r5,r1 + 0x00002c30: 7025 %p STRB r5,[r4,#0] + 0x00002c32: f000f8ee .... BL hw_delay ; 0x2e12 + 0x00002c36: 1228 (. ASRS r0,r5,#8 + 0x00002c38: 7060 `p STRB r0,[r4,#1] + 0x00002c3a: bd70 p. POP {r4-r6,pc} HR_REG_16BIT - 0x00002b10: b570 p. PUSH {r4-r6,lr} - 0x00002b12: 4604 .F MOV r4,r0 - 0x00002b14: 2500 .% MOVS r5,#0 - 0x00002b16: 2600 .& MOVS r6,#0 - 0x00002b18: f000f8e5 .... BL hw_delay ; 0x2ce6 - 0x00002b1c: 7825 %x LDRB r5,[r4,#0] - 0x00002b1e: f000f8e2 .... BL hw_delay ; 0x2ce6 - 0x00002b22: 7866 fx LDRB r6,[r4,#1] - 0x00002b24: 0230 0. LSLS r0,r6,#8 - 0x00002b26: 21ff .! MOVS r1,#0xff - 0x00002b28: 0209 .. LSLS r1,r1,#8 - 0x00002b2a: 4008 .@ ANDS r0,r0,r1 - 0x00002b2c: 4305 .C ORRS r5,r5,r0 - 0x00002b2e: 4628 (F MOV r0,r5 - 0x00002b30: bd70 p. POP {r4-r6,pc} + 0x00002c3c: b570 p. PUSH {r4-r6,lr} + 0x00002c3e: 4604 .F MOV r4,r0 + 0x00002c40: 2500 .% MOVS r5,#0 + 0x00002c42: 2600 .& MOVS r6,#0 + 0x00002c44: f000f8e5 .... BL hw_delay ; 0x2e12 + 0x00002c48: 7825 %x LDRB r5,[r4,#0] + 0x00002c4a: f000f8e2 .... BL hw_delay ; 0x2e12 + 0x00002c4e: 7866 fx LDRB r6,[r4,#1] + 0x00002c50: 0230 0. LSLS r0,r6,#8 + 0x00002c52: 21ff .! MOVS r1,#0xff + 0x00002c54: 0209 .. LSLS r1,r1,#8 + 0x00002c56: 4008 .@ ANDS r0,r0,r1 + 0x00002c58: 4305 .C ORRS r5,r5,r0 + 0x00002c5a: 4628 (F MOV r0,r5 + 0x00002c5c: bd70 p. POP {r4-r6,pc} HR_REG_24BIT - 0x00002b32: b570 p. PUSH {r4-r6,lr} - 0x00002b34: 4604 .F MOV r4,r0 - 0x00002b36: 2500 .% MOVS r5,#0 - 0x00002b38: f000f8d5 .... BL hw_delay ; 0x2ce6 - 0x00002b3c: 7825 %x LDRB r5,[r4,#0] - 0x00002b3e: f000f8d2 .... BL hw_delay ; 0x2ce6 - 0x00002b42: 7860 `x LDRB r0,[r4,#1] - 0x00002b44: 0200 .. LSLS r0,r0,#8 - 0x00002b46: 4305 .C ORRS r5,r5,r0 - 0x00002b48: f000f8cd .... BL hw_delay ; 0x2ce6 - 0x00002b4c: 78a0 .x LDRB r0,[r4,#2] - 0x00002b4e: 0400 .. LSLS r0,r0,#16 - 0x00002b50: 4305 .C ORRS r5,r5,r0 - 0x00002b52: 4628 (F MOV r0,r5 - 0x00002b54: bd70 p. POP {r4-r6,pc} + 0x00002c5e: b570 p. PUSH {r4-r6,lr} + 0x00002c60: 4604 .F MOV r4,r0 + 0x00002c62: 2500 .% MOVS r5,#0 + 0x00002c64: f000f8d5 .... BL hw_delay ; 0x2e12 + 0x00002c68: 7825 %x LDRB r5,[r4,#0] + 0x00002c6a: f000f8d2 .... BL hw_delay ; 0x2e12 + 0x00002c6e: 7860 `x LDRB r0,[r4,#1] + 0x00002c70: 0200 .. LSLS r0,r0,#8 + 0x00002c72: 4305 .C ORRS r5,r5,r0 + 0x00002c74: f000f8cd .... BL hw_delay ; 0x2e12 + 0x00002c78: 78a0 .x LDRB r0,[r4,#2] + 0x00002c7a: 0400 .. LSLS r0,r0,#16 + 0x00002c7c: 4305 .C ORRS r5,r5,r0 + 0x00002c7e: 4628 (F MOV r0,r5 + 0x00002c80: bd70 p. POP {r4-r6,pc} xmemcpy - 0x00002b56: b570 p. PUSH {r4-r6,lr} - 0x00002b58: 4603 .F MOV r3,r0 - 0x00002b5a: 2000 . MOVS r0,#0 - 0x00002b5c: e020 . B 0x2ba0 ; xmemcpy + 74 - 0x00002b5e: bf00 .. NOP - 0x00002b60: 4c64 dL LDR r4,[pc,#400] ; [0x2cf4] = 0x10004fe0 - 0x00002b62: 7fe4 .. LDRB r4,[r4,#0x1f] - 0x00002b64: 2400 .$ MOVS r4,#0 - 0x00002b66: 180d .. ADDS r5,r1,r0 - 0x00002b68: 2601 .& MOVS r6,#1 - 0x00002b6a: 0736 6. LSLS r6,r6,#28 - 0x00002b6c: 4335 5C ORRS r5,r5,r6 - 0x00002b6e: 782d -x LDRB r5,[r5,#0] - 0x00002b70: 4324 $C ORRS r4,r4,r4 - 0x00002b72: 180d .. ADDS r5,r1,r0 - 0x00002b74: 4335 5C ORRS r5,r5,r6 - 0x00002b76: 782d -x LDRB r5,[r5,#0] - 0x00002b78: 432c ,C ORRS r4,r4,r5 - 0x00002b7a: 181d .. ADDS r5,r3,r0 - 0x00002b7c: 4335 5C ORRS r5,r5,r6 - 0x00002b7e: 702c ,p STRB r4,[r5,#0] - 0x00002b80: 4c5c \L LDR r4,[pc,#368] ; [0x2cf4] = 0x10004fe0 - 0x00002b82: 7fe4 .. LDRB r4,[r4,#0x1f] - 0x00002b84: 2400 .$ MOVS r4,#0 - 0x00002b86: 180d .. ADDS r5,r1,r0 - 0x00002b88: 4335 5C ORRS r5,r5,r6 - 0x00002b8a: 782d -x LDRB r5,[r5,#0] - 0x00002b8c: 4324 $C ORRS r4,r4,r4 - 0x00002b8e: 180d .. ADDS r5,r1,r0 - 0x00002b90: 4335 5C ORRS r5,r5,r6 - 0x00002b92: 782d -x LDRB r5,[r5,#0] - 0x00002b94: 432c ,C ORRS r4,r4,r5 - 0x00002b96: 181d .. ADDS r5,r3,r0 - 0x00002b98: 4335 5C ORRS r5,r5,r6 - 0x00002b9a: 702c ,p STRB r4,[r5,#0] - 0x00002b9c: bf00 .. NOP - 0x00002b9e: 1c40 @. ADDS r0,r0,#1 - 0x00002ba0: 4290 .B CMP r0,r2 - 0x00002ba2: dbdc .. BLT 0x2b5e ; xmemcpy + 8 - 0x00002ba4: bd70 p. POP {r4-r6,pc} + 0x00002c82: b570 p. PUSH {r4-r6,lr} + 0x00002c84: 4603 .F MOV r3,r0 + 0x00002c86: 2000 . MOVS r0,#0 + 0x00002c88: e020 . B 0x2ccc ; xmemcpy + 74 + 0x00002c8a: bf00 .. NOP + 0x00002c8c: 4c64 dL LDR r4,[pc,#400] ; [0x2e20] = 0x10004fe0 + 0x00002c8e: 7fe4 .. LDRB r4,[r4,#0x1f] + 0x00002c90: 2400 .$ MOVS r4,#0 + 0x00002c92: 180d .. ADDS r5,r1,r0 + 0x00002c94: 2601 .& MOVS r6,#1 + 0x00002c96: 0736 6. LSLS r6,r6,#28 + 0x00002c98: 4335 5C ORRS r5,r5,r6 + 0x00002c9a: 782d -x LDRB r5,[r5,#0] + 0x00002c9c: 4324 $C ORRS r4,r4,r4 + 0x00002c9e: 180d .. ADDS r5,r1,r0 + 0x00002ca0: 4335 5C ORRS r5,r5,r6 + 0x00002ca2: 782d -x LDRB r5,[r5,#0] + 0x00002ca4: 432c ,C ORRS r4,r4,r5 + 0x00002ca6: 181d .. ADDS r5,r3,r0 + 0x00002ca8: 4335 5C ORRS r5,r5,r6 + 0x00002caa: 702c ,p STRB r4,[r5,#0] + 0x00002cac: 4c5c \L LDR r4,[pc,#368] ; [0x2e20] = 0x10004fe0 + 0x00002cae: 7fe4 .. LDRB r4,[r4,#0x1f] + 0x00002cb0: 2400 .$ MOVS r4,#0 + 0x00002cb2: 180d .. ADDS r5,r1,r0 + 0x00002cb4: 4335 5C ORRS r5,r5,r6 + 0x00002cb6: 782d -x LDRB r5,[r5,#0] + 0x00002cb8: 4324 $C ORRS r4,r4,r4 + 0x00002cba: 180d .. ADDS r5,r1,r0 + 0x00002cbc: 4335 5C ORRS r5,r5,r6 + 0x00002cbe: 782d -x LDRB r5,[r5,#0] + 0x00002cc0: 432c ,C ORRS r4,r4,r5 + 0x00002cc2: 181d .. ADDS r5,r3,r0 + 0x00002cc4: 4335 5C ORRS r5,r5,r6 + 0x00002cc6: 702c ,p STRB r4,[r5,#0] + 0x00002cc8: bf00 .. NOP + 0x00002cca: 1c40 @. ADDS r0,r0,#1 + 0x00002ccc: 4290 .B CMP r0,r2 + 0x00002cce: dbdc .. BLT 0x2c8a ; xmemcpy + 8 + 0x00002cd0: bd70 p. POP {r4-r6,pc} xstrlen - 0x00002ba6: 4601 .F MOV r1,r0 - 0x00002ba8: 2200 ." MOVS r2,#0 - 0x00002baa: e001 .. B 0x2bb0 ; xstrlen + 10 - 0x00002bac: 1c52 R. ADDS r2,r2,#1 - 0x00002bae: 1c49 I. ADDS r1,r1,#1 - 0x00002bb0: 7808 .x LDRB r0,[r1,#0] - 0x00002bb2: 2800 .( CMP r0,#0 - 0x00002bb4: d1fa .. BNE 0x2bac ; xstrlen + 6 - 0x00002bb6: b290 .. UXTH r0,r2 - 0x00002bb8: 4770 pG BX lr + 0x00002cd2: 4601 .F MOV r1,r0 + 0x00002cd4: 2200 ." MOVS r2,#0 + 0x00002cd6: e001 .. B 0x2cdc ; xstrlen + 10 + 0x00002cd8: 1c52 R. ADDS r2,r2,#1 + 0x00002cda: 1c49 I. ADDS r1,r1,#1 + 0x00002cdc: 7808 .x LDRB r0,[r1,#0] + 0x00002cde: 2800 .( CMP r0,#0 + 0x00002ce0: d1fa .. BNE 0x2cd8 ; xstrlen + 6 + 0x00002ce2: b290 .. UXTH r0,r2 + 0x00002ce4: 4770 pG BX lr error_handle - 0x00002bba: bf00 .. NOP - 0x00002bbc: e7fe .. B 0x2bbc ; error_handle + 2 + 0x00002ce6: bf00 .. NOP + 0x00002ce8: e7fe .. B 0x2ce8 ; error_handle + 2 Lpm_LockLpm - 0x00002bbe: b570 p. PUSH {r4-r6,lr} - 0x00002bc0: 4604 .F MOV r4,r0 - 0x00002bc2: 484d MH LDR r0,[pc,#308] ; [0x2cf8] = 0x1000442a - 0x00002bc4: f7ffffa4 .... BL HR_REG_16BIT ; 0x2b10 - 0x00002bc8: 4320 C ORRS r0,r0,r4 - 0x00002bca: 4605 .F MOV r5,r0 - 0x00002bcc: 4629 )F MOV r1,r5 - 0x00002bce: 484a JH LDR r0,[pc,#296] ; [0x2cf8] = 0x1000442a - 0x00002bd0: f7ffff95 .... BL HW_REG_16BIT ; 0x2afe - 0x00002bd4: bd70 p. POP {r4-r6,pc} + 0x00002cea: b570 p. PUSH {r4-r6,lr} + 0x00002cec: 4604 .F MOV r4,r0 + 0x00002cee: 484d MH LDR r0,[pc,#308] ; [0x2e24] = 0x1000442a + 0x00002cf0: f7ffffa4 .... BL HR_REG_16BIT ; 0x2c3c + 0x00002cf4: 4320 C ORRS r0,r0,r4 + 0x00002cf6: 4605 .F MOV r5,r0 + 0x00002cf8: 4629 )F MOV r1,r5 + 0x00002cfa: 484a JH LDR r0,[pc,#296] ; [0x2e24] = 0x1000442a + 0x00002cfc: f7ffff95 .... BL HW_REG_16BIT ; 0x2c2a + 0x00002d00: bd70 p. POP {r4-r6,pc} Lpm_unLockLpm - 0x00002bd6: b570 p. PUSH {r4-r6,lr} - 0x00002bd8: 4604 .F MOV r4,r0 - 0x00002bda: 4847 GH LDR r0,[pc,#284] ; [0x2cf8] = 0x1000442a - 0x00002bdc: f7ffff98 .... BL HR_REG_16BIT ; 0x2b10 - 0x00002be0: 43a0 .C BICS r0,r0,r4 - 0x00002be2: 4605 .F MOV r5,r0 - 0x00002be4: 4629 )F MOV r1,r5 - 0x00002be6: 4844 DH LDR r0,[pc,#272] ; [0x2cf8] = 0x1000442a - 0x00002be8: f7ffff89 .... BL HW_REG_16BIT ; 0x2afe - 0x00002bec: bd70 p. POP {r4-r6,pc} + 0x00002d02: b570 p. PUSH {r4-r6,lr} + 0x00002d04: 4604 .F MOV r4,r0 + 0x00002d06: 4847 GH LDR r0,[pc,#284] ; [0x2e24] = 0x1000442a + 0x00002d08: f7ffff98 .... BL HR_REG_16BIT ; 0x2c3c + 0x00002d0c: 43a0 .C BICS r0,r0,r4 + 0x00002d0e: 4605 .F MOV r5,r0 + 0x00002d10: 4629 )F MOV r1,r5 + 0x00002d12: 4844 DH LDR r0,[pc,#272] ; [0x2e24] = 0x1000442a + 0x00002d14: f7ffff89 .... BL HW_REG_16BIT ; 0x2c2a + 0x00002d18: bd70 p. POP {r4-r6,pc} Lpm_CheckLpmFlag - 0x00002bee: b510 .. PUSH {r4,lr} - 0x00002bf0: 4841 AH LDR r0,[pc,#260] ; [0x2cf8] = 0x1000442a - 0x00002bf2: f7ffff8d .... BL HR_REG_16BIT ; 0x2b10 - 0x00002bf6: 2800 .( CMP r0,#0 - 0x00002bf8: d101 .. BNE 0x2bfe ; Lpm_CheckLpmFlag + 16 - 0x00002bfa: 2001 . MOVS r0,#1 - 0x00002bfc: bd10 .. POP {r4,pc} - 0x00002bfe: 2000 . MOVS r0,#0 - 0x00002c00: e7fc .. B 0x2bfc ; Lpm_CheckLpmFlag + 14 + 0x00002d1a: b510 .. PUSH {r4,lr} + 0x00002d1c: 4841 AH LDR r0,[pc,#260] ; [0x2e24] = 0x1000442a + 0x00002d1e: f7ffff8d .... BL HR_REG_16BIT ; 0x2c3c + 0x00002d22: 2800 .( CMP r0,#0 + 0x00002d24: d101 .. BNE 0x2d2a ; Lpm_CheckLpmFlag + 16 + 0x00002d26: 2001 . MOVS r0,#1 + 0x00002d28: bd10 .. POP {r4,pc} + 0x00002d2a: 2000 . MOVS r0,#0 + 0x00002d2c: e7fc .. B 0x2d28 ; Lpm_CheckLpmFlag + 14 whileDelay - 0x00002c02: b510 .. PUSH {r4,lr} - 0x00002c04: 2100 .! MOVS r1,#0 - 0x00002c06: e006 .. B 0x2c16 ; whileDelay + 20 - 0x00002c08: 4a3c C ORRS r6,r6,r7 - 0x00002c6a: 7836 6x LDRB r6,[r6,#0] - 0x00002c6c: 4300 .C ORRS r0,r0,r0 - 0x00002c6e: 1866 f. ADDS r6,r4,r1 - 0x00002c70: 433e >C ORRS r6,r6,r7 - 0x00002c72: 7836 6x LDRB r6,[r6,#0] - 0x00002c74: 4330 0C ORRS r0,r0,r6 - 0x00002c76: 4285 .B CMP r5,r0 - 0x00002c78: d001 .. BEQ 0x2c7e ; xramcmp + 70 - 0x00002c7a: 2000 . MOVS r0,#0 - 0x00002c7c: bdf0 .. POP {r4-r7,pc} - 0x00002c7e: 1c49 I. ADDS r1,r1,#1 - 0x00002c80: 4291 .B CMP r1,r2 - 0x00002c82: dbde .. BLT 0x2c42 ; xramcmp + 10 - 0x00002c84: 2001 . MOVS r0,#1 - 0x00002c86: e7f9 .. B 0x2c7c ; xramcmp + 68 + 0x00002d64: b5f0 .. PUSH {r4-r7,lr} + 0x00002d66: 4603 .F MOV r3,r0 + 0x00002d68: 460c .F MOV r4,r1 + 0x00002d6a: 2100 .! MOVS r1,#0 + 0x00002d6c: e01e .. B 0x2dac ; xramcmp + 72 + 0x00002d6e: 482c ,H LDR r0,[pc,#176] ; [0x2e20] = 0x10004fe0 + 0x00002d70: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x00002d72: 2000 . MOVS r0,#0 + 0x00002d74: 185d ]. ADDS r5,r3,r1 + 0x00002d76: 2601 .& MOVS r6,#1 + 0x00002d78: 0736 6. LSLS r6,r6,#28 + 0x00002d7a: 4335 5C ORRS r5,r5,r6 + 0x00002d7c: 782d -x LDRB r5,[r5,#0] + 0x00002d7e: 4300 .C ORRS r0,r0,r0 + 0x00002d80: 185d ]. ADDS r5,r3,r1 + 0x00002d82: 4335 5C ORRS r5,r5,r6 + 0x00002d84: 782d -x LDRB r5,[r5,#0] + 0x00002d86: 4305 .C ORRS r5,r5,r0 + 0x00002d88: 4825 %H LDR r0,[pc,#148] ; [0x2e20] = 0x10004fe0 + 0x00002d8a: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x00002d8c: 2000 . MOVS r0,#0 + 0x00002d8e: 1866 f. ADDS r6,r4,r1 + 0x00002d90: 2701 .' MOVS r7,#1 + 0x00002d92: 073f ?. LSLS r7,r7,#28 + 0x00002d94: 433e >C ORRS r6,r6,r7 + 0x00002d96: 7836 6x LDRB r6,[r6,#0] + 0x00002d98: 4300 .C ORRS r0,r0,r0 + 0x00002d9a: 1866 f. ADDS r6,r4,r1 + 0x00002d9c: 433e >C ORRS r6,r6,r7 + 0x00002d9e: 7836 6x LDRB r6,[r6,#0] + 0x00002da0: 4330 0C ORRS r0,r0,r6 + 0x00002da2: 4285 .B CMP r5,r0 + 0x00002da4: d001 .. BEQ 0x2daa ; xramcmp + 70 + 0x00002da6: 2000 . MOVS r0,#0 + 0x00002da8: bdf0 .. POP {r4-r7,pc} + 0x00002daa: 1c49 I. ADDS r1,r1,#1 + 0x00002dac: 4291 .B CMP r1,r2 + 0x00002dae: dbde .. BLT 0x2d6e ; xramcmp + 10 + 0x00002db0: 2001 . MOVS r0,#1 + 0x00002db2: e7f9 .. B 0x2da8 ; xramcmp + 68 xramcpy - 0x00002c88: b570 p. PUSH {r4-r6,lr} - 0x00002c8a: 4603 .F MOV r3,r0 - 0x00002c8c: 2000 . MOVS r0,#0 - 0x00002c8e: e020 . B 0x2cd2 ; xramcpy + 74 - 0x00002c90: bf00 .. NOP - 0x00002c92: 4c18 .L LDR r4,[pc,#96] ; [0x2cf4] = 0x10004fe0 - 0x00002c94: 7fe4 .. LDRB r4,[r4,#0x1f] - 0x00002c96: 2400 .$ MOVS r4,#0 - 0x00002c98: 180d .. ADDS r5,r1,r0 - 0x00002c9a: 2601 .& MOVS r6,#1 - 0x00002c9c: 0736 6. LSLS r6,r6,#28 - 0x00002c9e: 4335 5C ORRS r5,r5,r6 - 0x00002ca0: 782d -x LDRB r5,[r5,#0] - 0x00002ca2: 4324 $C ORRS r4,r4,r4 - 0x00002ca4: 180d .. ADDS r5,r1,r0 - 0x00002ca6: 4335 5C ORRS r5,r5,r6 - 0x00002ca8: 782d -x LDRB r5,[r5,#0] - 0x00002caa: 432c ,C ORRS r4,r4,r5 - 0x00002cac: 181d .. ADDS r5,r3,r0 - 0x00002cae: 4335 5C ORRS r5,r5,r6 - 0x00002cb0: 702c ,p STRB r4,[r5,#0] - 0x00002cb2: 4c10 .L LDR r4,[pc,#64] ; [0x2cf4] = 0x10004fe0 - 0x00002cb4: 7fe4 .. LDRB r4,[r4,#0x1f] - 0x00002cb6: 2400 .$ MOVS r4,#0 - 0x00002cb8: 180d .. ADDS r5,r1,r0 - 0x00002cba: 4335 5C ORRS r5,r5,r6 - 0x00002cbc: 782d -x LDRB r5,[r5,#0] - 0x00002cbe: 4324 $C ORRS r4,r4,r4 - 0x00002cc0: 180d .. ADDS r5,r1,r0 - 0x00002cc2: 4335 5C ORRS r5,r5,r6 - 0x00002cc4: 782d -x LDRB r5,[r5,#0] - 0x00002cc6: 432c ,C ORRS r4,r4,r5 - 0x00002cc8: 181d .. ADDS r5,r3,r0 - 0x00002cca: 4335 5C ORRS r5,r5,r6 - 0x00002ccc: 702c ,p STRB r4,[r5,#0] - 0x00002cce: bf00 .. NOP - 0x00002cd0: 1c40 @. ADDS r0,r0,#1 - 0x00002cd2: 4290 .B CMP r0,r2 - 0x00002cd4: dbdc .. BLT 0x2c90 ; xramcpy + 8 - 0x00002cd6: bd70 p. POP {r4-r6,pc} + 0x00002db4: b570 p. PUSH {r4-r6,lr} + 0x00002db6: 4603 .F MOV r3,r0 + 0x00002db8: 2000 . MOVS r0,#0 + 0x00002dba: e020 . B 0x2dfe ; xramcpy + 74 + 0x00002dbc: bf00 .. NOP + 0x00002dbe: 4c18 .L LDR r4,[pc,#96] ; [0x2e20] = 0x10004fe0 + 0x00002dc0: 7fe4 .. LDRB r4,[r4,#0x1f] + 0x00002dc2: 2400 .$ MOVS r4,#0 + 0x00002dc4: 180d .. ADDS r5,r1,r0 + 0x00002dc6: 2601 .& MOVS r6,#1 + 0x00002dc8: 0736 6. LSLS r6,r6,#28 + 0x00002dca: 4335 5C ORRS r5,r5,r6 + 0x00002dcc: 782d -x LDRB r5,[r5,#0] + 0x00002dce: 4324 $C ORRS r4,r4,r4 + 0x00002dd0: 180d .. ADDS r5,r1,r0 + 0x00002dd2: 4335 5C ORRS r5,r5,r6 + 0x00002dd4: 782d -x LDRB r5,[r5,#0] + 0x00002dd6: 432c ,C ORRS r4,r4,r5 + 0x00002dd8: 181d .. ADDS r5,r3,r0 + 0x00002dda: 4335 5C ORRS r5,r5,r6 + 0x00002ddc: 702c ,p STRB r4,[r5,#0] + 0x00002dde: 4c10 .L LDR r4,[pc,#64] ; [0x2e20] = 0x10004fe0 + 0x00002de0: 7fe4 .. LDRB r4,[r4,#0x1f] + 0x00002de2: 2400 .$ MOVS r4,#0 + 0x00002de4: 180d .. ADDS r5,r1,r0 + 0x00002de6: 4335 5C ORRS r5,r5,r6 + 0x00002de8: 782d -x LDRB r5,[r5,#0] + 0x00002dea: 4324 $C ORRS r4,r4,r4 + 0x00002dec: 180d .. ADDS r5,r1,r0 + 0x00002dee: 4335 5C ORRS r5,r5,r6 + 0x00002df0: 782d -x LDRB r5,[r5,#0] + 0x00002df2: 432c ,C ORRS r4,r4,r5 + 0x00002df4: 181d .. ADDS r5,r3,r0 + 0x00002df6: 4335 5C ORRS r5,r5,r6 + 0x00002df8: 702c ,p STRB r4,[r5,#0] + 0x00002dfa: bf00 .. NOP + 0x00002dfc: 1c40 @. ADDS r0,r0,#1 + 0x00002dfe: 4290 .B CMP r0,r2 + 0x00002e00: dbdc .. BLT 0x2dbc ; xramcpy + 8 + 0x00002e02: bd70 p. POP {r4-r6,pc} math_abs - 0x00002cd8: 4601 .F MOV r1,r0 - 0x00002cda: 2900 .) CMP r1,#0 - 0x00002cdc: da01 .. BGE 0x2ce2 ; math_abs + 10 - 0x00002cde: 4248 HB RSBS r0,r1,#0 - 0x00002ce0: 4770 pG BX lr - 0x00002ce2: 4608 .F MOV r0,r1 - 0x00002ce4: e7fc .. B 0x2ce0 ; math_abs + 8 + 0x00002e04: 4601 .F MOV r1,r0 + 0x00002e06: 2900 .) CMP r1,#0 + 0x00002e08: da01 .. BGE 0x2e0e ; math_abs + 10 + 0x00002e0a: 4248 HB RSBS r0,r1,#0 + 0x00002e0c: 4770 pG BX lr + 0x00002e0e: 4608 .F MOV r0,r1 + 0x00002e10: e7fc .. B 0x2e0c ; math_abs + 8 hw_delay - 0x00002ce6: bf00 .. NOP - 0x00002ce8: bf00 .. NOP - 0x00002cea: bf00 .. NOP - 0x00002cec: bf00 .. NOP - 0x00002cee: bf00 .. NOP - 0x00002cf0: 4770 pG BX lr + 0x00002e12: bf00 .. NOP + 0x00002e14: bf00 .. NOP + 0x00002e16: bf00 .. NOP + 0x00002e18: bf00 .. NOP + 0x00002e1a: bf00 .. NOP + 0x00002e1c: 4770 pG BX lr $d - 0x00002cf2: 0000 .. DCW 0 - 0x00002cf4: 10004fe0 .O.. DCD 268455904 - 0x00002cf8: 1000442a *D.. DCD 268452906 - 0x00002cfc: 00004e20 N.. DCD 20000 + 0x00002e1e: 0000 .. DCW 0 + 0x00002e20: 10004fe0 .O.. DCD 268455904 + 0x00002e24: 1000442a *D.. DCD 268452906 + 0x00002e28: 00004e20 N.. DCD 20000 $t .text - Audio_EqDisable - 0x00002d00: bf00 .. NOP - 0x00002d02: 48f8 .H LDR r0,[pc,#992] ; [0x30e4] = 0x10004fe0 - 0x00002d04: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00002d06: 2000 . MOVS r0,#0 - 0x00002d08: 49f7 .I LDR r1,[pc,#988] ; [0x30e8] = 0x10008060 - 0x00002d0a: 78c9 .x LDRB r1,[r1,#3] - 0x00002d0c: 4300 .C ORRS r0,r0,r0 - 0x00002d0e: 49f6 .I LDR r1,[pc,#984] ; [0x30e8] = 0x10008060 - 0x00002d10: 78c9 .x LDRB r1,[r1,#3] - 0x00002d12: 4308 .C ORRS r0,r0,r1 - 0x00002d14: 2140 @! MOVS r1,#0x40 - 0x00002d16: 4388 .C BICS r0,r0,r1 - 0x00002d18: 49f3 .I LDR r1,[pc,#972] ; [0x30e8] = 0x10008060 - 0x00002d1a: 70c8 .p STRB r0,[r1,#3] - 0x00002d1c: 48f1 .H LDR r0,[pc,#964] ; [0x30e4] = 0x10004fe0 - 0x00002d1e: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00002d20: 2000 . MOVS r0,#0 - 0x00002d22: 78c9 .x LDRB r1,[r1,#3] - 0x00002d24: 4300 .C ORRS r0,r0,r0 - 0x00002d26: 49f0 .I LDR r1,[pc,#960] ; [0x30e8] = 0x10008060 - 0x00002d28: 78c9 .x LDRB r1,[r1,#3] - 0x00002d2a: 4308 .C ORRS r0,r0,r1 - 0x00002d2c: 2140 @! MOVS r1,#0x40 - 0x00002d2e: 4388 .C BICS r0,r0,r1 - 0x00002d30: 49ed .I LDR r1,[pc,#948] ; [0x30e8] = 0x10008060 - 0x00002d32: 70c8 .p STRB r0,[r1,#3] - 0x00002d34: bf00 .. NOP - 0x00002d36: 4770 pG BX lr - Audio_DACClkOff - 0x00002d38: bf00 .. NOP - 0x00002d3a: bf00 .. NOP - 0x00002d3c: 48e9 .H LDR r0,[pc,#932] ; [0x30e4] = 0x10004fe0 - 0x00002d3e: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00002d40: 2000 . MOVS r0,#0 - 0x00002d42: 49e9 .I LDR r1,[pc,#932] ; [0x30e8] = 0x10008060 - 0x00002d44: 3920 9 SUBS r1,r1,#0x20 - 0x00002d46: 7c09 .| LDRB r1,[r1,#0x10] - 0x00002d48: 4300 .C ORRS r0,r0,r0 - 0x00002d4a: 49e7 .I LDR r1,[pc,#924] ; [0x30e8] = 0x10008060 - 0x00002d4c: 3920 9 SUBS r1,r1,#0x20 - 0x00002d4e: 7c09 .| LDRB r1,[r1,#0x10] - 0x00002d50: 4308 .C ORRS r0,r0,r1 - 0x00002d52: 49e4 .I LDR r1,[pc,#912] ; [0x30e4] = 0x10004fe0 - 0x00002d54: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00002d56: 4ae4 .J LDR r2,[pc,#912] ; [0x30e8] = 0x10008060 - 0x00002d58: 3a20 : SUBS r2,r2,#0x20 - 0x00002d5a: 7c52 R| LDRB r2,[r2,#0x11] - 0x00002d5c: 4311 .C ORRS r1,r1,r2 - 0x00002d5e: 4ae2 .J LDR r2,[pc,#904] ; [0x30e8] = 0x10008060 - 0x00002d60: 3a20 : SUBS r2,r2,#0x20 - 0x00002d62: 7c52 R| LDRB r2,[r2,#0x11] - 0x00002d64: 4311 .C ORRS r1,r1,r2 - 0x00002d66: 0209 .. LSLS r1,r1,#8 - 0x00002d68: 4308 .C ORRS r0,r0,r1 - 0x00002d6a: 2120 ! MOVS r1,#0x20 - 0x00002d6c: 4308 .C ORRS r0,r0,r1 - 0x00002d6e: 49de .I LDR r1,[pc,#888] ; [0x30e8] = 0x10008060 - 0x00002d70: 3920 9 SUBS r1,r1,#0x20 - 0x00002d72: 7408 .t STRB r0,[r1,#0x10] - 0x00002d74: 48db .H LDR r0,[pc,#876] ; [0x30e4] = 0x10004fe0 - 0x00002d76: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00002d78: 2000 . MOVS r0,#0 - 0x00002d7a: 7c09 .| LDRB r1,[r1,#0x10] - 0x00002d7c: 4300 .C ORRS r0,r0,r0 - 0x00002d7e: 49da .I LDR r1,[pc,#872] ; [0x30e8] = 0x10008060 - 0x00002d80: 3920 9 SUBS r1,r1,#0x20 - 0x00002d82: 7c09 .| LDRB r1,[r1,#0x10] - 0x00002d84: 4308 .C ORRS r0,r0,r1 - 0x00002d86: 49d7 .I LDR r1,[pc,#860] ; [0x30e4] = 0x10004fe0 - 0x00002d88: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00002d8a: 4ad7 .J LDR r2,[pc,#860] ; [0x30e8] = 0x10008060 - 0x00002d8c: 3a20 : SUBS r2,r2,#0x20 - 0x00002d8e: 7c52 R| LDRB r2,[r2,#0x11] - 0x00002d90: 4311 .C ORRS r1,r1,r2 - 0x00002d92: 4ad5 .J LDR r2,[pc,#852] ; [0x30e8] = 0x10008060 - 0x00002d94: 3a20 : SUBS r2,r2,#0x20 - 0x00002d96: 7c52 R| LDRB r2,[r2,#0x11] - 0x00002d98: 4311 .C ORRS r1,r1,r2 - 0x00002d9a: 0209 .. LSLS r1,r1,#8 - 0x00002d9c: 4308 .C ORRS r0,r0,r1 - 0x00002d9e: 2120 ! MOVS r1,#0x20 - 0x00002da0: 4308 .C ORRS r0,r0,r1 - 0x00002da2: 49d1 .I LDR r1,[pc,#836] ; [0x30e8] = 0x10008060 - 0x00002da4: 3920 9 SUBS r1,r1,#0x20 - 0x00002da6: 7408 .t STRB r0,[r1,#0x10] - 0x00002da8: bf00 .. NOP - 0x00002daa: bf00 .. NOP - 0x00002dac: 48cd .H LDR r0,[pc,#820] ; [0x30e4] = 0x10004fe0 - 0x00002dae: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00002db0: 2000 . MOVS r0,#0 - 0x00002db2: 7c09 .| LDRB r1,[r1,#0x10] - 0x00002db4: 4300 .C ORRS r0,r0,r0 - 0x00002db6: 49cc .I LDR r1,[pc,#816] ; [0x30e8] = 0x10008060 - 0x00002db8: 3920 9 SUBS r1,r1,#0x20 - 0x00002dba: 7c09 .| LDRB r1,[r1,#0x10] - 0x00002dbc: 4308 .C ORRS r0,r0,r1 - 0x00002dbe: 49c9 .I LDR r1,[pc,#804] ; [0x30e4] = 0x10004fe0 - 0x00002dc0: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00002dc2: 2100 .! MOVS r1,#0 - 0x00002dc4: 4ac8 .J LDR r2,[pc,#800] ; [0x30e8] = 0x10008060 - 0x00002dc6: 3a20 : SUBS r2,r2,#0x20 - 0x00002dc8: 7c52 R| LDRB r2,[r2,#0x11] - 0x00002dca: 4309 .C ORRS r1,r1,r1 - 0x00002dcc: 4ac6 .J LDR r2,[pc,#792] ; [0x30e8] = 0x10008060 - 0x00002dce: 3a20 : SUBS r2,r2,#0x20 - 0x00002dd0: 7c52 R| LDRB r2,[r2,#0x11] - 0x00002dd2: 4311 .C ORRS r1,r1,r2 - 0x00002dd4: 0209 .. LSLS r1,r1,#8 - 0x00002dd6: 4308 .C ORRS r0,r0,r1 - 0x00002dd8: 2120 ! MOVS r1,#0x20 - 0x00002dda: 4308 .C ORRS r0,r0,r1 - 0x00002ddc: 1200 .. ASRS r0,r0,#8 - 0x00002dde: 49c2 .I LDR r1,[pc,#776] ; [0x30e8] = 0x10008060 - 0x00002de0: 3920 9 SUBS r1,r1,#0x20 - 0x00002de2: 7448 Ht STRB r0,[r1,#0x11] - 0x00002de4: 48bf .H LDR r0,[pc,#764] ; [0x30e4] = 0x10004fe0 - 0x00002de6: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00002de8: 2000 . MOVS r0,#0 - 0x00002dea: 7c09 .| LDRB r1,[r1,#0x10] - 0x00002dec: 4300 .C ORRS r0,r0,r0 - 0x00002dee: 49be .I LDR r1,[pc,#760] ; [0x30e8] = 0x10008060 - 0x00002df0: 3920 9 SUBS r1,r1,#0x20 - 0x00002df2: 7c09 .| LDRB r1,[r1,#0x10] - 0x00002df4: 4308 .C ORRS r0,r0,r1 - 0x00002df6: 49bb .I LDR r1,[pc,#748] ; [0x30e4] = 0x10004fe0 - 0x00002df8: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00002dfa: 2100 .! MOVS r1,#0 - 0x00002dfc: 4aba .J LDR r2,[pc,#744] ; [0x30e8] = 0x10008060 - 0x00002dfe: 3a20 : SUBS r2,r2,#0x20 - 0x00002e00: 7c52 R| LDRB r2,[r2,#0x11] - 0x00002e02: 4309 .C ORRS r1,r1,r1 - 0x00002e04: 4ab8 .J LDR r2,[pc,#736] ; [0x30e8] = 0x10008060 - 0x00002e06: 3a20 : SUBS r2,r2,#0x20 - 0x00002e08: 7c52 R| LDRB r2,[r2,#0x11] - 0x00002e0a: 4311 .C ORRS r1,r1,r2 - 0x00002e0c: 0209 .. LSLS r1,r1,#8 - 0x00002e0e: 4308 .C ORRS r0,r0,r1 - 0x00002e10: 2120 ! MOVS r1,#0x20 - 0x00002e12: 4308 .C ORRS r0,r0,r1 - 0x00002e14: 1200 .. ASRS r0,r0,#8 - 0x00002e16: 49b4 .I LDR r1,[pc,#720] ; [0x30e8] = 0x10008060 - 0x00002e18: 3920 9 SUBS r1,r1,#0x20 - 0x00002e1a: 7448 Ht STRB r0,[r1,#0x11] - 0x00002e1c: bf00 .. NOP - 0x00002e1e: bf00 .. NOP - 0x00002e20: bf00 .. NOP - 0x00002e22: bf00 .. NOP - 0x00002e24: 48af .H LDR r0,[pc,#700] ; [0x30e4] = 0x10004fe0 - 0x00002e26: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00002e28: 2000 . MOVS r0,#0 - 0x00002e2a: 7c09 .| LDRB r1,[r1,#0x10] - 0x00002e2c: 4300 .C ORRS r0,r0,r0 - 0x00002e2e: 49ae .I LDR r1,[pc,#696] ; [0x30e8] = 0x10008060 - 0x00002e30: 3920 9 SUBS r1,r1,#0x20 - 0x00002e32: 7c09 .| LDRB r1,[r1,#0x10] - 0x00002e34: 4308 .C ORRS r0,r0,r1 - 0x00002e36: 49ab .I LDR r1,[pc,#684] ; [0x30e4] = 0x10004fe0 - 0x00002e38: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00002e3a: 4aab .J LDR r2,[pc,#684] ; [0x30e8] = 0x10008060 - 0x00002e3c: 3a20 : SUBS r2,r2,#0x20 - 0x00002e3e: 7c52 R| LDRB r2,[r2,#0x11] - 0x00002e40: 4311 .C ORRS r1,r1,r2 - 0x00002e42: 4aa9 .J LDR r2,[pc,#676] ; [0x30e8] = 0x10008060 - 0x00002e44: 3a20 : SUBS r2,r2,#0x20 - 0x00002e46: 7c52 R| LDRB r2,[r2,#0x11] - 0x00002e48: 4311 .C ORRS r1,r1,r2 - 0x00002e4a: 0209 .. LSLS r1,r1,#8 - 0x00002e4c: 4308 .C ORRS r0,r0,r1 - 0x00002e4e: 2140 @! MOVS r1,#0x40 - 0x00002e50: 4308 .C ORRS r0,r0,r1 - 0x00002e52: 49a5 .I LDR r1,[pc,#660] ; [0x30e8] = 0x10008060 - 0x00002e54: 3920 9 SUBS r1,r1,#0x20 - 0x00002e56: 7408 .t STRB r0,[r1,#0x10] - 0x00002e58: 48a2 .H LDR r0,[pc,#648] ; [0x30e4] = 0x10004fe0 - 0x00002e5a: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00002e5c: 2000 . MOVS r0,#0 - 0x00002e5e: 7c09 .| LDRB r1,[r1,#0x10] - 0x00002e60: 4300 .C ORRS r0,r0,r0 - 0x00002e62: 49a1 .I LDR r1,[pc,#644] ; [0x30e8] = 0x10008060 - 0x00002e64: 3920 9 SUBS r1,r1,#0x20 - 0x00002e66: 7c09 .| LDRB r1,[r1,#0x10] - 0x00002e68: 4308 .C ORRS r0,r0,r1 - 0x00002e6a: 499e .I LDR r1,[pc,#632] ; [0x30e4] = 0x10004fe0 - 0x00002e6c: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00002e6e: 4a9e .J LDR r2,[pc,#632] ; [0x30e8] = 0x10008060 - 0x00002e70: 3a20 : SUBS r2,r2,#0x20 - 0x00002e72: 7c52 R| LDRB r2,[r2,#0x11] - 0x00002e74: 4311 .C ORRS r1,r1,r2 - 0x00002e76: 4a9c .J LDR r2,[pc,#624] ; [0x30e8] = 0x10008060 - 0x00002e78: 3a20 : SUBS r2,r2,#0x20 - 0x00002e7a: 7c52 R| LDRB r2,[r2,#0x11] - 0x00002e7c: 4311 .C ORRS r1,r1,r2 - 0x00002e7e: 0209 .. LSLS r1,r1,#8 - 0x00002e80: 4308 .C ORRS r0,r0,r1 - 0x00002e82: 2140 @! MOVS r1,#0x40 - 0x00002e84: 4308 .C ORRS r0,r0,r1 - 0x00002e86: 4998 .I LDR r1,[pc,#608] ; [0x30e8] = 0x10008060 - 0x00002e88: 3920 9 SUBS r1,r1,#0x20 - 0x00002e8a: 7408 .t STRB r0,[r1,#0x10] - 0x00002e8c: bf00 .. NOP - 0x00002e8e: bf00 .. NOP - 0x00002e90: 4894 .H LDR r0,[pc,#592] ; [0x30e4] = 0x10004fe0 - 0x00002e92: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00002e94: 2000 . MOVS r0,#0 - 0x00002e96: 7c09 .| LDRB r1,[r1,#0x10] - 0x00002e98: 4300 .C ORRS r0,r0,r0 - 0x00002e9a: 4993 .I LDR r1,[pc,#588] ; [0x30e8] = 0x10008060 - 0x00002e9c: 3920 9 SUBS r1,r1,#0x20 - 0x00002e9e: 7c09 .| LDRB r1,[r1,#0x10] - 0x00002ea0: 4308 .C ORRS r0,r0,r1 - 0x00002ea2: 4990 .I LDR r1,[pc,#576] ; [0x30e4] = 0x10004fe0 - 0x00002ea4: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00002ea6: 2100 .! MOVS r1,#0 - 0x00002ea8: 4a8f .J LDR r2,[pc,#572] ; [0x30e8] = 0x10008060 - 0x00002eaa: 3a20 : SUBS r2,r2,#0x20 - 0x00002eac: 7c52 R| LDRB r2,[r2,#0x11] - 0x00002eae: 4309 .C ORRS r1,r1,r1 - 0x00002eb0: 4a8d .J LDR r2,[pc,#564] ; [0x30e8] = 0x10008060 - 0x00002eb2: 3a20 : SUBS r2,r2,#0x20 - 0x00002eb4: 7c52 R| LDRB r2,[r2,#0x11] - 0x00002eb6: 4311 .C ORRS r1,r1,r2 - 0x00002eb8: 0209 .. LSLS r1,r1,#8 - 0x00002eba: 4308 .C ORRS r0,r0,r1 - 0x00002ebc: 2140 @! MOVS r1,#0x40 - 0x00002ebe: 4308 .C ORRS r0,r0,r1 - 0x00002ec0: 1200 .. ASRS r0,r0,#8 - 0x00002ec2: 4989 .I LDR r1,[pc,#548] ; [0x30e8] = 0x10008060 - 0x00002ec4: 3920 9 SUBS r1,r1,#0x20 - 0x00002ec6: 7448 Ht STRB r0,[r1,#0x11] - 0x00002ec8: 4886 .H LDR r0,[pc,#536] ; [0x30e4] = 0x10004fe0 - 0x00002eca: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00002ecc: 2000 . MOVS r0,#0 - 0x00002ece: 7c09 .| LDRB r1,[r1,#0x10] - 0x00002ed0: 4300 .C ORRS r0,r0,r0 - 0x00002ed2: 4985 .I LDR r1,[pc,#532] ; [0x30e8] = 0x10008060 - 0x00002ed4: 3920 9 SUBS r1,r1,#0x20 - 0x00002ed6: 7c09 .| LDRB r1,[r1,#0x10] - 0x00002ed8: 4308 .C ORRS r0,r0,r1 - 0x00002eda: 4982 .I LDR r1,[pc,#520] ; [0x30e4] = 0x10004fe0 - 0x00002edc: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00002ede: 2100 .! MOVS r1,#0 - 0x00002ee0: 4a81 .J LDR r2,[pc,#516] ; [0x30e8] = 0x10008060 - 0x00002ee2: 3a20 : SUBS r2,r2,#0x20 - 0x00002ee4: 7c52 R| LDRB r2,[r2,#0x11] - 0x00002ee6: 4309 .C ORRS r1,r1,r1 - 0x00002ee8: 4a7f .J LDR r2,[pc,#508] ; [0x30e8] = 0x10008060 - 0x00002eea: 3a20 : SUBS r2,r2,#0x20 - 0x00002eec: 7c52 R| LDRB r2,[r2,#0x11] - 0x00002eee: 4311 .C ORRS r1,r1,r2 - 0x00002ef0: 0209 .. LSLS r1,r1,#8 - 0x00002ef2: 4308 .C ORRS r0,r0,r1 - 0x00002ef4: 2140 @! MOVS r1,#0x40 - 0x00002ef6: 4308 .C ORRS r0,r0,r1 - 0x00002ef8: 1200 .. ASRS r0,r0,#8 - 0x00002efa: 497b {I LDR r1,[pc,#492] ; [0x30e8] = 0x10008060 - 0x00002efc: 3920 9 SUBS r1,r1,#0x20 - 0x00002efe: 7448 Ht STRB r0,[r1,#0x11] - 0x00002f00: bf00 .. NOP - 0x00002f02: bf00 .. NOP - 0x00002f04: 4770 pG BX lr - Audio_ClosePaDelay - 0x00002f06: 4770 pG BX lr - Audio_AdacPrepareSoftMute - 0x00002f08: 4770 pG BX lr - Audio_DacClearRampDown - 0x00002f0a: b510 .. PUSH {r4,lr} - 0x00002f0c: bf00 .. NOP - 0x00002f0e: 4875 uH LDR r0,[pc,#468] ; [0x30e4] = 0x10004fe0 - 0x00002f10: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00002f12: 2000 . MOVS r0,#0 - 0x00002f14: 4974 tI LDR r1,[pc,#464] ; [0x30e8] = 0x10008060 - 0x00002f16: 31c0 .1 ADDS r1,r1,#0xc0 - 0x00002f18: 7e09 .~ LDRB r1,[r1,#0x18] - 0x00002f1a: 4300 .C ORRS r0,r0,r0 - 0x00002f1c: 4972 rI LDR r1,[pc,#456] ; [0x30e8] = 0x10008060 - 0x00002f1e: 31c0 .1 ADDS r1,r1,#0xc0 - 0x00002f20: 7e09 .~ LDRB r1,[r1,#0x18] - 0x00002f22: 4308 .C ORRS r0,r0,r1 - 0x00002f24: 2110 .! MOVS r1,#0x10 - 0x00002f26: 4308 .C ORRS r0,r0,r1 - 0x00002f28: 496f oI LDR r1,[pc,#444] ; [0x30e8] = 0x10008060 - 0x00002f2a: 31c0 .1 ADDS r1,r1,#0xc0 - 0x00002f2c: 7608 .v STRB r0,[r1,#0x18] - 0x00002f2e: 486d mH LDR r0,[pc,#436] ; [0x30e4] = 0x10004fe0 - 0x00002f30: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00002f32: 2000 . MOVS r0,#0 - 0x00002f34: 7e09 .~ LDRB r1,[r1,#0x18] - 0x00002f36: 4300 .C ORRS r0,r0,r0 - 0x00002f38: 496b kI LDR r1,[pc,#428] ; [0x30e8] = 0x10008060 - 0x00002f3a: 31c0 .1 ADDS r1,r1,#0xc0 - 0x00002f3c: 7e09 .~ LDRB r1,[r1,#0x18] - 0x00002f3e: 4308 .C ORRS r0,r0,r1 - 0x00002f40: 2110 .! MOVS r1,#0x10 - 0x00002f42: 4308 .C ORRS r0,r0,r1 - 0x00002f44: 4968 hI LDR r1,[pc,#416] ; [0x30e8] = 0x10008060 - 0x00002f46: 31c0 .1 ADDS r1,r1,#0xc0 - 0x00002f48: 7608 .v STRB r0,[r1,#0x18] - 0x00002f4a: bf00 .. NOP - 0x00002f4c: 2001 . MOVS r0,#1 - 0x00002f4e: f7fff907 .... BL SYS_delay_us ; 0x2160 - 0x00002f52: bf00 .. NOP - 0x00002f54: 4863 cH LDR r0,[pc,#396] ; [0x30e4] = 0x10004fe0 - 0x00002f56: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00002f58: 2000 . MOVS r0,#0 - 0x00002f5a: 4963 cI LDR r1,[pc,#396] ; [0x30e8] = 0x10008060 - 0x00002f5c: 31c0 .1 ADDS r1,r1,#0xc0 - 0x00002f5e: 7e09 .~ LDRB r1,[r1,#0x18] - 0x00002f60: 4300 .C ORRS r0,r0,r0 - 0x00002f62: 4961 aI LDR r1,[pc,#388] ; [0x30e8] = 0x10008060 - 0x00002f64: 31c0 .1 ADDS r1,r1,#0xc0 - 0x00002f66: 7e09 .~ LDRB r1,[r1,#0x18] - 0x00002f68: 4308 .C ORRS r0,r0,r1 - 0x00002f6a: 2110 .! MOVS r1,#0x10 - 0x00002f6c: 4388 .C BICS r0,r0,r1 - 0x00002f6e: 495e ^I LDR r1,[pc,#376] ; [0x30e8] = 0x10008060 - 0x00002f70: 31c0 .1 ADDS r1,r1,#0xc0 - 0x00002f72: 7608 .v STRB r0,[r1,#0x18] - 0x00002f74: 485b [H LDR r0,[pc,#364] ; [0x30e4] = 0x10004fe0 - 0x00002f76: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00002f78: 2000 . MOVS r0,#0 - 0x00002f7a: 7e09 .~ LDRB r1,[r1,#0x18] - 0x00002f7c: 4300 .C ORRS r0,r0,r0 - 0x00002f7e: 495a ZI LDR r1,[pc,#360] ; [0x30e8] = 0x10008060 - 0x00002f80: 31c0 .1 ADDS r1,r1,#0xc0 - 0x00002f82: 7e09 .~ LDRB r1,[r1,#0x18] - 0x00002f84: 4308 .C ORRS r0,r0,r1 - 0x00002f86: 2110 .! MOVS r1,#0x10 - 0x00002f88: 4388 .C BICS r0,r0,r1 - 0x00002f8a: 4957 WI LDR r1,[pc,#348] ; [0x30e8] = 0x10008060 - 0x00002f8c: 31c0 .1 ADDS r1,r1,#0xc0 - 0x00002f8e: 7608 .v STRB r0,[r1,#0x18] - 0x00002f90: bf00 .. NOP - 0x00002f92: bd10 .. POP {r4,pc} - Audio_DacWaitRampDown - 0x00002f94: b510 .. PUSH {r4,lr} - 0x00002f96: 2400 .$ MOVS r4,#0 - 0x00002f98: 4852 RH LDR r0,[pc,#328] ; [0x30e4] = 0x10004fe0 - 0x00002f9a: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00002f9c: 2000 . MOVS r0,#0 - 0x00002f9e: 4953 SI LDR r1,[pc,#332] ; [0x30ec] = 0x100043c0 - 0x00002fa0: 7a09 .z LDRB r1,[r1,#8] - 0x00002fa2: 4300 .C ORRS r0,r0,r0 - 0x00002fa4: 4951 QI LDR r1,[pc,#324] ; [0x30ec] = 0x100043c0 - 0x00002fa6: 7a09 .z LDRB r1,[r1,#8] - 0x00002fa8: 4308 .C ORRS r0,r0,r1 - 0x00002faa: 2810 .( CMP r0,#0x10 - 0x00002fac: dc09 .. BGT 0x2fc2 ; Audio_DacWaitRampDown + 46 - 0x00002fae: bf00 .. NOP - 0x00002fb0: 2002 . MOVS r0,#2 - 0x00002fb2: 494d MI LDR r1,[pc,#308] ; [0x30e8] = 0x10008060 - 0x00002fb4: 73c8 .s STRB r0,[r1,#0xf] - 0x00002fb6: 73c8 .s STRB r0,[r1,#0xf] - 0x00002fb8: bf00 .. NOP - 0x00002fba: bf00 .. NOP - 0x00002fbc: 7408 .t STRB r0,[r1,#0x10] - 0x00002fbe: 7408 .t STRB r0,[r1,#0x10] - 0x00002fc0: bf00 .. NOP - 0x00002fc2: e030 0. B 0x3026 ; Audio_DacWaitRampDown + 146 - 0x00002fc4: 2001 . MOVS r0,#1 - 0x00002fc6: f7fff8cb .... BL SYS_delay_us ; 0x2160 - 0x00002fca: 4620 F MOV r0,r4 - 0x00002fcc: 1c61 a. ADDS r1,r4,#1 - 0x00002fce: b28c .. UXTH r4,r1 - 0x00002fd0: 217d }! MOVS r1,#0x7d - 0x00002fd2: 0109 .. LSLS r1,r1,#4 - 0x00002fd4: 4288 .B CMP r0,r1 - 0x00002fd6: dd26 &. BLE 0x3026 ; Audio_DacWaitRampDown + 146 - 0x00002fd8: 4942 BI LDR r1,[pc,#264] ; [0x30e4] = 0x10004fe0 - 0x00002fda: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00002fdc: 2100 .! MOVS r1,#0 - 0x00002fde: 4a42 BJ LDR r2,[pc,#264] ; [0x30e8] = 0x10008060 - 0x00002fe0: 7bd2 .{ LDRB r2,[r2,#0xf] - 0x00002fe2: 4309 .C ORRS r1,r1,r1 - 0x00002fe4: 4a40 @J LDR r2,[pc,#256] ; [0x30e8] = 0x10008060 - 0x00002fe6: 7bd2 .{ LDRB r2,[r2,#0xf] - 0x00002fe8: 4311 .C ORRS r1,r1,r2 - 0x00002fea: 4608 .F MOV r0,r1 - 0x00002fec: 280f .( CMP r0,#0xf - 0x00002fee: da0a .. BGE 0x3006 ; Audio_DacWaitRampDown + 114 - 0x00002ff0: 1c41 A. ADDS r1,r0,#1 - 0x00002ff2: b2c8 .. UXTB r0,r1 - 0x00002ff4: bf00 .. NOP - 0x00002ff6: 493c . BL Audio_AnaAdcHighControlDisable ; 0x3184 - 0x00003308: bd10 .. POP {r4,pc} - Audio_AdcStop - 0x0000330a: b510 .. PUSH {r4,lr} - 0x0000330c: f7fffff7 .... BL Audio_AnaStopAdcWork ; 0x32fe - 0x00003310: 487c |H LDR r0,[pc,#496] ; [0x3504] = 0x10004fe0 - 0x00003312: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00003314: 2000 . MOVS r0,#0 - 0x00003316: 497a zI LDR r1,[pc,#488] ; [0x3500] = 0x10008040 - 0x00003318: 3120 1 ADDS r1,r1,#0x20 - 0x0000331a: 7949 Iy LDRB r1,[r1,#5] - 0x0000331c: 4300 .C ORRS r0,r0,r0 - 0x0000331e: 4978 xI LDR r1,[pc,#480] ; [0x3500] = 0x10008040 - 0x00003320: 3120 1 ADDS r1,r1,#0x20 - 0x00003322: 7949 Iy LDRB r1,[r1,#5] - 0x00003324: 4308 .C ORRS r0,r0,r1 - 0x00003326: 4604 .F MOV r4,r0 - 0x00003328: 20f0 . MOVS r0,#0xf0 - 0x0000332a: 4004 .@ ANDS r4,r4,r0 - 0x0000332c: bf00 .. NOP - 0x0000332e: 4874 tH LDR r0,[pc,#464] ; [0x3500] = 0x10008040 - 0x00003330: 3020 0 ADDS r0,r0,#0x20 - 0x00003332: 7144 Dq STRB r4,[r0,#5] - 0x00003334: 7144 Dq STRB r4,[r0,#5] - 0x00003336: bf00 .. NOP - 0x00003338: bf00 .. NOP - 0x0000333a: 2000 . MOVS r0,#0 - 0x0000333c: 4972 rI LDR r1,[pc,#456] ; [0x3508] = 0x10004380 - 0x0000333e: 7488 .t STRB r0,[r1,#0x12] - 0x00003340: 7488 .t STRB r0,[r1,#0x12] - 0x00003342: bf00 .. NOP - 0x00003344: bf00 .. NOP - 0x00003346: 4971 qI LDR r1,[pc,#452] ; [0x350c] = 0x10004a00 - 0x00003348: 75c8 .u STRB r0,[r1,#0x17] - 0x0000334a: 75c8 .u STRB r0,[r1,#0x17] - 0x0000334c: bf00 .. NOP - 0x0000334e: bf00 .. NOP - 0x00003350: 496b kI LDR r1,[pc,#428] ; [0x3500] = 0x10008040 - 0x00003352: 3920 9 SUBS r1,r1,#0x20 - 0x00003354: 7688 .v STRB r0,[r1,#0x1a] - 0x00003356: 7688 .v STRB r0,[r1,#0x1a] - 0x00003358: bf00 .. NOP - 0x0000335a: bf00 .. NOP - 0x0000335c: 76c8 .v STRB r0,[r1,#0x1b] - 0x0000335e: 76c8 .v STRB r0,[r1,#0x1b] - 0x00003360: bf00 .. NOP - 0x00003362: bd10 .. POP {r4,pc} - Audio_CvsdClkEnable - 0x00003364: bf00 .. NOP - 0x00003366: bf00 .. NOP - 0x00003368: 4866 fH LDR r0,[pc,#408] ; [0x3504] = 0x10004fe0 - 0x0000336a: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x0000336c: 2000 . MOVS r0,#0 - 0x0000336e: 4964 dI LDR r1,[pc,#400] ; [0x3500] = 0x10008040 - 0x00003370: 7c09 .| LDRB r1,[r1,#0x10] - 0x00003372: 4300 .C ORRS r0,r0,r0 - 0x00003374: 4962 bI LDR r1,[pc,#392] ; [0x3500] = 0x10008040 - 0x00003376: 7c09 .| LDRB r1,[r1,#0x10] - 0x00003378: 4308 .C ORRS r0,r0,r1 - 0x0000337a: 4962 bI LDR r1,[pc,#392] ; [0x3504] = 0x10004fe0 - 0x0000337c: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x0000337e: 4a60 `J LDR r2,[pc,#384] ; [0x3500] = 0x10008040 - 0x00003380: 7c52 R| LDRB r2,[r2,#0x11] - 0x00003382: 4311 .C ORRS r1,r1,r2 - 0x00003384: 4a5e ^J LDR r2,[pc,#376] ; [0x3500] = 0x10008040 - 0x00003386: 7c52 R| LDRB r2,[r2,#0x11] - 0x00003388: 4311 .C ORRS r1,r1,r2 - 0x0000338a: 0209 .. LSLS r1,r1,#8 - 0x0000338c: 4308 .C ORRS r0,r0,r1 - 0x0000338e: 2140 @! MOVS r1,#0x40 - 0x00003390: 4388 .C BICS r0,r0,r1 - 0x00003392: 495b [I LDR r1,[pc,#364] ; [0x3500] = 0x10008040 - 0x00003394: 7408 .t STRB r0,[r1,#0x10] - 0x00003396: 485b [H LDR r0,[pc,#364] ; [0x3504] = 0x10004fe0 - 0x00003398: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x0000339a: 2000 . MOVS r0,#0 - 0x0000339c: 7c09 .| LDRB r1,[r1,#0x10] - 0x0000339e: 4300 .C ORRS r0,r0,r0 - 0x000033a0: 4957 WI LDR r1,[pc,#348] ; [0x3500] = 0x10008040 - 0x000033a2: 7c09 .| LDRB r1,[r1,#0x10] - 0x000033a4: 4308 .C ORRS r0,r0,r1 - 0x000033a6: 4957 WI LDR r1,[pc,#348] ; [0x3504] = 0x10004fe0 - 0x000033a8: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x000033aa: 4a55 UJ LDR r2,[pc,#340] ; [0x3500] = 0x10008040 - 0x000033ac: 7c52 R| LDRB r2,[r2,#0x11] - 0x000033ae: 4311 .C ORRS r1,r1,r2 - 0x000033b0: 4a53 SJ LDR r2,[pc,#332] ; [0x3500] = 0x10008040 - 0x000033b2: 7c52 R| LDRB r2,[r2,#0x11] - 0x000033b4: 4311 .C ORRS r1,r1,r2 - 0x000033b6: 0209 .. LSLS r1,r1,#8 - 0x000033b8: 4308 .C ORRS r0,r0,r1 - 0x000033ba: 2140 @! MOVS r1,#0x40 - 0x000033bc: 4388 .C BICS r0,r0,r1 - 0x000033be: 4950 PI LDR r1,[pc,#320] ; [0x3500] = 0x10008040 - 0x000033c0: 7408 .t STRB r0,[r1,#0x10] - 0x000033c2: bf00 .. NOP - 0x000033c4: bf00 .. NOP - 0x000033c6: 484f OH LDR r0,[pc,#316] ; [0x3504] = 0x10004fe0 - 0x000033c8: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x000033ca: 2000 . MOVS r0,#0 - 0x000033cc: 7c09 .| LDRB r1,[r1,#0x10] - 0x000033ce: 4300 .C ORRS r0,r0,r0 - 0x000033d0: 494b KI LDR r1,[pc,#300] ; [0x3500] = 0x10008040 - 0x000033d2: 7c09 .| LDRB r1,[r1,#0x10] - 0x000033d4: 4308 .C ORRS r0,r0,r1 - 0x000033d6: 494b KI LDR r1,[pc,#300] ; [0x3504] = 0x10004fe0 - 0x000033d8: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x000033da: 2100 .! MOVS r1,#0 - 0x000033dc: 4a48 HJ LDR r2,[pc,#288] ; [0x3500] = 0x10008040 - 0x000033de: 7c52 R| LDRB r2,[r2,#0x11] - 0x000033e0: 4309 .C ORRS r1,r1,r1 - 0x000033e2: 4a47 GJ LDR r2,[pc,#284] ; [0x3500] = 0x10008040 - 0x000033e4: 7c52 R| LDRB r2,[r2,#0x11] - 0x000033e6: 4311 .C ORRS r1,r1,r2 - 0x000033e8: 0209 .. LSLS r1,r1,#8 - 0x000033ea: 4308 .C ORRS r0,r0,r1 - 0x000033ec: 2140 @! MOVS r1,#0x40 - 0x000033ee: 4388 .C BICS r0,r0,r1 - 0x000033f0: 1200 .. ASRS r0,r0,#8 - 0x000033f2: 4943 CI LDR r1,[pc,#268] ; [0x3500] = 0x10008040 - 0x000033f4: 7448 Ht STRB r0,[r1,#0x11] - 0x000033f6: 4843 CH LDR r0,[pc,#268] ; [0x3504] = 0x10004fe0 - 0x000033f8: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x000033fa: 2000 . MOVS r0,#0 - 0x000033fc: 7c09 .| LDRB r1,[r1,#0x10] - 0x000033fe: 4300 .C ORRS r0,r0,r0 - 0x00003400: 493f ?I LDR r1,[pc,#252] ; [0x3500] = 0x10008040 - 0x00003402: 7c09 .| LDRB r1,[r1,#0x10] - 0x00003404: 4308 .C ORRS r0,r0,r1 - 0x00003406: 493f ?I LDR r1,[pc,#252] ; [0x3504] = 0x10004fe0 - 0x00003408: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x0000340a: 2100 .! MOVS r1,#0 - 0x0000340c: 4a3c J LDR r2,[pc,#248] ; [0x4d94] = 0x10008100 - 0x00004c9a: 3220 2 ADDS r2,r2,#0x20 - 0x00004c9c: 78d2 .x LDRB r2,[r2,#3] - 0x00004c9e: 4311 .C ORRS r1,r1,r2 - 0x00004ca0: 0209 .. LSLS r1,r1,#8 - 0x00004ca2: 4308 .C ORRS r0,r0,r1 - 0x00004ca4: b204 .. SXTH r4,r0 - 0x00004ca6: 4840 @H LDR r0,[pc,#256] ; [0x4da8] = 0x10011022 - 0x00004ca8: 2500 .% MOVS r5,#0 - 0x00004caa: 5f45 E_ LDRSH r5,[r0,r5] - 0x00004cac: 4628 (F MOV r0,r5 - 0x00004cae: f7fefe90 .... BL Audio_AdacToolGetAdjustInterval ; 0x39d2 - 0x00004cb2: 4606 .F MOV r6,r0 - 0x00004cb4: e018 .. B 0x4ce8 ; Audio_AdacAdjustDCCaliToNormal + 118 - 0x00004cb6: 4632 2F MOV r2,r6 - 0x00004cb8: 4629 )F MOV r1,r5 - 0x00004cba: 4620 F MOV r0,r4 - 0x00004cbc: f7fefe79 ..y. BL Audio_AdacToolGetSrcToDstVal ; 0x39b2 - 0x00004cc0: 4604 .F MOV r4,r0 - 0x00004cc2: bf00 .. NOP - 0x00004cc4: bf00 .. NOP - 0x00004cc6: 4933 3I LDR r1,[pc,#204] ; [0x4d94] = 0x10008100 - 0x00004cc8: 3120 1 ADDS r1,r1,#0x20 - 0x00004cca: 708c .p STRB r4,[r1,#2] - 0x00004ccc: 708c .p STRB r4,[r1,#2] - 0x00004cce: bf00 .. NOP - 0x00004cd0: bf00 .. NOP - 0x00004cd2: 0420 . LSLS r0,r4,#16 - 0x00004cd4: 0e00 .. LSRS r0,r0,#24 - 0x00004cd6: 70c8 .p STRB r0,[r1,#3] - 0x00004cd8: 0420 . LSLS r0,r4,#16 - 0x00004cda: 0e00 .. LSRS r0,r0,#24 - 0x00004cdc: 70c8 .p STRB r0,[r1,#3] - 0x00004cde: bf00 .. NOP - 0x00004ce0: bf00 .. NOP - 0x00004ce2: 2001 . MOVS r0,#1 - 0x00004ce4: f7fdfa62 ..b. BL SYS_delay_ms ; 0x21ac - 0x00004ce8: 42ac .B CMP r4,r5 - 0x00004cea: d1e4 .. BNE 0x4cb6 ; Audio_AdacAdjustDCCaliToNormal + 68 - 0x00004cec: bd70 p. POP {r4-r6,pc} - Audio_AdacPreparePAClose - 0x00004cee: b510 .. PUSH {r4,lr} - 0x00004cf0: f7ffffbf .... BL Audio_AdacAdjustDCCaliToNormal ; 0x4c72 - 0x00004cf4: f7fff9da .... BL Audio_AdacAdjustDigitalVolToCali ; 0x40ac - 0x00004cf8: bd10 .. POP {r4,pc} - Audio_DacCheckDaAdacOpaEnable - 0x00004cfa: 4827 'H LDR r0,[pc,#156] ; [0x4d98] = 0x10004fe0 - 0x00004cfc: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00004cfe: 2000 . MOVS r0,#0 - 0x00004d00: 4a26 &J LDR r2,[pc,#152] ; [0x4d9c] = 0x10008a00 - 0x00004d02: 7a52 Rz LDRB r2,[r2,#9] - 0x00004d04: 4300 .C ORRS r0,r0,r0 - 0x00004d06: 4a25 %J LDR r2,[pc,#148] ; [0x4d9c] = 0x10008a00 - 0x00004d08: 7a52 Rz LDRB r2,[r2,#9] - 0x00004d0a: 4310 .C ORRS r0,r0,r2 - 0x00004d0c: 4601 .F MOV r1,r0 - 0x00004d0e: 4608 .F MOV r0,r1 - 0x00004d10: 2210 ." MOVS r2,#0x10 - 0x00004d12: 4010 .@ ANDS r0,r0,r2 - 0x00004d14: 2220 " MOVS r2,#0x20 - 0x00004d16: 400a .@ ANDS r2,r2,r1 - 0x00004d18: 4310 .C ORRS r0,r0,r2 - 0x00004d1a: 4770 pG BX lr - Audio_AdacStopPAWithPop - 0x00004d1c: b510 .. PUSH {r4,lr} - 0x00004d1e: f7ffffec .... BL Audio_DacCheckDaAdacOpaEnable ; 0x4cfa - 0x00004d22: 2800 .( CMP r0,#0 - 0x00004d24: d100 .. BNE 0x4d28 ; Audio_AdacStopPAWithPop + 12 - 0x00004d26: bd10 .. POP {r4,pc} - 0x00004d28: f7ffffe1 .... BL Audio_AdacPreparePAClose ; 0x4cee - 0x00004d2c: 2005 . MOVS r0,#5 - 0x00004d2e: f7fdfa3d ..=. BL SYS_delay_ms ; 0x21ac - 0x00004d32: f7ffff82 .... BL Audio_DacSetDaAdacOpaMainToDummy ; 0x4c3a - 0x00004d36: 2005 . MOVS r0,#5 - 0x00004d38: f7fdfa38 ..8. BL SYS_delay_ms ; 0x21ac - 0x00004d3c: f7ffff39 ..9. BL Audio_DacDisableDaAdacDepopSw ; 0x4bb2 - 0x00004d40: f7ffff1f .... BL Audio_DacDisableDaAdacPath ; 0x4b82 - 0x00004d44: f7ffff05 .... BL Audio_DacDisableDaAdacOpa ; 0x4b52 - 0x00004d48: f7fffeeb .... BL Audio_DacDisableDaAdacInt ; 0x4b22 - 0x00004d4c: bf00 .. NOP - 0x00004d4e: 4812 .H LDR r0,[pc,#72] ; [0x4d98] = 0x10004fe0 - 0x00004d50: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00004d52: 2000 . MOVS r0,#0 - 0x00004d54: 4911 .I LDR r1,[pc,#68] ; [0x4d9c] = 0x10008a00 - 0x00004d56: 7a49 Iz LDRB r1,[r1,#9] - 0x00004d58: 4300 .C ORRS r0,r0,r0 - 0x00004d5a: 4910 .I LDR r1,[pc,#64] ; [0x4d9c] = 0x10008a00 - 0x00004d5c: 7a49 Iz LDRB r1,[r1,#9] - 0x00004d5e: 4308 .C ORRS r0,r0,r1 - 0x00004d60: 2102 .! MOVS r1,#2 - 0x00004d62: 4388 .C BICS r0,r0,r1 - 0x00004d64: 490d .I LDR r1,[pc,#52] ; [0x4d9c] = 0x10008a00 - 0x00004d66: 7248 Hr STRB r0,[r1,#9] - 0x00004d68: 480b .H LDR r0,[pc,#44] ; [0x4d98] = 0x10004fe0 - 0x00004d6a: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00004d6c: 2000 . MOVS r0,#0 - 0x00004d6e: 7a49 Iz LDRB r1,[r1,#9] - 0x00004d70: 4300 .C ORRS r0,r0,r0 - 0x00004d72: 490a .I LDR r1,[pc,#40] ; [0x4d9c] = 0x10008a00 - 0x00004d74: 7a49 Iz LDRB r1,[r1,#9] - 0x00004d76: 4308 .C ORRS r0,r0,r1 - 0x00004d78: 2102 .! MOVS r1,#2 - 0x00004d7a: 4388 .C BICS r0,r0,r1 - 0x00004d7c: 4907 .I LDR r1,[pc,#28] ; [0x4d9c] = 0x10008a00 - 0x00004d7e: 7248 Hr STRB r0,[r1,#9] - 0x00004d80: bf00 .. NOP - 0x00004d82: bf00 .. NOP - 0x00004d84: 4804 .H LDR r0,[pc,#16] ; [0x4d98] = 0x10004fe0 - 0x00004d86: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00004d88: 2000 . MOVS r0,#0 - 0x00004d8a: 7a09 .z LDRB r1,[r1,#8] - 0x00004d8c: 4300 .C ORRS r0,r0,r0 - 0x00004d8e: 4903 .I LDR r1,[pc,#12] ; [0x4d9c] = 0x10008a00 - 0x00004d90: 7a09 .z LDRB r1,[r1,#8] - 0x00004d92: e00b .. B 0x4dac ; Audio_AdacStopPAWithPop + 144 - $d - 0x00004d94: 10008100 .... DCD 268468480 - 0x00004d98: 10004fe0 .O.. DCD 268455904 - 0x00004d9c: 10008a00 .... DCD 268470784 - 0x00004da0: 10004ea0 .N.. DCD 268455584 - 0x00004da4: 100042c0 .B.. DCD 268452544 - 0x00004da8: 10011022 "... DCD 268505122 - $t - 0x00004dac: 4308 .C ORRS r0,r0,r1 - 0x00004dae: 2180 .! MOVS r1,#0x80 - 0x00004db0: 4388 .C BICS r0,r0,r1 - 0x00004db2: 49fe .I LDR r1,[pc,#1016] ; [0x51ac] = 0x10008a00 - 0x00004db4: 7208 .r STRB r0,[r1,#8] - 0x00004db6: 48fe .H LDR r0,[pc,#1016] ; [0x51b0] = 0x10004fe0 - 0x00004db8: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00004dba: 2000 . MOVS r0,#0 - 0x00004dbc: 7a09 .z LDRB r1,[r1,#8] - 0x00004dbe: 4300 .C ORRS r0,r0,r0 - 0x00004dc0: 49fa .I LDR r1,[pc,#1000] ; [0x51ac] = 0x10008a00 - 0x00004dc2: 7a09 .z LDRB r1,[r1,#8] - 0x00004dc4: 4308 .C ORRS r0,r0,r1 - 0x00004dc6: 2180 .! MOVS r1,#0x80 - 0x00004dc8: 4388 .C BICS r0,r0,r1 - 0x00004dca: 49f8 .I LDR r1,[pc,#992] ; [0x51ac] = 0x10008a00 - 0x00004dcc: 7208 .r STRB r0,[r1,#8] - 0x00004dce: bf00 .. NOP - 0x00004dd0: bf00 .. NOP - 0x00004dd2: 48f7 .H LDR r0,[pc,#988] ; [0x51b0] = 0x10004fe0 - 0x00004dd4: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00004dd6: 2000 . MOVS r0,#0 - 0x00004dd8: 7a09 .z LDRB r1,[r1,#8] - 0x00004dda: 4300 .C ORRS r0,r0,r0 - 0x00004ddc: 49f3 .I LDR r1,[pc,#972] ; [0x51ac] = 0x10008a00 - 0x00004dde: 7a09 .z LDRB r1,[r1,#8] - 0x00004de0: 4308 .C ORRS r0,r0,r1 - 0x00004de2: 2120 ! MOVS r1,#0x20 - 0x00004de4: 4388 .C BICS r0,r0,r1 - 0x00004de6: 49f1 .I LDR r1,[pc,#964] ; [0x51ac] = 0x10008a00 - 0x00004de8: 7208 .r STRB r0,[r1,#8] - 0x00004dea: 48f1 .H LDR r0,[pc,#964] ; [0x51b0] = 0x10004fe0 - 0x00004dec: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00004dee: 2000 . MOVS r0,#0 - 0x00004df0: 7a09 .z LDRB r1,[r1,#8] - 0x00004df2: 4300 .C ORRS r0,r0,r0 - 0x00004df4: 49ed .I LDR r1,[pc,#948] ; [0x51ac] = 0x10008a00 - 0x00004df6: 7a09 .z LDRB r1,[r1,#8] - 0x00004df8: 4308 .C ORRS r0,r0,r1 - 0x00004dfa: 2120 ! MOVS r1,#0x20 - 0x00004dfc: 4388 .C BICS r0,r0,r1 - 0x00004dfe: 49eb .I LDR r1,[pc,#940] ; [0x51ac] = 0x10008a00 - 0x00004e00: 7208 .r STRB r0,[r1,#8] - 0x00004e02: bf00 .. NOP - 0x00004e04: bf00 .. NOP - 0x00004e06: 48ea .H LDR r0,[pc,#936] ; [0x51b0] = 0x10004fe0 - 0x00004e08: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00004e0a: 2000 . MOVS r0,#0 - 0x00004e0c: 7a49 Iz LDRB r1,[r1,#9] - 0x00004e0e: 4300 .C ORRS r0,r0,r0 - 0x00004e10: 49e6 .I LDR r1,[pc,#920] ; [0x51ac] = 0x10008a00 - 0x00004e12: 7a49 Iz LDRB r1,[r1,#9] - 0x00004e14: 4308 .C ORRS r0,r0,r1 - 0x00004e16: 0840 @. LSRS r0,r0,#1 - 0x00004e18: 0040 @. LSLS r0,r0,#1 - 0x00004e1a: 49e4 .I LDR r1,[pc,#912] ; [0x51ac] = 0x10008a00 - 0x00004e1c: 7248 Hr STRB r0,[r1,#9] - 0x00004e1e: 48e4 .H LDR r0,[pc,#912] ; [0x51b0] = 0x10004fe0 - 0x00004e20: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00004e22: 2000 . MOVS r0,#0 - 0x00004e24: 7a49 Iz LDRB r1,[r1,#9] - 0x00004e26: 4300 .C ORRS r0,r0,r0 - 0x00004e28: 49e0 .I LDR r1,[pc,#896] ; [0x51ac] = 0x10008a00 - 0x00004e2a: 7a49 Iz LDRB r1,[r1,#9] - 0x00004e2c: 4308 .C ORRS r0,r0,r1 - 0x00004e2e: 0840 @. LSRS r0,r0,#1 - 0x00004e30: 0040 @. LSLS r0,r0,#1 - 0x00004e32: 49de .I LDR r1,[pc,#888] ; [0x51ac] = 0x10008a00 - 0x00004e34: 7248 Hr STRB r0,[r1,#9] - 0x00004e36: bf00 .. NOP - 0x00004e38: f7fff85a ..Z. BL Audio_DacSetDaAdacRstInt ; 0x3ef0 - 0x00004e3c: f7fffe5d ..]. BL Audio_DacDisableDaAdacOpaDummy ; 0x4afa - 0x00004e40: f7fffe26 ..&. BL Audio_DaAaddaBgDisable ; 0x4a90 - 0x00004e44: bf00 .. NOP - 0x00004e46: bf00 .. NOP - 0x00004e48: 2000 . MOVS r0,#0 - 0x00004e4a: 49da .I LDR r1,[pc,#872] ; [0x51b4] = 0x10008100 - 0x00004e4c: 7788 .w STRB r0,[r1,#0x1e] - 0x00004e4e: 7788 .w STRB r0,[r1,#0x1e] - 0x00004e50: bf00 .. NOP - 0x00004e52: bf00 .. NOP - 0x00004e54: 77c8 .w STRB r0,[r1,#0x1f] - 0x00004e56: 77c8 .w STRB r0,[r1,#0x1f] - 0x00004e58: bf00 .. NOP - 0x00004e5a: bf00 .. NOP - 0x00004e5c: bf00 .. NOP - 0x00004e5e: bf00 .. NOP - 0x00004e60: 7188 .q STRB r0,[r1,#6] - 0x00004e62: 7188 .q STRB r0,[r1,#6] - 0x00004e64: bf00 .. NOP - 0x00004e66: bf00 .. NOP - 0x00004e68: 71c8 .q STRB r0,[r1,#7] - 0x00004e6a: 71c8 .q STRB r0,[r1,#7] - 0x00004e6c: bf00 .. NOP - 0x00004e6e: bf00 .. NOP - 0x00004e70: bf00 .. NOP - 0x00004e72: bf00 .. NOP - 0x00004e74: 48ce .H LDR r0,[pc,#824] ; [0x51b0] = 0x10004fe0 - 0x00004e76: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00004e78: 2000 . MOVS r0,#0 - 0x00004e7a: 49ce .I LDR r1,[pc,#824] ; [0x51b4] = 0x10008100 - 0x00004e7c: 39c0 .9 SUBS r1,r1,#0xc0 - 0x00004e7e: 7c09 .| LDRB r1,[r1,#0x10] - 0x00004e80: 4300 .C ORRS r0,r0,r0 - 0x00004e82: 49cc .I LDR r1,[pc,#816] ; [0x51b4] = 0x10008100 - 0x00004e84: 39c0 .9 SUBS r1,r1,#0xc0 - 0x00004e86: 7c09 .| LDRB r1,[r1,#0x10] - 0x00004e88: 4308 .C ORRS r0,r0,r1 - 0x00004e8a: 49c9 .I LDR r1,[pc,#804] ; [0x51b0] = 0x10004fe0 - 0x00004e8c: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00004e8e: 4ac9 .J LDR r2,[pc,#804] ; [0x51b4] = 0x10008100 - 0x00004e90: 3ac0 .: SUBS r2,r2,#0xc0 - 0x00004e92: 7c52 R| LDRB r2,[r2,#0x11] - 0x00004e94: 4311 .C ORRS r1,r1,r2 - 0x00004e96: 4ac7 .J LDR r2,[pc,#796] ; [0x51b4] = 0x10008100 - 0x00004e98: 3ac0 .: SUBS r2,r2,#0xc0 - 0x00004e9a: 7c52 R| LDRB r2,[r2,#0x11] - 0x00004e9c: 4311 .C ORRS r1,r1,r2 - 0x00004e9e: 0209 .. LSLS r1,r1,#8 - 0x00004ea0: 4308 .C ORRS r0,r0,r1 - 0x00004ea2: 2120 ! MOVS r1,#0x20 - 0x00004ea4: 4308 .C ORRS r0,r0,r1 - 0x00004ea6: 49c3 .I LDR r1,[pc,#780] ; [0x51b4] = 0x10008100 - 0x00004ea8: 39c0 .9 SUBS r1,r1,#0xc0 - 0x00004eaa: 7408 .t STRB r0,[r1,#0x10] - 0x00004eac: 48c0 .H LDR r0,[pc,#768] ; [0x51b0] = 0x10004fe0 - 0x00004eae: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00004eb0: 2000 . MOVS r0,#0 - 0x00004eb2: 7c09 .| LDRB r1,[r1,#0x10] - 0x00004eb4: 4300 .C ORRS r0,r0,r0 - 0x00004eb6: 49bf .I LDR r1,[pc,#764] ; [0x51b4] = 0x10008100 - 0x00004eb8: 39c0 .9 SUBS r1,r1,#0xc0 - 0x00004eba: 7c09 .| LDRB r1,[r1,#0x10] - 0x00004ebc: 4308 .C ORRS r0,r0,r1 - 0x00004ebe: 49bc .I LDR r1,[pc,#752] ; [0x51b0] = 0x10004fe0 - 0x00004ec0: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00004ec2: 4abc .J LDR r2,[pc,#752] ; [0x51b4] = 0x10008100 - 0x00004ec4: 3ac0 .: SUBS r2,r2,#0xc0 - 0x00004ec6: 7c52 R| LDRB r2,[r2,#0x11] - 0x00004ec8: 4311 .C ORRS r1,r1,r2 - 0x00004eca: 4aba .J LDR r2,[pc,#744] ; [0x51b4] = 0x10008100 - 0x00004ecc: 3ac0 .: SUBS r2,r2,#0xc0 - 0x00004ece: 7c52 R| LDRB r2,[r2,#0x11] - 0x00004ed0: 4311 .C ORRS r1,r1,r2 - 0x00004ed2: 0209 .. LSLS r1,r1,#8 - 0x00004ed4: 4308 .C ORRS r0,r0,r1 - 0x00004ed6: 2120 ! MOVS r1,#0x20 - 0x00004ed8: 4308 .C ORRS r0,r0,r1 - 0x00004eda: 49b6 .I LDR r1,[pc,#728] ; [0x51b4] = 0x10008100 - 0x00004edc: 39c0 .9 SUBS r1,r1,#0xc0 - 0x00004ede: 7408 .t STRB r0,[r1,#0x10] - 0x00004ee0: bf00 .. NOP - 0x00004ee2: bf00 .. NOP - 0x00004ee4: 48b2 .H LDR r0,[pc,#712] ; [0x51b0] = 0x10004fe0 - 0x00004ee6: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00004ee8: 2000 . MOVS r0,#0 - 0x00004eea: 7c09 .| LDRB r1,[r1,#0x10] - 0x00004eec: 4300 .C ORRS r0,r0,r0 - 0x00004eee: 49b1 .I LDR r1,[pc,#708] ; [0x51b4] = 0x10008100 - 0x00004ef0: 39c0 .9 SUBS r1,r1,#0xc0 - 0x00004ef2: 7c09 .| LDRB r1,[r1,#0x10] - 0x00004ef4: 4308 .C ORRS r0,r0,r1 - 0x00004ef6: 49ae .I LDR r1,[pc,#696] ; [0x51b0] = 0x10004fe0 - 0x00004ef8: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00004efa: 2100 .! MOVS r1,#0 - 0x00004efc: 4aad .J LDR r2,[pc,#692] ; [0x51b4] = 0x10008100 - 0x00004efe: 3ac0 .: SUBS r2,r2,#0xc0 - 0x00004f00: 7c52 R| LDRB r2,[r2,#0x11] - 0x00004f02: 4309 .C ORRS r1,r1,r1 - 0x00004f04: 4aab .J LDR r2,[pc,#684] ; [0x51b4] = 0x10008100 - 0x00004f06: 3ac0 .: SUBS r2,r2,#0xc0 - 0x00004f08: 7c52 R| LDRB r2,[r2,#0x11] - 0x00004f0a: 4311 .C ORRS r1,r1,r2 - 0x00004f0c: 0209 .. LSLS r1,r1,#8 - 0x00004f0e: 4308 .C ORRS r0,r0,r1 - 0x00004f10: 2120 ! MOVS r1,#0x20 - 0x00004f12: 4308 .C ORRS r0,r0,r1 - 0x00004f14: 1200 .. ASRS r0,r0,#8 - 0x00004f16: 49a7 .I LDR r1,[pc,#668] ; [0x51b4] = 0x10008100 - 0x00004f18: 39c0 .9 SUBS r1,r1,#0xc0 - 0x00004f1a: 7448 Ht STRB r0,[r1,#0x11] - 0x00004f1c: 48a4 .H LDR r0,[pc,#656] ; [0x51b0] = 0x10004fe0 - 0x00004f1e: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00004f20: 2000 . MOVS r0,#0 - 0x00004f22: 7c09 .| LDRB r1,[r1,#0x10] - 0x00004f24: 4300 .C ORRS r0,r0,r0 - 0x00004f26: 49a3 .I LDR r1,[pc,#652] ; [0x51b4] = 0x10008100 - 0x00004f28: 39c0 .9 SUBS r1,r1,#0xc0 - 0x00004f2a: 7c09 .| LDRB r1,[r1,#0x10] - 0x00004f2c: 4308 .C ORRS r0,r0,r1 - 0x00004f2e: 49a0 .I LDR r1,[pc,#640] ; [0x51b0] = 0x10004fe0 - 0x00004f30: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00004f32: 2100 .! MOVS r1,#0 - 0x00004f34: 4a9f .J LDR r2,[pc,#636] ; [0x51b4] = 0x10008100 - 0x00004f36: 3ac0 .: SUBS r2,r2,#0xc0 - 0x00004f38: 7c52 R| LDRB r2,[r2,#0x11] - 0x00004f3a: 4309 .C ORRS r1,r1,r1 - 0x00004f3c: 4a9d .J LDR r2,[pc,#628] ; [0x51b4] = 0x10008100 - 0x00004f3e: 3ac0 .: SUBS r2,r2,#0xc0 - 0x00004f40: 7c52 R| LDRB r2,[r2,#0x11] - 0x00004f42: 4311 .C ORRS r1,r1,r2 - 0x00004f44: 0209 .. LSLS r1,r1,#8 - 0x00004f46: 4308 .C ORRS r0,r0,r1 - 0x00004f48: 2120 ! MOVS r1,#0x20 - 0x00004f4a: 4308 .C ORRS r0,r0,r1 - 0x00004f4c: 1200 .. ASRS r0,r0,#8 - 0x00004f4e: 4999 .I LDR r1,[pc,#612] ; [0x51b4] = 0x10008100 - 0x00004f50: 39c0 .9 SUBS r1,r1,#0xc0 - 0x00004f52: 7448 Ht STRB r0,[r1,#0x11] - 0x00004f54: bf00 .. NOP - 0x00004f56: bf00 .. NOP - 0x00004f58: bf00 .. NOP - 0x00004f5a: bf00 .. NOP - 0x00004f5c: 4894 .H LDR r0,[pc,#592] ; [0x51b0] = 0x10004fe0 - 0x00004f5e: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00004f60: 2000 . MOVS r0,#0 - 0x00004f62: 7c09 .| LDRB r1,[r1,#0x10] - 0x00004f64: 4300 .C ORRS r0,r0,r0 - 0x00004f66: 4993 .I LDR r1,[pc,#588] ; [0x51b4] = 0x10008100 - 0x00004f68: 39c0 .9 SUBS r1,r1,#0xc0 - 0x00004f6a: 7c09 .| LDRB r1,[r1,#0x10] - 0x00004f6c: 4308 .C ORRS r0,r0,r1 - 0x00004f6e: 4990 .I LDR r1,[pc,#576] ; [0x51b0] = 0x10004fe0 - 0x00004f70: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00004f72: 4a90 .J LDR r2,[pc,#576] ; [0x51b4] = 0x10008100 - 0x00004f74: 3ac0 .: SUBS r2,r2,#0xc0 - 0x00004f76: 7c52 R| LDRB r2,[r2,#0x11] - 0x00004f78: 4311 .C ORRS r1,r1,r2 - 0x00004f7a: 4a8e .J LDR r2,[pc,#568] ; [0x51b4] = 0x10008100 - 0x00004f7c: 3ac0 .: SUBS r2,r2,#0xc0 - 0x00004f7e: 7c52 R| LDRB r2,[r2,#0x11] - 0x00004f80: 4311 .C ORRS r1,r1,r2 - 0x00004f82: 0209 .. LSLS r1,r1,#8 - 0x00004f84: 4308 .C ORRS r0,r0,r1 - 0x00004f86: 2140 @! MOVS r1,#0x40 - 0x00004f88: 4308 .C ORRS r0,r0,r1 - 0x00004f8a: 498a .I LDR r1,[pc,#552] ; [0x51b4] = 0x10008100 - 0x00004f8c: 39c0 .9 SUBS r1,r1,#0xc0 - 0x00004f8e: 7408 .t STRB r0,[r1,#0x10] - 0x00004f90: 4887 .H LDR r0,[pc,#540] ; [0x51b0] = 0x10004fe0 - 0x00004f92: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00004f94: 2000 . MOVS r0,#0 - 0x00004f96: 7c09 .| LDRB r1,[r1,#0x10] - 0x00004f98: 4300 .C ORRS r0,r0,r0 - 0x00004f9a: 4986 .I LDR r1,[pc,#536] ; [0x51b4] = 0x10008100 - 0x00004f9c: 39c0 .9 SUBS r1,r1,#0xc0 - 0x00004f9e: 7c09 .| LDRB r1,[r1,#0x10] - 0x00004fa0: 4308 .C ORRS r0,r0,r1 - 0x00004fa2: 4983 .I LDR r1,[pc,#524] ; [0x51b0] = 0x10004fe0 - 0x00004fa4: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00004fa6: 4a83 .J LDR r2,[pc,#524] ; [0x51b4] = 0x10008100 - 0x00004fa8: 3ac0 .: SUBS r2,r2,#0xc0 - 0x00004faa: 7c52 R| LDRB r2,[r2,#0x11] - 0x00004fac: 4311 .C ORRS r1,r1,r2 - 0x00004fae: 4a81 .J LDR r2,[pc,#516] ; [0x51b4] = 0x10008100 - 0x00004fb0: 3ac0 .: SUBS r2,r2,#0xc0 - 0x00004fb2: 7c52 R| LDRB r2,[r2,#0x11] - 0x00004fb4: 4311 .C ORRS r1,r1,r2 - 0x00004fb6: 0209 .. LSLS r1,r1,#8 - 0x00004fb8: 4308 .C ORRS r0,r0,r1 - 0x00004fba: 2140 @! MOVS r1,#0x40 - 0x00004fbc: 4308 .C ORRS r0,r0,r1 - 0x00004fbe: 497d }I LDR r1,[pc,#500] ; [0x51b4] = 0x10008100 - 0x00004fc0: 39c0 .9 SUBS r1,r1,#0xc0 - 0x00004fc2: 7408 .t STRB r0,[r1,#0x10] - 0x00004fc4: bf00 .. NOP - 0x00004fc6: bf00 .. NOP - 0x00004fc8: 4879 yH LDR r0,[pc,#484] ; [0x51b0] = 0x10004fe0 - 0x00004fca: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00004fcc: 2000 . MOVS r0,#0 - 0x00004fce: 7c09 .| LDRB r1,[r1,#0x10] - 0x00004fd0: 4300 .C ORRS r0,r0,r0 - 0x00004fd2: 4978 xI LDR r1,[pc,#480] ; [0x51b4] = 0x10008100 - 0x00004fd4: 39c0 .9 SUBS r1,r1,#0xc0 - 0x00004fd6: 7c09 .| LDRB r1,[r1,#0x10] - 0x00004fd8: 4308 .C ORRS r0,r0,r1 - 0x00004fda: 4975 uI LDR r1,[pc,#468] ; [0x51b0] = 0x10004fe0 - 0x00004fdc: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00004fde: 2100 .! MOVS r1,#0 - 0x00004fe0: 4a74 tJ LDR r2,[pc,#464] ; [0x51b4] = 0x10008100 - 0x00004fe2: 3ac0 .: SUBS r2,r2,#0xc0 - 0x00004fe4: 7c52 R| LDRB r2,[r2,#0x11] - 0x00004fe6: 4309 .C ORRS r1,r1,r1 - 0x00004fe8: 4a72 rJ LDR r2,[pc,#456] ; [0x51b4] = 0x10008100 - 0x00004fea: 3ac0 .: SUBS r2,r2,#0xc0 - 0x00004fec: 7c52 R| LDRB r2,[r2,#0x11] - 0x00004fee: 4311 .C ORRS r1,r1,r2 - 0x00004ff0: 0209 .. LSLS r1,r1,#8 - 0x00004ff2: 4308 .C ORRS r0,r0,r1 - 0x00004ff4: 2140 @! MOVS r1,#0x40 - 0x00004ff6: 4308 .C ORRS r0,r0,r1 - 0x00004ff8: 1200 .. ASRS r0,r0,#8 - 0x00004ffa: 496e nI LDR r1,[pc,#440] ; [0x51b4] = 0x10008100 - 0x00004ffc: 39c0 .9 SUBS r1,r1,#0xc0 - 0x00004ffe: 7448 Ht STRB r0,[r1,#0x11] - 0x00005000: 486b kH LDR r0,[pc,#428] ; [0x51b0] = 0x10004fe0 - 0x00005002: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00005004: 2000 . MOVS r0,#0 - 0x00005006: 7c09 .| LDRB r1,[r1,#0x10] - 0x00005008: 4300 .C ORRS r0,r0,r0 - 0x0000500a: 496a jI LDR r1,[pc,#424] ; [0x51b4] = 0x10008100 - 0x0000500c: 39c0 .9 SUBS r1,r1,#0xc0 - 0x0000500e: 7c09 .| LDRB r1,[r1,#0x10] - 0x00005010: 4308 .C ORRS r0,r0,r1 - 0x00005012: 4967 gI LDR r1,[pc,#412] ; [0x51b0] = 0x10004fe0 - 0x00005014: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00005016: 2100 .! MOVS r1,#0 - 0x00005018: 4a66 fJ LDR r2,[pc,#408] ; [0x51b4] = 0x10008100 - 0x0000501a: 3ac0 .: SUBS r2,r2,#0xc0 - 0x0000501c: 7c52 R| LDRB r2,[r2,#0x11] - 0x0000501e: 4309 .C ORRS r1,r1,r1 - 0x00005020: 4a64 dJ LDR r2,[pc,#400] ; [0x51b4] = 0x10008100 - 0x00005022: 3ac0 .: SUBS r2,r2,#0xc0 - 0x00005024: 7c52 R| LDRB r2,[r2,#0x11] - 0x00005026: 4311 .C ORRS r1,r1,r2 - 0x00005028: 0209 .. LSLS r1,r1,#8 - 0x0000502a: 4308 .C ORRS r0,r0,r1 - 0x0000502c: 2140 @! MOVS r1,#0x40 - 0x0000502e: 4308 .C ORRS r0,r0,r1 - 0x00005030: 1200 .. ASRS r0,r0,#8 - 0x00005032: 4960 `I LDR r1,[pc,#384] ; [0x51b4] = 0x10008100 - 0x00005034: 39c0 .9 SUBS r1,r1,#0xc0 - 0x00005036: 7448 Ht STRB r0,[r1,#0x11] - 0x00005038: bf00 .. NOP - 0x0000503a: bf00 .. NOP - 0x0000503c: bf00 .. NOP - 0x0000503e: e672 r. B 0x4d26 ; Audio_AdacStopPAWithPop + 10 - Audio_AdacCheckLastDacClkSame - 0x00005040: 4601 .F MOV r1,r0 - 0x00005042: 485d ]H LDR r0,[pc,#372] ; [0x51b8] = 0x10011028 - 0x00005044: 7800 .x LDRB r0,[r0,#0] - 0x00005046: 4288 .B CMP r0,r1 - 0x00005048: d101 .. BNE 0x504e ; Audio_AdacCheckLastDacClkSame + 14 - 0x0000504a: 2001 . MOVS r0,#1 - 0x0000504c: 4770 pG BX lr - 0x0000504e: 2000 . MOVS r0,#0 - 0x00005050: e7fc .. B 0x504c ; Audio_AdacCheckLastDacClkSame + 12 - Audio_DacInit - 0x00005052: b5ff .. PUSH {r0-r7,lr} - 0x00005054: b083 .. SUB sp,sp,#0xc - 0x00005056: 460f .F MOV r7,r1 - 0x00005058: 461d .F MOV r5,r3 - 0x0000505a: 9e0e .. LDR r6,[sp,#0x38] - 0x0000505c: 9c0d .. LDR r4,[sp,#0x34] - 0x0000505e: 2000 . MOVS r0,#0 - 0x00005060: 9002 .. STR r0,[sp,#8] - 0x00005062: 4853 SH LDR r0,[pc,#332] ; [0x51b0] = 0x10004fe0 - 0x00005064: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00005066: 2000 . MOVS r0,#0 - 0x00005068: 4952 RI LDR r1,[pc,#328] ; [0x51b4] = 0x10008100 - 0x0000506a: 7989 .y LDRB r1,[r1,#6] - 0x0000506c: 4300 .C ORRS r0,r0,r0 - 0x0000506e: 4951 QI LDR r1,[pc,#324] ; [0x51b4] = 0x10008100 - 0x00005070: 7989 .y LDRB r1,[r1,#6] - 0x00005072: 4308 .C ORRS r0,r0,r1 - 0x00005074: 9001 .. STR r0,[sp,#4] - 0x00005076: 9801 .. LDR r0,[sp,#4] - 0x00005078: 07c0 .. LSLS r0,r0,#31 - 0x0000507a: 0fc0 .. LSRS r0,r0,#31 - 0x0000507c: 2800 .( CMP r0,#0 - 0x0000507e: d001 .. BEQ 0x5084 ; Audio_DacInit + 50 - 0x00005080: b007 .. ADD sp,sp,#0x1c - 0x00005082: bdf0 .. POP {r4-r7,pc} - 0x00005084: bf00 .. NOP - 0x00005086: 484d MH LDR r0,[pc,#308] ; [0x51bc] = 0x10004ac0 - 0x00005088: 7445 Et STRB r5,[r0,#0x11] - 0x0000508a: 7445 Et STRB r5,[r0,#0x11] - 0x0000508c: bf00 .. NOP - 0x0000508e: f7fffe34 ..4. BL Audio_DacCheckDaAdacOpaEnable ; 0x4cfa - 0x00005092: 2800 .( CMP r0,#0 - 0x00005094: d00c .. BEQ 0x50b0 ; Audio_DacInit + 94 - 0x00005096: 4628 (F MOV r0,r5 - 0x00005098: f7ffffd2 .... BL Audio_AdacCheckLastDacClkSame ; 0x5040 - 0x0000509c: 2800 .( CMP r0,#0 - 0x0000509e: d109 .. BNE 0x50b4 ; Audio_DacInit + 98 - 0x000050a0: f7fffe3c ..<. BL Audio_AdacStopPAWithPop ; 0x4d1c - 0x000050a4: 2005 . MOVS r0,#5 - 0x000050a6: f7fdf881 .... BL SYS_delay_ms ; 0x21ac - 0x000050aa: 2001 . MOVS r0,#1 - 0x000050ac: 9002 .. STR r0,[sp,#8] - 0x000050ae: e001 .. B 0x50b4 ; Audio_DacInit + 98 - 0x000050b0: 2001 . MOVS r0,#1 - 0x000050b2: 9002 .. STR r0,[sp,#8] - 0x000050b4: 9802 .. LDR r0,[sp,#8] - 0x000050b6: 2800 .( CMP r0,#0 - 0x000050b8: d005 .. BEQ 0x50c6 ; Audio_DacInit + 116 - 0x000050ba: 4628 (F MOV r0,r5 - 0x000050bc: f7fffc75 ..u. BL Audio_AdacStartPAWithPop ; 0x49aa - 0x000050c0: 2005 . MOVS r0,#5 - 0x000050c2: f7fdf873 ..s. BL SYS_delay_ms ; 0x21ac - 0x000050c6: f7fefd02 .... BL Audio_AdacPrepareReadyWork ; 0x3ace - 0x000050ca: f7fdff1e .... BL Audio_DacClearRampDown ; 0x2f0a - 0x000050ce: 4638 8F MOV r0,r7 - 0x000050d0: f7fefc51 ..Q. BL Audio_DacSetL ; 0x3976 - 0x000050d4: 9805 .. LDR r0,[sp,#0x14] - 0x000050d6: f7fefc03 .... BL Audio_DacSetR ; 0x38e0 - 0x000050da: 9803 .. LDR r0,[sp,#0xc] - 0x000050dc: f7fefbd5 .... BL Audio_DacMonoStero ; 0x388a - 0x000050e0: 980c .. LDR r0,[sp,#0x30] - 0x000050e2: 2800 .( CMP r0,#0 - 0x000050e4: d01a .. BEQ 0x511c ; Audio_DacInit + 202 - 0x000050e6: bf00 .. NOP - 0x000050e8: 4831 1H LDR r0,[pc,#196] ; [0x51b0] = 0x10004fe0 - 0x000050ea: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x000050ec: 2000 . MOVS r0,#0 - 0x000050ee: 4931 1I LDR r1,[pc,#196] ; [0x51b4] = 0x10008100 - 0x000050f0: 7989 .y LDRB r1,[r1,#6] - 0x000050f2: 4300 .C ORRS r0,r0,r0 - 0x000050f4: 492f /I LDR r1,[pc,#188] ; [0x51b4] = 0x10008100 - 0x000050f6: 7989 .y LDRB r1,[r1,#6] - 0x000050f8: 4308 .C ORRS r0,r0,r1 - 0x000050fa: 2102 .! MOVS r1,#2 - 0x000050fc: 4308 .C ORRS r0,r0,r1 - 0x000050fe: 492d -I LDR r1,[pc,#180] ; [0x51b4] = 0x10008100 - 0x00005100: 7188 .q STRB r0,[r1,#6] - 0x00005102: 482b +H LDR r0,[pc,#172] ; [0x51b0] = 0x10004fe0 - 0x00005104: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00005106: 2000 . MOVS r0,#0 - 0x00005108: 7989 .y LDRB r1,[r1,#6] - 0x0000510a: 4300 .C ORRS r0,r0,r0 - 0x0000510c: 4929 )I LDR r1,[pc,#164] ; [0x51b4] = 0x10008100 - 0x0000510e: 7989 .y LDRB r1,[r1,#6] - 0x00005110: 4308 .C ORRS r0,r0,r1 - 0x00005112: 2102 .! MOVS r1,#2 - 0x00005114: 4308 .C ORRS r0,r0,r1 - 0x00005116: 4927 'I LDR r1,[pc,#156] ; [0x51b4] = 0x10008100 - 0x00005118: 7188 .q STRB r0,[r1,#6] - 0x0000511a: e01a .. B 0x5152 ; Audio_DacInit + 256 - 0x0000511c: bf00 .. NOP - 0x0000511e: 4824 $H LDR r0,[pc,#144] ; [0x51b0] = 0x10004fe0 - 0x00005120: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00005122: 2000 . MOVS r0,#0 - 0x00005124: 4923 #I LDR r1,[pc,#140] ; [0x51b4] = 0x10008100 - 0x00005126: 7989 .y LDRB r1,[r1,#6] - 0x00005128: 4300 .C ORRS r0,r0,r0 - 0x0000512a: 4922 "I LDR r1,[pc,#136] ; [0x51b4] = 0x10008100 - 0x0000512c: 7989 .y LDRB r1,[r1,#6] - 0x0000512e: 4308 .C ORRS r0,r0,r1 - 0x00005130: 2102 .! MOVS r1,#2 - 0x00005132: 4388 .C BICS r0,r0,r1 - 0x00005134: 491f .I LDR r1,[pc,#124] ; [0x51b4] = 0x10008100 - 0x00005136: 7188 .q STRB r0,[r1,#6] - 0x00005138: 481d .H LDR r0,[pc,#116] ; [0x51b0] = 0x10004fe0 - 0x0000513a: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x0000513c: 2000 . MOVS r0,#0 - 0x0000513e: 7989 .y LDRB r1,[r1,#6] - 0x00005140: 4300 .C ORRS r0,r0,r0 - 0x00005142: 491c .I LDR r1,[pc,#112] ; [0x51b4] = 0x10008100 - 0x00005144: 7989 .y LDRB r1,[r1,#6] - 0x00005146: 4308 .C ORRS r0,r0,r1 - 0x00005148: 2102 .! MOVS r1,#2 - 0x0000514a: 4388 .C BICS r0,r0,r1 - 0x0000514c: 4919 .I LDR r1,[pc,#100] ; [0x51b4] = 0x10008100 - 0x0000514e: 7188 .q STRB r0,[r1,#6] - 0x00005150: bf00 .. NOP - 0x00005152: bf00 .. NOP - 0x00005154: 4816 .H LDR r0,[pc,#88] ; [0x51b0] = 0x10004fe0 - 0x00005156: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00005158: 2000 . MOVS r0,#0 - 0x0000515a: 4916 .I LDR r1,[pc,#88] ; [0x51b4] = 0x10008100 - 0x0000515c: 7989 .y LDRB r1,[r1,#6] - 0x0000515e: 4300 .C ORRS r0,r0,r0 - 0x00005160: 4914 .I LDR r1,[pc,#80] ; [0x51b4] = 0x10008100 - 0x00005162: 7989 .y LDRB r1,[r1,#6] - 0x00005164: 4308 .C ORRS r0,r0,r1 - 0x00005166: 2104 .! MOVS r1,#4 - 0x00005168: 4388 .C BICS r0,r0,r1 - 0x0000516a: 4912 .I LDR r1,[pc,#72] ; [0x51b4] = 0x10008100 - 0x0000516c: 7188 .q STRB r0,[r1,#6] - 0x0000516e: 4810 .H LDR r0,[pc,#64] ; [0x51b0] = 0x10004fe0 - 0x00005170: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00005172: 2000 . MOVS r0,#0 - 0x00005174: 7989 .y LDRB r1,[r1,#6] - 0x00005176: 4300 .C ORRS r0,r0,r0 - 0x00005178: 490e .I LDR r1,[pc,#56] ; [0x51b4] = 0x10008100 - 0x0000517a: 7989 .y LDRB r1,[r1,#6] - 0x0000517c: 4308 .C ORRS r0,r0,r1 - 0x0000517e: 2104 .! MOVS r1,#4 - 0x00005180: 4388 .C BICS r0,r0,r1 - 0x00005182: 490c .I LDR r1,[pc,#48] ; [0x51b4] = 0x10008100 - 0x00005184: 7188 .q STRB r0,[r1,#6] - 0x00005186: bf00 .. NOP - 0x00005188: bf00 .. NOP - 0x0000518a: 4809 .H LDR r0,[pc,#36] ; [0x51b0] = 0x10004fe0 - 0x0000518c: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x0000518e: 2000 . MOVS r0,#0 - 0x00005190: 7989 .y LDRB r1,[r1,#6] - 0x00005192: 4300 .C ORRS r0,r0,r0 - 0x00005194: 4907 .I LDR r1,[pc,#28] ; [0x51b4] = 0x10008100 - 0x00005196: 7989 .y LDRB r1,[r1,#6] - 0x00005198: 4308 .C ORRS r0,r0,r1 - 0x0000519a: 2108 .! MOVS r1,#8 - 0x0000519c: 4388 .C BICS r0,r0,r1 - 0x0000519e: 4905 .I LDR r1,[pc,#20] ; [0x51b4] = 0x10008100 - 0x000051a0: 7188 .q STRB r0,[r1,#6] - 0x000051a2: 4803 .H LDR r0,[pc,#12] ; [0x51b0] = 0x10004fe0 - 0x000051a4: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x000051a6: 2000 . MOVS r0,#0 - 0x000051a8: 7989 .y LDRB r1,[r1,#6] - 0x000051aa: e009 .. B 0x51c0 ; Audio_DacInit + 366 - $d - 0x000051ac: 10008a00 .... DCD 268470784 - 0x000051b0: 10004fe0 .O.. DCD 268455904 - 0x000051b4: 10008100 .... DCD 268468480 - 0x000051b8: 10011028 (... DCD 268505128 - 0x000051bc: 10004ac0 .J.. DCD 268454592 - $t - 0x000051c0: 4300 .C ORRS r0,r0,r0 - 0x000051c2: 49fe .I LDR r1,[pc,#1016] ; [0x55bc] = 0x10008100 - 0x000051c4: 7989 .y LDRB r1,[r1,#6] - 0x000051c6: 4308 .C ORRS r0,r0,r1 - 0x000051c8: 2108 .! MOVS r1,#8 - 0x000051ca: 4388 .C BICS r0,r0,r1 - 0x000051cc: 49fb .I LDR r1,[pc,#1004] ; [0x55bc] = 0x10008100 - 0x000051ce: 7188 .q STRB r0,[r1,#6] - 0x000051d0: bf00 .. NOP - 0x000051d2: bf00 .. NOP - 0x000051d4: bf00 .. NOP - 0x000051d6: 700c .p STRB r4,[r1,#0] - 0x000051d8: 700c .p STRB r4,[r1,#0] - 0x000051da: bf00 .. NOP - 0x000051dc: bf00 .. NOP - 0x000051de: 1220 . ASRS r0,r4,#8 - 0x000051e0: 7048 Hp STRB r0,[r1,#1] - 0x000051e2: 1220 . ASRS r0,r4,#8 - 0x000051e4: 7048 Hp STRB r0,[r1,#1] - 0x000051e6: bf00 .. NOP - 0x000051e8: bf00 .. NOP - 0x000051ea: bf00 .. NOP - 0x000051ec: bf00 .. NOP - 0x000051ee: 710c .q STRB r4,[r1,#4] - 0x000051f0: 710c .q STRB r4,[r1,#4] - 0x000051f2: bf00 .. NOP - 0x000051f4: bf00 .. NOP - 0x000051f6: 1220 . ASRS r0,r4,#8 - 0x000051f8: 7148 Hq STRB r0,[r1,#5] - 0x000051fa: 1220 . ASRS r0,r4,#8 - 0x000051fc: 7148 Hq STRB r0,[r1,#5] - 0x000051fe: bf00 .. NOP - 0x00005200: bf00 .. NOP - 0x00005202: bf00 .. NOP - 0x00005204: bf00 .. NOP - 0x00005206: 49ee .I LDR r1,[pc,#952] ; [0x55c0] = 0x10008360 - 0x00005208: 728c .r STRB r4,[r1,#0xa] - 0x0000520a: 728c .r STRB r4,[r1,#0xa] - 0x0000520c: bf00 .. NOP - 0x0000520e: bf00 .. NOP - 0x00005210: 1220 . ASRS r0,r4,#8 - 0x00005212: 72c8 .r STRB r0,[r1,#0xb] - 0x00005214: 1220 . ASRS r0,r4,#8 - 0x00005216: 72c8 .r STRB r0,[r1,#0xb] - 0x00005218: bf00 .. NOP - 0x0000521a: bf00 .. NOP - 0x0000521c: bf00 .. NOP - 0x0000521e: bf00 .. NOP - 0x00005220: 1e70 p. SUBS r0,r6,#1 - 0x00005222: 49e6 .I LDR r1,[pc,#920] ; [0x55bc] = 0x10008100 - 0x00005224: 7088 .p STRB r0,[r1,#2] - 0x00005226: 7088 .p STRB r0,[r1,#2] - 0x00005228: bf00 .. NOP - 0x0000522a: bf00 .. NOP - 0x0000522c: 0400 .. LSLS r0,r0,#16 - 0x0000522e: 0e00 .. LSRS r0,r0,#24 - 0x00005230: 70c8 .p STRB r0,[r1,#3] - 0x00005232: 1e70 p. SUBS r0,r6,#1 - 0x00005234: 0400 .. LSLS r0,r0,#16 - 0x00005236: 0e00 .. LSRS r0,r0,#24 - 0x00005238: 70c8 .p STRB r0,[r1,#3] - 0x0000523a: bf00 .. NOP - 0x0000523c: bf00 .. NOP - 0x0000523e: bf00 .. NOP - 0x00005240: 48e0 .H LDR r0,[pc,#896] ; [0x55c4] = 0x10004fe0 - 0x00005242: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00005244: 2000 . MOVS r0,#0 - 0x00005246: 7989 .y LDRB r1,[r1,#6] - 0x00005248: 4300 .C ORRS r0,r0,r0 - 0x0000524a: 49dc .I LDR r1,[pc,#880] ; [0x55bc] = 0x10008100 - 0x0000524c: 7989 .y LDRB r1,[r1,#6] - 0x0000524e: 4308 .C ORRS r0,r0,r1 - 0x00005250: 2101 .! MOVS r1,#1 - 0x00005252: 4308 .C ORRS r0,r0,r1 - 0x00005254: 49d9 .I LDR r1,[pc,#868] ; [0x55bc] = 0x10008100 - 0x00005256: 7188 .q STRB r0,[r1,#6] - 0x00005258: 48da .H LDR r0,[pc,#872] ; [0x55c4] = 0x10004fe0 - 0x0000525a: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x0000525c: 2000 . MOVS r0,#0 - 0x0000525e: 7989 .y LDRB r1,[r1,#6] - 0x00005260: 4300 .C ORRS r0,r0,r0 - 0x00005262: 49d6 .I LDR r1,[pc,#856] ; [0x55bc] = 0x10008100 - 0x00005264: 7989 .y LDRB r1,[r1,#6] - 0x00005266: 4308 .C ORRS r0,r0,r1 - 0x00005268: 2101 .! MOVS r1,#1 - 0x0000526a: 4308 .C ORRS r0,r0,r1 - 0x0000526c: 49d3 .I LDR r1,[pc,#844] ; [0x55bc] = 0x10008100 - 0x0000526e: 7188 .q STRB r0,[r1,#6] - 0x00005270: bf00 .. NOP - 0x00005272: f7fefac3 .... BL Audio_RelasePaDelay ; 0x37fc - 0x00005276: bf00 .. NOP - 0x00005278: 20f2 . MOVS r0,#0xf2 - 0x0000527a: 49d3 .I LDR r1,[pc,#844] ; [0x55c8] = 0x10008a00 - 0x0000527c: 7048 Hp STRB r0,[r1,#1] - 0x0000527e: 7048 Hp STRB r0,[r1,#1] - 0x00005280: bf00 .. NOP - 0x00005282: 48d0 .H LDR r0,[pc,#832] ; [0x55c4] = 0x10004fe0 - 0x00005284: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00005286: 2000 . MOVS r0,#0 - 0x00005288: 49d0 .I LDR r1,[pc,#832] ; [0x55cc] = 0x10004ac0 - 0x0000528a: 7dc9 .} LDRB r1,[r1,#0x17] - 0x0000528c: 4300 .C ORRS r0,r0,r0 - 0x0000528e: 49cf .I LDR r1,[pc,#828] ; [0x55cc] = 0x10004ac0 - 0x00005290: 7dc9 .} LDRB r1,[r1,#0x17] - 0x00005292: 4308 .C ORRS r0,r0,r1 - 0x00005294: 2800 .( CMP r0,#0 - 0x00005296: d177 w. BNE 0x5388 ; Audio_DacInit + 822 - 0x00005298: f7fefaa1 .... BL Audio_CheckAdcDmaEnable ; 0x37de - 0x0000529c: 2800 .( CMP r0,#0 - 0x0000529e: d173 s. BNE 0x5388 ; Audio_DacInit + 822 - 0x000052a0: bf00 .. NOP - 0x000052a2: bf00 .. NOP - 0x000052a4: 48c7 .H LDR r0,[pc,#796] ; [0x55c4] = 0x10004fe0 - 0x000052a6: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x000052a8: 2000 . MOVS r0,#0 - 0x000052aa: 49c4 .I LDR r1,[pc,#784] ; [0x55bc] = 0x10008100 - 0x000052ac: 39c0 .9 SUBS r1,r1,#0xc0 - 0x000052ae: 7c09 .| LDRB r1,[r1,#0x10] - 0x000052b0: 4300 .C ORRS r0,r0,r0 - 0x000052b2: 49c2 .I LDR r1,[pc,#776] ; [0x55bc] = 0x10008100 - 0x000052b4: 39c0 .9 SUBS r1,r1,#0xc0 - 0x000052b6: 7c09 .| LDRB r1,[r1,#0x10] - 0x000052b8: 4308 .C ORRS r0,r0,r1 - 0x000052ba: 49c2 .I LDR r1,[pc,#776] ; [0x55c4] = 0x10004fe0 - 0x000052bc: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x000052be: 4abf .J LDR r2,[pc,#764] ; [0x55bc] = 0x10008100 - 0x000052c0: 3ac0 .: SUBS r2,r2,#0xc0 - 0x000052c2: 7c52 R| LDRB r2,[r2,#0x11] - 0x000052c4: 4311 .C ORRS r1,r1,r2 - 0x000052c6: 4abd .J LDR r2,[pc,#756] ; [0x55bc] = 0x10008100 - 0x000052c8: 3ac0 .: SUBS r2,r2,#0xc0 - 0x000052ca: 7c52 R| LDRB r2,[r2,#0x11] - 0x000052cc: 4311 .C ORRS r1,r1,r2 - 0x000052ce: 0209 .. LSLS r1,r1,#8 - 0x000052d0: 4308 .C ORRS r0,r0,r1 - 0x000052d2: 2140 @! MOVS r1,#0x40 - 0x000052d4: 4308 .C ORRS r0,r0,r1 - 0x000052d6: 49b9 .I LDR r1,[pc,#740] ; [0x55bc] = 0x10008100 - 0x000052d8: 39c0 .9 SUBS r1,r1,#0xc0 - 0x000052da: 7408 .t STRB r0,[r1,#0x10] - 0x000052dc: 48b9 .H LDR r0,[pc,#740] ; [0x55c4] = 0x10004fe0 - 0x000052de: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x000052e0: 2000 . MOVS r0,#0 - 0x000052e2: 7c09 .| LDRB r1,[r1,#0x10] - 0x000052e4: 4300 .C ORRS r0,r0,r0 - 0x000052e6: 49b5 .I LDR r1,[pc,#724] ; [0x55bc] = 0x10008100 - 0x000052e8: 39c0 .9 SUBS r1,r1,#0xc0 - 0x000052ea: 7c09 .| LDRB r1,[r1,#0x10] - 0x000052ec: 4308 .C ORRS r0,r0,r1 - 0x000052ee: 49b5 .I LDR r1,[pc,#724] ; [0x55c4] = 0x10004fe0 - 0x000052f0: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x000052f2: 4ab2 .J LDR r2,[pc,#712] ; [0x55bc] = 0x10008100 - 0x000052f4: 3ac0 .: SUBS r2,r2,#0xc0 - 0x000052f6: 7c52 R| LDRB r2,[r2,#0x11] - 0x000052f8: 4311 .C ORRS r1,r1,r2 - 0x000052fa: 4ab0 .J LDR r2,[pc,#704] ; [0x55bc] = 0x10008100 - 0x000052fc: 3ac0 .: SUBS r2,r2,#0xc0 - 0x000052fe: 7c52 R| LDRB r2,[r2,#0x11] - 0x00005300: 4311 .C ORRS r1,r1,r2 - 0x00005302: 0209 .. LSLS r1,r1,#8 - 0x00005304: 4308 .C ORRS r0,r0,r1 - 0x00005306: 2140 @! MOVS r1,#0x40 - 0x00005308: 4308 .C ORRS r0,r0,r1 - 0x0000530a: 49ac .I LDR r1,[pc,#688] ; [0x55bc] = 0x10008100 - 0x0000530c: 39c0 .9 SUBS r1,r1,#0xc0 - 0x0000530e: 7408 .t STRB r0,[r1,#0x10] - 0x00005310: bf00 .. NOP - 0x00005312: bf00 .. NOP - 0x00005314: 48ab .H LDR r0,[pc,#684] ; [0x55c4] = 0x10004fe0 - 0x00005316: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00005318: 2000 . MOVS r0,#0 - 0x0000531a: 7c09 .| LDRB r1,[r1,#0x10] - 0x0000531c: 4300 .C ORRS r0,r0,r0 - 0x0000531e: 49a7 .I LDR r1,[pc,#668] ; [0x55bc] = 0x10008100 - 0x00005320: 39c0 .9 SUBS r1,r1,#0xc0 - 0x00005322: 7c09 .| LDRB r1,[r1,#0x10] - 0x00005324: 4308 .C ORRS r0,r0,r1 - 0x00005326: 49a7 .I LDR r1,[pc,#668] ; [0x55c4] = 0x10004fe0 - 0x00005328: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x0000532a: 2100 .! MOVS r1,#0 - 0x0000532c: 4aa3 .J LDR r2,[pc,#652] ; [0x55bc] = 0x10008100 - 0x0000532e: 3ac0 .: SUBS r2,r2,#0xc0 - 0x00005330: 7c52 R| LDRB r2,[r2,#0x11] - 0x00005332: 4309 .C ORRS r1,r1,r1 - 0x00005334: 4aa1 .J LDR r2,[pc,#644] ; [0x55bc] = 0x10008100 - 0x00005336: 3ac0 .: SUBS r2,r2,#0xc0 - 0x00005338: 7c52 R| LDRB r2,[r2,#0x11] - 0x0000533a: 4311 .C ORRS r1,r1,r2 - 0x0000533c: 0209 .. LSLS r1,r1,#8 - 0x0000533e: 4308 .C ORRS r0,r0,r1 - 0x00005340: 2140 @! MOVS r1,#0x40 - 0x00005342: 4308 .C ORRS r0,r0,r1 - 0x00005344: 1200 .. ASRS r0,r0,#8 - 0x00005346: 499d .I LDR r1,[pc,#628] ; [0x55bc] = 0x10008100 - 0x00005348: 39c0 .9 SUBS r1,r1,#0xc0 - 0x0000534a: 7448 Ht STRB r0,[r1,#0x11] - 0x0000534c: 489d .H LDR r0,[pc,#628] ; [0x55c4] = 0x10004fe0 - 0x0000534e: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00005350: 2000 . MOVS r0,#0 - 0x00005352: 7c09 .| LDRB r1,[r1,#0x10] - 0x00005354: 4300 .C ORRS r0,r0,r0 - 0x00005356: 4999 .I LDR r1,[pc,#612] ; [0x55bc] = 0x10008100 - 0x00005358: 39c0 .9 SUBS r1,r1,#0xc0 - 0x0000535a: 7c09 .| LDRB r1,[r1,#0x10] - 0x0000535c: 4308 .C ORRS r0,r0,r1 - 0x0000535e: 4999 .I LDR r1,[pc,#612] ; [0x55c4] = 0x10004fe0 - 0x00005360: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00005362: 2100 .! MOVS r1,#0 - 0x00005364: 4a95 .J LDR r2,[pc,#596] ; [0x55bc] = 0x10008100 - 0x00005366: 3ac0 .: SUBS r2,r2,#0xc0 - 0x00005368: 7c52 R| LDRB r2,[r2,#0x11] - 0x0000536a: 4309 .C ORRS r1,r1,r1 - 0x0000536c: 4a93 .J LDR r2,[pc,#588] ; [0x55bc] = 0x10008100 - 0x0000536e: 3ac0 .: SUBS r2,r2,#0xc0 - 0x00005370: 7c52 R| LDRB r2,[r2,#0x11] - 0x00005372: 4311 .C ORRS r1,r1,r2 - 0x00005374: 0209 .. LSLS r1,r1,#8 - 0x00005376: 4308 .C ORRS r0,r0,r1 - 0x00005378: 2140 @! MOVS r1,#0x40 - 0x0000537a: 4308 .C ORRS r0,r0,r1 - 0x0000537c: 1200 .. ASRS r0,r0,#8 - 0x0000537e: 498f .I LDR r1,[pc,#572] ; [0x55bc] = 0x10008100 - 0x00005380: 39c0 .9 SUBS r1,r1,#0xc0 - 0x00005382: 7448 Ht STRB r0,[r1,#0x11] - 0x00005384: bf00 .. NOP - 0x00005386: bf00 .. NOP - 0x00005388: bf00 .. NOP - 0x0000538a: e679 y. B 0x5080 ; Audio_DacInit + 46 - Audio_DacInitMono - 0x0000538c: b5fe .. PUSH {r1-r7,lr} - 0x0000538e: 4604 .F MOV r4,r0 - 0x00005390: 460d .F MOV r5,r1 - 0x00005392: 4616 .F MOV r6,r2 - 0x00005394: 461f .F MOV r7,r3 - 0x00005396: 4623 #F MOV r3,r4 - 0x00005398: 2200 ." MOVS r2,#0 - 0x0000539a: 4611 .F MOV r1,r2 - 0x0000539c: 2001 . MOVS r0,#1 - 0x0000539e: 9702 .. STR r7,[sp,#8] - 0x000053a0: 9601 .. STR r6,[sp,#4] - 0x000053a2: 9500 .. STR r5,[sp,#0] - 0x000053a4: f7fffe55 ..U. BL Audio_DacInit ; 0x5052 - 0x000053a8: bdfe .. POP {r1-r7,pc} - Audio_DacInitTwsRightMonoStero - 0x000053aa: b5fe .. PUSH {r1-r7,lr} - 0x000053ac: 4604 .F MOV r4,r0 - 0x000053ae: 460d .F MOV r5,r1 - 0x000053b0: 4616 .F MOV r6,r2 - 0x000053b2: 461f .F MOV r7,r3 - 0x000053b4: 4623 #F MOV r3,r4 - 0x000053b6: 2200 ." MOVS r2,#0 - 0x000053b8: 21ff .! MOVS r1,#0xff - 0x000053ba: 2001 . MOVS r0,#1 - 0x000053bc: 9702 .. STR r7,[sp,#8] - 0x000053be: 9601 .. STR r6,[sp,#4] - 0x000053c0: 9500 .. STR r5,[sp,#0] - 0x000053c2: f7fffe46 ..F. BL Audio_DacInit ; 0x5052 - 0x000053c6: bdfe .. POP {r1-r7,pc} - Audio_DacInitTwsLeftMonoStero - 0x000053c8: b5fe .. PUSH {r1-r7,lr} - 0x000053ca: 4604 .F MOV r4,r0 - 0x000053cc: 460d .F MOV r5,r1 - 0x000053ce: 4616 .F MOV r6,r2 - 0x000053d0: 461f .F MOV r7,r3 - 0x000053d2: 4623 #F MOV r3,r4 - 0x000053d4: 22ff ." MOVS r2,#0xff - 0x000053d6: 2100 .! MOVS r1,#0 - 0x000053d8: 2001 . MOVS r0,#1 - 0x000053da: 9702 .. STR r7,[sp,#8] - 0x000053dc: 9601 .. STR r6,[sp,#4] - 0x000053de: 9500 .. STR r5,[sp,#0] - 0x000053e0: f7fffe37 ..7. BL Audio_DacInit ; 0x5052 - 0x000053e4: bdfe .. POP {r1-r7,pc} - Audio_DacInitVpCall - 0x000053e6: b5f8 .. PUSH {r3-r7,lr} - 0x000053e8: 4604 .F MOV r4,r0 - 0x000053ea: 460d .F MOV r5,r1 - 0x000053ec: 4616 .F MOV r6,r2 - 0x000053ee: 461f .F MOV r7,r3 - 0x000053f0: 4874 tH LDR r0,[pc,#464] ; [0x55c4] = 0x10004fe0 - 0x000053f2: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x000053f4: 2000 . MOVS r0,#0 - 0x000053f6: 4976 vI LDR r1,[pc,#472] ; [0x55d0] = 0x100042c0 - 0x000053f8: 7f49 I. LDRB r1,[r1,#0x1d] - 0x000053fa: 4300 .C ORRS r0,r0,r0 - 0x000053fc: 4974 tI LDR r1,[pc,#464] ; [0x55d0] = 0x100042c0 - 0x000053fe: 7f49 I. LDRB r1,[r1,#0x1d] - 0x00005400: 4308 .C ORRS r0,r0,r1 - 0x00005402: 2801 .( CMP r0,#1 - 0x00005404: d002 .. BEQ 0x540c ; Audio_DacInitVpCall + 38 - 0x00005406: 2802 .( CMP r0,#2 - 0x00005408: d10e .. BNE 0x5428 ; Audio_DacInitVpCall + 66 - 0x0000540a: e006 .. B 0x541a ; Audio_DacInitVpCall + 52 - 0x0000540c: 463b ;F MOV r3,r7 - 0x0000540e: 4632 2F MOV r2,r6 - 0x00005410: 4629 )F MOV r1,r5 - 0x00005412: 4620 F MOV r0,r4 - 0x00005414: f7ffffd8 .... BL Audio_DacInitTwsLeftMonoStero ; 0x53c8 - 0x00005418: e00d .. B 0x5436 ; Audio_DacInitVpCall + 80 - 0x0000541a: 463b ;F MOV r3,r7 - 0x0000541c: 4632 2F MOV r2,r6 - 0x0000541e: 4629 )F MOV r1,r5 - 0x00005420: 4620 F MOV r0,r4 - 0x00005422: f7ffffc2 .... BL Audio_DacInitTwsRightMonoStero ; 0x53aa - 0x00005426: e006 .. B 0x5436 ; Audio_DacInitVpCall + 80 - 0x00005428: 463b ;F MOV r3,r7 - 0x0000542a: 4632 2F MOV r2,r6 - 0x0000542c: 4629 )F MOV r1,r5 - 0x0000542e: 4620 F MOV r0,r4 - 0x00005430: f7ffffac .... BL Audio_DacInitMono ; 0x538c - 0x00005434: bf00 .. NOP - 0x00005436: bf00 .. NOP - 0x00005438: bdf8 .. POP {r3-r7,pc} - Audio_CvsdInitDac - 0x0000543a: b5f8 .. PUSH {r3-r7,lr} - 0x0000543c: 4861 aH LDR r0,[pc,#388] ; [0x55c4] = 0x10004fe0 - 0x0000543e: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00005440: 2000 . MOVS r0,#0 - 0x00005442: 495e ^I LDR r1,[pc,#376] ; [0x55bc] = 0x10008100 - 0x00005444: 3120 1 ADDS r1,r1,#0x20 - 0x00005446: 7909 .y LDRB r1,[r1,#4] - 0x00005448: 4300 .C ORRS r0,r0,r0 - 0x0000544a: 495c \I LDR r1,[pc,#368] ; [0x55bc] = 0x10008100 - 0x0000544c: 3120 1 ADDS r1,r1,#0x20 - 0x0000544e: 7909 .y LDRB r1,[r1,#4] - 0x00005450: 4308 .C ORRS r0,r0,r1 - 0x00005452: 495c \I LDR r1,[pc,#368] ; [0x55c4] = 0x10004fe0 - 0x00005454: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00005456: 2100 .! MOVS r1,#0 - 0x00005458: 4a58 XJ LDR r2,[pc,#352] ; [0x55bc] = 0x10008100 - 0x0000545a: 3220 2 ADDS r2,r2,#0x20 - 0x0000545c: 7952 Ry LDRB r2,[r2,#5] - 0x0000545e: 4309 .C ORRS r1,r1,r1 - 0x00005460: 4a56 VJ LDR r2,[pc,#344] ; [0x55bc] = 0x10008100 - 0x00005462: 3220 2 ADDS r2,r2,#0x20 - 0x00005464: 7952 Ry LDRB r2,[r2,#5] - 0x00005466: 4311 .C ORRS r1,r1,r2 - 0x00005468: 0209 .. LSLS r1,r1,#8 - 0x0000546a: 4308 .C ORRS r0,r0,r1 - 0x0000546c: 4604 .F MOV r4,r0 - 0x0000546e: 2530 0% MOVS r5,#0x30 - 0x00005470: 4854 TH LDR r0,[pc,#336] ; [0x55c4] = 0x10004fe0 - 0x00005472: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00005474: 2000 . MOVS r0,#0 - 0x00005476: 4951 QI LDR r1,[pc,#324] ; [0x55bc] = 0x10008100 - 0x00005478: 3920 9 SUBS r1,r1,#0x20 - 0x0000547a: 7e89 .~ LDRB r1,[r1,#0x1a] - 0x0000547c: 4300 .C ORRS r0,r0,r0 - 0x0000547e: 494f OI LDR r1,[pc,#316] ; [0x55bc] = 0x10008100 - 0x00005480: 3920 9 SUBS r1,r1,#0x20 - 0x00005482: 7e89 .~ LDRB r1,[r1,#0x1a] - 0x00005484: 4308 .C ORRS r0,r0,r1 - 0x00005486: 494f OI LDR r1,[pc,#316] ; [0x55c4] = 0x10004fe0 - 0x00005488: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x0000548a: 2100 .! MOVS r1,#0 - 0x0000548c: 4a4b KJ LDR r2,[pc,#300] ; [0x55bc] = 0x10008100 - 0x0000548e: 3a20 : SUBS r2,r2,#0x20 - 0x00005490: 7ed2 .~ LDRB r2,[r2,#0x1b] - 0x00005492: 4309 .C ORRS r1,r1,r1 - 0x00005494: 4a49 IJ LDR r2,[pc,#292] ; [0x55bc] = 0x10008100 - 0x00005496: 3a20 : SUBS r2,r2,#0x20 - 0x00005498: 7ed2 .~ LDRB r2,[r2,#0x1b] - 0x0000549a: 4311 .C ORRS r1,r1,r2 - 0x0000549c: 0209 .. LSLS r1,r1,#8 - 0x0000549e: 4308 .C ORRS r0,r0,r1 - 0x000054a0: 1c40 @. ADDS r0,r0,#1 - 0x000054a2: 210c .! MOVS r1,#0xc - 0x000054a4: 4348 HC MULS r0,r1,r0 - 0x000054a6: b286 .. UXTH r6,r0 - 0x000054a8: 4846 FH LDR r0,[pc,#280] ; [0x55c4] = 0x10004fe0 - 0x000054aa: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x000054ac: 2000 . MOVS r0,#0 - 0x000054ae: 4943 CI LDR r1,[pc,#268] ; [0x55bc] = 0x10008100 - 0x000054b0: 3920 9 SUBS r1,r1,#0x20 - 0x000054b2: 7d49 I} LDRB r1,[r1,#0x15] - 0x000054b4: 4300 .C ORRS r0,r0,r0 - 0x000054b6: 4941 AI LDR r1,[pc,#260] ; [0x55bc] = 0x10008100 - 0x000054b8: 3920 9 SUBS r1,r1,#0x20 - 0x000054ba: 7d49 I} LDRB r1,[r1,#0x15] - 0x000054bc: 4308 .C ORRS r0,r0,r1 - 0x000054be: 2140 @! MOVS r1,#0x40 - 0x000054c0: 4008 .@ ANDS r0,r0,r1 - 0x000054c2: 0987 .. LSRS r7,r0,#6 - 0x000054c4: 4622 "F MOV r2,r4 - 0x000054c6: 4628 (F MOV r0,r5 - 0x000054c8: 4633 3F MOV r3,r6 - 0x000054ca: 4639 9F MOV r1,r7 - 0x000054cc: f7ffff8b .... BL Audio_DacInitVpCall ; 0x53e6 - 0x000054d0: bdf8 .. POP {r3-r7,pc} - NrAec_Init - 0x000054d2: 4770 pG BX lr - Audio_AdcDmaEnable - 0x000054d4: bf00 .. NOP - 0x000054d6: 483b ;H LDR r0,[pc,#236] ; [0x55c4] = 0x10004fe0 - 0x000054d8: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x000054da: 2000 . MOVS r0,#0 - 0x000054dc: 4937 7I LDR r1,[pc,#220] ; [0x55bc] = 0x10008100 - 0x000054de: 39e0 .9 SUBS r1,r1,#0xe0 - 0x000054e0: 7ec9 .~ LDRB r1,[r1,#0x1b] - 0x000054e2: 4300 .C ORRS r0,r0,r0 - 0x000054e4: 4935 5I LDR r1,[pc,#212] ; [0x55bc] = 0x10008100 - 0x000054e6: 39e0 .9 SUBS r1,r1,#0xe0 - 0x000054e8: 7ec9 .~ LDRB r1,[r1,#0x1b] - 0x000054ea: 4308 .C ORRS r0,r0,r1 - 0x000054ec: 2180 .! MOVS r1,#0x80 - 0x000054ee: 4308 .C ORRS r0,r0,r1 - 0x000054f0: 4932 2I LDR r1,[pc,#200] ; [0x55bc] = 0x10008100 - 0x000054f2: 39e0 .9 SUBS r1,r1,#0xe0 - 0x000054f4: 76c8 .v STRB r0,[r1,#0x1b] - 0x000054f6: 4833 3H LDR r0,[pc,#204] ; [0x55c4] = 0x10004fe0 - 0x000054f8: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x000054fa: 2000 . MOVS r0,#0 - 0x000054fc: 7ec9 .~ LDRB r1,[r1,#0x1b] - 0x000054fe: 4300 .C ORRS r0,r0,r0 - 0x00005500: 492e .I LDR r1,[pc,#184] ; [0x55bc] = 0x10008100 - 0x00005502: 39e0 .9 SUBS r1,r1,#0xe0 - 0x00005504: 7ec9 .~ LDRB r1,[r1,#0x1b] - 0x00005506: 4308 .C ORRS r0,r0,r1 - 0x00005508: 2180 .! MOVS r1,#0x80 - 0x0000550a: 4308 .C ORRS r0,r0,r1 - 0x0000550c: 492b +I LDR r1,[pc,#172] ; [0x55bc] = 0x10008100 - 0x0000550e: 39e0 .9 SUBS r1,r1,#0xe0 - 0x00005510: 76c8 .v STRB r0,[r1,#0x1b] - 0x00005512: bf00 .. NOP - 0x00005514: 4770 pG BX lr - Audio_AdcStart8K - 0x00005516: b500 .. PUSH {lr} - 0x00005518: 4602 .F MOV r2,r0 - 0x0000551a: bf00 .. NOP - 0x0000551c: 2080 . MOVS r0,#0x80 - 0x0000551e: 4927 'I LDR r1,[pc,#156] ; [0x55bc] = 0x10008100 - 0x00005520: 39e0 .9 SUBS r1,r1,#0xe0 - 0x00005522: 7688 .v STRB r0,[r1,#0x1a] - 0x00005524: 7688 .v STRB r0,[r1,#0x1a] - 0x00005526: bf00 .. NOP - 0x00005528: bf00 .. NOP - 0x0000552a: 2000 . MOVS r0,#0 - 0x0000552c: 76c8 .v STRB r0,[r1,#0x1b] - 0x0000552e: 76c8 .v STRB r0,[r1,#0x1b] - 0x00005530: bf00 .. NOP - 0x00005532: 2a00 .* CMP r2,#0 - 0x00005534: d01d .. BEQ 0x5572 ; Audio_AdcStart8K + 92 - 0x00005536: bf00 .. NOP - 0x00005538: 4822 "H LDR r0,[pc,#136] ; [0x55c4] = 0x10004fe0 - 0x0000553a: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x0000553c: 2000 . MOVS r0,#0 - 0x0000553e: 7ec9 .~ LDRB r1,[r1,#0x1b] - 0x00005540: 4300 .C ORRS r0,r0,r0 - 0x00005542: 491e .I LDR r1,[pc,#120] ; [0x55bc] = 0x10008100 - 0x00005544: 39e0 .9 SUBS r1,r1,#0xe0 - 0x00005546: 7ec9 .~ LDRB r1,[r1,#0x1b] - 0x00005548: 4308 .C ORRS r0,r0,r1 - 0x0000554a: 2140 @! MOVS r1,#0x40 - 0x0000554c: 4308 .C ORRS r0,r0,r1 - 0x0000554e: 491b .I LDR r1,[pc,#108] ; [0x55bc] = 0x10008100 - 0x00005550: 39e0 .9 SUBS r1,r1,#0xe0 - 0x00005552: 76c8 .v STRB r0,[r1,#0x1b] - 0x00005554: 481b .H LDR r0,[pc,#108] ; [0x55c4] = 0x10004fe0 - 0x00005556: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00005558: 2000 . MOVS r0,#0 - 0x0000555a: 7ec9 .~ LDRB r1,[r1,#0x1b] - 0x0000555c: 4300 .C ORRS r0,r0,r0 - 0x0000555e: 4917 .I LDR r1,[pc,#92] ; [0x55bc] = 0x10008100 - 0x00005560: 39e0 .9 SUBS r1,r1,#0xe0 - 0x00005562: 7ec9 .~ LDRB r1,[r1,#0x1b] - 0x00005564: 4308 .C ORRS r0,r0,r1 - 0x00005566: 2140 @! MOVS r1,#0x40 - 0x00005568: 4308 .C ORRS r0,r0,r1 - 0x0000556a: 4914 .I LDR r1,[pc,#80] ; [0x55bc] = 0x10008100 - 0x0000556c: 39e0 .9 SUBS r1,r1,#0xe0 - 0x0000556e: 76c8 .v STRB r0,[r1,#0x1b] - 0x00005570: e01f .. B 0x55b2 ; Audio_AdcStart8K + 156 - 0x00005572: bf00 .. NOP - 0x00005574: 4813 .H LDR r0,[pc,#76] ; [0x55c4] = 0x10004fe0 - 0x00005576: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00005578: 2000 . MOVS r0,#0 - 0x0000557a: 4910 .I LDR r1,[pc,#64] ; [0x55bc] = 0x10008100 - 0x0000557c: 39e0 .9 SUBS r1,r1,#0xe0 - 0x0000557e: 7ec9 .~ LDRB r1,[r1,#0x1b] - 0x00005580: 4300 .C ORRS r0,r0,r0 - 0x00005582: 490e .I LDR r1,[pc,#56] ; [0x55bc] = 0x10008100 - 0x00005584: 39e0 .9 SUBS r1,r1,#0xe0 - 0x00005586: 7ec9 .~ LDRB r1,[r1,#0x1b] - 0x00005588: 4308 .C ORRS r0,r0,r1 - 0x0000558a: 2140 @! MOVS r1,#0x40 - 0x0000558c: 4388 .C BICS r0,r0,r1 - 0x0000558e: 490b .I LDR r1,[pc,#44] ; [0x55bc] = 0x10008100 - 0x00005590: 39e0 .9 SUBS r1,r1,#0xe0 - 0x00005592: 76c8 .v STRB r0,[r1,#0x1b] - 0x00005594: 480b .H LDR r0,[pc,#44] ; [0x55c4] = 0x10004fe0 - 0x00005596: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00005598: 2000 . MOVS r0,#0 - 0x0000559a: 7ec9 .~ LDRB r1,[r1,#0x1b] - 0x0000559c: 4300 .C ORRS r0,r0,r0 - 0x0000559e: 4907 .I LDR r1,[pc,#28] ; [0x55bc] = 0x10008100 - 0x000055a0: 39e0 .9 SUBS r1,r1,#0xe0 - 0x000055a2: 7ec9 .~ LDRB r1,[r1,#0x1b] - 0x000055a4: 4308 .C ORRS r0,r0,r1 - 0x000055a6: 2140 @! MOVS r1,#0x40 - 0x000055a8: 4388 .C BICS r0,r0,r1 - 0x000055aa: 4904 .I LDR r1,[pc,#16] ; [0x55bc] = 0x10008100 - 0x000055ac: 39e0 .9 SUBS r1,r1,#0xe0 - 0x000055ae: 76c8 .v STRB r0,[r1,#0x1b] - 0x000055b0: bf00 .. NOP - 0x000055b2: f7ffff8f .... BL Audio_AdcDmaEnable ; 0x54d4 - 0x000055b6: bf00 .. NOP - 0x000055b8: bf00 .. NOP - 0x000055ba: e00b .. B 0x55d4 ; Audio_AdcStart8K + 190 - $d - 0x000055bc: 10008100 .... DCD 268468480 - 0x000055c0: 10008360 `... DCD 268469088 - 0x000055c4: 10004fe0 .O.. DCD 268455904 - 0x000055c8: 10008a00 .... DCD 268470784 - 0x000055cc: 10004ac0 .J.. DCD 268454592 - 0x000055d0: 100042c0 .B.. DCD 268452544 - $t - 0x000055d4: 48fe .H LDR r0,[pc,#1016] ; [0x59d0] = 0x10004fe0 - 0x000055d6: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x000055d8: 2000 . MOVS r0,#0 - 0x000055da: 49fe .I LDR r1,[pc,#1016] ; [0x59d4] = 0x10008040 - 0x000055dc: 7c09 .| LDRB r1,[r1,#0x10] - 0x000055de: 4300 .C ORRS r0,r0,r0 - 0x000055e0: 49fc .I LDR r1,[pc,#1008] ; [0x59d4] = 0x10008040 - 0x000055e2: 7c09 .| LDRB r1,[r1,#0x10] - 0x000055e4: 4308 .C ORRS r0,r0,r1 - 0x000055e6: 49fa .I LDR r1,[pc,#1000] ; [0x59d0] = 0x10004fe0 - 0x000055e8: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x000055ea: 4bfa .K LDR r3,[pc,#1000] ; [0x59d4] = 0x10008040 - 0x000055ec: 7c5b [| LDRB r3,[r3,#0x11] - 0x000055ee: 4319 .C ORRS r1,r1,r3 - 0x000055f0: 4bf8 .K LDR r3,[pc,#992] ; [0x59d4] = 0x10008040 - 0x000055f2: 7c5b [| LDRB r3,[r3,#0x11] - 0x000055f4: 4319 .C ORRS r1,r1,r3 - 0x000055f6: 0209 .. LSLS r1,r1,#8 - 0x000055f8: 4308 .C ORRS r0,r0,r1 - 0x000055fa: 2140 @! MOVS r1,#0x40 - 0x000055fc: 4388 .C BICS r0,r0,r1 - 0x000055fe: 49f5 .I LDR r1,[pc,#980] ; [0x59d4] = 0x10008040 - 0x00005600: 7408 .t STRB r0,[r1,#0x10] - 0x00005602: 48f3 .H LDR r0,[pc,#972] ; [0x59d0] = 0x10004fe0 - 0x00005604: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00005606: 2000 . MOVS r0,#0 - 0x00005608: 7c09 .| LDRB r1,[r1,#0x10] - 0x0000560a: 4300 .C ORRS r0,r0,r0 - 0x0000560c: 49f1 .I LDR r1,[pc,#964] ; [0x59d4] = 0x10008040 - 0x0000560e: 7c09 .| LDRB r1,[r1,#0x10] - 0x00005610: 4308 .C ORRS r0,r0,r1 - 0x00005612: 49ef .I LDR r1,[pc,#956] ; [0x59d0] = 0x10004fe0 - 0x00005614: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00005616: 4bef .K LDR r3,[pc,#956] ; [0x59d4] = 0x10008040 - 0x00005618: 7c5b [| LDRB r3,[r3,#0x11] - 0x0000561a: 4319 .C ORRS r1,r1,r3 - 0x0000561c: 4bed .K LDR r3,[pc,#948] ; [0x59d4] = 0x10008040 - 0x0000561e: 7c5b [| LDRB r3,[r3,#0x11] - 0x00005620: 4319 .C ORRS r1,r1,r3 - 0x00005622: 0209 .. LSLS r1,r1,#8 - 0x00005624: 4308 .C ORRS r0,r0,r1 - 0x00005626: 2140 @! MOVS r1,#0x40 - 0x00005628: 4388 .C BICS r0,r0,r1 - 0x0000562a: 49ea .I LDR r1,[pc,#936] ; [0x59d4] = 0x10008040 - 0x0000562c: 7408 .t STRB r0,[r1,#0x10] - 0x0000562e: bf00 .. NOP - 0x00005630: bf00 .. NOP - 0x00005632: 48e7 .H LDR r0,[pc,#924] ; [0x59d0] = 0x10004fe0 - 0x00005634: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00005636: 2000 . MOVS r0,#0 - 0x00005638: 7c09 .| LDRB r1,[r1,#0x10] - 0x0000563a: 4300 .C ORRS r0,r0,r0 - 0x0000563c: 49e5 .I LDR r1,[pc,#916] ; [0x59d4] = 0x10008040 - 0x0000563e: 7c09 .| LDRB r1,[r1,#0x10] - 0x00005640: 4308 .C ORRS r0,r0,r1 - 0x00005642: 49e3 .I LDR r1,[pc,#908] ; [0x59d0] = 0x10004fe0 - 0x00005644: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00005646: 2100 .! MOVS r1,#0 - 0x00005648: 4be2 .K LDR r3,[pc,#904] ; [0x59d4] = 0x10008040 - 0x0000564a: 7c5b [| LDRB r3,[r3,#0x11] - 0x0000564c: 4309 .C ORRS r1,r1,r1 - 0x0000564e: 4be1 .K LDR r3,[pc,#900] ; [0x59d4] = 0x10008040 - 0x00005650: 7c5b [| LDRB r3,[r3,#0x11] - 0x00005652: 4319 .C ORRS r1,r1,r3 - 0x00005654: 0209 .. LSLS r1,r1,#8 - 0x00005656: 4308 .C ORRS r0,r0,r1 - 0x00005658: 2140 @! MOVS r1,#0x40 - 0x0000565a: 4388 .C BICS r0,r0,r1 - 0x0000565c: 1200 .. ASRS r0,r0,#8 - 0x0000565e: 49dd .I LDR r1,[pc,#884] ; [0x59d4] = 0x10008040 - 0x00005660: 7448 Ht STRB r0,[r1,#0x11] - 0x00005662: 48db .H LDR r0,[pc,#876] ; [0x59d0] = 0x10004fe0 - 0x00005664: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00005666: 2000 . MOVS r0,#0 - 0x00005668: 7c09 .| LDRB r1,[r1,#0x10] - 0x0000566a: 4300 .C ORRS r0,r0,r0 - 0x0000566c: 49d9 .I LDR r1,[pc,#868] ; [0x59d4] = 0x10008040 - 0x0000566e: 7c09 .| LDRB r1,[r1,#0x10] - 0x00005670: 4308 .C ORRS r0,r0,r1 - 0x00005672: 49d7 .I LDR r1,[pc,#860] ; [0x59d0] = 0x10004fe0 - 0x00005674: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00005676: 2100 .! MOVS r1,#0 - 0x00005678: 4bd6 .K LDR r3,[pc,#856] ; [0x59d4] = 0x10008040 - 0x0000567a: 7c5b [| LDRB r3,[r3,#0x11] - 0x0000567c: 4309 .C ORRS r1,r1,r1 - 0x0000567e: 4bd5 .K LDR r3,[pc,#852] ; [0x59d4] = 0x10008040 - 0x00005680: 7c5b [| LDRB r3,[r3,#0x11] - 0x00005682: 4319 .C ORRS r1,r1,r3 - 0x00005684: 0209 .. LSLS r1,r1,#8 - 0x00005686: 4308 .C ORRS r0,r0,r1 - 0x00005688: 2140 @! MOVS r1,#0x40 - 0x0000568a: 4388 .C BICS r0,r0,r1 - 0x0000568c: 1200 .. ASRS r0,r0,#8 - 0x0000568e: 49d1 .I LDR r1,[pc,#836] ; [0x59d4] = 0x10008040 - 0x00005690: 7448 Ht STRB r0,[r1,#0x11] - 0x00005692: bf00 .. NOP - 0x00005694: bf00 .. NOP - 0x00005696: bd00 .. POP {pc} - Audio_AdcFilterInit - 0x00005698: b570 p. PUSH {r4-r6,lr} - 0x0000569a: 48cf .H LDR r0,[pc,#828] ; [0x59d8] = 0x292 - 0x0000569c: f7fdffad .... BL Audio_GetCoefStartAddr ; 0x35fa - 0x000056a0: 4606 .F MOV r6,r0 - 0x000056a2: 4ace .J LDR r2,[pc,#824] ; [0x59dc] = 0x10000285 - 0x000056a4: 21ff .! MOVS r1,#0xff - 0x000056a6: 3151 Q1 ADDS r1,r1,#0x51 - 0x000056a8: 4630 0F MOV r0,r6 - 0x000056aa: f001ff15 .... BL QSPI_ReadFlashDataToXRAM ; 0x74d8 - 0x000056ae: bf00 .. NOP - 0x000056b0: 2010 . MOVS r0,#0x10 - 0x000056b2: 49c8 .I LDR r1,[pc,#800] ; [0x59d4] = 0x10008040 - 0x000056b4: 31c0 .1 ADDS r1,r1,#0xc0 - 0x000056b6: 7748 Hw STRB r0,[r1,#0x1d] - 0x000056b8: 7748 Hw STRB r0,[r1,#0x1d] - 0x000056ba: bf00 .. NOP - 0x000056bc: 2400 .$ MOVS r4,#0 - 0x000056be: e071 q. B 0x57a4 ; Audio_AdcFilterInit + 268 - 0x000056c0: 48c3 .H LDR r0,[pc,#780] ; [0x59d0] = 0x10004fe0 - 0x000056c2: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x000056c4: 2000 . MOVS r0,#0 - 0x000056c6: 0061 a. LSLS r1,r4,#1 - 0x000056c8: 1861 a. ADDS r1,r4,r1 - 0x000056ca: 4ac3 .J LDR r2,[pc,#780] ; [0x59d8] = 0x292 - 0x000056cc: 3a0d .: SUBS r2,r2,#0xd - 0x000056ce: 1889 .. ADDS r1,r1,r2 - 0x000056d0: 2201 ." MOVS r2,#1 - 0x000056d2: 0712 .. LSLS r2,r2,#28 - 0x000056d4: 1889 .. ADDS r1,r1,r2 - 0x000056d6: 7809 .x LDRB r1,[r1,#0] - 0x000056d8: 4300 .C ORRS r0,r0,r0 - 0x000056da: 0061 a. LSLS r1,r4,#1 - 0x000056dc: 1861 a. ADDS r1,r4,r1 - 0x000056de: 4abe .J LDR r2,[pc,#760] ; [0x59d8] = 0x292 - 0x000056e0: 3a0d .: SUBS r2,r2,#0xd - 0x000056e2: 1889 .. ADDS r1,r1,r2 - 0x000056e4: 2201 ." MOVS r2,#1 - 0x000056e6: 0712 .. LSLS r2,r2,#28 - 0x000056e8: 1889 .. ADDS r1,r1,r2 - 0x000056ea: 7809 .x LDRB r1,[r1,#0] - 0x000056ec: 4308 .C ORRS r0,r0,r1 - 0x000056ee: 49b8 .I LDR r1,[pc,#736] ; [0x59d0] = 0x10004fe0 - 0x000056f0: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x000056f2: 2100 .! MOVS r1,#0 - 0x000056f4: 0062 b. LSLS r2,r4,#1 - 0x000056f6: 18a2 .. ADDS r2,r4,r2 - 0x000056f8: 4bb7 .K LDR r3,[pc,#732] ; [0x59d8] = 0x292 - 0x000056fa: 3b0d .; SUBS r3,r3,#0xd - 0x000056fc: 18d2 .. ADDS r2,r2,r3 - 0x000056fe: 1c52 R. ADDS r2,r2,#1 - 0x00005700: 2301 .# MOVS r3,#1 - 0x00005702: 071b .. LSLS r3,r3,#28 - 0x00005704: 18d2 .. ADDS r2,r2,r3 - 0x00005706: 7812 .x LDRB r2,[r2,#0] - 0x00005708: 4309 .C ORRS r1,r1,r1 - 0x0000570a: 0062 b. LSLS r2,r4,#1 - 0x0000570c: 18a2 .. ADDS r2,r4,r2 - 0x0000570e: 4bb2 .K LDR r3,[pc,#712] ; [0x59d8] = 0x292 - 0x00005710: 3b0d .; SUBS r3,r3,#0xd - 0x00005712: 18d2 .. ADDS r2,r2,r3 - 0x00005714: 1c52 R. ADDS r2,r2,#1 - 0x00005716: 2301 .# MOVS r3,#1 - 0x00005718: 071b .. LSLS r3,r3,#28 - 0x0000571a: 18d2 .. ADDS r2,r2,r3 - 0x0000571c: 7812 .x LDRB r2,[r2,#0] - 0x0000571e: 4311 .C ORRS r1,r1,r2 - 0x00005720: 0209 .. LSLS r1,r1,#8 - 0x00005722: 4308 .C ORRS r0,r0,r1 - 0x00005724: 49aa .I LDR r1,[pc,#680] ; [0x59d0] = 0x10004fe0 - 0x00005726: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00005728: 2100 .! MOVS r1,#0 - 0x0000572a: 0062 b. LSLS r2,r4,#1 - 0x0000572c: 18a2 .. ADDS r2,r4,r2 - 0x0000572e: 4baa .K LDR r3,[pc,#680] ; [0x59d8] = 0x292 - 0x00005730: 3b0d .; SUBS r3,r3,#0xd - 0x00005732: 18d2 .. ADDS r2,r2,r3 - 0x00005734: 1c92 .. ADDS r2,r2,#2 - 0x00005736: 2301 .# MOVS r3,#1 - 0x00005738: 071b .. LSLS r3,r3,#28 - 0x0000573a: 18d2 .. ADDS r2,r2,r3 - 0x0000573c: 7812 .x LDRB r2,[r2,#0] - 0x0000573e: 4309 .C ORRS r1,r1,r1 - 0x00005740: 0062 b. LSLS r2,r4,#1 - 0x00005742: 18a2 .. ADDS r2,r4,r2 - 0x00005744: 4ba4 .K LDR r3,[pc,#656] ; [0x59d8] = 0x292 - 0x00005746: 3b0d .; SUBS r3,r3,#0xd - 0x00005748: 18d2 .. ADDS r2,r2,r3 - 0x0000574a: 1c92 .. ADDS r2,r2,#2 - 0x0000574c: 2301 .# MOVS r3,#1 - 0x0000574e: 071b .. LSLS r3,r3,#28 - 0x00005750: 18d2 .. ADDS r2,r2,r3 - 0x00005752: 7812 .x LDRB r2,[r2,#0] - 0x00005754: 4311 .C ORRS r1,r1,r2 - 0x00005756: 0409 .. LSLS r1,r1,#16 - 0x00005758: 4308 .C ORRS r0,r0,r1 - 0x0000575a: 4605 .F MOV r5,r0 - 0x0000575c: bf00 .. NOP - 0x0000575e: bf00 .. NOP - 0x00005760: 499c .I LDR r1,[pc,#624] ; [0x59d4] = 0x10008040 - 0x00005762: 31c0 .1 ADDS r1,r1,#0xc0 - 0x00005764: 764d Mv STRB r5,[r1,#0x19] - 0x00005766: 764d Mv STRB r5,[r1,#0x19] - 0x00005768: bf00 .. NOP - 0x0000576a: bf00 .. NOP - 0x0000576c: 0428 (. LSLS r0,r5,#16 - 0x0000576e: 0e00 .. LSRS r0,r0,#24 - 0x00005770: 7688 .v STRB r0,[r1,#0x1a] - 0x00005772: 0428 (. LSLS r0,r5,#16 - 0x00005774: 0e00 .. LSRS r0,r0,#24 - 0x00005776: 7688 .v STRB r0,[r1,#0x1a] - 0x00005778: bf00 .. NOP - 0x0000577a: bf00 .. NOP - 0x0000577c: 0228 (. LSLS r0,r5,#8 - 0x0000577e: 0e00 .. LSRS r0,r0,#24 - 0x00005780: 76c8 .v STRB r0,[r1,#0x1b] - 0x00005782: 0228 (. LSLS r0,r5,#8 - 0x00005784: 0e00 .. LSRS r0,r0,#24 - 0x00005786: 76c8 .v STRB r0,[r1,#0x1b] - 0x00005788: bf00 .. NOP - 0x0000578a: bf00 .. NOP - 0x0000578c: bf00 .. NOP - 0x0000578e: 2030 0 MOVS r0,#0x30 - 0x00005790: 7748 Hw STRB r0,[r1,#0x1d] - 0x00005792: 7748 Hw STRB r0,[r1,#0x1d] - 0x00005794: bf00 .. NOP - 0x00005796: bf00 .. NOP - 0x00005798: 2010 . MOVS r0,#0x10 - 0x0000579a: 7748 Hw STRB r0,[r1,#0x1d] - 0x0000579c: 7748 Hw STRB r0,[r1,#0x1d] - 0x0000579e: bf00 .. NOP - 0x000057a0: 1c60 `. ADDS r0,r4,#1 - 0x000057a2: b2c4 .. UXTB r4,r0 - 0x000057a4: 2c70 p, CMP r4,#0x70 - 0x000057a6: db8b .. BLT 0x56c0 ; Audio_AdcFilterInit + 40 - 0x000057a8: 2400 .$ MOVS r4,#0 - 0x000057aa: e01c .. B 0x57e6 ; Audio_AdcFilterInit + 334 - 0x000057ac: bf00 .. NOP - 0x000057ae: bf00 .. NOP - 0x000057b0: 2000 . MOVS r0,#0 - 0x000057b2: 4988 .I LDR r1,[pc,#544] ; [0x59d4] = 0x10008040 - 0x000057b4: 31c0 .1 ADDS r1,r1,#0xc0 - 0x000057b6: 7648 Hv STRB r0,[r1,#0x19] - 0x000057b8: 7648 Hv STRB r0,[r1,#0x19] - 0x000057ba: bf00 .. NOP - 0x000057bc: bf00 .. NOP - 0x000057be: 7688 .v STRB r0,[r1,#0x1a] - 0x000057c0: 7688 .v STRB r0,[r1,#0x1a] - 0x000057c2: bf00 .. NOP - 0x000057c4: bf00 .. NOP - 0x000057c6: 76c8 .v STRB r0,[r1,#0x1b] - 0x000057c8: 76c8 .v STRB r0,[r1,#0x1b] - 0x000057ca: bf00 .. NOP - 0x000057cc: bf00 .. NOP - 0x000057ce: bf00 .. NOP - 0x000057d0: 2030 0 MOVS r0,#0x30 - 0x000057d2: 7748 Hw STRB r0,[r1,#0x1d] - 0x000057d4: 7748 Hw STRB r0,[r1,#0x1d] - 0x000057d6: bf00 .. NOP - 0x000057d8: bf00 .. NOP - 0x000057da: 2010 . MOVS r0,#0x10 - 0x000057dc: 7748 Hw STRB r0,[r1,#0x1d] - 0x000057de: 7748 Hw STRB r0,[r1,#0x1d] - 0x000057e0: bf00 .. NOP - 0x000057e2: 1c60 `. ADDS r0,r4,#1 - 0x000057e4: b2c4 .. UXTB r4,r0 - 0x000057e6: 2ce0 ., CMP r4,#0xe0 - 0x000057e8: dbe0 .. BLT 0x57ac ; Audio_AdcFilterInit + 276 - 0x000057ea: bf00 .. NOP - 0x000057ec: 2000 . MOVS r0,#0 - 0x000057ee: 4979 yI LDR r1,[pc,#484] ; [0x59d4] = 0x10008040 - 0x000057f0: 31c0 .1 ADDS r1,r1,#0xc0 - 0x000057f2: 7748 Hw STRB r0,[r1,#0x1d] - 0x000057f4: 7748 Hw STRB r0,[r1,#0x1d] - 0x000057f6: bf00 .. NOP - 0x000057f8: bd70 p. POP {r4-r6,pc} - Audio_AnaAdcHighControlEn - 0x000057fa: b510 .. PUSH {r4,lr} - 0x000057fc: 4874 tH LDR r0,[pc,#464] ; [0x59d0] = 0x10004fe0 - 0x000057fe: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00005800: 2000 . MOVS r0,#0 - 0x00005802: 4977 wI LDR r1,[pc,#476] ; [0x59e0] = 0x10004ea0 - 0x00005804: 7dc9 .} LDRB r1,[r1,#0x17] - 0x00005806: 4300 .C ORRS r0,r0,r0 - 0x00005808: 4975 uI LDR r1,[pc,#468] ; [0x59e0] = 0x10004ea0 - 0x0000580a: 7dc9 .} LDRB r1,[r1,#0x17] - 0x0000580c: 4308 .C ORRS r0,r0,r1 - 0x0000580e: 4970 pI LDR r1,[pc,#448] ; [0x59d0] = 0x10004fe0 - 0x00005810: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00005812: 2100 .! MOVS r1,#0 - 0x00005814: 4a72 rJ LDR r2,[pc,#456] ; [0x59e0] = 0x10004ea0 - 0x00005816: 7e12 .~ LDRB r2,[r2,#0x18] - 0x00005818: 4309 .C ORRS r1,r1,r1 - 0x0000581a: 4a71 qJ LDR r2,[pc,#452] ; [0x59e0] = 0x10004ea0 - 0x0000581c: 7e12 .~ LDRB r2,[r2,#0x18] - 0x0000581e: 4311 .C ORRS r1,r1,r2 - 0x00005820: 0209 .. LSLS r1,r1,#8 - 0x00005822: 4308 .C ORRS r0,r0,r1 - 0x00005824: 496a jI LDR r1,[pc,#424] ; [0x59d0] = 0x10004fe0 - 0x00005826: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00005828: 2100 .! MOVS r1,#0 - 0x0000582a: 4a6d mJ LDR r2,[pc,#436] ; [0x59e0] = 0x10004ea0 - 0x0000582c: 7e52 R~ LDRB r2,[r2,#0x19] - 0x0000582e: 4309 .C ORRS r1,r1,r1 - 0x00005830: 4a6b kJ LDR r2,[pc,#428] ; [0x59e0] = 0x10004ea0 - 0x00005832: 7e52 R~ LDRB r2,[r2,#0x19] - 0x00005834: 4311 .C ORRS r1,r1,r2 - 0x00005836: 0409 .. LSLS r1,r1,#16 - 0x00005838: 4308 .C ORRS r0,r0,r1 - 0x0000583a: 4965 eI LDR r1,[pc,#404] ; [0x59d0] = 0x10004fe0 - 0x0000583c: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x0000583e: 2100 .! MOVS r1,#0 - 0x00005840: 4a67 gJ LDR r2,[pc,#412] ; [0x59e0] = 0x10004ea0 - 0x00005842: 7e92 .~ LDRB r2,[r2,#0x1a] - 0x00005844: 4309 .C ORRS r1,r1,r1 - 0x00005846: 4a66 fJ LDR r2,[pc,#408] ; [0x59e0] = 0x10004ea0 - 0x00005848: 7e92 .~ LDRB r2,[r2,#0x1a] - 0x0000584a: 4311 .C ORRS r1,r1,r2 - 0x0000584c: 0609 .. LSLS r1,r1,#24 - 0x0000584e: 4308 .C ORRS r0,r0,r1 - 0x00005850: 4604 .F MOV r4,r0 - 0x00005852: 2001 . MOVS r0,#1 - 0x00005854: 4304 .C ORRS r4,r4,r0 - 0x00005856: 2002 . MOVS r0,#2 - 0x00005858: 4304 .C ORRS r4,r4,r0 - 0x0000585a: 4620 F MOV r0,r4 - 0x0000585c: f7fdfc4c ..L. BL Audio_LpmWrite2AdcHigh ; 0x30f8 - 0x00005860: bd10 .. POP {r4,pc} - Audio_AnaAdcLowControlEn - 0x00005862: b510 .. PUSH {r4,lr} - 0x00005864: 485a ZH LDR r0,[pc,#360] ; [0x59d0] = 0x10004fe0 - 0x00005866: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00005868: 2000 . MOVS r0,#0 - 0x0000586a: 495d ]I LDR r1,[pc,#372] ; [0x59e0] = 0x10004ea0 - 0x0000586c: 7cc9 .| LDRB r1,[r1,#0x13] - 0x0000586e: 4300 .C ORRS r0,r0,r0 - 0x00005870: 495b [I LDR r1,[pc,#364] ; [0x59e0] = 0x10004ea0 - 0x00005872: 7cc9 .| LDRB r1,[r1,#0x13] - 0x00005874: 4308 .C ORRS r0,r0,r1 - 0x00005876: 4956 VI LDR r1,[pc,#344] ; [0x59d0] = 0x10004fe0 - 0x00005878: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x0000587a: 2100 .! MOVS r1,#0 - 0x0000587c: 4a58 XJ LDR r2,[pc,#352] ; [0x59e0] = 0x10004ea0 - 0x0000587e: 7d12 .} LDRB r2,[r2,#0x14] - 0x00005880: 4309 .C ORRS r1,r1,r1 - 0x00005882: 4a57 WJ LDR r2,[pc,#348] ; [0x59e0] = 0x10004ea0 - 0x00005884: 7d12 .} LDRB r2,[r2,#0x14] - 0x00005886: 4311 .C ORRS r1,r1,r2 - 0x00005888: 0209 .. LSLS r1,r1,#8 - 0x0000588a: 4308 .C ORRS r0,r0,r1 - 0x0000588c: 4950 PI LDR r1,[pc,#320] ; [0x59d0] = 0x10004fe0 - 0x0000588e: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00005890: 2100 .! MOVS r1,#0 - 0x00005892: 4a53 SJ LDR r2,[pc,#332] ; [0x59e0] = 0x10004ea0 - 0x00005894: 7d52 R} LDRB r2,[r2,#0x15] - 0x00005896: 4309 .C ORRS r1,r1,r1 - 0x00005898: 4a51 QJ LDR r2,[pc,#324] ; [0x59e0] = 0x10004ea0 - 0x0000589a: 7d52 R} LDRB r2,[r2,#0x15] - 0x0000589c: 4311 .C ORRS r1,r1,r2 - 0x0000589e: 0409 .. LSLS r1,r1,#16 - 0x000058a0: 4308 .C ORRS r0,r0,r1 - 0x000058a2: 494b KI LDR r1,[pc,#300] ; [0x59d0] = 0x10004fe0 - 0x000058a4: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x000058a6: 2100 .! MOVS r1,#0 - 0x000058a8: 4a4d MJ LDR r2,[pc,#308] ; [0x59e0] = 0x10004ea0 - 0x000058aa: 7d92 .} LDRB r2,[r2,#0x16] - 0x000058ac: 4309 .C ORRS r1,r1,r1 - 0x000058ae: 4a4c LJ LDR r2,[pc,#304] ; [0x59e0] = 0x10004ea0 - 0x000058b0: 7d92 .} LDRB r2,[r2,#0x16] - 0x000058b2: 4311 .C ORRS r1,r1,r2 - 0x000058b4: 0609 .. LSLS r1,r1,#24 - 0x000058b6: 4308 .C ORRS r0,r0,r1 - 0x000058b8: 4604 .F MOV r4,r0 - 0x000058ba: 2001 . MOVS r0,#1 - 0x000058bc: 0680 .. LSLS r0,r0,#26 - 0x000058be: 4304 .C ORRS r4,r4,r0 - 0x000058c0: 0040 @. LSLS r0,r0,#1 - 0x000058c2: 4304 .C ORRS r4,r4,r0 - 0x000058c4: 0040 @. LSLS r0,r0,#1 - 0x000058c6: 4304 .C ORRS r4,r4,r0 - 0x000058c8: 0040 @. LSLS r0,r0,#1 - 0x000058ca: 4304 .C ORRS r4,r4,r0 - 0x000058cc: 11c0 .. ASRS r0,r0,#7 - 0x000058ce: 4304 .C ORRS r4,r4,r0 - 0x000058d0: 4620 F MOV r0,r4 - 0x000058d2: f7fdfc8d .... BL Audio_LpmWrite2AdcLow ; 0x31f0 - 0x000058d6: bd10 .. POP {r4,pc} - Audio_AnaStartAdcWork - 0x000058d8: b510 .. PUSH {r4,lr} - 0x000058da: f7fefb25 ..%. BL Audio_DaAaddaBgEn ; 0x3f28 - 0x000058de: f7ffffc0 .... BL Audio_AnaAdcLowControlEn ; 0x5862 - 0x000058e2: f7ffff8a .... BL Audio_AnaAdcHighControlEn ; 0x57fa - 0x000058e6: bd10 .. POP {r4,pc} - Audio_AdcInit - 0x000058e8: b5f7 .. PUSH {r0-r2,r4-r7,lr} - 0x000058ea: 4604 .F MOV r4,r0 - 0x000058ec: 460d .F MOV r5,r1 - 0x000058ee: 1960 `. ADDS r0,r4,r5 - 0x000058f0: 1e40 @. SUBS r0,r0,#1 - 0x000058f2: b287 .. UXTH r7,r0 - 0x000058f4: f7fffff0 .... BL Audio_AnaStartAdcWork ; 0x58d8 - 0x000058f8: f7fffece .... BL Audio_AdcFilterInit ; 0x5698 - 0x000058fc: bf00 .. NOP - 0x000058fe: bf00 .. NOP - 0x00005900: 4938 8I LDR r1,[pc,#224] ; [0x59e4] = 0x10004ac0 - 0x00005902: 724c Lr STRB r4,[r1,#9] - 0x00005904: 724c Lr STRB r4,[r1,#9] - 0x00005906: bf00 .. NOP - 0x00005908: bf00 .. NOP - 0x0000590a: 1220 . ASRS r0,r4,#8 - 0x0000590c: 7288 .r STRB r0,[r1,#0xa] - 0x0000590e: 1220 . ASRS r0,r4,#8 - 0x00005910: 7288 .r STRB r0,[r1,#0xa] - 0x00005912: bf00 .. NOP - 0x00005914: bf00 .. NOP - 0x00005916: bf00 .. NOP - 0x00005918: bf00 .. NOP - 0x0000591a: 72cd .r STRB r5,[r1,#0xb] - 0x0000591c: 72cd .r STRB r5,[r1,#0xb] - 0x0000591e: bf00 .. NOP - 0x00005920: bf00 .. NOP - 0x00005922: 1228 (. ASRS r0,r5,#8 - 0x00005924: 7308 .s STRB r0,[r1,#0xc] - 0x00005926: 1228 (. ASRS r0,r5,#8 - 0x00005928: 7308 .s STRB r0,[r1,#0xc] - 0x0000592a: bf00 .. NOP - 0x0000592c: bf00 .. NOP - 0x0000592e: bf00 .. NOP - 0x00005930: bf00 .. NOP - 0x00005932: 4928 (I LDR r1,[pc,#160] ; [0x59d4] = 0x10008040 - 0x00005934: 3920 9 SUBS r1,r1,#0x20 - 0x00005936: 770c .w STRB r4,[r1,#0x1c] - 0x00005938: 770c .w STRB r4,[r1,#0x1c] - 0x0000593a: bf00 .. NOP - 0x0000593c: bf00 .. NOP - 0x0000593e: 1220 . ASRS r0,r4,#8 - 0x00005940: 7748 Hw STRB r0,[r1,#0x1d] - 0x00005942: 1220 . ASRS r0,r4,#8 - 0x00005944: 7748 Hw STRB r0,[r1,#0x1d] - 0x00005946: bf00 .. NOP - 0x00005948: bf00 .. NOP - 0x0000594a: bf00 .. NOP - 0x0000594c: bf00 .. NOP - 0x0000594e: 778f .w STRB r7,[r1,#0x1e] - 0x00005950: 778f .w STRB r7,[r1,#0x1e] - 0x00005952: bf00 .. NOP - 0x00005954: bf00 .. NOP - 0x00005956: 1238 8. ASRS r0,r7,#8 - 0x00005958: 77c8 .w STRB r0,[r1,#0x1f] - 0x0000595a: 1238 8. ASRS r0,r7,#8 - 0x0000595c: 77c8 .w STRB r0,[r1,#0x1f] - 0x0000595e: bf00 .. NOP - 0x00005960: bf00 .. NOP - 0x00005962: bf00 .. NOP - 0x00005964: 2028 ( MOVS r0,#0x28 - 0x00005966: 491b .I LDR r1,[pc,#108] ; [0x59d4] = 0x10008040 - 0x00005968: 31c0 .1 ADDS r1,r1,#0xc0 - 0x0000596a: 7708 .w STRB r0,[r1,#0x1c] - 0x0000596c: 7708 .w STRB r0,[r1,#0x1c] - 0x0000596e: bf00 .. NOP - 0x00005970: 4817 .H LDR r0,[pc,#92] ; [0x59d0] = 0x10004fe0 - 0x00005972: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00005974: 2000 . MOVS r0,#0 - 0x00005976: 4917 .I LDR r1,[pc,#92] ; [0x59d4] = 0x10008040 - 0x00005978: 3120 1 ADDS r1,r1,#0x20 - 0x0000597a: 7949 Iy LDRB r1,[r1,#5] - 0x0000597c: 4300 .C ORRS r0,r0,r0 - 0x0000597e: 4915 .I LDR r1,[pc,#84] ; [0x59d4] = 0x10008040 - 0x00005980: 3120 1 ADDS r1,r1,#0x20 - 0x00005982: 7949 Iy LDRB r1,[r1,#5] - 0x00005984: 4308 .C ORRS r0,r0,r1 - 0x00005986: 4606 .F MOV r6,r0 - 0x00005988: 20f0 . MOVS r0,#0xf0 - 0x0000598a: 4006 .@ ANDS r6,r6,r0 - 0x0000598c: 200e . MOVS r0,#0xe - 0x0000598e: 4306 .C ORRS r6,r6,r0 - 0x00005990: bf00 .. NOP - 0x00005992: 4810 .H LDR r0,[pc,#64] ; [0x59d4] = 0x10008040 - 0x00005994: 3020 0 ADDS r0,r0,#0x20 - 0x00005996: 7146 Fq STRB r6,[r0,#5] - 0x00005998: 7146 Fq STRB r6,[r0,#5] - 0x0000599a: bf00 .. NOP - 0x0000599c: 9802 .. LDR r0,[sp,#8] - 0x0000599e: f7fffdba .... BL Audio_AdcStart8K ; 0x5516 - 0x000059a2: bdfe .. POP {r1-r7,pc} - Audio_AdcCvsdInit - 0x000059a4: b5f8 .. PUSH {r3-r7,lr} - 0x000059a6: 480a .H LDR r0,[pc,#40] ; [0x59d0] = 0x10004fe0 - 0x000059a8: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x000059aa: 2000 . MOVS r0,#0 - 0x000059ac: 490e .I LDR r1,[pc,#56] ; [0x59e8] = 0x10004380 - 0x000059ae: 7909 .y LDRB r1,[r1,#4] - 0x000059b0: 4300 .C ORRS r0,r0,r0 - 0x000059b2: 490d .I LDR r1,[pc,#52] ; [0x59e8] = 0x10004380 - 0x000059b4: 7909 .y LDRB r1,[r1,#4] - 0x000059b6: 4308 .C ORRS r0,r0,r1 - 0x000059b8: 4905 .I LDR r1,[pc,#20] ; [0x59d0] = 0x10004fe0 - 0x000059ba: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x000059bc: 2100 .! MOVS r1,#0 - 0x000059be: 4a0a .J LDR r2,[pc,#40] ; [0x59e8] = 0x10004380 - 0x000059c0: 7952 Ry LDRB r2,[r2,#5] - 0x000059c2: 4309 .C ORRS r1,r1,r1 - 0x000059c4: 4a08 .J LDR r2,[pc,#32] ; [0x59e8] = 0x10004380 - 0x000059c6: 7952 Ry LDRB r2,[r2,#5] - 0x000059c8: 4311 .C ORRS r1,r1,r2 - 0x000059ca: 0209 .. LSLS r1,r1,#8 - 0x000059cc: 4308 .C ORRS r0,r0,r1 - 0x000059ce: e00d .. B 0x59ec ; Audio_AdcCvsdInit + 72 - $d - 0x000059d0: 10004fe0 .O.. DCD 268455904 - 0x000059d4: 10008040 @... DCD 268468288 - 0x000059d8: 00000292 .... DCD 658 - 0x000059dc: 10000285 .... DCD 268436101 - 0x000059e0: 10004ea0 .N.. DCD 268455584 - 0x000059e4: 10004ac0 .J.. DCD 268454592 - 0x000059e8: 10004380 .C.. DCD 268452736 - $t - 0x000059ec: 4605 .F MOV r5,r0 - 0x000059ee: 262d -& MOVS r6,#0x2d - 0x000059f0: 0176 v. LSLS r6,r6,#5 - 0x000059f2: 48fe .H LDR r0,[pc,#1016] ; [0x5dec] = 0x10004fe0 - 0x000059f4: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x000059f6: 2000 . MOVS r0,#0 - 0x000059f8: 49fd .I LDR r1,[pc,#1012] ; [0x5df0] = 0x10004380 - 0x000059fa: 78c9 .x LDRB r1,[r1,#3] - 0x000059fc: 4300 .C ORRS r0,r0,r0 - 0x000059fe: 49fc .I LDR r1,[pc,#1008] ; [0x5df0] = 0x10004380 - 0x00005a00: 78c9 .x LDRB r1,[r1,#3] - 0x00005a02: 4308 .C ORRS r0,r0,r1 - 0x00005a04: 9000 .. STR r0,[sp,#0] - 0x00005a06: 4631 1F MOV r1,r6 - 0x00005a08: 4628 (F MOV r0,r5 - 0x00005a0a: 9a00 .. LDR r2,[sp,#0] - 0x00005a0c: f7ffff6c ..l. BL Audio_AdcInit ; 0x58e8 - 0x00005a10: bf00 .. NOP - 0x00005a12: bf00 .. NOP - 0x00005a14: 49f7 .I LDR r1,[pc,#988] ; [0x5df4] = 0x100080e0 - 0x00005a16: 770d .w STRB r5,[r1,#0x1c] - 0x00005a18: 770d .w STRB r5,[r1,#0x1c] - 0x00005a1a: bf00 .. NOP - 0x00005a1c: bf00 .. NOP - 0x00005a1e: 1228 (. ASRS r0,r5,#8 - 0x00005a20: 7748 Hw STRB r0,[r1,#0x1d] - 0x00005a22: 1228 (. ASRS r0,r5,#8 - 0x00005a24: 7748 Hw STRB r0,[r1,#0x1d] - 0x00005a26: bf00 .. NOP - 0x00005a28: bf00 .. NOP - 0x00005a2a: bf00 .. NOP - 0x00005a2c: bf00 .. NOP - 0x00005a2e: 19a8 .. ADDS r0,r5,r6 - 0x00005a30: 1e40 @. SUBS r0,r0,#1 - 0x00005a32: 49ef .I LDR r1,[pc,#956] ; [0x5df0] = 0x10004380 - 0x00005a34: 7048 Hp STRB r0,[r1,#1] - 0x00005a36: 19a8 .. ADDS r0,r5,r6 - 0x00005a38: 1e40 @. SUBS r0,r0,#1 - 0x00005a3a: 7048 Hp STRB r0,[r1,#1] - 0x00005a3c: bf00 .. NOP - 0x00005a3e: bf00 .. NOP - 0x00005a40: 19a8 .. ADDS r0,r5,r6 - 0x00005a42: 1e40 @. SUBS r0,r0,#1 - 0x00005a44: 0400 .. LSLS r0,r0,#16 - 0x00005a46: 0e00 .. LSRS r0,r0,#24 - 0x00005a48: 7088 .p STRB r0,[r1,#2] - 0x00005a4a: 19a8 .. ADDS r0,r5,r6 - 0x00005a4c: 1e40 @. SUBS r0,r0,#1 - 0x00005a4e: 0400 .. LSLS r0,r0,#16 - 0x00005a50: 0e00 .. LSRS r0,r0,#24 - 0x00005a52: 7088 .p STRB r0,[r1,#2] - 0x00005a54: bf00 .. NOP - 0x00005a56: bf00 .. NOP - 0x00005a58: 9800 .. LDR r0,[sp,#0] - 0x00005a5a: 2800 .( CMP r0,#0 - 0x00005a5c: d01f .. BEQ 0x5a9e ; Audio_AdcCvsdInit + 250 - 0x00005a5e: bf00 .. NOP - 0x00005a60: 48e2 .H LDR r0,[pc,#904] ; [0x5dec] = 0x10004fe0 - 0x00005a62: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00005a64: 2000 . MOVS r0,#0 - 0x00005a66: 49e3 .I LDR r1,[pc,#908] ; [0x5df4] = 0x100080e0 - 0x00005a68: 3920 9 SUBS r1,r1,#0x20 - 0x00005a6a: 7a89 .z LDRB r1,[r1,#0xa] - 0x00005a6c: 4300 .C ORRS r0,r0,r0 - 0x00005a6e: 49e1 .I LDR r1,[pc,#900] ; [0x5df4] = 0x100080e0 - 0x00005a70: 3920 9 SUBS r1,r1,#0x20 - 0x00005a72: 7a89 .z LDRB r1,[r1,#0xa] - 0x00005a74: 4308 .C ORRS r0,r0,r1 - 0x00005a76: 2101 .! MOVS r1,#1 - 0x00005a78: 4308 .C ORRS r0,r0,r1 - 0x00005a7a: 49de .I LDR r1,[pc,#888] ; [0x5df4] = 0x100080e0 - 0x00005a7c: 3920 9 SUBS r1,r1,#0x20 - 0x00005a7e: 7288 .r STRB r0,[r1,#0xa] - 0x00005a80: 48da .H LDR r0,[pc,#872] ; [0x5dec] = 0x10004fe0 - 0x00005a82: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00005a84: 2000 . MOVS r0,#0 - 0x00005a86: 7a89 .z LDRB r1,[r1,#0xa] - 0x00005a88: 4300 .C ORRS r0,r0,r0 - 0x00005a8a: 49da .I LDR r1,[pc,#872] ; [0x5df4] = 0x100080e0 - 0x00005a8c: 3920 9 SUBS r1,r1,#0x20 - 0x00005a8e: 7a89 .z LDRB r1,[r1,#0xa] - 0x00005a90: 4308 .C ORRS r0,r0,r1 - 0x00005a92: 2101 .! MOVS r1,#1 - 0x00005a94: 4308 .C ORRS r0,r0,r1 - 0x00005a96: 49d7 .I LDR r1,[pc,#860] ; [0x5df4] = 0x100080e0 - 0x00005a98: 3920 9 SUBS r1,r1,#0x20 - 0x00005a9a: 7288 .r STRB r0,[r1,#0xa] - 0x00005a9c: e01f .. B 0x5ade ; Audio_AdcCvsdInit + 314 - 0x00005a9e: bf00 .. NOP - 0x00005aa0: 48d2 .H LDR r0,[pc,#840] ; [0x5dec] = 0x10004fe0 - 0x00005aa2: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00005aa4: 2000 . MOVS r0,#0 - 0x00005aa6: 49d3 .I LDR r1,[pc,#844] ; [0x5df4] = 0x100080e0 - 0x00005aa8: 3920 9 SUBS r1,r1,#0x20 - 0x00005aaa: 7a89 .z LDRB r1,[r1,#0xa] - 0x00005aac: 4300 .C ORRS r0,r0,r0 - 0x00005aae: 49d1 .I LDR r1,[pc,#836] ; [0x5df4] = 0x100080e0 - 0x00005ab0: 3920 9 SUBS r1,r1,#0x20 - 0x00005ab2: 7a89 .z LDRB r1,[r1,#0xa] - 0x00005ab4: 4308 .C ORRS r0,r0,r1 - 0x00005ab6: 0840 @. LSRS r0,r0,#1 - 0x00005ab8: 0040 @. LSLS r0,r0,#1 - 0x00005aba: 49ce .I LDR r1,[pc,#824] ; [0x5df4] = 0x100080e0 - 0x00005abc: 3920 9 SUBS r1,r1,#0x20 - 0x00005abe: 7288 .r STRB r0,[r1,#0xa] - 0x00005ac0: 48ca .H LDR r0,[pc,#808] ; [0x5dec] = 0x10004fe0 - 0x00005ac2: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00005ac4: 2000 . MOVS r0,#0 - 0x00005ac6: 7a89 .z LDRB r1,[r1,#0xa] - 0x00005ac8: 4300 .C ORRS r0,r0,r0 - 0x00005aca: 49ca .I LDR r1,[pc,#808] ; [0x5df4] = 0x100080e0 - 0x00005acc: 3920 9 SUBS r1,r1,#0x20 - 0x00005ace: 7a89 .z LDRB r1,[r1,#0xa] - 0x00005ad0: 4308 .C ORRS r0,r0,r1 - 0x00005ad2: 0840 @. LSRS r0,r0,#1 - 0x00005ad4: 0040 @. LSLS r0,r0,#1 - 0x00005ad6: 49c7 .I LDR r1,[pc,#796] ; [0x5df4] = 0x100080e0 - 0x00005ad8: 3920 9 SUBS r1,r1,#0x20 - 0x00005ada: 7288 .r STRB r0,[r1,#0xa] - 0x00005adc: bf00 .. NOP - 0x00005ade: 48c3 .H LDR r0,[pc,#780] ; [0x5dec] = 0x10004fe0 - 0x00005ae0: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00005ae2: 2000 . MOVS r0,#0 - 0x00005ae4: 49c2 .I LDR r1,[pc,#776] ; [0x5df0] = 0x10004380 - 0x00005ae6: 79c9 .y LDRB r1,[r1,#7] - 0x00005ae8: 4300 .C ORRS r0,r0,r0 - 0x00005aea: 49c1 .I LDR r1,[pc,#772] ; [0x5df0] = 0x10004380 - 0x00005aec: 79c9 .y LDRB r1,[r1,#7] - 0x00005aee: 4308 .C ORRS r0,r0,r1 - 0x00005af0: 49be .I LDR r1,[pc,#760] ; [0x5dec] = 0x10004fe0 - 0x00005af2: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00005af4: 2100 .! MOVS r1,#0 - 0x00005af6: 4abe .J LDR r2,[pc,#760] ; [0x5df0] = 0x10004380 - 0x00005af8: 7a12 .z LDRB r2,[r2,#8] - 0x00005afa: 4309 .C ORRS r1,r1,r1 - 0x00005afc: 4abc .J LDR r2,[pc,#752] ; [0x5df0] = 0x10004380 - 0x00005afe: 7a12 .z LDRB r2,[r2,#8] - 0x00005b00: 4311 .C ORRS r1,r1,r2 - 0x00005b02: 0209 .. LSLS r1,r1,#8 - 0x00005b04: 4308 .C ORRS r0,r0,r1 - 0x00005b06: 4604 .F MOV r4,r0 - 0x00005b08: bf00 .. NOP - 0x00005b0a: bf00 .. NOP - 0x00005b0c: 49b9 .I LDR r1,[pc,#740] ; [0x5df4] = 0x100080e0 - 0x00005b0e: 760c .v STRB r4,[r1,#0x18] - 0x00005b10: 760c .v STRB r4,[r1,#0x18] - 0x00005b12: bf00 .. NOP - 0x00005b14: bf00 .. NOP - 0x00005b16: 1220 . ASRS r0,r4,#8 - 0x00005b18: 7648 Hv STRB r0,[r1,#0x19] - 0x00005b1a: 1220 . ASRS r0,r4,#8 - 0x00005b1c: 7648 Hv STRB r0,[r1,#0x19] - 0x00005b1e: bf00 .. NOP - 0x00005b20: bf00 .. NOP - 0x00005b22: bf00 .. NOP - 0x00005b24: bf00 .. NOP - 0x00005b26: 49b2 .I LDR r1,[pc,#712] ; [0x5df0] = 0x10004380 - 0x00005b28: 3920 9 SUBS r1,r1,#0x20 - 0x00005b2a: 77cc .w STRB r4,[r1,#0x1f] - 0x00005b2c: 77cc .w STRB r4,[r1,#0x1f] - 0x00005b2e: bf00 .. NOP - 0x00005b30: bf00 .. NOP - 0x00005b32: 1220 . ASRS r0,r4,#8 - 0x00005b34: 49ae .I LDR r1,[pc,#696] ; [0x5df0] = 0x10004380 - 0x00005b36: 7008 .p STRB r0,[r1,#0] - 0x00005b38: 1220 . ASRS r0,r4,#8 - 0x00005b3a: 7008 .p STRB r0,[r1,#0] - 0x00005b3c: bf00 .. NOP - 0x00005b3e: bf00 .. NOP - 0x00005b40: bf00 .. NOP - 0x00005b42: bf00 .. NOP - 0x00005b44: 202d - MOVS r0,#0x2d - 0x00005b46: 0100 .. LSLS r0,r0,#4 - 0x00005b48: 1820 . ADDS r0,r4,r0 - 0x00005b4a: 49a9 .I LDR r1,[pc,#676] ; [0x5df0] = 0x10004380 - 0x00005b4c: 3920 9 SUBS r1,r1,#0x20 - 0x00005b4e: 7748 Hw STRB r0,[r1,#0x1d] - 0x00005b50: 202d - MOVS r0,#0x2d - 0x00005b52: 0100 .. LSLS r0,r0,#4 - 0x00005b54: 1820 . ADDS r0,r4,r0 - 0x00005b56: 7748 Hw STRB r0,[r1,#0x1d] - 0x00005b58: bf00 .. NOP - 0x00005b5a: bf00 .. NOP - 0x00005b5c: 202d - MOVS r0,#0x2d - 0x00005b5e: 0100 .. LSLS r0,r0,#4 - 0x00005b60: 1820 . ADDS r0,r4,r0 - 0x00005b62: 0400 .. LSLS r0,r0,#16 - 0x00005b64: 0e00 .. LSRS r0,r0,#24 - 0x00005b66: 7788 .w STRB r0,[r1,#0x1e] - 0x00005b68: 202d - MOVS r0,#0x2d - 0x00005b6a: 0100 .. LSLS r0,r0,#4 - 0x00005b6c: 1820 . ADDS r0,r4,r0 - 0x00005b6e: 0400 .. LSLS r0,r0,#16 - 0x00005b70: 0e00 .. LSRS r0,r0,#24 - 0x00005b72: 7788 .w STRB r0,[r1,#0x1e] - 0x00005b74: bf00 .. NOP - 0x00005b76: bf00 .. NOP - 0x00005b78: 489c .H LDR r0,[pc,#624] ; [0x5dec] = 0x10004fe0 - 0x00005b7a: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00005b7c: 2000 . MOVS r0,#0 - 0x00005b7e: 499c .I LDR r1,[pc,#624] ; [0x5df0] = 0x10004380 - 0x00005b80: 7989 .y LDRB r1,[r1,#6] - 0x00005b82: 4300 .C ORRS r0,r0,r0 - 0x00005b84: 499a .I LDR r1,[pc,#616] ; [0x5df0] = 0x10004380 - 0x00005b86: 7989 .y LDRB r1,[r1,#6] - 0x00005b88: 4607 .F MOV r7,r0 - 0x00005b8a: 430f .C ORRS r7,r7,r1 - 0x00005b8c: 2f00 ./ CMP r7,#0 - 0x00005b8e: d01f .. BEQ 0x5bd0 ; Audio_AdcCvsdInit + 556 - 0x00005b90: bf00 .. NOP - 0x00005b92: 4896 .H LDR r0,[pc,#600] ; [0x5dec] = 0x10004fe0 - 0x00005b94: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00005b96: 2000 . MOVS r0,#0 - 0x00005b98: 4996 .I LDR r1,[pc,#600] ; [0x5df4] = 0x100080e0 - 0x00005b9a: 3920 9 SUBS r1,r1,#0x20 - 0x00005b9c: 7a89 .z LDRB r1,[r1,#0xa] - 0x00005b9e: 4300 .C ORRS r0,r0,r0 - 0x00005ba0: 4994 .I LDR r1,[pc,#592] ; [0x5df4] = 0x100080e0 - 0x00005ba2: 3920 9 SUBS r1,r1,#0x20 - 0x00005ba4: 7a89 .z LDRB r1,[r1,#0xa] - 0x00005ba6: 4308 .C ORRS r0,r0,r1 - 0x00005ba8: 2108 .! MOVS r1,#8 - 0x00005baa: 4308 .C ORRS r0,r0,r1 - 0x00005bac: 4991 .I LDR r1,[pc,#580] ; [0x5df4] = 0x100080e0 - 0x00005bae: 3920 9 SUBS r1,r1,#0x20 - 0x00005bb0: 7288 .r STRB r0,[r1,#0xa] - 0x00005bb2: 488e .H LDR r0,[pc,#568] ; [0x5dec] = 0x10004fe0 - 0x00005bb4: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00005bb6: 2000 . MOVS r0,#0 - 0x00005bb8: 7a89 .z LDRB r1,[r1,#0xa] - 0x00005bba: 4300 .C ORRS r0,r0,r0 - 0x00005bbc: 498d .I LDR r1,[pc,#564] ; [0x5df4] = 0x100080e0 - 0x00005bbe: 3920 9 SUBS r1,r1,#0x20 - 0x00005bc0: 7a89 .z LDRB r1,[r1,#0xa] - 0x00005bc2: 4308 .C ORRS r0,r0,r1 - 0x00005bc4: 2108 .! MOVS r1,#8 - 0x00005bc6: 4308 .C ORRS r0,r0,r1 - 0x00005bc8: 498a .I LDR r1,[pc,#552] ; [0x5df4] = 0x100080e0 - 0x00005bca: 3920 9 SUBS r1,r1,#0x20 - 0x00005bcc: 7288 .r STRB r0,[r1,#0xa] - 0x00005bce: e01f .. B 0x5c10 ; Audio_AdcCvsdInit + 620 - 0x00005bd0: bf00 .. NOP - 0x00005bd2: 4886 .H LDR r0,[pc,#536] ; [0x5dec] = 0x10004fe0 - 0x00005bd4: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00005bd6: 2000 . MOVS r0,#0 - 0x00005bd8: 4986 .I LDR r1,[pc,#536] ; [0x5df4] = 0x100080e0 - 0x00005bda: 3920 9 SUBS r1,r1,#0x20 - 0x00005bdc: 7a89 .z LDRB r1,[r1,#0xa] - 0x00005bde: 4300 .C ORRS r0,r0,r0 - 0x00005be0: 4984 .I LDR r1,[pc,#528] ; [0x5df4] = 0x100080e0 - 0x00005be2: 3920 9 SUBS r1,r1,#0x20 - 0x00005be4: 7a89 .z LDRB r1,[r1,#0xa] - 0x00005be6: 4308 .C ORRS r0,r0,r1 - 0x00005be8: 2108 .! MOVS r1,#8 - 0x00005bea: 4388 .C BICS r0,r0,r1 - 0x00005bec: 4981 .I LDR r1,[pc,#516] ; [0x5df4] = 0x100080e0 - 0x00005bee: 3920 9 SUBS r1,r1,#0x20 - 0x00005bf0: 7288 .r STRB r0,[r1,#0xa] - 0x00005bf2: 487e ~H LDR r0,[pc,#504] ; [0x5dec] = 0x10004fe0 - 0x00005bf4: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00005bf6: 2000 . MOVS r0,#0 - 0x00005bf8: 7a89 .z LDRB r1,[r1,#0xa] - 0x00005bfa: 4300 .C ORRS r0,r0,r0 - 0x00005bfc: 497d }I LDR r1,[pc,#500] ; [0x5df4] = 0x100080e0 - 0x00005bfe: 3920 9 SUBS r1,r1,#0x20 - 0x00005c00: 7a89 .z LDRB r1,[r1,#0xa] - 0x00005c02: 4308 .C ORRS r0,r0,r1 - 0x00005c04: 2108 .! MOVS r1,#8 - 0x00005c06: 4388 .C BICS r0,r0,r1 - 0x00005c08: 497a zI LDR r1,[pc,#488] ; [0x5df4] = 0x100080e0 - 0x00005c0a: 3920 9 SUBS r1,r1,#0x20 - 0x00005c0c: 7288 .r STRB r0,[r1,#0xa] - 0x00005c0e: bf00 .. NOP - 0x00005c10: bf00 .. NOP - 0x00005c12: bf00 .. NOP - 0x00005c14: 20cf . MOVS r0,#0xcf - 0x00005c16: 4977 wI LDR r1,[pc,#476] ; [0x5df4] = 0x100080e0 - 0x00005c18: 7688 .v STRB r0,[r1,#0x1a] - 0x00005c1a: 7688 .v STRB r0,[r1,#0x1a] - 0x00005c1c: bf00 .. NOP - 0x00005c1e: bf00 .. NOP - 0x00005c20: 2002 . MOVS r0,#2 - 0x00005c22: 76c8 .v STRB r0,[r1,#0x1b] - 0x00005c24: 76c8 .v STRB r0,[r1,#0x1b] - 0x00005c26: bf00 .. NOP - 0x00005c28: bf00 .. NOP - 0x00005c2a: f7fffc52 ..R. BL NrAec_Init ; 0x54d2 - 0x00005c2e: bdf8 .. POP {r3-r7,pc} - Audio_CvsdInitProcess - 0x00005c30: b570 p. PUSH {r4-r6,lr} - 0x00005c32: 486e nH LDR r0,[pc,#440] ; [0x5dec] = 0x10004fe0 - 0x00005c34: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00005c36: 2000 . MOVS r0,#0 - 0x00005c38: 496d mI LDR r1,[pc,#436] ; [0x5df0] = 0x10004380 - 0x00005c3a: 7a89 .z LDRB r1,[r1,#0xa] - 0x00005c3c: 4300 .C ORRS r0,r0,r0 - 0x00005c3e: 496c lI LDR r1,[pc,#432] ; [0x5df0] = 0x10004380 - 0x00005c40: 7a89 .z LDRB r1,[r1,#0xa] - 0x00005c42: 4308 .C ORRS r0,r0,r1 - 0x00005c44: 4969 iI LDR r1,[pc,#420] ; [0x5dec] = 0x10004fe0 - 0x00005c46: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00005c48: 2100 .! MOVS r1,#0 - 0x00005c4a: 4a69 iJ LDR r2,[pc,#420] ; [0x5df0] = 0x10004380 - 0x00005c4c: 7ad2 .z LDRB r2,[r2,#0xb] - 0x00005c4e: 4309 .C ORRS r1,r1,r1 - 0x00005c50: 4a67 gJ LDR r2,[pc,#412] ; [0x5df0] = 0x10004380 - 0x00005c52: 7ad2 .z LDRB r2,[r2,#0xb] - 0x00005c54: 4311 .C ORRS r1,r1,r2 - 0x00005c56: 0209 .. LSLS r1,r1,#8 - 0x00005c58: 4308 .C ORRS r0,r0,r1 - 0x00005c5a: 4604 .F MOV r4,r0 - 0x00005c5c: 202d - MOVS r0,#0x2d - 0x00005c5e: 0100 .. LSLS r0,r0,#4 - 0x00005c60: 1820 . ADDS r0,r4,r0 - 0x00005c62: b285 .. UXTH r5,r0 - 0x00005c64: f7fdfb7e ..~. BL Audio_CvsdClkEnable ; 0x3364 - 0x00005c68: f7fffe9c .... BL Audio_AdcCvsdInit ; 0x59a4 - 0x00005c6c: bf00 .. NOP - 0x00005c6e: 485f _H LDR r0,[pc,#380] ; [0x5dec] = 0x10004fe0 - 0x00005c70: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00005c72: 2000 . MOVS r0,#0 - 0x00005c74: 495f _I LDR r1,[pc,#380] ; [0x5df4] = 0x100080e0 - 0x00005c76: 3120 1 ADDS r1,r1,#0x20 - 0x00005c78: 7d89 .} LDRB r1,[r1,#0x16] - 0x00005c7a: 4300 .C ORRS r0,r0,r0 - 0x00005c7c: 495d ]I LDR r1,[pc,#372] ; [0x5df4] = 0x100080e0 - 0x00005c7e: 3120 1 ADDS r1,r1,#0x20 - 0x00005c80: 7d89 .} LDRB r1,[r1,#0x16] - 0x00005c82: 4308 .C ORRS r0,r0,r1 - 0x00005c84: 2180 .! MOVS r1,#0x80 - 0x00005c86: 4308 .C ORRS r0,r0,r1 - 0x00005c88: 495a ZI LDR r1,[pc,#360] ; [0x5df4] = 0x100080e0 - 0x00005c8a: 3120 1 ADDS r1,r1,#0x20 - 0x00005c8c: 7588 .u STRB r0,[r1,#0x16] - 0x00005c8e: 4857 WH LDR r0,[pc,#348] ; [0x5dec] = 0x10004fe0 - 0x00005c90: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00005c92: 2000 . MOVS r0,#0 - 0x00005c94: 7d89 .} LDRB r1,[r1,#0x16] - 0x00005c96: 4300 .C ORRS r0,r0,r0 - 0x00005c98: 4956 VI LDR r1,[pc,#344] ; [0x5df4] = 0x100080e0 - 0x00005c9a: 3120 1 ADDS r1,r1,#0x20 - 0x00005c9c: 7d89 .} LDRB r1,[r1,#0x16] - 0x00005c9e: 4308 .C ORRS r0,r0,r1 - 0x00005ca0: 2180 .! MOVS r1,#0x80 - 0x00005ca2: 4308 .C ORRS r0,r0,r1 - 0x00005ca4: 4953 SI LDR r1,[pc,#332] ; [0x5df4] = 0x100080e0 - 0x00005ca6: 3120 1 ADDS r1,r1,#0x20 - 0x00005ca8: 7588 .u STRB r0,[r1,#0x16] - 0x00005caa: bf00 .. NOP - 0x00005cac: bf00 .. NOP - 0x00005cae: bf00 .. NOP - 0x00005cb0: 4950 PI LDR r1,[pc,#320] ; [0x5df4] = 0x100080e0 - 0x00005cb2: 758c .u STRB r4,[r1,#0x16] - 0x00005cb4: 758c .u STRB r4,[r1,#0x16] - 0x00005cb6: bf00 .. NOP - 0x00005cb8: bf00 .. NOP - 0x00005cba: 1220 . ASRS r0,r4,#8 - 0x00005cbc: 75c8 .u STRB r0,[r1,#0x17] - 0x00005cbe: 1220 . ASRS r0,r4,#8 - 0x00005cc0: 75c8 .u STRB r0,[r1,#0x17] - 0x00005cc2: bf00 .. NOP - 0x00005cc4: bf00 .. NOP - 0x00005cc6: bf00 .. NOP - 0x00005cc8: bf00 .. NOP - 0x00005cca: 4949 II LDR r1,[pc,#292] ; [0x5df0] = 0x10004380 - 0x00005ccc: 3920 9 SUBS r1,r1,#0x20 - 0x00005cce: 764c Lv STRB r4,[r1,#0x19] - 0x00005cd0: 764c Lv STRB r4,[r1,#0x19] - 0x00005cd2: bf00 .. NOP - 0x00005cd4: bf00 .. NOP - 0x00005cd6: 1220 . ASRS r0,r4,#8 - 0x00005cd8: 7688 .v STRB r0,[r1,#0x1a] - 0x00005cda: 1220 . ASRS r0,r4,#8 - 0x00005cdc: 7688 .v STRB r0,[r1,#0x1a] - 0x00005cde: bf00 .. NOP - 0x00005ce0: bf00 .. NOP - 0x00005ce2: bf00 .. NOP - 0x00005ce4: bf00 .. NOP - 0x00005ce6: 75cd .u STRB r5,[r1,#0x17] - 0x00005ce8: 75cd .u STRB r5,[r1,#0x17] - 0x00005cea: bf00 .. NOP - 0x00005cec: bf00 .. NOP - 0x00005cee: 1228 (. ASRS r0,r5,#8 - 0x00005cf0: 7608 .v STRB r0,[r1,#0x18] - 0x00005cf2: 1228 (. ASRS r0,r5,#8 - 0x00005cf4: 7608 .v STRB r0,[r1,#0x18] - 0x00005cf6: bf00 .. NOP - 0x00005cf8: bf00 .. NOP - 0x00005cfa: 483c H LDR r0,[pc,#248] ; [0x6600] = 0x10004fe0 - 0x00006506: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00006508: 2100 .! MOVS r1,#0 - 0x0000650a: 483e >H LDR r0,[pc,#248] ; [0x6604] = 0x10008300 - 0x0000650c: 3060 `0 ADDS r0,r0,#0x60 - 0x0000650e: 7a80 .z LDRB r0,[r0,#0xa] - 0x00006510: 4309 .C ORRS r1,r1,r1 - 0x00006512: 483c . BL Audio_DacLDOOutputControl ; 0x68ee - 0x00006a72: 2002 . MOVS r0,#2 - 0x00006a74: f7ffff51 ..Q. BL Audio_AdacDacCommonModeVoltageControl ; 0x691a - 0x00006a78: f7ffff65 ..e. BL Audio_AdacLdoAvddByPassEnable ; 0x6946 - 0x00006a7c: f7ffff75 ..u. BL Audio_AdacLdoHpvddByPassEnable ; 0x696a - 0x00006a80: bf00 .. NOP - 0x00006a82: 2012 . MOVS r0,#0x12 - 0x00006a84: 49f8 .I LDR r1,[pc,#992] ; [0x6e68] = 0x10008a00 - 0x00006a86: 7008 .p STRB r0,[r1,#0] - 0x00006a88: 7008 .p STRB r0,[r1,#0] - 0x00006a8a: bf00 .. NOP - 0x00006a8c: bf00 .. NOP - 0x00006a8e: 20f2 . MOVS r0,#0xf2 - 0x00006a90: 7048 Hp STRB r0,[r1,#1] - 0x00006a92: 7048 Hp STRB r0,[r1,#1] - 0x00006a94: bf00 .. NOP - 0x00006a96: bf00 .. NOP - 0x00006a98: 2021 ! MOVS r0,#0x21 - 0x00006a9a: 7088 .p STRB r0,[r1,#2] - 0x00006a9c: 7088 .p STRB r0,[r1,#2] - 0x00006a9e: bf00 .. NOP - 0x00006aa0: bf00 .. NOP - 0x00006aa2: 20f3 . MOVS r0,#0xf3 - 0x00006aa4: 70c8 .p STRB r0,[r1,#3] - 0x00006aa6: 70c8 .p STRB r0,[r1,#3] - 0x00006aa8: bf00 .. NOP - 0x00006aaa: bf00 .. NOP - 0x00006aac: 2018 . MOVS r0,#0x18 - 0x00006aae: 7108 .q STRB r0,[r1,#4] - 0x00006ab0: 7108 .q STRB r0,[r1,#4] - 0x00006ab2: bf00 .. NOP - 0x00006ab4: bf00 .. NOP - 0x00006ab6: 2050 P MOVS r0,#0x50 - 0x00006ab8: 7148 Hq STRB r0,[r1,#5] - 0x00006aba: 7148 Hq STRB r0,[r1,#5] - 0x00006abc: bf00 .. NOP - 0x00006abe: bf00 .. NOP - 0x00006ac0: 2020 MOVS r0,#0x20 - 0x00006ac2: 7188 .q STRB r0,[r1,#6] - 0x00006ac4: 7188 .q STRB r0,[r1,#6] - 0x00006ac6: bf00 .. NOP - 0x00006ac8: bf00 .. NOP - 0x00006aca: 20d0 . MOVS r0,#0xd0 - 0x00006acc: 71c8 .q STRB r0,[r1,#7] - 0x00006ace: 71c8 .q STRB r0,[r1,#7] - 0x00006ad0: bf00 .. NOP - 0x00006ad2: 48e6 .H LDR r0,[pc,#920] ; [0x6e6c] = 0x10004fe0 - 0x00006ad4: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00006ad6: 2000 . MOVS r0,#0 - 0x00006ad8: 7909 .y LDRB r1,[r1,#4] - 0x00006ada: 4300 .C ORRS r0,r0,r0 - 0x00006adc: 49e2 .I LDR r1,[pc,#904] ; [0x6e68] = 0x10008a00 - 0x00006ade: 7909 .y LDRB r1,[r1,#4] - 0x00006ae0: 4308 .C ORRS r0,r0,r1 - 0x00006ae2: 10c0 .. ASRS r0,r0,#3 - 0x00006ae4: 2803 .( CMP r0,#3 - 0x00006ae6: db52 R. BLT 0x6b8e ; Audio_AdacPorDefaultInit + 370 - 0x00006ae8: 48e0 .H LDR r0,[pc,#896] ; [0x6e6c] = 0x10004fe0 - 0x00006aea: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00006aec: 2000 . MOVS r0,#0 - 0x00006aee: 49de .I LDR r1,[pc,#888] ; [0x6e68] = 0x10008a00 - 0x00006af0: 7909 .y LDRB r1,[r1,#4] - 0x00006af2: 4300 .C ORRS r0,r0,r0 - 0x00006af4: 49dc .I LDR r1,[pc,#880] ; [0x6e68] = 0x10008a00 - 0x00006af6: 7909 .y LDRB r1,[r1,#4] - 0x00006af8: 4308 .C ORRS r0,r0,r1 - 0x00006afa: 10c0 .. ASRS r0,r0,#3 - 0x00006afc: 2806 .( CMP r0,#6 - 0x00006afe: da46 F. BGE 0x6b8e ; Audio_AdacPorDefaultInit + 370 - 0x00006b00: 48da .H LDR r0,[pc,#872] ; [0x6e6c] = 0x10004fe0 - 0x00006b02: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00006b04: 2000 . MOVS r0,#0 - 0x00006b06: 49da .I LDR r1,[pc,#872] ; [0x6e70] = 0x10004ec0 - 0x00006b08: 79c9 .y LDRB r1,[r1,#7] - 0x00006b0a: 4300 .C ORRS r0,r0,r0 - 0x00006b0c: 49d8 .I LDR r1,[pc,#864] ; [0x6e70] = 0x10004ec0 - 0x00006b0e: 79c9 .y LDRB r1,[r1,#7] - 0x00006b10: 4308 .C ORRS r0,r0,r1 - 0x00006b12: 49d6 .I LDR r1,[pc,#856] ; [0x6e6c] = 0x10004fe0 - 0x00006b14: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00006b16: 2100 .! MOVS r1,#0 - 0x00006b18: 4ad5 .J LDR r2,[pc,#852] ; [0x6e70] = 0x10004ec0 - 0x00006b1a: 7a12 .z LDRB r2,[r2,#8] - 0x00006b1c: 4309 .C ORRS r1,r1,r1 - 0x00006b1e: 4ad4 .J LDR r2,[pc,#848] ; [0x6e70] = 0x10004ec0 - 0x00006b20: 7a12 .z LDRB r2,[r2,#8] - 0x00006b22: 4311 .C ORRS r1,r1,r2 - 0x00006b24: 0209 .. LSLS r1,r1,#8 - 0x00006b26: 4308 .C ORRS r0,r0,r1 - 0x00006b28: b200 .. SXTH r0,r0 - 0x00006b2a: 49d2 .I LDR r1,[pc,#840] ; [0x6e74] = 0x10011022 - 0x00006b2c: 8008 .. STRH r0,[r1,#0] - 0x00006b2e: 2000 . MOVS r0,#0 - 0x00006b30: 5e08 .^ LDRSH r0,[r1,r0] - 0x00006b32: 2800 .( CMP r0,#0 - 0x00006b34: db01 .. BLT 0x6b3a ; Audio_AdacPorDefaultInit + 286 - 0x00006b36: 4601 .F MOV r1,r0 - 0x00006b38: e000 .. B 0x6b3c ; Audio_AdacPorDefaultInit + 288 - 0x00006b3a: 4241 AB RSBS r1,r0,#0 - 0x00006b3c: 29f0 .) CMP r1,#0xf0 - 0x00006b3e: dd02 .. BLE 0x6b46 ; Audio_AdacPorDefaultInit + 298 - 0x00006b40: 2000 . MOVS r0,#0 - 0x00006b42: 49cc .I LDR r1,[pc,#816] ; [0x6e74] = 0x10011022 - 0x00006b44: 8008 .. STRH r0,[r1,#0] - 0x00006b46: 48c9 .H LDR r0,[pc,#804] ; [0x6e6c] = 0x10004fe0 - 0x00006b48: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00006b4a: 2000 . MOVS r0,#0 - 0x00006b4c: 49c8 .I LDR r1,[pc,#800] ; [0x6e70] = 0x10004ec0 - 0x00006b4e: 7a49 Iz LDRB r1,[r1,#9] - 0x00006b50: 4300 .C ORRS r0,r0,r0 - 0x00006b52: 49c7 .I LDR r1,[pc,#796] ; [0x6e70] = 0x10004ec0 - 0x00006b54: 7a49 Iz LDRB r1,[r1,#9] - 0x00006b56: 4308 .C ORRS r0,r0,r1 - 0x00006b58: 49c4 .I LDR r1,[pc,#784] ; [0x6e6c] = 0x10004fe0 - 0x00006b5a: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00006b5c: 2100 .! MOVS r1,#0 - 0x00006b5e: 4ac4 .J LDR r2,[pc,#784] ; [0x6e70] = 0x10004ec0 - 0x00006b60: 7a92 .z LDRB r2,[r2,#0xa] - 0x00006b62: 4309 .C ORRS r1,r1,r1 - 0x00006b64: 4ac2 .J LDR r2,[pc,#776] ; [0x6e70] = 0x10004ec0 - 0x00006b66: 7a92 .z LDRB r2,[r2,#0xa] - 0x00006b68: 4311 .C ORRS r1,r1,r2 - 0x00006b6a: 0209 .. LSLS r1,r1,#8 - 0x00006b6c: 4308 .C ORRS r0,r0,r1 - 0x00006b6e: b200 .. SXTH r0,r0 - 0x00006b70: 49c1 .I LDR r1,[pc,#772] ; [0x6e78] = 0x10011024 - 0x00006b72: 8008 .. STRH r0,[r1,#0] - 0x00006b74: 2000 . MOVS r0,#0 - 0x00006b76: 5e08 .^ LDRSH r0,[r1,r0] - 0x00006b78: 2800 .( CMP r0,#0 - 0x00006b7a: db01 .. BLT 0x6b80 ; Audio_AdacPorDefaultInit + 356 - 0x00006b7c: 4601 .F MOV r1,r0 - 0x00006b7e: e000 .. B 0x6b82 ; Audio_AdacPorDefaultInit + 358 - 0x00006b80: 4241 AB RSBS r1,r0,#0 - 0x00006b82: 29f0 .) CMP r1,#0xf0 - 0x00006b84: dd02 .. BLE 0x6b8c ; Audio_AdacPorDefaultInit + 368 - 0x00006b86: 2000 . MOVS r0,#0 - 0x00006b88: 49bb .I LDR r1,[pc,#748] ; [0x6e78] = 0x10011024 - 0x00006b8a: 8008 .. STRH r0,[r1,#0] - 0x00006b8c: e0b2 .. B 0x6cf4 ; Audio_AdacPorDefaultInit + 728 - 0x00006b8e: 48b7 .H LDR r0,[pc,#732] ; [0x6e6c] = 0x10004fe0 - 0x00006b90: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00006b92: 2000 . MOVS r0,#0 - 0x00006b94: 49b4 .I LDR r1,[pc,#720] ; [0x6e68] = 0x10008a00 - 0x00006b96: 7909 .y LDRB r1,[r1,#4] - 0x00006b98: 4300 .C ORRS r0,r0,r0 - 0x00006b9a: 49b3 .I LDR r1,[pc,#716] ; [0x6e68] = 0x10008a00 - 0x00006b9c: 7909 .y LDRB r1,[r1,#4] - 0x00006b9e: 4308 .C ORRS r0,r0,r1 - 0x00006ba0: 10c0 .. ASRS r0,r0,#3 - 0x00006ba2: 2806 .( CMP r0,#6 - 0x00006ba4: db46 F. BLT 0x6c34 ; Audio_AdacPorDefaultInit + 536 - 0x00006ba6: 48b1 .H LDR r0,[pc,#708] ; [0x6e6c] = 0x10004fe0 - 0x00006ba8: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00006baa: 2000 . MOVS r0,#0 - 0x00006bac: 49b0 .I LDR r1,[pc,#704] ; [0x6e70] = 0x10004ec0 - 0x00006bae: 7ac9 .z LDRB r1,[r1,#0xb] - 0x00006bb0: 4300 .C ORRS r0,r0,r0 - 0x00006bb2: 49af .I LDR r1,[pc,#700] ; [0x6e70] = 0x10004ec0 - 0x00006bb4: 7ac9 .z LDRB r1,[r1,#0xb] - 0x00006bb6: 4308 .C ORRS r0,r0,r1 - 0x00006bb8: 49ac .I LDR r1,[pc,#688] ; [0x6e6c] = 0x10004fe0 - 0x00006bba: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00006bbc: 2100 .! MOVS r1,#0 - 0x00006bbe: 4aac .J LDR r2,[pc,#688] ; [0x6e70] = 0x10004ec0 - 0x00006bc0: 7b12 .{ LDRB r2,[r2,#0xc] - 0x00006bc2: 4309 .C ORRS r1,r1,r1 - 0x00006bc4: 4aaa .J LDR r2,[pc,#680] ; [0x6e70] = 0x10004ec0 - 0x00006bc6: 7b12 .{ LDRB r2,[r2,#0xc] - 0x00006bc8: 4311 .C ORRS r1,r1,r2 - 0x00006bca: 0209 .. LSLS r1,r1,#8 - 0x00006bcc: 4308 .C ORRS r0,r0,r1 - 0x00006bce: b200 .. SXTH r0,r0 - 0x00006bd0: 49a8 .I LDR r1,[pc,#672] ; [0x6e74] = 0x10011022 - 0x00006bd2: 8008 .. STRH r0,[r1,#0] - 0x00006bd4: 2000 . MOVS r0,#0 - 0x00006bd6: 5e08 .^ LDRSH r0,[r1,r0] - 0x00006bd8: 2800 .( CMP r0,#0 - 0x00006bda: db01 .. BLT 0x6be0 ; Audio_AdacPorDefaultInit + 452 - 0x00006bdc: 4601 .F MOV r1,r0 - 0x00006bde: e000 .. B 0x6be2 ; Audio_AdacPorDefaultInit + 454 - 0x00006be0: 4241 AB RSBS r1,r0,#0 - 0x00006be2: 29f0 .) CMP r1,#0xf0 - 0x00006be4: dd02 .. BLE 0x6bec ; Audio_AdacPorDefaultInit + 464 - 0x00006be6: 2000 . MOVS r0,#0 - 0x00006be8: 49a2 .I LDR r1,[pc,#648] ; [0x6e74] = 0x10011022 - 0x00006bea: 8008 .. STRH r0,[r1,#0] - 0x00006bec: 489f .H LDR r0,[pc,#636] ; [0x6e6c] = 0x10004fe0 - 0x00006bee: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00006bf0: 2000 . MOVS r0,#0 - 0x00006bf2: 499f .I LDR r1,[pc,#636] ; [0x6e70] = 0x10004ec0 - 0x00006bf4: 7b49 I{ LDRB r1,[r1,#0xd] - 0x00006bf6: 4300 .C ORRS r0,r0,r0 - 0x00006bf8: 499d .I LDR r1,[pc,#628] ; [0x6e70] = 0x10004ec0 - 0x00006bfa: 7b49 I{ LDRB r1,[r1,#0xd] - 0x00006bfc: 4308 .C ORRS r0,r0,r1 - 0x00006bfe: 499b .I LDR r1,[pc,#620] ; [0x6e6c] = 0x10004fe0 - 0x00006c00: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00006c02: 2100 .! MOVS r1,#0 - 0x00006c04: 4a9a .J LDR r2,[pc,#616] ; [0x6e70] = 0x10004ec0 - 0x00006c06: 7b92 .{ LDRB r2,[r2,#0xe] - 0x00006c08: 4309 .C ORRS r1,r1,r1 - 0x00006c0a: 4a99 .J LDR r2,[pc,#612] ; [0x6e70] = 0x10004ec0 - 0x00006c0c: 7b92 .{ LDRB r2,[r2,#0xe] - 0x00006c0e: 4311 .C ORRS r1,r1,r2 - 0x00006c10: 0209 .. LSLS r1,r1,#8 - 0x00006c12: 4308 .C ORRS r0,r0,r1 - 0x00006c14: b200 .. SXTH r0,r0 - 0x00006c16: 4998 .I LDR r1,[pc,#608] ; [0x6e78] = 0x10011024 - 0x00006c18: 8008 .. STRH r0,[r1,#0] - 0x00006c1a: 2000 . MOVS r0,#0 - 0x00006c1c: 5e08 .^ LDRSH r0,[r1,r0] - 0x00006c1e: 2800 .( CMP r0,#0 - 0x00006c20: db01 .. BLT 0x6c26 ; Audio_AdacPorDefaultInit + 522 - 0x00006c22: 4601 .F MOV r1,r0 - 0x00006c24: e000 .. B 0x6c28 ; Audio_AdacPorDefaultInit + 524 - 0x00006c26: 4241 AB RSBS r1,r0,#0 - 0x00006c28: 29f0 .) CMP r1,#0xf0 - 0x00006c2a: dd63 c. BLE 0x6cf4 ; Audio_AdacPorDefaultInit + 728 - 0x00006c2c: 2000 . MOVS r0,#0 - 0x00006c2e: 4992 .I LDR r1,[pc,#584] ; [0x6e78] = 0x10011024 - 0x00006c30: 8008 .. STRH r0,[r1,#0] - 0x00006c32: e05f _. B 0x6cf4 ; Audio_AdacPorDefaultInit + 728 - 0x00006c34: 488d .H LDR r0,[pc,#564] ; [0x6e6c] = 0x10004fe0 - 0x00006c36: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00006c38: 2000 . MOVS r0,#0 - 0x00006c3a: 498b .I LDR r1,[pc,#556] ; [0x6e68] = 0x10008a00 - 0x00006c3c: 7909 .y LDRB r1,[r1,#4] - 0x00006c3e: 4300 .C ORRS r0,r0,r0 - 0x00006c40: 4989 .I LDR r1,[pc,#548] ; [0x6e68] = 0x10008a00 - 0x00006c42: 7909 .y LDRB r1,[r1,#4] - 0x00006c44: 4308 .C ORRS r0,r0,r1 - 0x00006c46: 10c0 .. ASRS r0,r0,#3 - 0x00006c48: 2800 .( CMP r0,#0 - 0x00006c4a: d153 S. BNE 0x6cf4 ; Audio_AdacPorDefaultInit + 728 - 0x00006c4c: 4887 .H LDR r0,[pc,#540] ; [0x6e6c] = 0x10004fe0 - 0x00006c4e: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00006c50: 2000 . MOVS r0,#0 - 0x00006c52: 4987 .I LDR r1,[pc,#540] ; [0x6e70] = 0x10004ec0 - 0x00006c54: 79c9 .y LDRB r1,[r1,#7] - 0x00006c56: 4300 .C ORRS r0,r0,r0 - 0x00006c58: 4985 .I LDR r1,[pc,#532] ; [0x6e70] = 0x10004ec0 - 0x00006c5a: 79c9 .y LDRB r1,[r1,#7] - 0x00006c5c: 4308 .C ORRS r0,r0,r1 - 0x00006c5e: 4983 .I LDR r1,[pc,#524] ; [0x6e6c] = 0x10004fe0 - 0x00006c60: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00006c62: 2100 .! MOVS r1,#0 - 0x00006c64: 4a82 .J LDR r2,[pc,#520] ; [0x6e70] = 0x10004ec0 - 0x00006c66: 7a12 .z LDRB r2,[r2,#8] - 0x00006c68: 4309 .C ORRS r1,r1,r1 - 0x00006c6a: 4a81 .J LDR r2,[pc,#516] ; [0x6e70] = 0x10004ec0 - 0x00006c6c: 7a12 .z LDRB r2,[r2,#8] - 0x00006c6e: 4311 .C ORRS r1,r1,r2 - 0x00006c70: 0209 .. LSLS r1,r1,#8 - 0x00006c72: 4308 .C ORRS r0,r0,r1 - 0x00006c74: b200 .. SXTH r0,r0 - 0x00006c76: 497f .I LDR r1,[pc,#508] ; [0x6e74] = 0x10011022 - 0x00006c78: 8008 .. STRH r0,[r1,#0] - 0x00006c7a: 4608 .F MOV r0,r1 - 0x00006c7c: 8800 .. LDRH r0,[r0,#0] - 0x00006c7e: 0040 @. LSLS r0,r0,#1 - 0x00006c80: b200 .. SXTH r0,r0 - 0x00006c82: 8008 .. STRH r0,[r1,#0] - 0x00006c84: 2000 . MOVS r0,#0 - 0x00006c86: 5e08 .^ LDRSH r0,[r1,r0] - 0x00006c88: 2800 .( CMP r0,#0 - 0x00006c8a: db01 .. BLT 0x6c90 ; Audio_AdacPorDefaultInit + 628 - 0x00006c8c: 4601 .F MOV r1,r0 - 0x00006c8e: e000 .. B 0x6c92 ; Audio_AdacPorDefaultInit + 630 - 0x00006c90: 4241 AB RSBS r1,r0,#0 - 0x00006c92: 22ff ." MOVS r2,#0xff - 0x00006c94: 32e1 .2 ADDS r2,r2,#0xe1 - 0x00006c96: 4291 .B CMP r1,r2 - 0x00006c98: dd02 .. BLE 0x6ca0 ; Audio_AdacPorDefaultInit + 644 - 0x00006c9a: 2000 . MOVS r0,#0 - 0x00006c9c: 4975 uI LDR r1,[pc,#468] ; [0x6e74] = 0x10011022 - 0x00006c9e: 8008 .. STRH r0,[r1,#0] - 0x00006ca0: 4872 rH LDR r0,[pc,#456] ; [0x6e6c] = 0x10004fe0 - 0x00006ca2: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00006ca4: 2000 . MOVS r0,#0 - 0x00006ca6: 4972 rI LDR r1,[pc,#456] ; [0x6e70] = 0x10004ec0 - 0x00006ca8: 7a49 Iz LDRB r1,[r1,#9] - 0x00006caa: 4300 .C ORRS r0,r0,r0 - 0x00006cac: 4970 pI LDR r1,[pc,#448] ; [0x6e70] = 0x10004ec0 - 0x00006cae: 7a49 Iz LDRB r1,[r1,#9] - 0x00006cb0: 4308 .C ORRS r0,r0,r1 - 0x00006cb2: 496e nI LDR r1,[pc,#440] ; [0x6e6c] = 0x10004fe0 - 0x00006cb4: 7fc9 .. LDRB r1,[r1,#0x1f] - 0x00006cb6: 2100 .! MOVS r1,#0 - 0x00006cb8: 4a6d mJ LDR r2,[pc,#436] ; [0x6e70] = 0x10004ec0 - 0x00006cba: 7a92 .z LDRB r2,[r2,#0xa] - 0x00006cbc: 4309 .C ORRS r1,r1,r1 - 0x00006cbe: 4a6c lJ LDR r2,[pc,#432] ; [0x6e70] = 0x10004ec0 - 0x00006cc0: 7a92 .z LDRB r2,[r2,#0xa] - 0x00006cc2: 4311 .C ORRS r1,r1,r2 - 0x00006cc4: 0209 .. LSLS r1,r1,#8 - 0x00006cc6: 4308 .C ORRS r0,r0,r1 - 0x00006cc8: b200 .. SXTH r0,r0 - 0x00006cca: 496b kI LDR r1,[pc,#428] ; [0x6e78] = 0x10011024 - 0x00006ccc: 8008 .. STRH r0,[r1,#0] - 0x00006cce: 4608 .F MOV r0,r1 - 0x00006cd0: 8800 .. LDRH r0,[r0,#0] - 0x00006cd2: 0040 @. LSLS r0,r0,#1 - 0x00006cd4: b200 .. SXTH r0,r0 - 0x00006cd6: 8008 .. STRH r0,[r1,#0] - 0x00006cd8: 2000 . MOVS r0,#0 - 0x00006cda: 5e08 .^ LDRSH r0,[r1,r0] - 0x00006cdc: 2800 .( CMP r0,#0 - 0x00006cde: db01 .. BLT 0x6ce4 ; Audio_AdacPorDefaultInit + 712 - 0x00006ce0: 4601 .F MOV r1,r0 - 0x00006ce2: e000 .. B 0x6ce6 ; Audio_AdacPorDefaultInit + 714 - 0x00006ce4: 4241 AB RSBS r1,r0,#0 - 0x00006ce6: 22ff ." MOVS r2,#0xff - 0x00006ce8: 32e1 .2 ADDS r2,r2,#0xe1 - 0x00006cea: 4291 .B CMP r1,r2 - 0x00006cec: dd02 .. BLE 0x6cf4 ; Audio_AdacPorDefaultInit + 728 - 0x00006cee: 2000 . MOVS r0,#0 - 0x00006cf0: 4961 aI LDR r1,[pc,#388] ; [0x6e78] = 0x10011024 - 0x00006cf2: 8008 .. STRH r0,[r1,#0] - 0x00006cf4: bf00 .. NOP - 0x00006cf6: bf00 .. NOP - 0x00006cf8: 485e ^H LDR r0,[pc,#376] ; [0x6e74] = 0x10011022 - 0x00006cfa: 7800 .x LDRB r0,[r0,#0] - 0x00006cfc: 495f _I LDR r1,[pc,#380] ; [0x6e7c] = 0x10008120 - 0x00006cfe: 7088 .p STRB r0,[r1,#2] - 0x00006d00: 485c \H LDR r0,[pc,#368] ; [0x6e74] = 0x10011022 - 0x00006d02: 7800 .x LDRB r0,[r0,#0] - 0x00006d04: 7088 .p STRB r0,[r1,#2] - 0x00006d06: bf00 .. NOP - 0x00006d08: bf00 .. NOP - 0x00006d0a: 485a ZH LDR r0,[pc,#360] ; [0x6e74] = 0x10011022 - 0x00006d0c: 8800 .. LDRH r0,[r0,#0] - 0x00006d0e: 0400 .. LSLS r0,r0,#16 - 0x00006d10: 0e00 .. LSRS r0,r0,#24 - 0x00006d12: 70c8 .p STRB r0,[r1,#3] - 0x00006d14: 4857 WH LDR r0,[pc,#348] ; [0x6e74] = 0x10011022 - 0x00006d16: 8800 .. LDRH r0,[r0,#0] - 0x00006d18: 0400 .. LSLS r0,r0,#16 - 0x00006d1a: 0e00 .. LSRS r0,r0,#24 - 0x00006d1c: 70c8 .p STRB r0,[r1,#3] - 0x00006d1e: bf00 .. NOP - 0x00006d20: bf00 .. NOP - 0x00006d22: bf00 .. NOP - 0x00006d24: bf00 .. NOP - 0x00006d26: 4854 TH LDR r0,[pc,#336] ; [0x6e78] = 0x10011024 - 0x00006d28: 7800 .x LDRB r0,[r0,#0] - 0x00006d2a: 7008 .p STRB r0,[r1,#0] - 0x00006d2c: 4852 RH LDR r0,[pc,#328] ; [0x6e78] = 0x10011024 - 0x00006d2e: 7800 .x LDRB r0,[r0,#0] - 0x00006d30: 7008 .p STRB r0,[r1,#0] - 0x00006d32: bf00 .. NOP - 0x00006d34: bf00 .. NOP - 0x00006d36: 4850 PH LDR r0,[pc,#320] ; [0x6e78] = 0x10011024 - 0x00006d38: 8800 .. LDRH r0,[r0,#0] - 0x00006d3a: 0400 .. LSLS r0,r0,#16 - 0x00006d3c: 0e00 .. LSRS r0,r0,#24 - 0x00006d3e: 7048 Hp STRB r0,[r1,#1] - 0x00006d40: 484d MH LDR r0,[pc,#308] ; [0x6e78] = 0x10011024 - 0x00006d42: 8800 .. LDRH r0,[r0,#0] - 0x00006d44: 0400 .. LSLS r0,r0,#16 - 0x00006d46: 0e00 .. LSRS r0,r0,#24 - 0x00006d48: 7048 Hp STRB r0,[r1,#1] - 0x00006d4a: bf00 .. NOP - 0x00006d4c: bf00 .. NOP - 0x00006d4e: bd00 .. POP {pc} - Audio_DacSetDaEnAdacOpaDummyL - 0x00006d50: bf00 .. NOP - 0x00006d52: 4846 FH LDR r0,[pc,#280] ; [0x6e6c] = 0x10004fe0 - 0x00006d54: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00006d56: 2000 . MOVS r0,#0 - 0x00006d58: 4943 CI LDR r1,[pc,#268] ; [0x6e68] = 0x10008a00 - 0x00006d5a: 7a89 .z LDRB r1,[r1,#0xa] - 0x00006d5c: 4300 .C ORRS r0,r0,r0 - 0x00006d5e: 4942 BI LDR r1,[pc,#264] ; [0x6e68] = 0x10008a00 - 0x00006d60: 7a89 .z LDRB r1,[r1,#0xa] - 0x00006d62: 4308 .C ORRS r0,r0,r1 - 0x00006d64: 2140 @! MOVS r1,#0x40 - 0x00006d66: 4308 .C ORRS r0,r0,r1 - 0x00006d68: 493f ?I LDR r1,[pc,#252] ; [0x6e68] = 0x10008a00 - 0x00006d6a: 7288 .r STRB r0,[r1,#0xa] - 0x00006d6c: 483f ?H LDR r0,[pc,#252] ; [0x6e6c] = 0x10004fe0 - 0x00006d6e: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00006d70: 2000 . MOVS r0,#0 - 0x00006d72: 7a89 .z LDRB r1,[r1,#0xa] - 0x00006d74: 4300 .C ORRS r0,r0,r0 - 0x00006d76: 493c . BL Audio_SbcStop ; 0x632e - 0x00006eb2: f7fcf8d3 .... BL Audio_DacStop ; 0x305c - 0x00006eb6: bd10 .. POP {r4,pc} - Audio_CheckDacEnable - 0x00006eb8: 4806 .H LDR r0,[pc,#24] ; [0x6ed4] = 0x10004fe0 - 0x00006eba: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00006ebc: 2000 . MOVS r0,#0 - 0x00006ebe: 4906 .I LDR r1,[pc,#24] ; [0x6ed8] = 0x10008100 - 0x00006ec0: 7989 .y LDRB r1,[r1,#6] - 0x00006ec2: 4300 .C ORRS r0,r0,r0 - 0x00006ec4: 4904 .I LDR r1,[pc,#16] ; [0x6ed8] = 0x10008100 - 0x00006ec6: 7989 .y LDRB r1,[r1,#6] - 0x00006ec8: 4308 .C ORRS r0,r0,r1 - 0x00006eca: 07c0 .. LSLS r0,r0,#31 - 0x00006ecc: 0fc0 .. LSRS r0,r0,#31 - 0x00006ece: 4770 pG BX lr - $d - 0x00006ed0: 100042a0 .B.. DCD 268452512 - 0x00006ed4: 10004fe0 .O.. DCD 268455904 - 0x00006ed8: 10008100 .... DCD 268468480 - $t - .text - SetLockQSPI - __tagsym$$noinline - 0x00006edc: bf00 .. NOP - 0x00006ede: 2001 . MOVS r0,#1 - 0x00006ee0: 49fe .I LDR r1,[pc,#1016] ; [0x72dc] = 0x10004860 - 0x00006ee2: 7648 Hv STRB r0,[r1,#0x19] - 0x00006ee4: 7648 Hv STRB r0,[r1,#0x19] - 0x00006ee6: bf00 .. NOP - 0x00006ee8: 4770 pG BX lr - SetReleaseQSPI - __tagsym$$noinline - 0x00006eea: bf00 .. NOP - 0x00006eec: 2000 . MOVS r0,#0 - 0x00006eee: 49fb .I LDR r1,[pc,#1004] ; [0x72dc] = 0x10004860 - 0x00006ef0: 7648 Hv STRB r0,[r1,#0x19] - 0x00006ef2: 7648 Hv STRB r0,[r1,#0x19] - 0x00006ef4: bf00 .. NOP - 0x00006ef6: 4770 pG BX lr - prefetch - __tagsym$$noinline - 0x00006ef8: 4602 .F MOV r2,r0 - 0x00006efa: 0950 P. LSRS r0,r2,#5 - 0x00006efc: 0140 @. LSLS r0,r0,#5 - 0x00006efe: e002 .. B 0x6f06 ; prefetch + 14 - 0x00006f00: 2300 .# MOVS r3,#0 - 0x00006f02: 6003 .` STR r3,[r0,#0] - 0x00006f04: 3020 0 ADDS r0,r0,#0x20 - 0x00006f06: 460b .F MOV r3,r1 - 0x00006f08: 3320 3 ADDS r3,r3,#0x20 - 0x00006f0a: 4298 .B CMP r0,r3 - 0x00006f0c: dbf8 .. BLT 0x6f00 ; prefetch + 8 - 0x00006f0e: 4770 pG BX lr - qspi_dma_start - 0x00006f10: b530 0. PUSH {r4,r5,lr} - 0x00006f12: bf00 .. NOP - 0x00006f14: bf00 .. NOP - 0x00006f16: 4df2 .M LDR r5,[pc,#968] ; [0x72e0] = 0x100080a0 - 0x00006f18: 7128 (q STRB r0,[r5,#4] - 0x00006f1a: 7128 (q STRB r0,[r5,#4] - 0x00006f1c: bf00 .. NOP - 0x00006f1e: bf00 .. NOP - 0x00006f20: 0404 .. LSLS r4,r0,#16 - 0x00006f22: 0e24 $. LSRS r4,r4,#24 - 0x00006f24: 716c lq STRB r4,[r5,#5] - 0x00006f26: 0404 .. LSLS r4,r0,#16 - 0x00006f28: 0e24 $. LSRS r4,r4,#24 - 0x00006f2a: 716c lq STRB r4,[r5,#5] - 0x00006f2c: bf00 .. NOP - 0x00006f2e: bf00 .. NOP - 0x00006f30: bf00 .. NOP - 0x00006f32: bf00 .. NOP - 0x00006f34: 70a9 .p STRB r1,[r5,#2] - 0x00006f36: 70a9 .p STRB r1,[r5,#2] - 0x00006f38: bf00 .. NOP - 0x00006f3a: bf00 .. NOP - 0x00006f3c: 040c .. LSLS r4,r1,#16 - 0x00006f3e: 0e24 $. LSRS r4,r4,#24 - 0x00006f40: 70ec .p STRB r4,[r5,#3] - 0x00006f42: 040c .. LSLS r4,r1,#16 - 0x00006f44: 0e24 $. LSRS r4,r4,#24 - 0x00006f46: 70ec .p STRB r4,[r5,#3] - 0x00006f48: bf00 .. NOP - 0x00006f4a: bf00 .. NOP - 0x00006f4c: bf00 .. NOP - 0x00006f4e: bf00 .. NOP - 0x00006f50: 71aa .q STRB r2,[r5,#6] - 0x00006f52: 71aa .q STRB r2,[r5,#6] - 0x00006f54: bf00 .. NOP - 0x00006f56: bf00 .. NOP - 0x00006f58: 0414 .. LSLS r4,r2,#16 - 0x00006f5a: 0e24 $. LSRS r4,r4,#24 - 0x00006f5c: 71ec .q STRB r4,[r5,#7] - 0x00006f5e: 0414 .. LSLS r4,r2,#16 - 0x00006f60: 0e24 $. LSRS r4,r4,#24 - 0x00006f62: 71ec .q STRB r4,[r5,#7] - 0x00006f64: bf00 .. NOP - 0x00006f66: bf00 .. NOP - 0x00006f68: bf00 .. NOP - 0x00006f6a: bf00 .. NOP - 0x00006f6c: 722b +r STRB r3,[r5,#8] - 0x00006f6e: 722b +r STRB r3,[r5,#8] - 0x00006f70: bf00 .. NOP - 0x00006f72: bf00 .. NOP - 0x00006f74: 041c .. LSLS r4,r3,#16 - 0x00006f76: 0e24 $. LSRS r4,r4,#24 - 0x00006f78: 726c lr STRB r4,[r5,#9] - 0x00006f7a: 041c .. LSLS r4,r3,#16 - 0x00006f7c: 0e24 $. LSRS r4,r4,#24 - 0x00006f7e: 726c lr STRB r4,[r5,#9] - 0x00006f80: bf00 .. NOP - 0x00006f82: bf00 .. NOP - 0x00006f84: bf00 .. NOP - 0x00006f86: 2408 .$ MOVS r4,#8 - 0x00006f88: 4dd5 .M LDR r5,[pc,#852] ; [0x72e0] = 0x100080a0 - 0x00006f8a: 3da0 .= SUBS r5,r5,#0xa0 - 0x00006f8c: 72ac .r STRB r4,[r5,#0xa] - 0x00006f8e: 72ac .r STRB r4,[r5,#0xa] - 0x00006f90: bf00 .. NOP - 0x00006f92: bd30 0. POP {r4,r5,pc} - qspi_dma_wait - 0x00006f94: 2100 .! MOVS r1,#0 - 0x00006f96: e006 .. B 0x6fa6 ; qspi_dma_wait + 18 - 0x00006f98: 1c49 I. ADDS r1,r1,#1 - 0x00006f9a: 2001 . MOVS r0,#1 - 0x00006f9c: 0400 .. LSLS r0,r0,#16 - 0x00006f9e: 4281 .B CMP r1,r0 - 0x00006fa0: dd01 .. BLE 0x6fa6 ; qspi_dma_wait + 18 - 0x00006fa2: 2000 . MOVS r0,#0 - 0x00006fa4: 4770 pG BX lr - 0x00006fa6: 48cf .H LDR r0,[pc,#828] ; [0x72e4] = 0x10004fe0 - 0x00006fa8: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00006faa: 2000 . MOVS r0,#0 - 0x00006fac: 4ace .J LDR r2,[pc,#824] ; [0x72e8] = 0x10008320 - 0x00006fae: 7c12 .| LDRB r2,[r2,#0x10] - 0x00006fb0: 4300 .C ORRS r0,r0,r0 - 0x00006fb2: 4acd .J LDR r2,[pc,#820] ; [0x72e8] = 0x10008320 - 0x00006fb4: 7c12 .| LDRB r2,[r2,#0x10] - 0x00006fb6: 4310 .C ORRS r0,r0,r2 - 0x00006fb8: 2208 ." MOVS r2,#8 - 0x00006fba: 4010 .@ ANDS r0,r0,r2 - 0x00006fbc: 2800 .( CMP r0,#0 - 0x00006fbe: d0eb .. BEQ 0x6f98 ; qspi_dma_wait + 4 - 0x00006fc0: 2001 . MOVS r0,#1 - 0x00006fc2: e7ef .. B 0x6fa4 ; qspi_dma_wait + 16 - qspi_write - 0x00006fc4: b5f8 .. PUSH {r3-r7,lr} - 0x00006fc6: 4606 .F MOV r6,r0 - 0x00006fc8: 460f .F MOV r7,r1 - 0x00006fca: 48c6 .H LDR r0,[pc,#792] ; [0x72e4] = 0x10004fe0 - 0x00006fcc: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00006fce: 2000 . MOVS r0,#0 - 0x00006fd0: 49c3 .I LDR r1,[pc,#780] ; [0x72e0] = 0x100080a0 - 0x00006fd2: 7809 .x LDRB r1,[r1,#0] - 0x00006fd4: 4300 .C ORRS r0,r0,r0 - 0x00006fd6: 49c2 .I LDR r1,[pc,#776] ; [0x72e0] = 0x100080a0 - 0x00006fd8: 7809 .x LDRB r1,[r1,#0] - 0x00006fda: 4308 .C ORRS r0,r0,r1 - 0x00006fdc: 4604 .F MOV r4,r0 - 0x00006fde: 48c1 .H LDR r0,[pc,#772] ; [0x72e4] = 0x10004fe0 - 0x00006fe0: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00006fe2: 2000 . MOVS r0,#0 - 0x00006fe4: 49be .I LDR r1,[pc,#760] ; [0x72e0] = 0x100080a0 - 0x00006fe6: 7849 Ix LDRB r1,[r1,#1] - 0x00006fe8: 4300 .C ORRS r0,r0,r0 - 0x00006fea: 49bd .I LDR r1,[pc,#756] ; [0x72e0] = 0x100080a0 - 0x00006fec: 7849 Ix LDRB r1,[r1,#1] - 0x00006fee: 4308 .C ORRS r0,r0,r1 - 0x00006ff0: 4605 .F MOV r5,r0 - 0x00006ff2: 2000 . MOVS r0,#0 - 0x00006ff4: 9000 .. STR r0,[sp,#0] - 0x00006ff6: bf00 .. NOP - 0x00006ff8: 2044 D MOVS r0,#0x44 - 0x00006ffa: 49b9 .I LDR r1,[pc,#740] ; [0x72e0] = 0x100080a0 - 0x00006ffc: 7008 .p STRB r0,[r1,#0] - 0x00006ffe: 7008 .p STRB r0,[r1,#0] - 0x00007000: bf00 .. NOP - 0x00007002: bf00 .. NOP - 0x00007004: 2080 . MOVS r0,#0x80 - 0x00007006: 7048 Hp STRB r0,[r1,#1] - 0x00007008: 7048 Hp STRB r0,[r1,#1] - 0x0000700a: bf00 .. NOP - 0x0000700c: 2300 .# MOVS r3,#0 - 0x0000700e: 461a .F MOV r2,r3 - 0x00007010: 4639 9F MOV r1,r7 - 0x00007012: 4630 0F MOV r0,r6 - 0x00007014: f7ffff7c ..|. BL qspi_dma_start ; 0x6f10 - 0x00007018: f7ffffbc .... BL qspi_dma_wait ; 0x6f94 - 0x0000701c: 9000 .. STR r0,[sp,#0] - 0x0000701e: bf00 .. NOP - 0x00007020: 48af .H LDR r0,[pc,#700] ; [0x72e0] = 0x100080a0 - 0x00007022: 7004 .p STRB r4,[r0,#0] - 0x00007024: 7004 .p STRB r4,[r0,#0] - 0x00007026: bf00 .. NOP - 0x00007028: bf00 .. NOP - 0x0000702a: 7045 Ep STRB r5,[r0,#1] - 0x0000702c: 7045 Ep STRB r5,[r0,#1] - 0x0000702e: bf00 .. NOP - 0x00007030: 9800 .. LDR r0,[sp,#0] - 0x00007032: bdf8 .. POP {r3-r7,pc} - qspi_read_write - 0x00007034: b5ff .. PUSH {r0-r7,lr} - 0x00007036: b081 .. SUB sp,sp,#4 - 0x00007038: 4606 .F MOV r6,r0 - 0x0000703a: 460f .F MOV r7,r1 - 0x0000703c: 48a9 .H LDR r0,[pc,#676] ; [0x72e4] = 0x10004fe0 - 0x0000703e: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00007040: 2000 . MOVS r0,#0 - 0x00007042: 49a7 .I LDR r1,[pc,#668] ; [0x72e0] = 0x100080a0 - 0x00007044: 7809 .x LDRB r1,[r1,#0] - 0x00007046: 4300 .C ORRS r0,r0,r0 - 0x00007048: 49a5 .I LDR r1,[pc,#660] ; [0x72e0] = 0x100080a0 - 0x0000704a: 7809 .x LDRB r1,[r1,#0] - 0x0000704c: 4308 .C ORRS r0,r0,r1 - 0x0000704e: 4604 .F MOV r4,r0 - 0x00007050: 48a4 .H LDR r0,[pc,#656] ; [0x72e4] = 0x10004fe0 - 0x00007052: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x00007054: 2000 . MOVS r0,#0 - 0x00007056: 49a2 .I LDR r1,[pc,#648] ; [0x72e0] = 0x100080a0 - 0x00007058: 7849 Ix LDRB r1,[r1,#1] - 0x0000705a: 4300 .C ORRS r0,r0,r0 - 0x0000705c: 49a0 .I LDR r1,[pc,#640] ; [0x72e0] = 0x100080a0 - 0x0000705e: 7849 Ix LDRB r1,[r1,#1] - 0x00007060: 4308 .C ORRS r0,r0,r1 - 0x00007062: 4605 .F MOV r5,r0 - 0x00007064: 2000 . MOVS r0,#0 - 0x00007066: 9000 .. STR r0,[sp,#0] - 0x00007068: bf00 .. NOP - 0x0000706a: 2044 D MOVS r0,#0x44 - 0x0000706c: 499c .I LDR r1,[pc,#624] ; [0x72e0] = 0x100080a0 - 0x0000706e: 7008 .p STRB r0,[r1,#0] - 0x00007070: 7008 .p STRB r0,[r1,#0] - 0x00007072: bf00 .. NOP - 0x00007074: bf00 .. NOP - 0x00007076: 2080 . MOVS r0,#0x80 - 0x00007078: 7048 Hp STRB r0,[r1,#1] - 0x0000707a: 7048 Hp STRB r0,[r1,#1] - 0x0000707c: bf00 .. NOP - 0x0000707e: 4639 9F MOV r1,r7 - 0x00007080: 4630 0F MOV r0,r6 - 0x00007082: 9b04 .. LDR r3,[sp,#0x10] - 0x00007084: 9a03 .. LDR r2,[sp,#0xc] - 0x00007086: f7ffff43 ..C. BL qspi_dma_start ; 0x6f10 - 0x0000708a: f7ffff83 .... BL qspi_dma_wait ; 0x6f94 - 0x0000708e: 9000 .. STR r0,[sp,#0] - 0x00007090: bf00 .. NOP - 0x00007092: 4893 .H LDR r0,[pc,#588] ; [0x72e0] = 0x100080a0 - 0x00007094: 7004 .p STRB r4,[r0,#0] - 0x00007096: 7004 .p STRB r4,[r0,#0] - 0x00007098: bf00 .. NOP - 0x0000709a: bf00 .. NOP - 0x0000709c: 7045 Ep STRB r5,[r0,#1] - 0x0000709e: 7045 Ep STRB r5,[r0,#1] - 0x000070a0: bf00 .. NOP - 0x000070a2: 9800 .. LDR r0,[sp,#0] - 0x000070a4: b005 .. ADD sp,sp,#0x14 - 0x000070a6: bdf0 .. POP {r4-r7,pc} - qspi_flash_cmd - 0x000070a8: b518 .. PUSH {r3,r4,lr} - 0x000070aa: 4604 .F MOV r4,r0 - 0x000070ac: 9400 .. STR r4,[sp,#0] - 0x000070ae: 2101 .! MOVS r1,#1 - 0x000070b0: 4668 hF MOV r0,sp - 0x000070b2: f7ffff87 .... BL qspi_write ; 0x6fc4 - 0x000070b6: bd18 .. POP {r3,r4,pc} - qspi_flash_readstatus1 - 0x000070b8: b518 .. PUSH {r3,r4,lr} - 0x000070ba: 4604 .F MOV r4,r0 - 0x000070bc: 2005 . MOVS r0,#5 - 0x000070be: 9000 .. STR r0,[sp,#0] - 0x000070c0: 2301 .# MOVS r3,#1 - 0x000070c2: 4622 "F MOV r2,r4 - 0x000070c4: 4619 .F MOV r1,r3 - 0x000070c6: 4668 hF MOV r0,sp - 0x000070c8: f7ffffb4 .... BL qspi_read_write ; 0x7034 - 0x000070cc: bd18 .. POP {r3,r4,pc} - qspi_flash_readstatus2 - 0x000070ce: b518 .. PUSH {r3,r4,lr} - 0x000070d0: 4604 .F MOV r4,r0 - 0x000070d2: 2035 5 MOVS r0,#0x35 - 0x000070d4: 9000 .. STR r0,[sp,#0] - 0x000070d6: 2301 .# MOVS r3,#1 - 0x000070d8: 4622 "F MOV r2,r4 - 0x000070da: 4619 .F MOV r1,r3 - 0x000070dc: 4668 hF MOV r0,sp - 0x000070de: f7ffffa9 .... BL qspi_read_write ; 0x7034 - 0x000070e2: bd18 .. POP {r3,r4,pc} - qspi_flash_waitfinish - 0x000070e4: b518 .. PUSH {r3,r4,lr} - 0x000070e6: 2400 .$ MOVS r4,#0 - 0x000070e8: 2001 . MOVS r0,#1 - 0x000070ea: 9000 .. STR r0,[sp,#0] - 0x000070ec: e00a .. B 0x7104 ; qspi_flash_waitfinish + 32 - 0x000070ee: 4668 hF MOV r0,sp - 0x000070f0: f7ffffe2 .... BL qspi_flash_readstatus1 ; 0x70b8 - 0x000070f4: 1c60 `. ADDS r0,r4,#1 - 0x000070f6: 4604 .F MOV r4,r0 - 0x000070f8: 2101 .! MOVS r1,#1 - 0x000070fa: 0609 .. LSLS r1,r1,#24 - 0x000070fc: 4288 .B CMP r0,r1 - 0x000070fe: d901 .. BLS 0x7104 ; qspi_flash_waitfinish + 32 - 0x00007100: 2000 . MOVS r0,#0 - 0x00007102: bd18 .. POP {r3,r4,pc} - 0x00007104: 4668 hF MOV r0,sp - 0x00007106: 7800 .x LDRB r0,[r0,#0] - 0x00007108: 07c0 .. LSLS r0,r0,#31 - 0x0000710a: 0fc0 .. LSRS r0,r0,#31 - 0x0000710c: 2800 .( CMP r0,#0 - 0x0000710e: d1ee .. BNE 0x70ee ; qspi_flash_waitfinish + 10 - 0x00007110: 2001 . MOVS r0,#1 - 0x00007112: e7f6 .. B 0x7102 ; qspi_flash_waitfinish + 30 - qspi_flash_writestatus - 0x00007114: b518 .. PUSH {r3,r4,lr} - 0x00007116: 4604 .F MOV r4,r0 - 0x00007118: 2101 .! MOVS r1,#1 - 0x0000711a: 4668 hF MOV r0,sp - 0x0000711c: 7001 .p STRB r1,[r0,#0] - 0x0000711e: 7821 !x LDRB r1,[r4,#0] - 0x00007120: 7041 Ap STRB r1,[r0,#1] - 0x00007122: 7861 ax LDRB r1,[r4,#1] - 0x00007124: 7081 .p STRB r1,[r0,#2] - 0x00007126: 2006 . MOVS r0,#6 - 0x00007128: f7ffffbe .... BL qspi_flash_cmd ; 0x70a8 - 0x0000712c: 2800 .( CMP r0,#0 - 0x0000712e: d100 .. BNE 0x7132 ; qspi_flash_writestatus + 30 - 0x00007130: bd18 .. POP {r3,r4,pc} - 0x00007132: 2103 .! MOVS r1,#3 - 0x00007134: 4668 hF MOV r0,sp - 0x00007136: f7ffff45 ..E. BL qspi_write ; 0x6fc4 - 0x0000713a: f7ffffd3 .... BL qspi_flash_waitfinish ; 0x70e4 - 0x0000713e: e7f7 .. B 0x7130 ; qspi_flash_writestatus + 28 - qspi_flash_quadenable - 0x00007140: b518 .. PUSH {r3,r4,lr} - 0x00007142: 4604 .F MOV r4,r0 - 0x00007144: 2000 . MOVS r0,#0 - 0x00007146: 9000 .. STR r0,[sp,#0] - 0x00007148: 4668 hF MOV r0,sp - 0x0000714a: f7ffffb5 .... BL qspi_flash_readstatus1 ; 0x70b8 - 0x0000714e: 2800 .( CMP r0,#0 - 0x00007150: d100 .. BNE 0x7154 ; qspi_flash_quadenable + 20 - 0x00007152: bd18 .. POP {r3,r4,pc} - 0x00007154: a800 .. ADD r0,sp,#0 - 0x00007156: 3001 .0 ADDS r0,#1 - 0x00007158: f7ffffb9 .... BL qspi_flash_readstatus2 ; 0x70ce - 0x0000715c: 2800 .( CMP r0,#0 - 0x0000715e: d100 .. BNE 0x7162 ; qspi_flash_quadenable + 34 - 0x00007160: e7f7 .. B 0x7152 ; qspi_flash_quadenable + 18 - 0x00007162: 2c00 ., CMP r4,#0 - 0x00007164: d006 .. BEQ 0x7174 ; qspi_flash_quadenable + 52 - 0x00007166: 4669 iF MOV r1,sp - 0x00007168: 7848 Hx LDRB r0,[r1,#1] - 0x0000716a: 2102 .! MOVS r1,#2 - 0x0000716c: 4308 .C ORRS r0,r0,r1 - 0x0000716e: 4669 iF MOV r1,sp - 0x00007170: 7048 Hp STRB r0,[r1,#1] - 0x00007172: e005 .. B 0x7180 ; qspi_flash_quadenable + 64 - 0x00007174: 4669 iF MOV r1,sp - 0x00007176: 7848 Hx LDRB r0,[r1,#1] - 0x00007178: 21fd .! MOVS r1,#0xfd - 0x0000717a: 4008 .@ ANDS r0,r0,r1 - 0x0000717c: 4669 iF MOV r1,sp - 0x0000717e: 7048 Hp STRB r0,[r1,#1] - 0x00007180: 4668 hF MOV r0,sp - 0x00007182: f7ffffc7 .... BL qspi_flash_writestatus ; 0x7114 - 0x00007186: e7e4 .. B 0x7152 ; qspi_flash_quadenable + 18 - qspi_flash_writeenable - 0x00007188: b500 .. PUSH {lr} - 0x0000718a: 2006 . MOVS r0,#6 - 0x0000718c: f7ffff8c .... BL qspi_flash_cmd ; 0x70a8 - 0x00007190: bd00 .. POP {pc} - qspi_flash_writedisable - 0x00007192: b500 .. PUSH {lr} - 0x00007194: 2004 . MOVS r0,#4 - 0x00007196: f7ffff87 .... BL qspi_flash_cmd ; 0x70a8 - 0x0000719a: bd00 .. POP {pc} - qspi_flash_precmd - 0x0000719c: 2302 .# MOVS r3,#2 - 0x0000719e: 7003 .p STRB r3,[r0,#0] - 0x000071a0: 0213 .. LSLS r3,r2,#8 - 0x000071a2: 0e1b .. LSRS r3,r3,#24 - 0x000071a4: 7043 Cp STRB r3,[r0,#1] - 0x000071a6: 0413 .. LSLS r3,r2,#16 - 0x000071a8: 0e1b .. LSRS r3,r3,#24 - 0x000071aa: 7083 .p STRB r3,[r0,#2] - 0x000071ac: 70c2 .p STRB r2,[r0,#3] - 0x000071ae: 4770 pG BX lr - _qspi_flash_write - 0x000071b0: b5f7 .. PUSH {r0-r2,r4-r7,lr} - 0x000071b2: b0c2 .. SUB sp,sp,#0x108 - 0x000071b4: 4607 .F MOV r7,r0 - 0x000071b6: 460c .F MOV r4,r1 - 0x000071b8: 21ff .! MOVS r1,#0xff - 0x000071ba: 3105 .1 ADDS r1,#5 - 0x000071bc: a801 .. ADD r0,sp,#4 - 0x000071be: f000fac8 .... BL __aeabi_memclr ; 0x7752 - 0x000071c2: 1de0 .. ADDS r0,r4,#7 - 0x000071c4: 30f8 .0 ADDS r0,r0,#0xf8 - 0x000071c6: 0a00 .. LSRS r0,r0,#8 - 0x000071c8: 9000 .. STR r0,[sp,#0] - 0x000071ca: 2600 .& MOVS r6,#0 - 0x000071cc: 2500 .% MOVS r5,#0 - 0x000071ce: e02c ,. B 0x722a ; _qspi_flash_write + 122 - 0x000071d0: 20ff . MOVS r0,#0xff - 0x000071d2: 3001 .0 ADDS r0,#1 - 0x000071d4: 4284 .B CMP r4,r0 - 0x000071d6: d900 .. BLS 0x71da ; _qspi_flash_write + 42 - 0x000071d8: e000 .. B 0x71dc ; _qspi_flash_write + 44 - 0x000071da: 4620 F MOV r0,r4 - 0x000071dc: 4606 .F MOV r6,r0 - 0x000071de: 0228 (. LSLS r0,r5,#8 - 0x000071e0: 19c2 .. ADDS r2,r0,r7 - 0x000071e2: 2102 .! MOVS r1,#2 - 0x000071e4: a801 .. ADD r0,sp,#4 - 0x000071e6: f7ffffd9 .... BL qspi_flash_precmd ; 0x719c - 0x000071ea: 2000 . MOVS r0,#0 - 0x000071ec: e007 .. B 0x71fe ; _qspi_flash_write + 78 - 0x000071ee: 0229 ). LSLS r1,r5,#8 - 0x000071f0: 180a .. ADDS r2,r1,r0 - 0x000071f2: 9944 D. LDR r1,[sp,#0x110] - 0x000071f4: 5c8a .\ LDRB r2,[r1,r2] - 0x000071f6: 1d01 .. ADDS r1,r0,#4 - 0x000071f8: ab01 .. ADD r3,sp,#4 - 0x000071fa: 545a ZT STRB r2,[r3,r1] - 0x000071fc: 1c40 @. ADDS r0,r0,#1 - 0x000071fe: 42b0 .B CMP r0,r6 - 0x00007200: d3f5 .. BCC 0x71ee ; _qspi_flash_write + 62 - 0x00007202: f7ffffc1 .... BL qspi_flash_writeenable ; 0x7188 - 0x00007206: 2800 .( CMP r0,#0 - 0x00007208: d101 .. BNE 0x720e ; _qspi_flash_write + 94 - 0x0000720a: b045 E. ADD sp,sp,#0x114 - 0x0000720c: bdf0 .. POP {r4-r7,pc} - 0x0000720e: 1d31 1. ADDS r1,r6,#4 - 0x00007210: a801 .. ADD r0,sp,#4 - 0x00007212: f7fffed7 .... BL qspi_write ; 0x6fc4 - 0x00007216: 2800 .( CMP r0,#0 - 0x00007218: d100 .. BNE 0x721c ; _qspi_flash_write + 108 - 0x0000721a: e7f6 .. B 0x720a ; _qspi_flash_write + 90 - 0x0000721c: f7ffff62 ..b. BL qspi_flash_waitfinish ; 0x70e4 - 0x00007220: 2800 .( CMP r0,#0 - 0x00007222: d100 .. BNE 0x7226 ; _qspi_flash_write + 118 - 0x00007224: e7f1 .. B 0x720a ; _qspi_flash_write + 90 - 0x00007226: 1ba4 .. SUBS r4,r4,r6 - 0x00007228: 1c6d m. ADDS r5,r5,#1 - 0x0000722a: 9800 .. LDR r0,[sp,#0] - 0x0000722c: 4285 .B CMP r5,r0 - 0x0000722e: d3cf .. BCC 0x71d0 ; _qspi_flash_write + 32 - 0x00007230: 2001 . MOVS r0,#1 - 0x00007232: e7ea .. B 0x720a ; _qspi_flash_write + 90 - _qspi_flash_chiperase - 0x00007234: b500 .. PUSH {lr} - 0x00007236: f7ffffa7 .... BL qspi_flash_writeenable ; 0x7188 - 0x0000723a: 2800 .( CMP r0,#0 - 0x0000723c: d100 .. BNE 0x7240 ; _qspi_flash_chiperase + 12 - 0x0000723e: bd00 .. POP {pc} - 0x00007240: 20c7 . MOVS r0,#0xc7 - 0x00007242: f7ffff31 ..1. BL qspi_flash_cmd ; 0x70a8 - 0x00007246: 2800 .( CMP r0,#0 - 0x00007248: d100 .. BNE 0x724c ; _qspi_flash_chiperase + 24 - 0x0000724a: e7f8 .. B 0x723e ; _qspi_flash_chiperase + 10 - 0x0000724c: f7ffff4a ..J. BL qspi_flash_waitfinish ; 0x70e4 - 0x00007250: e7f5 .. B 0x723e ; _qspi_flash_chiperase + 10 - _qspi_flash_erase - 0x00007252: b538 8. PUSH {r3-r5,lr} - 0x00007254: 4605 .F MOV r5,r0 - 0x00007256: 460c .F MOV r4,r1 - 0x00007258: 2000 . MOVS r0,#0 - 0x0000725a: 9000 .. STR r0,[sp,#0] - 0x0000725c: f7ffff94 .... BL qspi_flash_writeenable ; 0x7188 - 0x00007260: 2800 .( CMP r0,#0 - 0x00007262: d100 .. BNE 0x7266 ; _qspi_flash_erase + 20 - 0x00007264: bd38 8. POP {r3-r5,pc} - 0x00007266: 4668 hF MOV r0,sp - 0x00007268: 7005 .p STRB r5,[r0,#0] - 0x0000726a: 0220 . LSLS r0,r4,#8 - 0x0000726c: 0e01 .. LSRS r1,r0,#24 - 0x0000726e: 4668 hF MOV r0,sp - 0x00007270: 7041 Ap STRB r1,[r0,#1] - 0x00007272: 0420 . LSLS r0,r4,#16 - 0x00007274: 0e01 .. LSRS r1,r0,#24 - 0x00007276: 4668 hF MOV r0,sp - 0x00007278: 7081 .p STRB r1,[r0,#2] - 0x0000727a: 70c4 .p STRB r4,[r0,#3] - 0x0000727c: 2104 .! MOVS r1,#4 - 0x0000727e: f7fffea1 .... BL qspi_write ; 0x6fc4 - 0x00007282: 2800 .( CMP r0,#0 - 0x00007284: d100 .. BNE 0x7288 ; _qspi_flash_erase + 54 - 0x00007286: e7ed .. B 0x7264 ; _qspi_flash_erase + 18 - 0x00007288: f7ffff2c ..,. BL qspi_flash_waitfinish ; 0x70e4 - 0x0000728c: e7ea .. B 0x7264 ; _qspi_flash_erase + 18 - _qspi_flash_read - 0x0000728e: b5ff .. PUSH {r0-r7,lr} - 0x00007290: b085 .. SUB sp,sp,#0x14 - 0x00007292: 4605 .F MOV r5,r0 - 0x00007294: 460c .F MOV r4,r1 - 0x00007296: 4616 .F MOV r6,r2 - 0x00007298: 2000 . MOVS r0,#0 - 0x0000729a: 9004 .. STR r0,[sp,#0x10] - 0x0000729c: 9002 .. STR r0,[sp,#8] - 0x0000729e: 9003 .. STR r0,[sp,#0xc] - 0x000072a0: 2005 . MOVS r0,#5 - 0x000072a2: 9001 .. STR r0,[sp,#4] - 0x000072a4: 480f .H LDR r0,[pc,#60] ; [0x72e4] = 0x10004fe0 - 0x000072a6: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x000072a8: 2000 . MOVS r0,#0 - 0x000072aa: 490d .I LDR r1,[pc,#52] ; [0x72e0] = 0x100080a0 - 0x000072ac: 7809 .x LDRB r1,[r1,#0] - 0x000072ae: 4300 .C ORRS r0,r0,r0 - 0x000072b0: 490b .I LDR r1,[pc,#44] ; [0x72e0] = 0x100080a0 - 0x000072b2: 7809 .x LDRB r1,[r1,#0] - 0x000072b4: 4308 .C ORRS r0,r0,r1 - 0x000072b6: 9000 .. STR r0,[sp,#0] - 0x000072b8: 480a .H LDR r0,[pc,#40] ; [0x72e4] = 0x10004fe0 - 0x000072ba: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x000072bc: 2000 . MOVS r0,#0 - 0x000072be: 4908 .I LDR r1,[pc,#32] ; [0x72e0] = 0x100080a0 - 0x000072c0: 7849 Ix LDRB r1,[r1,#1] - 0x000072c2: 4300 .C ORRS r0,r0,r0 - 0x000072c4: 4906 .I LDR r1,[pc,#24] ; [0x72e0] = 0x100080a0 - 0x000072c6: 7849 Ix LDRB r1,[r1,#1] - 0x000072c8: 4308 .C ORRS r0,r0,r1 - 0x000072ca: 4607 .F MOV r7,r0 - 0x000072cc: 4668 hF MOV r0,sp - 0x000072ce: 7205 .r STRB r5,[r0,#8] - 0x000072d0: 0220 . LSLS r0,r4,#8 - 0x000072d2: 0e01 .. LSRS r1,r0,#24 - 0x000072d4: 4668 hF MOV r0,sp - 0x000072d6: 7241 Ar STRB r1,[r0,#9] - 0x000072d8: 0420 . LSLS r0,r4,#16 - 0x000072da: e007 .. B 0x72ec ; _qspi_flash_read + 94 - $d - 0x000072dc: 10004860 `H.. DCD 268453984 - 0x000072e0: 100080a0 .... DCD 268468384 - 0x000072e4: 10004fe0 .O.. DCD 268455904 - 0x000072e8: 10008320 ... DCD 268469024 - $t - 0x000072ec: 0e01 .. LSRS r1,r0,#24 - 0x000072ee: 4668 hF MOV r0,sp - 0x000072f0: 7281 .r STRB r1,[r0,#0xa] - 0x000072f2: 72c4 .r STRB r4,[r0,#0xb] - 0x000072f4: 2100 .! MOVS r1,#0 - 0x000072f6: 7301 .s STRB r1,[r0,#0xc] - 0x000072f8: 2dbb .- CMP r5,#0xbb - 0x000072fa: d01a .. BEQ 0x7332 ; _qspi_flash_read + 164 - 0x000072fc: dc04 .. BGT 0x7308 ; _qspi_flash_read + 122 - 0x000072fe: 2d3b ;- CMP r5,#0x3b - 0x00007300: d007 .. BEQ 0x7312 ; _qspi_flash_read + 132 - 0x00007302: 2d6b k- CMP r5,#0x6b - 0x00007304: d14f O. BNE 0x73a6 ; _qspi_flash_read + 280 - 0x00007306: e022 ". B 0x734e ; _qspi_flash_read + 192 - 0x00007308: 2de7 .- CMP r5,#0xe7 - 0x0000730a: d03e >. BEQ 0x738a ; _qspi_flash_read + 252 - 0x0000730c: 2deb .- CMP r5,#0xeb - 0x0000730e: d14a J. BNE 0x73a6 ; _qspi_flash_read + 280 - 0x00007310: e02d -. B 0x736e ; _qspi_flash_read + 224 - 0x00007312: 2004 . MOVS r0,#4 - 0x00007314: 9001 .. STR r0,[sp,#4] - 0x00007316: bf00 .. NOP - 0x00007318: bf00 .. NOP - 0x0000731a: 2041 A MOVS r0,#0x41 - 0x0000731c: 49e8 .I LDR r1,[pc,#928] ; [0x76c0] = 0x100080a0 - 0x0000731e: 7008 .p STRB r0,[r1,#0] - 0x00007320: 7008 .p STRB r0,[r1,#0] - 0x00007322: bf00 .. NOP - 0x00007324: bf00 .. NOP - 0x00007326: 2008 . MOVS r0,#8 - 0x00007328: 7048 Hp STRB r0,[r1,#1] - 0x0000732a: 7048 Hp STRB r0,[r1,#1] - 0x0000732c: bf00 .. NOP - 0x0000732e: bf00 .. NOP - 0x00007330: e049 I. B 0x73c6 ; _qspi_flash_read + 312 - 0x00007332: bf00 .. NOP - 0x00007334: bf00 .. NOP - 0x00007336: 2051 Q MOVS r0,#0x51 - 0x00007338: 49e1 .I LDR r1,[pc,#900] ; [0x76c0] = 0x100080a0 - 0x0000733a: 7008 .p STRB r0,[r1,#0] - 0x0000733c: 7008 .p STRB r0,[r1,#0] - 0x0000733e: bf00 .. NOP - 0x00007340: bf00 .. NOP - 0x00007342: 2060 ` MOVS r0,#0x60 - 0x00007344: 7048 Hp STRB r0,[r1,#1] - 0x00007346: 7048 Hp STRB r0,[r1,#1] - 0x00007348: bf00 .. NOP - 0x0000734a: bf00 .. NOP - 0x0000734c: e03b ;. B 0x73c6 ; _qspi_flash_read + 312 - 0x0000734e: 2004 . MOVS r0,#4 - 0x00007350: 9001 .. STR r0,[sp,#4] - 0x00007352: bf00 .. NOP - 0x00007354: bf00 .. NOP - 0x00007356: 2042 B MOVS r0,#0x42 - 0x00007358: 49d9 .I LDR r1,[pc,#868] ; [0x76c0] = 0x100080a0 - 0x0000735a: 7008 .p STRB r0,[r1,#0] - 0x0000735c: 7008 .p STRB r0,[r1,#0] - 0x0000735e: bf00 .. NOP - 0x00007360: bf00 .. NOP - 0x00007362: 2008 . MOVS r0,#8 - 0x00007364: 7048 Hp STRB r0,[r1,#1] - 0x00007366: 7048 Hp STRB r0,[r1,#1] - 0x00007368: bf00 .. NOP - 0x0000736a: bf00 .. NOP - 0x0000736c: e02b +. B 0x73c6 ; _qspi_flash_read + 312 - 0x0000736e: bf00 .. NOP - 0x00007370: bf00 .. NOP - 0x00007372: 2052 R MOVS r0,#0x52 - 0x00007374: 49d2 .I LDR r1,[pc,#840] ; [0x76c0] = 0x100080a0 - 0x00007376: 7008 .p STRB r0,[r1,#0] - 0x00007378: 7008 .p STRB r0,[r1,#0] - 0x0000737a: bf00 .. NOP - 0x0000737c: bf00 .. NOP - 0x0000737e: 2064 d MOVS r0,#0x64 - 0x00007380: 7048 Hp STRB r0,[r1,#1] - 0x00007382: 7048 Hp STRB r0,[r1,#1] - 0x00007384: bf00 .. NOP - 0x00007386: bf00 .. NOP - 0x00007388: e01d .. B 0x73c6 ; _qspi_flash_read + 312 - 0x0000738a: bf00 .. NOP - 0x0000738c: bf00 .. NOP - 0x0000738e: 2052 R MOVS r0,#0x52 - 0x00007390: 49cb .I LDR r1,[pc,#812] ; [0x76c0] = 0x100080a0 - 0x00007392: 7008 .p STRB r0,[r1,#0] - 0x00007394: 7008 .p STRB r0,[r1,#0] - 0x00007396: bf00 .. NOP - 0x00007398: bf00 .. NOP - 0x0000739a: 2062 b MOVS r0,#0x62 - 0x0000739c: 7048 Hp STRB r0,[r1,#1] - 0x0000739e: 7048 Hp STRB r0,[r1,#1] - 0x000073a0: bf00 .. NOP - 0x000073a2: bf00 .. NOP - 0x000073a4: e00f .. B 0x73c6 ; _qspi_flash_read + 312 - 0x000073a6: 2004 . MOVS r0,#4 - 0x000073a8: 9001 .. STR r0,[sp,#4] - 0x000073aa: bf00 .. NOP - 0x000073ac: bf00 .. NOP - 0x000073ae: 2044 D MOVS r0,#0x44 - 0x000073b0: 49c3 .I LDR r1,[pc,#780] ; [0x76c0] = 0x100080a0 - 0x000073b2: 7008 .p STRB r0,[r1,#0] - 0x000073b4: 7008 .p STRB r0,[r1,#0] - 0x000073b6: bf00 .. NOP - 0x000073b8: bf00 .. NOP - 0x000073ba: 2000 . MOVS r0,#0 - 0x000073bc: 7048 Hp STRB r0,[r1,#1] - 0x000073be: 7048 Hp STRB r0,[r1,#1] - 0x000073c0: bf00 .. NOP - 0x000073c2: bf00 .. NOP - 0x000073c4: bf00 .. NOP - 0x000073c6: bf00 .. NOP - 0x000073c8: 4633 3F MOV r3,r6 - 0x000073ca: a802 .. ADD r0,sp,#8 - 0x000073cc: 9a08 .. LDR r2,[sp,#0x20] - 0x000073ce: 9901 .. LDR r1,[sp,#4] - 0x000073d0: f7fffd9e .... BL qspi_dma_start ; 0x6f10 - 0x000073d4: f7fffdde .... BL qspi_dma_wait ; 0x6f94 - 0x000073d8: 9004 .. STR r0,[sp,#0x10] - 0x000073da: bf00 .. NOP - 0x000073dc: 49b8 .I LDR r1,[pc,#736] ; [0x76c0] = 0x100080a0 - 0x000073de: 9800 .. LDR r0,[sp,#0] - 0x000073e0: 7008 .p STRB r0,[r1,#0] - 0x000073e2: 9800 .. LDR r0,[sp,#0] - 0x000073e4: 7008 .p STRB r0,[r1,#0] - 0x000073e6: bf00 .. NOP - 0x000073e8: bf00 .. NOP - 0x000073ea: 4608 .F MOV r0,r1 - 0x000073ec: 7047 Gp STRB r7,[r0,#1] - 0x000073ee: 7047 Gp STRB r7,[r0,#1] - 0x000073f0: bf00 .. NOP - 0x000073f2: 9804 .. LDR r0,[sp,#0x10] - 0x000073f4: b009 .. ADD sp,sp,#0x24 - 0x000073f6: bdf0 .. POP {r4-r7,pc} - _qspi_flash_JEDECID - 0x000073f8: b51c .. PUSH {r2-r4,lr} - 0x000073fa: 219f .! MOVS r1,#0x9f - 0x000073fc: 9101 .. STR r1,[sp,#4] - 0x000073fe: 2303 .# MOVS r3,#3 - 0x00007400: 466a jF MOV r2,sp - 0x00007402: 2101 .! MOVS r1,#1 - 0x00007404: a801 .. ADD r0,sp,#4 - 0x00007406: f7fffe15 .... BL qspi_read_write ; 0x7034 - 0x0000740a: 4668 hF MOV r0,sp - 0x0000740c: 7800 .x LDRB r0,[r0,#0] - 0x0000740e: 0401 .. LSLS r1,r0,#16 - 0x00007410: 4668 hF MOV r0,sp - 0x00007412: 7840 @x LDRB r0,[r0,#1] - 0x00007414: 0200 .. LSLS r0,r0,#8 - 0x00007416: 4308 .C ORRS r0,r0,r1 - 0x00007418: 4669 iF MOV r1,sp - 0x0000741a: 7889 .x LDRB r1,[r1,#2] - 0x0000741c: 4308 .C ORRS r0,r0,r1 - 0x0000741e: 4604 .F MOV r4,r0 - 0x00007420: 4620 F MOV r0,r4 - 0x00007422: bd1c .. POP {r2-r4,pc} - qspi_flash_sectorerase - 0x00007424: b510 .. PUSH {r4,lr} - 0x00007426: 4604 .F MOV r4,r0 - 0x00007428: 49a6 .I LDR r1,[pc,#664] ; [0x76c4] = 0x7425 - 0x0000742a: 48a7 .H LDR r0,[pc,#668] ; [0x76c8] = 0x6f11 - 0x0000742c: f7fffd64 ..d. BL prefetch ; 0x6ef8 - 0x00007430: 4621 !F MOV r1,r4 - 0x00007432: 2020 MOVS r0,#0x20 - 0x00007434: f7ffff0d .... BL _qspi_flash_erase ; 0x7252 - 0x00007438: bd10 .. POP {r4,pc} - qspi_flash_blockerase32k - 0x0000743a: b510 .. PUSH {r4,lr} - 0x0000743c: 4604 .F MOV r4,r0 - 0x0000743e: 49a3 .I LDR r1,[pc,#652] ; [0x76cc] = 0x743b - 0x00007440: 48a1 .H LDR r0,[pc,#644] ; [0x76c8] = 0x6f11 - 0x00007442: f7fffd59 ..Y. BL prefetch ; 0x6ef8 - 0x00007446: 4621 !F MOV r1,r4 - 0x00007448: 2052 R MOVS r0,#0x52 - 0x0000744a: f7ffff02 .... BL _qspi_flash_erase ; 0x7252 - 0x0000744e: bd10 .. POP {r4,pc} - qspi_flash_blockerase64k - 0x00007450: b510 .. PUSH {r4,lr} - 0x00007452: 4604 .F MOV r4,r0 - 0x00007454: 499e .I LDR r1,[pc,#632] ; [0x76d0] = 0x7451 - 0x00007456: 489c .H LDR r0,[pc,#624] ; [0x76c8] = 0x6f11 - 0x00007458: f7fffd4e ..N. BL prefetch ; 0x6ef8 - 0x0000745c: 4621 !F MOV r1,r4 - 0x0000745e: 20d8 . MOVS r0,#0xd8 - 0x00007460: f7fffef7 .... BL _qspi_flash_erase ; 0x7252 - 0x00007464: bd10 .. POP {r4,pc} - qspi_flash_blockerasepage - 0x00007466: b510 .. PUSH {r4,lr} - 0x00007468: 4604 .F MOV r4,r0 - 0x0000746a: 499a .I LDR r1,[pc,#616] ; [0x76d4] = 0x7467 - 0x0000746c: 4896 .H LDR r0,[pc,#600] ; [0x76c8] = 0x6f11 - 0x0000746e: f7fffd43 ..C. BL prefetch ; 0x6ef8 - 0x00007472: 4621 !F MOV r1,r4 - 0x00007474: 2081 . MOVS r0,#0x81 - 0x00007476: f7fffeec .... BL _qspi_flash_erase ; 0x7252 - 0x0000747a: bd10 .. POP {r4,pc} - qspi_flash_chiperase - 0x0000747c: b500 .. PUSH {lr} - 0x0000747e: 4996 .I LDR r1,[pc,#600] ; [0x76d8] = 0x747d - 0x00007480: 4891 .H LDR r0,[pc,#580] ; [0x76c8] = 0x6f11 - 0x00007482: f7fffd39 ..9. BL prefetch ; 0x6ef8 - 0x00007486: f7fffed5 .... BL _qspi_flash_chiperase ; 0x7234 - 0x0000748a: bd00 .. POP {pc} - qspi_flash_write - 0x0000748c: b570 p. PUSH {r4-r6,lr} - 0x0000748e: 4604 .F MOV r4,r0 - 0x00007490: 460d .F MOV r5,r1 - 0x00007492: 4616 .F MOV r6,r2 - 0x00007494: 4991 .I LDR r1,[pc,#580] ; [0x76dc] = 0x748d - 0x00007496: 488c .H LDR r0,[pc,#560] ; [0x76c8] = 0x6f11 - 0x00007498: f7fffd2e .... BL prefetch ; 0x6ef8 - 0x0000749c: 4632 2F MOV r2,r6 - 0x0000749e: 4629 )F MOV r1,r5 - 0x000074a0: 4620 F MOV r0,r4 - 0x000074a2: f7fffe85 .... BL _qspi_flash_write ; 0x71b0 - 0x000074a6: bd70 p. POP {r4-r6,pc} - qspi_flash_read - 0x000074a8: b5f0 .. PUSH {r4-r7,lr} - 0x000074aa: 4604 .F MOV r4,r0 - 0x000074ac: 460d .F MOV r5,r1 - 0x000074ae: 4616 .F MOV r6,r2 - 0x000074b0: 461f .F MOV r7,r3 - 0x000074b2: 498b .I LDR r1,[pc,#556] ; [0x76e0] = 0x74a9 - 0x000074b4: 4884 .H LDR r0,[pc,#528] ; [0x76c8] = 0x6f11 - 0x000074b6: f7fffd1f .... BL prefetch ; 0x6ef8 - 0x000074ba: 463b ;F MOV r3,r7 - 0x000074bc: 4632 2F MOV r2,r6 - 0x000074be: 4629 )F MOV r1,r5 - 0x000074c0: 4620 F MOV r0,r4 - 0x000074c2: f7fffee4 .... BL _qspi_flash_read ; 0x728e - 0x000074c6: bdf0 .. POP {r4-r7,pc} - qspi_flash_JEDECID - 0x000074c8: b500 .. PUSH {lr} - 0x000074ca: 4986 .I LDR r1,[pc,#536] ; [0x76e4] = 0x74c9 - 0x000074cc: 487e ~H LDR r0,[pc,#504] ; [0x76c8] = 0x6f11 - 0x000074ce: f7fffd13 .... BL prefetch ; 0x6ef8 - 0x000074d2: f7ffff91 .... BL _qspi_flash_JEDECID ; 0x73f8 - 0x000074d6: bd00 .. POP {pc} - QSPI_ReadFlashDataToXRAM - 0x000074d8: b5f0 .. PUSH {r4-r7,lr} - 0x000074da: b0c3 .. SUB sp,sp,#0x10c - 0x000074dc: 4605 .F MOV r5,r0 - 0x000074de: 460e .F MOV r6,r1 - 0x000074e0: 4617 .F MOV r7,r2 - 0x000074e2: 0430 0. LSLS r0,r6,#16 - 0x000074e4: 0e00 .. LSRS r0,r0,#24 - 0x000074e6: 9041 A. STR r0,[sp,#0x104] - 0x000074e8: 9841 A. LDR r0,[sp,#0x104] - 0x000074ea: 0200 .. LSLS r0,r0,#8 - 0x000074ec: 1a30 0. SUBS r0,r6,r0 - 0x000074ee: 9000 .. STR r0,[sp,#0] - 0x000074f0: b672 r. CPSID i - 0x000074f2: f7fffcf3 .... BL SetLockQSPI ; 0x6edc - 0x000074f6: 2400 .$ MOVS r4,#0 - 0x000074f8: e011 .. B 0x751e ; QSPI_ReadFlashDataToXRAM + 70 - 0x000074fa: 0220 . LSLS r0,r4,#8 - 0x000074fc: 1941 A. ADDS r1,r0,r5 - 0x000074fe: ab01 .. ADD r3,sp,#4 - 0x00007500: 22ff ." MOVS r2,#0xff - 0x00007502: 3201 .2 ADDS r2,#1 - 0x00007504: 203b ; MOVS r0,#0x3b - 0x00007506: f7ffffcf .... BL qspi_flash_read ; 0x74a8 - 0x0000750a: 9042 B. STR r0,[sp,#0x108] - 0x0000750c: 0221 !. LSLS r1,r4,#8 - 0x0000750e: 19c8 .. ADDS r0,r1,r7 - 0x00007510: 22ff ." MOVS r2,#0xff - 0x00007512: 3201 .2 ADDS r2,#1 - 0x00007514: a901 .. ADD r1,sp,#4 - 0x00007516: f7fbfb1e .... BL xmemcpy ; 0x2b56 - 0x0000751a: 1c60 `. ADDS r0,r4,#1 - 0x0000751c: b2c4 .. UXTB r4,r0 - 0x0000751e: 9841 A. LDR r0,[sp,#0x104] - 0x00007520: 4284 .B CMP r4,r0 - 0x00007522: dbea .. BLT 0x74fa ; QSPI_ReadFlashDataToXRAM + 34 - 0x00007524: 9800 .. LDR r0,[sp,#0] - 0x00007526: 2800 .( CMP r0,#0 - 0x00007528: d00e .. BEQ 0x7548 ; QSPI_ReadFlashDataToXRAM + 112 - 0x0000752a: 0220 . LSLS r0,r4,#8 - 0x0000752c: 1941 A. ADDS r1,r0,r5 - 0x0000752e: ab01 .. ADD r3,sp,#4 - 0x00007530: 203b ; MOVS r0,#0x3b - 0x00007532: 9a00 .. LDR r2,[sp,#0] - 0x00007534: f7ffffb8 .... BL qspi_flash_read ; 0x74a8 - 0x00007538: 9042 B. STR r0,[sp,#0x108] - 0x0000753a: 9900 .. LDR r1,[sp,#0] - 0x0000753c: b28a .. UXTH r2,r1 - 0x0000753e: 0221 !. LSLS r1,r4,#8 - 0x00007540: 19c8 .. ADDS r0,r1,r7 - 0x00007542: a901 .. ADD r1,sp,#4 - 0x00007544: f7fbfb07 .... BL xmemcpy ; 0x2b56 - 0x00007548: f7fffccf .... BL SetReleaseQSPI ; 0x6eea - 0x0000754c: b662 b. CPSIE i - 0x0000754e: 9842 B. LDR r0,[sp,#0x108] - 0x00007550: b043 C. ADD sp,sp,#0x10c - 0x00007552: bdf0 .. POP {r4-r7,pc} - QSPI_ReadFlashData - 0x00007554: b5f0 .. PUSH {r4-r7,lr} - 0x00007556: 4604 .F MOV r4,r0 - 0x00007558: 460d .F MOV r5,r1 - 0x0000755a: 4616 .F MOV r6,r2 - 0x0000755c: b672 r. CPSID i - 0x0000755e: f7fffcbd .... BL SetLockQSPI ; 0x6edc - 0x00007562: 4633 3F MOV r3,r6 - 0x00007564: 462a *F MOV r2,r5 - 0x00007566: 4621 !F MOV r1,r4 - 0x00007568: 203b ; MOVS r0,#0x3b - 0x0000756a: f7ffff9d .... BL qspi_flash_read ; 0x74a8 - 0x0000756e: 4607 .F MOV r7,r0 - 0x00007570: f7fffcbb .... BL SetReleaseQSPI ; 0x6eea - 0x00007574: b662 b. CPSIE i - 0x00007576: 4638 8F MOV r0,r7 - 0x00007578: bdf0 .. POP {r4-r7,pc} - QSPI_WriteFlashData - 0x0000757a: b5f8 .. PUSH {r3-r7,lr} - 0x0000757c: 4604 .F MOV r4,r0 - 0x0000757e: 460d .F MOV r5,r1 - 0x00007580: 4616 .F MOV r6,r2 - 0x00007582: b672 r. CPSID i - 0x00007584: f7fffcaa .... BL SetLockQSPI ; 0x6edc - 0x00007588: 4632 2F MOV r2,r6 - 0x0000758a: 4629 )F MOV r1,r5 - 0x0000758c: 4620 F MOV r0,r4 - 0x0000758e: f7ffff7d ..}. BL qspi_flash_write ; 0x748c - 0x00007592: 4607 .F MOV r7,r0 - 0x00007594: f7fffca9 .... BL SetReleaseQSPI ; 0x6eea - 0x00007598: b662 b. CPSIE i - 0x0000759a: 4638 8F MOV r0,r7 - 0x0000759c: bdf8 .. POP {r3-r7,pc} - QSPI_SectorEraseFlash - 0x0000759e: b530 0. PUSH {r4,r5,lr} - 0x000075a0: 4604 .F MOV r4,r0 - 0x000075a2: b672 r. CPSID i - 0x000075a4: f7fffc9a .... BL SetLockQSPI ; 0x6edc - 0x000075a8: 4620 F MOV r0,r4 - 0x000075aa: f7ffff3b ..;. BL qspi_flash_sectorerase ; 0x7424 - 0x000075ae: 4605 .F MOV r5,r0 - 0x000075b0: f7fffc9b .... BL SetReleaseQSPI ; 0x6eea - 0x000075b4: b662 b. CPSIE i - 0x000075b6: 4628 (F MOV r0,r5 - 0x000075b8: bd30 0. POP {r4,r5,pc} - _QSPI_WriteFlashData - __tagsym$$noinline - 0x000075ba: b570 p. PUSH {r4-r6,lr} - 0x000075bc: 4604 .F MOV r4,r0 - 0x000075be: 460d .F MOV r5,r1 - 0x000075c0: 4616 .F MOV r6,r2 - 0x000075c2: 4949 II LDR r1,[pc,#292] ; [0x76e8] = 0x75bb - 0x000075c4: 4849 IH LDR r0,[pc,#292] ; [0x76ec] = 0x6ef9 - 0x000075c6: f7fffc97 .... BL prefetch ; 0x6ef8 - 0x000075ca: 4632 2F MOV r2,r6 - 0x000075cc: 4629 )F MOV r1,r5 - 0x000075ce: 4620 F MOV r0,r4 - 0x000075d0: f7ffffd3 .... BL QSPI_WriteFlashData ; 0x757a - 0x000075d4: 2000 . MOVS r0,#0 - 0x000075d6: bd70 p. POP {r4-r6,pc} - _Qspi_WritebyEarsePage - 0x000075d8: b5f7 .. PUSH {r0-r2,r4-r7,lr} - 0x000075da: b0c2 .. SUB sp,sp,#0x108 - 0x000075dc: 4605 .F MOV r5,r0 - 0x000075de: 2400 .$ MOVS r4,#0 - 0x000075e0: ae01 .. ADD r6,sp,#4 - 0x000075e2: b2ef .. UXTB r7,r5 - 0x000075e4: 21ff .! MOVS r1,#0xff - 0x000075e6: 3101 .1 ADDS r1,#1 - 0x000075e8: 9843 C. LDR r0,[sp,#0x10c] - 0x000075ea: 4288 .B CMP r0,r1 - 0x000075ec: d006 .. BEQ 0x75fc ; _Qspi_WritebyEarsePage + 36 - 0x000075ee: 1be8 .. SUBS r0,r5,r7 - 0x000075f0: 1d32 2. ADDS r2,r6,#4 - 0x000075f2: f7ffffaf .... BL QSPI_ReadFlashData ; 0x7554 - 0x000075f6: 4628 (F MOV r0,r5 - 0x000075f8: f7ffff35 ..5. BL qspi_flash_blockerasepage ; 0x7466 - 0x000075fc: 2400 .$ MOVS r4,#0 - 0x000075fe: e004 .. B 0x760a ; _Qspi_WritebyEarsePage + 50 - 0x00007600: 9844 D. LDR r0,[sp,#0x110] - 0x00007602: 5d00 .] LDRB r0,[r0,r4] - 0x00007604: 1939 9. ADDS r1,r7,r4 - 0x00007606: 5470 pT STRB r0,[r6,r1] - 0x00007608: 1c64 d. ADDS r4,r4,#1 - 0x0000760a: 9843 C. LDR r0,[sp,#0x10c] - 0x0000760c: 4284 .B CMP r4,r0 - 0x0000760e: d3f7 .. BCC 0x7600 ; _Qspi_WritebyEarsePage + 40 - 0x00007610: 9844 D. LDR r0,[sp,#0x110] - 0x00007612: 5d00 .] LDRB r0,[r0,r4] - 0x00007614: 1939 9. ADDS r1,r7,r4 - 0x00007616: 5470 pT STRB r0,[r6,r1] - 0x00007618: 1be8 .. SUBS r0,r5,r7 - 0x0000761a: 4632 2F MOV r2,r6 - 0x0000761c: 21ff .! MOVS r1,#0xff - 0x0000761e: 3101 .1 ADDS r1,#1 - 0x00007620: f7ffffcb .... BL _QSPI_WriteFlashData ; 0x75ba - 0x00007624: b045 E. ADD sp,sp,#0x114 - 0x00007626: bdf0 .. POP {r4-r7,pc} - QSPI_WriteFlashDatabyPage - 0x00007628: b5fe .. PUSH {r1-r7,lr} - 0x0000762a: 4605 .F MOV r5,r0 - 0x0000762c: 460e .F MOV r6,r1 - 0x0000762e: 4617 .F MOV r7,r2 - 0x00007630: 2000 . MOVS r0,#0 - 0x00007632: 9001 .. STR r0,[sp,#4] - 0x00007634: 9000 .. STR r0,[sp,#0] - 0x00007636: 4628 (F MOV r0,r5 - 0x00007638: 17e9 .. ASRS r1,r5,#31 - 0x0000763a: 0e09 .. LSRS r1,r1,#24 - 0x0000763c: 1809 .. ADDS r1,r1,r0 - 0x0000763e: 1209 .. ASRS r1,r1,#8 - 0x00007640: 0209 .. LSLS r1,r1,#8 - 0x00007642: 1a69 i. SUBS r1,r5,r1 - 0x00007644: 22ff ." MOVS r2,#0xff - 0x00007646: 3201 .2 ADDS r2,#1 - 0x00007648: 1a54 T. SUBS r4,r2,r1 - 0x0000764a: 42b4 .B CMP r4,r6 - 0x0000764c: d901 .. BLS 0x7652 ; QSPI_WriteFlashDatabyPage + 42 - 0x0000764e: 4630 0F MOV r0,r6 - 0x00007650: e000 .. B 0x7654 ; QSPI_WriteFlashDatabyPage + 44 - 0x00007652: 4620 F MOV r0,r4 - 0x00007654: 4604 .F MOV r4,r0 - 0x00007656: 463a :F MOV r2,r7 - 0x00007658: 4621 !F MOV r1,r4 - 0x0000765a: 4628 (F MOV r0,r5 - 0x0000765c: f7ffffbc .... BL _Qspi_WritebyEarsePage ; 0x75d8 - 0x00007660: 192d -. ADDS r5,r5,r4 - 0x00007662: 193f ?. ADDS r7,r7,r4 - 0x00007664: 1b36 6. SUBS r6,r6,r4 - 0x00007666: 1df0 .. ADDS r0,r6,#7 - 0x00007668: 30f8 .0 ADDS r0,r0,#0xf8 - 0x0000766a: 17c1 .. ASRS r1,r0,#31 - 0x0000766c: 0e09 .. LSRS r1,r1,#24 - 0x0000766e: 1809 .. ADDS r1,r1,r0 - 0x00007670: 1209 .. ASRS r1,r1,#8 - 0x00007672: 9100 .. STR r1,[sp,#0] - 0x00007674: 2000 . MOVS r0,#0 - 0x00007676: 9001 .. STR r0,[sp,#4] - 0x00007678: e011 .. B 0x769e ; QSPI_WriteFlashDatabyPage + 118 - 0x0000767a: 20ff . MOVS r0,#0xff - 0x0000767c: 3001 .0 ADDS r0,#1 - 0x0000767e: 4286 .B CMP r6,r0 - 0x00007680: dd00 .. BLE 0x7684 ; QSPI_WriteFlashDatabyPage + 92 - 0x00007682: e000 .. B 0x7686 ; QSPI_WriteFlashDatabyPage + 94 - 0x00007684: 4630 0F MOV r0,r6 - 0x00007686: 4604 .F MOV r4,r0 - 0x00007688: 463a :F MOV r2,r7 - 0x0000768a: 4621 !F MOV r1,r4 - 0x0000768c: 4628 (F MOV r0,r5 - 0x0000768e: f7ffffa3 .... BL _Qspi_WritebyEarsePage ; 0x75d8 - 0x00007692: 192d -. ADDS r5,r5,r4 - 0x00007694: 193f ?. ADDS r7,r7,r4 - 0x00007696: 1b36 6. SUBS r6,r6,r4 - 0x00007698: 9801 .. LDR r0,[sp,#4] - 0x0000769a: 1c40 @. ADDS r0,r0,#1 - 0x0000769c: 9001 .. STR r0,[sp,#4] - 0x0000769e: 9900 .. LDR r1,[sp,#0] - 0x000076a0: 9801 .. LDR r0,[sp,#4] - 0x000076a2: 4288 .B CMP r0,r1 - 0x000076a4: d3e9 .. BCC 0x767a ; QSPI_WriteFlashDatabyPage + 82 - 0x000076a6: bdfe .. POP {r1-r7,pc} - YC_FlashWrite - 0x000076a8: b570 p. PUSH {r4-r6,lr} - 0x000076aa: 4604 .F MOV r4,r0 - 0x000076ac: 460d .F MOV r5,r1 - 0x000076ae: 4616 .F MOV r6,r2 - 0x000076b0: 4632 2F MOV r2,r6 - 0x000076b2: 4629 )F MOV r1,r5 - 0x000076b4: 4620 F MOV r0,r4 - 0x000076b6: f7ffffb7 .... BL QSPI_WriteFlashDatabyPage ; 0x7628 - 0x000076ba: 2000 . MOVS r0,#0 - 0x000076bc: bd70 p. POP {r4-r6,pc} - $d - 0x000076be: 0000 .. DCW 0 - 0x000076c0: 100080a0 .... DCD 268468384 - 0x000076c4: 00007425 %t.. DCD 29733 - 0x000076c8: 00006f11 .o.. DCD 28433 - 0x000076cc: 0000743b ;t.. DCD 29755 - 0x000076d0: 00007451 Qt.. DCD 29777 - 0x000076d4: 00007467 gt.. DCD 29799 - 0x000076d8: 0000747d }t.. DCD 29821 - 0x000076dc: 0000748d .t.. DCD 29837 - 0x000076e0: 000074a9 .t.. DCD 29865 - 0x000076e4: 000074c9 .t.. DCD 29897 - 0x000076e8: 000075bb .u.. DCD 30139 - 0x000076ec: 00006ef9 .n.. DCD 28409 - $t - .text - __aeabi_uidiv - __aeabi_uidivmod - 0x000076f0: b530 0. PUSH {r4,r5,lr} - 0x000076f2: 460b .F MOV r3,r1 - 0x000076f4: 4601 .F MOV r1,r0 - 0x000076f6: 2000 . MOVS r0,#0 - 0x000076f8: 2220 " MOVS r2,#0x20 - 0x000076fa: 2401 .$ MOVS r4,#1 - 0x000076fc: e009 .. B 0x7712 ; __aeabi_uidiv + 34 - 0x000076fe: 460d .F MOV r5,r1 - 0x00007700: 40d5 .@ LSRS r5,r5,r2 - 0x00007702: 429d .B CMP r5,r3 - 0x00007704: d305 .. BCC 0x7712 ; __aeabi_uidiv + 34 - 0x00007706: 461d .F MOV r5,r3 - 0x00007708: 4095 .@ LSLS r5,r5,r2 - 0x0000770a: 1b49 I. SUBS r1,r1,r5 - 0x0000770c: 4625 %F MOV r5,r4 - 0x0000770e: 4095 .@ LSLS r5,r5,r2 - 0x00007710: 1940 @. ADDS r0,r0,r5 - 0x00007712: 4615 .F MOV r5,r2 - 0x00007714: 1e52 R. SUBS r2,r2,#1 - 0x00007716: 2d00 .- CMP r5,#0 - 0x00007718: dcf1 .. BGT 0x76fe ; __aeabi_uidiv + 14 - 0x0000771a: bd30 0. POP {r4,r5,pc} - .text - __aeabi_idiv - __aeabi_idivmod - 0x0000771c: b570 p. PUSH {r4-r6,lr} - 0x0000771e: 2400 .$ MOVS r4,#0 - 0x00007720: 4625 %F MOV r5,r4 - 0x00007722: 2800 .( CMP r0,#0 - 0x00007724: da01 .. BGE 0x772a ; __aeabi_idiv + 14 - 0x00007726: 2401 .$ MOVS r4,#1 - 0x00007728: 4240 @B RSBS r0,r0,#0 - 0x0000772a: 2900 .) CMP r1,#0 - 0x0000772c: da01 .. BGE 0x7732 ; __aeabi_idiv + 22 - 0x0000772e: 2501 .% MOVS r5,#1 - 0x00007730: 4249 IB RSBS r1,r1,#0 - 0x00007732: f7ffffdd .... BL __aeabi_uidiv ; 0x76f0 - 0x00007736: 42ac .B CMP r4,r5 - 0x00007738: d000 .. BEQ 0x773c ; __aeabi_idiv + 32 - 0x0000773a: 4240 @B RSBS r0,r0,#0 - 0x0000773c: 2c00 ., CMP r4,#0 - 0x0000773e: d000 .. BEQ 0x7742 ; __aeabi_idiv + 38 - 0x00007740: 4249 IB RSBS r1,r1,#0 - 0x00007742: bd70 p. POP {r4-r6,pc} - .text - __aeabi_memset - __aeabi_memset4 - __aeabi_memset8 - 0x00007744: b2d2 .. UXTB r2,r2 - 0x00007746: e001 .. B 0x774c ; __aeabi_memset + 8 - 0x00007748: 7002 .p STRB r2,[r0,#0] - 0x0000774a: 1c40 @. ADDS r0,r0,#1 - 0x0000774c: 1e49 I. SUBS r1,r1,#1 - 0x0000774e: d2fb .. BCS 0x7748 ; __aeabi_memset + 4 - 0x00007750: 4770 pG BX lr - __aeabi_memclr - __aeabi_memclr4 - __aeabi_memclr8 - 0x00007752: 2200 ." MOVS r2,#0 - 0x00007754: e7f6 .. B __aeabi_memset ; 0x7744 - _memset$wrapper - 0x00007756: b510 .. PUSH {r4,lr} - 0x00007758: 4613 .F MOV r3,r2 - 0x0000775a: 460a .F MOV r2,r1 - 0x0000775c: 4604 .F MOV r4,r0 - 0x0000775e: 4619 .F MOV r1,r3 - 0x00007760: f7fffff0 .... BL __aeabi_memset ; 0x7744 - 0x00007764: 4620 F MOV r0,r4 - 0x00007766: bd10 .. POP {r4,pc} + __aeabi_memcpy + __aeabi_memcpy4 + __aeabi_memcpy8 + 0x00002e2c: 4603 .F MOV r3,r0 + 0x00002e2e: 430b .C ORRS r3,r3,r1 + 0x00002e30: 079b .. LSLS r3,r3,#30 + 0x00002e32: d003 .. BEQ 0x2e3c ; __aeabi_memcpy + 16 + 0x00002e34: e009 .. B 0x2e4a ; __aeabi_memcpy + 30 + 0x00002e36: c908 .. LDM r1!,{r3} + 0x00002e38: 1f12 .. SUBS r2,r2,#4 + 0x00002e3a: c008 .. STM r0!,{r3} + 0x00002e3c: 2a04 .* CMP r2,#4 + 0x00002e3e: d2fa .. BCS 0x2e36 ; __aeabi_memcpy + 10 + 0x00002e40: e003 .. B 0x2e4a ; __aeabi_memcpy + 30 + 0x00002e42: 780b .x LDRB r3,[r1,#0] + 0x00002e44: 7003 .p STRB r3,[r0,#0] + 0x00002e46: 1c40 @. ADDS r0,r0,#1 + 0x00002e48: 1c49 I. ADDS r1,r1,#1 + 0x00002e4a: 1e52 R. SUBS r2,r2,#1 + 0x00002e4c: d2f9 .. BCS 0x2e42 ; __aeabi_memcpy + 22 + 0x00002e4e: 4770 pG BX lr .text __scatterload __scatterload_rt2 - 0x00007768: 4c06 .L LDR r4,[pc,#24] ; [0x7784] = 0x7844 - 0x0000776a: 2501 .% MOVS r5,#1 - 0x0000776c: 4e06 .N LDR r6,[pc,#24] ; [0x7788] = 0x7864 - 0x0000776e: e005 .. B 0x777c ; __scatterload + 20 - 0x00007770: 68e3 .h LDR r3,[r4,#0xc] - 0x00007772: cc07 .. LDM r4!,{r0-r2} - 0x00007774: 432b +C ORRS r3,r3,r5 - 0x00007776: 3c0c .< SUBS r4,r4,#0xc - 0x00007778: 4798 .G BLX r3 - 0x0000777a: 3410 .4 ADDS r4,r4,#0x10 - 0x0000777c: 42b4 .B CMP r4,r6 - 0x0000777e: d3f7 .. BCC 0x7770 ; __scatterload + 8 - 0x00007780: f7f9fc42 ..B. BL __main_after_scatterload ; 0x1008 + 0x00002e50: 4c06 .L LDR r4,[pc,#24] ; [0x2e6c] = 0x2e98 + 0x00002e52: 2501 .% MOVS r5,#1 + 0x00002e54: 4e06 .N LDR r6,[pc,#24] ; [0x2e70] = 0x2eb8 + 0x00002e56: e005 .. B 0x2e64 ; __scatterload + 20 + 0x00002e58: 68e3 .h LDR r3,[r4,#0xc] + 0x00002e5a: cc07 .. LDM r4!,{r0-r2} + 0x00002e5c: 432b +C ORRS r3,r3,r5 + 0x00002e5e: 3c0c .< SUBS r4,r4,#0xc + 0x00002e60: 4798 .G BLX r3 + 0x00002e62: 3410 .4 ADDS r4,r4,#0x10 + 0x00002e64: 42b4 .B CMP r4,r6 + 0x00002e66: d3f7 .. BCC 0x2e58 ; __scatterload + 8 + 0x00002e68: f7fef8ce .... BL __main_after_scatterload ; 0x1008 $d - 0x00007784: 00007844 Dx.. DCD 30788 - 0x00007788: 00007864 dx.. DCD 30820 + 0x00002e6c: 00002e98 .... DCD 11928 + 0x00002e70: 00002eb8 .... DCD 11960 $t i.__scatterload_copy __scatterload_copy - 0x0000778c: e002 .. B 0x7794 ; __scatterload_copy + 8 - 0x0000778e: c808 .. LDM r0!,{r3} - 0x00007790: 1f12 .. SUBS r2,r2,#4 - 0x00007792: c108 .. STM r1!,{r3} - 0x00007794: 2a00 .* CMP r2,#0 - 0x00007796: d1fa .. BNE 0x778e ; __scatterload_copy + 2 - 0x00007798: 4770 pG BX lr + 0x00002e74: e002 .. B 0x2e7c ; __scatterload_copy + 8 + 0x00002e76: c808 .. LDM r0!,{r3} + 0x00002e78: 1f12 .. SUBS r2,r2,#4 + 0x00002e7a: c108 .. STM r1!,{r3} + 0x00002e7c: 2a00 .* CMP r2,#0 + 0x00002e7e: d1fa .. BNE 0x2e76 ; __scatterload_copy + 2 + 0x00002e80: 4770 pG BX lr i.__scatterload_null __scatterload_null - 0x0000779a: 4770 pG BX lr + 0x00002e82: 4770 pG BX lr i.__scatterload_zeroinit __scatterload_zeroinit - 0x0000779c: 2000 . MOVS r0,#0 - 0x0000779e: e001 .. B 0x77a4 ; __scatterload_zeroinit + 8 - 0x000077a0: c101 .. STM r1!,{r0} - 0x000077a2: 1f12 .. SUBS r2,r2,#4 - 0x000077a4: 2a00 .* CMP r2,#0 - 0x000077a6: d1fb .. BNE 0x77a0 ; __scatterload_zeroinit + 4 - 0x000077a8: 4770 pG BX lr + 0x00002e84: 2000 . MOVS r0,#0 + 0x00002e86: e001 .. B 0x2e8c ; __scatterload_zeroinit + 8 + 0x00002e88: c101 .. STM r1!,{r0} + 0x00002e8a: 1f12 .. SUBS r2,r2,#4 + 0x00002e8c: 2a00 .* CMP r2,#0 + 0x00002e8e: d1fb .. BNE 0x2e88 ; __scatterload_zeroinit + 4 + 0x00002e90: 4770 pG BX lr + 0x00002e92: 0000 .. MOVS r0,r0 $d.realdata .constdata - __FUNCTION__ - 0x000077aa: 5355 US DCW 21333 - 0x000077ac: 5f545241 ART_ DCD 1599361601 - 0x000077b0: 74696e49 Init DCD 1953066569 - 0x000077b4: 00 . DCB 0 - __FUNCTION__ - 0x000077b5: 555341 USA DCB 85,83,65 - 0x000077b8: 445f5452 RT_D DCD 1147098194 - 0x000077bc: 696e4965 eIni DCD 1768835429 - 0x000077c0: 0074 t. DCW 116 - __FUNCTION__ - 0x000077c2: 5355 US DCW 21333 - 0x000077c4: 5f545241 ART_ DCD 1599361601 - 0x000077c8: 646e6553 Send DCD 1684956499 - 0x000077cc: 61746144 Data DCD 1635017028 - 0x000077d0: 00 . DCB 0 - __FUNCTION__ - 0x000077d1: 555341 USA DCB 85,83,65 - 0x000077d4: 525f5452 RT_R DCD 1381979218 - 0x000077d8: 69656365 ecei DCD 1768252261 - 0x000077dc: 61446576 veDa DCD 1631872374 - 0x000077e0: 6174 ta DCW 24948 - 0x000077e2: 00 . DCB 0 - __FUNCTION__ - 0x000077e3: 55 U DCB 85 - 0x000077e4: 54524153 SART DCD 1414676819 - 0x000077e8: 7465475f _Get DCD 1952794463 - 0x000077ec: 6f437852 RxCo DCD 1866692690 - 0x000077f0: 00746e75 unt. DCD 7630453 - __FUNCTION__ - 0x000077f4: 52415355 USAR DCD 1380012885 - 0x000077f8: 65525f54 T_Re DCD 1699897172 - 0x000077fc: 61446461 adDa DCD 1631872097 - 0x00007800: 6f746174 tato DCD 1869898100 - 0x00007804: 66667542 Buff DCD 1717990722 - 0x00007808: 00 . DCB 0 - __FUNCTION__ - 0x00007809: 555341 USA DCB 85,83,65 - 0x0000780c: 535f5452 RT_S DCD 1398756434 - 0x00007810: 44646e65 endD DCD 1147432549 - 0x00007814: 46617461 ataF DCD 1180791905 - 0x00007818: 426d6f72 romB DCD 1114468210 - 0x0000781c: 00666675 uff. DCD 6710901 - __FUNCTION__ - 0x00007820: 52415355 USAR DCD 1380012885 - 0x00007824: 65535f54 T_Se DCD 1699962708 - 0x00007828: 49785274 tRxI DCD 1232622196 - 0x0000782c: 6d754e54 TNum DCD 1836404308 - 0x00007830: 00 . DCB 0 - __FUNCTION__ - 0x00007831: 555341 USA DCB 85,83,65 - 0x00007834: 535f5452 RT_S DCD 1398756434 - 0x00007838: 78527465 etRx DCD 2018669669 - 0x0000783c: 656d6954 Time DCD 1701669204 - 0x00007840: 0074756f out. DCD 7632239 + 0x00002e94: 00000101 .... DCD 257 Region$$Table$$Base - 0x00007844: 00007864 dx.. DCD 30820 - 0x00007848: 10011000 .... DCD 268505088 - 0x0000784c: 0000002c ,... DCD 44 - 0x00007850: 0000778c .w.. DCD 30604 - 0x00007854: 00007890 .x.. DCD 30864 - 0x00007858: 1001102c ,... DCD 268505132 - 0x0000785c: 00002054 T .. DCD 8276 - 0x00007860: 0000779c .w.. DCD 30620 + 0x00002e98: 00002eb8 .... DCD 11960 + 0x00002e9c: 10011000 .... DCD 268505088 + 0x00002ea0: 0000001c .... DCD 28 + 0x00002ea4: 00002e74 t... DCD 11892 + 0x00002ea8: 00002ed4 .... DCD 11988 + 0x00002eac: 1001101c .... DCD 268505116 + 0x00002eb0: 00000130 0... DCD 304 + 0x00002eb4: 00002e84 .... DCD 11908 Region$$Table$$Limit ** Section #3 'RW_IRAM3' (SHT_PROGBITS) [SHF_ALLOC + SHF_WRITE] - Size : 44 bytes (alignment 4) + Size : 28 bytes (alignment 4) Address: 0x10011000 ** Section #4 'RW_IRAM3' (SHT_NOBITS) [SHF_ALLOC + SHF_WRITE] - Size : 8276 bytes (alignment 4) - Address: 0x1001102c + Size : 304 bytes (alignment 4) + Address: 0x1001101c ** Section #5 '.debug_abbrev' (SHT_PROGBITS) @@ -13267,37 +4083,37 @@ ** Section #6 '.debug_frame' (SHT_PROGBITS) - Size : 6736 bytes + Size : 2524 bytes ** Section #7 '.debug_info' (SHT_PROGBITS) - Size : 34732 bytes + Size : 18540 bytes ** Section #8 '.debug_line' (SHT_PROGBITS) - Size : 15212 bytes + Size : 6556 bytes ** Section #9 '.debug_loc' (SHT_PROGBITS) - Size : 15052 bytes + Size : 5228 bytes ** Section #10 '.debug_macinfo' (SHT_PROGBITS) - Size : 25596 bytes + Size : 40208 bytes ** Section #11 '.debug_pubnames' (SHT_PROGBITS) - Size : 7360 bytes + Size : 2007 bytes ** Section #12 '.symtab' (SHT_SYMTAB) - Size : 8176 bytes (alignment 4) + Size : 4048 bytes (alignment 4) String table #13 '.strtab' - Last local symbol no. 163 + Last local symbol no. 108 ** Section #13 '.strtab' (SHT_STRTAB) - Size : 8396 bytes + Size : 3788 bytes ** Section #14 '.note' (SHT_NOTE) @@ -13313,83 +4129,58 @@ address size variable name type -0x10013068 0x18 gClosePaDelayTimer SYS_TIMER_TYPE -0x10013068 0x4 gClosePaDelayTimer.mTimerValue uint32_t -0x1001306c 0x4 gClosePaDelayTimer.mTick uint32_t -0x10013070 0x4 gClosePaDelayTimer.pfExpireCb Timer_Expire_CB -0x10013074 0x4 gClosePaDelayTimer.pNextTimer pointer to sTimerType -0x10013078 0x4 gClosePaDelayTimer.cbParams int32_t -0x1001307c 0x1 gClosePaDelayTimer.mTimerStatus TIMER_STATUS -0x1001307d 0x1 gClosePaDelayTimer.mIsCycle TIMER_TYPE - -address size variable name type -0x10011026 0x1 gDacAnaVolTargetLeft uint8_t - -address size variable name type -0x10011027 0x1 gDacAnaVolTargetRight uint8_t - -address size variable name type -0x10011020 0x2 gDacBufOffset uint16_t - -address size variable name type -0x10011022 0x2 gDacDcCaliTargetLeft int16_t - -address size variable name type -0x10011024 0x2 gDacDcCaliTargetRight int16_t - -address size variable name type -0x10011028 0x1 gLastStartDacClk uint8_t - -address size variable name type -0x10011018 0x4 printportcb printport_CB -0x10011018 0x1 printportcb.UARTA_rxio uint8_t -0x10011019 0x1 printportcb.UARTA_txio uint8_t -0x1001101a 0x1 printportcb.UARTB_rxio uint8_t -0x1001101b 0x1 printportcb.UARTB_txio uint8_t - -address size variable name type -0x10011044 0x20 regBeck array[2] of UartxRegControlBackup +0x1001101a 0x2 a2dpLen uint16_t address size variable name type -0x10012065 0x1001 uartA_RX_buf array[4097] of uint8_t +0x10011018 0x1 gIPC_test uint8_t address size variable name type -0x10011064 0x1001 uartA_TX_buf array[4097] of uint8_t +0x10011034 0x28 ipcCb tIPCControlBlock +0x10011034 0x4 ipcCb.evtcb tIPCEventCb +0x10011038 0x4 ipcCb.sppcb tIPCSppCb +0x1001103c 0x4 ipcCb.timercb tIPCTimer +0x10011040 0x4 ipcCb.stimercb tIPCTimer +0x10011044 0x4 ipcCb.blecb tIPCBleCb +0x10011048 0x4 ipcCb.advcb tIPCAdvCb +0x1001104c 0x4 ipcCb.hidcb tIPCHidCb +0x10011050 0x4 ipcCb.meshcb tIPCMeshCb +0x10011054 0x4 ipcCb.a2dpcb tIPCa2dpCb +0x10011058 0x4 ipcCb.readreqcb tIPCReadReq address size variable name type -0x1001101e 0x2 uartB_RX_buf array[2] of uint8_t +0x10011014 0x4 ipcCbArray tIPCHandleCbArray address size variable name type -0x1001101c 0x2 uartB_TX_buf array[2] of uint8_t +0x1001105c 0xc8 ipcReadBuff array[200] of uint8_t address size variable name type -0x10011014 0x4 SystickCount tick +0x10011124 0x28 ipcSendBuff array[40] of uint8_t address size variable name type -0x10011011 0x1 gSystemInFastDpll uint8_t +0x10011010 0x4 SystickCount tick address size variable name type -0x1001100c 0x4 gSystemTimerAdjustClknbt uint32_t +0x1001100d 0x1 gSystemInFastDpll uint8_t address size variable name type -0x1001102c 0x18 header_Timer SYS_TIMER_TYPE -0x1001102c 0x4 header_Timer.mTimerValue uint32_t -0x10011030 0x4 header_Timer.mTick uint32_t -0x10011034 0x4 header_Timer.pfExpireCb Timer_Expire_CB -0x10011038 0x4 header_Timer.pNextTimer pointer to sTimerType -0x1001103c 0x4 header_Timer.cbParams int32_t -0x10011040 0x1 header_Timer.mTimerStatus TIMER_STATUS -0x10011041 0x1 header_Timer.mIsCycle TIMER_TYPE +0x10011008 0x4 gSystemTimerAdjustClknbt uint32_t address size variable name type -0x10011004 0x4 pheader pointer to SYS_TIMER_TYPE +0x1001101c 0x18 header_Timer SYS_TIMER_TYPE +0x1001101c 0x4 header_Timer.mTimerValue uint32_t +0x10011020 0x4 header_Timer.mTick uint32_t +0x10011024 0x4 header_Timer.pfExpireCb Timer_Expire_CB +0x10011028 0x4 header_Timer.pNextTimer pointer to sTimerType +0x1001102c 0x4 header_Timer.cbParams int32_t +0x10011030 0x1 header_Timer.mTimerStatus TIMER_STATUS +0x10011031 0x1 header_Timer.mIsCycle TIMER_TYPE address size variable name type -0x10011010 0x1 sys_Timer_Check_Flag uint8_t +0x10011000 0x4 pheader pointer to SYS_TIMER_TYPE address size variable name type -0x10011008 0x4 sys_tick_count uint32_t +0x1001100c 0x1 sys_Timer_Check_Flag uint8_t address size variable name type -0x10011000 0x2 AdcBufferReadPtr uint16_t +0x10011004 0x4 sys_tick_count uint32_t Index: tag/Soft/ModuleDemo/ADC/AD_Sound_Recording/CM0/Prj/Output/flash.dat =================================================================== --- /YC1121E/SoftCode/MCU/tag/Soft/ModuleDemo/ADC/AD_Sound_Recording/CM0/Prj/Output/flash.dat (revision 4280) +++ /YC1121E/SoftCode/MCU/tag/Soft/ModuleDemo/ADC/AD_Sound_Recording/CM0/Prj/Output/flash.dat (nonexistent) @@ -1,38383 +0,0 @@ -00 -00 -03 -aa -55 -2e -16 -c2 -84 -00 -1f -c0 -1c -01 -04 -c0 -1d -02 -e4 -c0 -1d -80 -67 -c0 -1e -01 -1f -c0 -1e -81 -24 -c0 -2a -05 -88 -c0 -2c -03 -64 -c0 -2e -02 -c7 -c0 -30 -02 -fb -c0 -36 -02 -d7 -c0 -40 -84 -d1 -c0 -42 -84 -79 -c0 -4f -04 -a9 -c0 -50 -02 -84 -c0 -52 -05 -0e -c0 -58 -83 -06 -c0 -5a -03 -5a -c0 -5b -01 -89 -c0 -5c -80 -83 -c0 -60 -03 -ae -c0 -61 -83 -b0 -c0 -62 -03 -b2 -c0 -64 -02 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-00 -00 -00 -00 -00 -00 -00 -17 -0c -1c -19 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -16 -05 -c8 -a2 Index: tag/Soft/ModuleDemo/ADC/AD_Sound_Recording/CM0/Prj/Output/memmap.format =================================================================== --- /YC1121E/SoftCode/MCU/tag/Soft/ModuleDemo/ADC/AD_Sound_Recording/CM0/Prj/Output/memmap.format (revision 4280) +++ /YC1121E/SoftCode/MCU/tag/Soft/ModuleDemo/ADC/AD_Sound_Recording/CM0/Prj/Output/memmap.format (nonexistent) @@ -1,1555 +0,0 @@ -0x0000 mem_le_adv_transmit -0x0001 mem_le_adv_waitcnt -0x0002 mem_sbc_error -0x0002 mem_le_adv_rcv -0x0003 mem_le_req_rcv -0x0004 mem_le_scanrsp_rcv -0x0005 mem_le_conn_rcv -0x0006 mem_inquiryscan_waitcnt -0x0007 mem_inquiryscan_rcvcnt -0x0008 mem_pagescan_waitcnt -0x0009 mem_pagescan_rcvcnt -0x000a mem_pagescan_rcvfhscnt -0x000b mem_slave_rcvcnt -0x000c mem_page_transmit -0x000d mem_page_rcv -0x000e mem_page_rcv_fhs -0x000f mem_master_rcvcnt -0x0010 mem_fhs_wait_counter -0x0011 mem_newconnto_counter -0x0012 mem_inquiry_transmit -0x0013 mem_inquiry_rcv -0x0014 mem_fw_ver -0x0015 mem_current_context -0x0016 mem_empty_block -0x0017 mem_last_freq -0x0018 mem_rssi -0x0019 mem_rx_type -0x001a mem_rx_hec_err -0x001c mem_rx_crc_err -0x001e mem_context_ptr -0x0020 mem_display -0x0028 mem_bcd -0x0030 mem_state -0x0031 mem_mode -0x0032 mem_tsniff -0x0034 mem_sniff_anchor -0x0038 mem_clk_offset -0x003e mem_rx_window -0x0040 mem_plap -0x0043 mem_puap -0x0044 mem_pnap -0x0046 mem_conn_handle -0x0047 mem_cur_arq -0x0048 mem_lmp_to_send -0x0049 mem_lmi_opcode -0x004a mem_lmo_reason -0x004b mem_op -0x004c mem_state_map -0x004d mem_supervision_timer -0x0051 mem_supervision_to -0x0053 mem_name_offset -0x0054 mem_key_size -0x0055 mem_reconn_lmp_sm -0x0056 mem_aco -0x0062 mem_kc -0x0072 mem_conn_timer -0x0073 mem_sniff_attempt -0x0074 mem_sniff_timeout -0x0075 mem_dsniff -0x0077 mem_amaddr -0x0078 mem_lmo_opcode1 -0x0079 mem_lmi_opcode1 -0x007a mem_lmo_reason1 -0x007b mem_lmo_tid1 -0x007c mem_lmo_opcode2 -0x007d mem_lmi_opcode2 -0x007e mem_lmo_reason2 -0x007f mem_lmo_tid2 -0x0080 mem_mark_load -0x0088 mem_hci_version -0x008b mem_acl_pktlen -0x008d mem_sco_pktlen -0x008e mem_acl_pktcnt -0x0090 mem_sco_pktcnt -0x0092 mem_current_sniff_attempt -0x0093 mem_current_sniff_timeout -0x0094 mem_nfreq_index_inq -0x0095 mem_nfreq_index_page -0x0096 mem_ninqy_index -0x0097 mem_fhs_misc -0x0098 mem_tx_lch -0x0099 mem_tx_len -0x009b mem_subsniff_instant -0x009f mem_subsniff_rate -0x00a0 mem_subsniff_tcmax -0x00a2 mem_subsniff_tsniff -0x00a3 mem_lpm_adjust -0x00a4 mem_sync_clke -0x00aa mem_lpm_current_mult -0x00ab mem_gpio_wakeup_low -0x00b0 mem_gpio_wakeup_high -0x00b5 mem_npage_index -0x00b6 mem_page_mode -0x00b7 mem_page_clk -0x00bb mem_tst_pktcnt_sync -0x00bd mem_tst_pktcnt_hec -0x00bf mem_tst_pktcnt_crc -0x00c1 mem_tst_pktcnt_dmh -0x00c3 mem_tmp_buffer_head -0x00c6 mem_tmp_buffer -0x0116 mem_tester_emulate -0x0117 mem_temp_payload -0x0117 test_mode_scenario -0x0118 test_mode_hopping_mode -0x0119 test_mode_tx_freq -0x011a test_mode_rx_freq -0x011b test_mode_power_mode -0x011c test_mode_poll_period -0x011d test_mode_packet_type -0x011e test_mode_data_length -0x0120 mem_test_mode_old_debug_config -0x0121 mem_tester_cnt -0x0122 mem_temp_am_addr -0x0123 mem_temp_arq -0x0124 mem_pdatatemp -0x012c mem_len -0x012e mem_clkn_bt -0x0132 mem_clke_bt -0x0136 mem_dpll_clkn -0x013a mem_connection_options -0x013b mem_nameres_cnt -0x013c mem_txptr -0x013e mem_slot_offset -0x0140 mem_wait_auth_clk -0x0144 extm_fhs_misc -0x0145 extm_newconn_am_addr -0x0146 extm_class -0x0149 extm_lap -0x014c extm_uap -0x014d extm_nap -0x0150 mem_debug_config -0x0151 mem_lch_code -0x0152 mem_fhs_am_addr -0x0153 mem_dpll_error -0x0155 mem_bdaddr_list_buff -0x0179 mem_select_list_item -0x017a mem_temp_reconn_record -0x017a mem_record_bt_mode -0x017b mem_temp_lap -0x0181 mem_list_item_ptr -0x0183 mem_eir -0x01e7 mem_switch_timeout -0x01e9 mem_acl_dsniff -0x01eb mem_acl_tsniff -0x01ed mem_acl_attempt -0x01ee mem_acl_timeout -0x01ef mem_temp_force_nack -0x01f0 mem_avdtp_signal_cmd -0x01f1 mem_transaction_label -0x01f2 mem_temp_sbc_decode_buffer_size -0x01f4 mem_temp_dac_soft_dma_work_wptr -0x01f6 mem_temp_sbc_soft_dma_start_addr -0x01f8 mem_temp_dac_soft_dma_start_addr -0x01fa mem_temp_soft_dma_work_length -0x01fc mem_temp_soft_dma_work_table_index_value -0x01fd mem_ucode_status -0x01fe mem_ucode_flag -0x0200 mem_qspi_tbuf/* spid buf: 03 addr[23:16] addr[15:8] addr[7:0] */ -0x0201 mem_iicd_tbuf/* iicd buf: iic_adr addr[15:8] addr[7:0] iic_adr */ -0x0201 mem_addr_hi -0x0202 mem_eep_addr_hi -0x0202 mem_addr_mi -0x0203 mem_addr_lo -0x0204 mem_iicd_addr -0x0205 mem_spid_rbuf -0x0209 mem_ucode_buf -0x020b mem_ucode_len -0x020d mem_sched_addr -0x020f mem_ucode_ptr -0x0212 mem_ucode_keybuf -0x0222 mem_check_plap_temp -0x0234 mem_start_addr_temp -0x0237 mem_spid_tbuf -0x0239 mem_qspi_defualt -0x023a mem_switch_fail_master_count -0x023b mem_app_evt_timer_count -0x023c mem_flash_address -0x023f mem_flash_data_address -0x0241 mem_flash_trans_length -0x0243 mem_soft_dma_src_addr -0x0247 mem_soft_dma_dst_addr -0x024b mem_avctp_command_response -0x024c mem_avrcp_vol -0x024d mem_avctp_rx_label -0x024e mem_h5rx_ackcnt -0x024f mem_check_err_acl_cont -0x0250 mem_rp_packets -0x0251 mem_packet_type -0x0253 mem_hci_sniff_conn_handle -0x0255 mem_hci_sniff_max_interval -0x0257 mem_hci_sniff_min_interval -0x0259 mem_hci_sniff_attempt -0x025b mem_hci_sniff_timeout -0x025d mem_voice_setting -0x025f mem_retransmission_effort -0x0260 mem_sco_ptype -0x0262 mem_extm_uap_restore -0x0265 mem_h5rx_rptr -0x0267 mem_h5rx_ack -0x0268 mem_h5tx_ack -0x0269 mem_h5tx_rptr -0x026b mem_h5tx_wptr -0x026d mem_h5tx_free -0x026f mem_h5rx_tmp -0x0270 mem_h5tx_seq -0x0271 mem_hci_acl_queue_wptr -0x0273 mem_hci_acl_queue_rptr -0x0275 mem_hci_acl_queue_end -0x0277 mem_hci_acl_queue_wcnt -0x0278 mem_hci_acl_cnt -0x0279 mem_hci_acl_tx_trigger_wptr//tx via uart -0x027b mem_ucode_id_local -0x027c mem_ucode_id_remote -0x027d mem_check_sum -0x027e mem_ucode_temp -0x027f mem_ucode_temp1 -0x0280 mem_lock_in_enc -0x0281 mem_hci_disconn_reason -0x0282 mem_hci_curr_len -0x0283 mem_hci_curr_target -0x0285 mem_coef_table_temp -0x03d7 mem_sco_indata -0x0413 mem_sco_outdata -0x044f mem_phone_num_count -0x0450 mem_phone_num_len -0x0451 mem_phone_number -0x0460 mem_at_command_data -0x047e mem_sco_flag -0x047f mem_l2cap_mem_start -0x047f mem_l2cap_rxbuff1_len -0x0481 mem_l2cap_rxbuff2_len -0x0483 mem_l2cap_rxbuff_new_temp -0x0484 mem_l2cap_rxbuff_new -0x0485 mem_l2cap_rxbuff_fifo -0x0485 mem_l2cap_rxbuff_fifo1 -0x0486 mem_l2cap_rxbuff_fifo2 -0x0487 mem_l2cap_payload_ptr -0x0489 mem_l2cap_rx_pkt_length -0x048b mem_l2cap_rx_cid -0x048d mem_l2cap_rx_done -0x048e mem_l2cap_signal_ident -0x048f mem_sdp_tx_buff_ptr -0x0491 mem_sdp_tx_payload_ptr -0x0493 mem_sdp_tx_pkt_length -0x0495 mem_tx_malloc_log -0x04d5 mem_l2cap_temp_ch_info -0x04d5 mem_l2cap_temp_ch_psm -0x04d6 mem_l2cap_temp_ch_state -0x04d7 mem_l2cap_temp_local_cid -0x04d9 mem_l2cap_temp_remote_cid -0x04db mem_l2cap_mem_end -0x04db mem_le_rxbuf -0x0503 mem_le_l2capbuf -0x05db mem_le_mic -0x05df mem_le_peer_mic -0x05e3 mem_le_skdm -0x05eb mem_le_skds -0x05f3 mem_le_peer_ltk -0x0603 mem_le_my_ltk -0x0613 mem_le_mrand -0x0623 mem_le_state -0x0624 mem_le_mode -0x0625 mem_le_tsniff -0x0627 mem_le_anchor -0x062b mem_le_clk_offset -0x0631 mem_le_receive_window -0x0633 mem_le_plap -0x0639 mem_le_conn_handle -0x063a mem_le_arq -0x063b mem_le_ch -0x063c mem_le_hop -0x063d mem_le_event_count -0x063f mem_le_supervision_timer -0x0643 mem_le_instant -0x0645 mem_le_channels -0x0646 mem_le_conn_sm -0x0647 mem_le_op -0x0648 mem_le_access -0x064c mem_le_crcinit -0x064f mem_le_window_size -0x0650 mem_le_slave_latency -0x0652 mem_le_superto -0x0654 mem_le_channel_map -0x0659 mem_le_no_using -0x065b mem_le_peer_sca -0x065c mem_le_att_opcode -0x065d mem_le_att_handle -0x065f mem_le_err_code -0x0660 mem_le_ll_pairing_fail_reason -0x0661 mem_le_sk -0x0671 mem_le_testtype -0x0672 mem_le_test_sync -0x0674 mem_le_test_pcnt -0x0676 mem_le_notify_len -0x0677 mem_cmd_le_create_conn -0x0678 mem_le_adv_temp -0x068c mem_le_packet_size -0x068d mem_le_packet_llid -0x068e mem_le_payload_ptr -0x0690 mem_lmo_header_length -0x0691 mem_lmo_header_opcode -0x0692 mem_lmo_payload -0x06a3 mem_lmi_accepted_opcode -0x06a4 mem_disconn_reason_send -0x06a5 mem_tx_fixed_freq -0x06a6 mem_rx_fixed_freq -0x06a7 mem_ext_features_page -0x06a8 mem_lmpext_ssp_enable -0x06aa mem_remote_sppcap -0x06ab mem_lmp_conn_state -0x06ac mem_soft_timer -0x06ae mem_pincode_state -0x06af mem_sres_tid -0x06b0 mem_accptsco_tid -0x06b1 mem_wait_encryption -0x06b2 mem_sniff_payload -0x06c2 mem_aurand_send_delay_time -0x06c6 mem_prcp_data -0x06da mem_prcp -0x06db mem_prcp_tx_len -0x06dc rx_buf_data_ptr -0x06de mem_mod2div_temp -0x06e1 mem_contw_temp -0x06e3 mem_rfc_adss -0x06e4 mem_rfc_current_channel -0x06e5 mem_rfc_frame_type -0x06e6 mem_current_fcs -0x06e7 mem_rfc_paylead_length -0x06e9 mem_rfc_paylead_ptr -0x06eb mem_uih_cmd_type -0x06ec mem_uih_length -0x06ee mem_rfc_payload_ptr -0x06f0 mem_ms_param -0x06f1 mem_pn_credit_flow_type_info -0x06f2 mem_pn_priority -0x06f3 mem_pn_acknowledg_timer -0x06f4 mem_pn_max_retrans -0x06f5 mem_rfcomm_send_adss -0x06f6 mem_rfcomm_send_frame_type -0x06f7 mem_rfcomm_send_fcs -0x06f8 mem_sdp_mem_start -0x06f8 mem_sdp_uuid_search_ptr -0x0700 mem_sdp_continue_byte -0x0702 mem_sdp_pduid -0x0703 mem_sdp_transactionid -0x0705 mem_sdp_transactionid_local -0x0707 mem_sdp_attribute_maxbyte -0x0709 mem_sdp_record_maxcnt -0x070b mem_sdp_record_handle -0x070f mem_sdp_LACAP_found -0x0710 mem_sdp_RFCOMM_found -0x0711 mem_sdp_handle_list -0x0711 mem_sdp_attrib_list -0x0731 mem_sdp_error_code -0x0733 mem_sdp_all_length -0x0735 mem_handle_humber -0x0736 mem_search_uuid -0x0738 mem_sdp_mem_end -0x0738 mem_rxbuf -0x0749 mem_random_number -0x0759 mem_round_key -0x0769 mem_kinit -0x0779 mem_input_store -0x0789 mem_x -0x0799 mem_y -0x07a8 mem_y15 -0x07a9 mem_key_store -0x07ba mem_key_store_end -0x07bb memp_ar_key -0x07bd memp_ar_input -0x07bf mem_ar_hround -0x07c9 mem_ec_infinite -0x07ca mem_ec_loopc -0x07cc mem_aes_cmac_data_length -0x07cd memdat -0x07cd mem_ax -0x07e5 mem_ay -0x07fd mem_az -0x0815 mem_bx -0x082d mem_ax_256//32 bytes -0x082d mem_by -0x0845 mem_bz -0x084d mem_ay_256// 32 bytes -0x085d mem_cx -0x086d mem_az_256// 32 bytes -0x0875 mem_cy -0x088c mem_cy5 -0x088d mem_bx_256// 32 bytes -0x088d mem_cz -0x08a5 mem_k -0x08ad mem_by_256// 31 bytes -0x08bd mem_align -0x08cd mem_bz_256//32 bytes -0x08cd mem_tmp1 -0x08cd memahbak -0x08e5 mem_tmp5 -0x08ed mem_cx_256//32 bytes -0x08ed memahsave -0x08fd mem_tmp2 -0x090d mem_cy_256// 32 bytes -0x090d memahsave_end -0x090d mem_addr_padding -0x090e mem_addr_value/* 12 bytes */ -0x0915 mem_tmp3 -0x0915 mem_t1 -0x091a mem_addr_value_end -0x091d mem_addr_iocap_end -0x092c mem_cy5_256// 1 byte -0x092d mem_cz_256// 32 bytes -0x092d mem_tmp0 -0x092d mem_t0 -0x0935 mem_tmp0a -0x0945 mem_t2 -0x094d mem_k_256//32 bytes -0x095d mem_t3 -0x096d mem_tmp1_256//32 bytes -0x0975 mem_t7 -0x098d mem_tmp5_256 -0x09ad mem_tmp2_256 -0x09cd mem_tmp3_256 -0x09cd mem_t1_256 -0x09ed mem_tmp0_256 -0x09ed mem_t0_256 -0x0a0d mem_t2_256 -0x0a2d mem_t3_256 -0x0a4d mem_t7_256 -0x0a6d mem_p -0x0a85 mem_a -0x0a9d mem_b -0x0ab5 mem_gx -0x0acd mem_gy -0x0ae5 memh0 -0x0b05 mem_p_256 -0x0b25 mem_a_256 -0x0b45 mem_gx_256 -0x0b65 mem_gy_256 -0x0b85 mem_le_slat -0x0b95 mem_sp_state_start -0x0b95 mem_sp_state -0x0b96 mem_master_sp_state -0x0b97 mem_sp_flag -0x0b98 mem_master_sp_flag -0x0b99 mem_sp_calc -0x0b9a mem_sp_dh_ready -0x0b9b mem_sp_localsm -0x0b9c mem_pairing_auth -0x0b9d mem_sp_flag_start -0x0b9d mem_sp_local_key_send_count -0x0b9e mem_sp_remote_key_recv_count -0x0b9f mem_sp_remote_key_invalid -0x0ba0 mem_sp_dhkey_invalid -0x0ba1 mem_gkey -0x0ba5 mem_le_pubkey_remote_x_256 -0x0bad mem_sp_pubkey_remote -0x0bad mem_sp_pubkey_remote_x -0x0bc5 mem_sp_pubkey_remote_x_end -0x0bc5 mem_sp_pubkey_remote_y -0x0bc5 mem_le_pubkey_remote_y_256 -0x0be5 mem_le_dhkey_256 -0x0bed mem_sp_dhkey -0x0c05 mem_sp_dhkey_end -0x0c05 mem_sp_random_local -0x0c15 mem_sp_random_local_end -0x0c15 mem_sp_random_remote -0x0c25 mem_sp_random_remote_end -0x0c25 memresult -0x0c25 mem_sp_calc_result -0x0c25 memh -0x0c29 memg -0x0c2d memf -0x0c31 meme -0x0c35 mem_sp_calc_result_high -0x0c35 memd -0x0c39 memc -0x0c3d memb -0x0c41 mema -0x0c45 mem_sp_check_result -0x0c55 mem_sp_confirm_remote -0x0c65 mem_sp_prarm_stack -0x0c75 mem_ipc_skip_continue_proc -0x0c76 mem_row_scanned_record -0x0c77 mem_col_scanned_record -0x0c78 mem_get_keypress_flag_record -0x0c79 mem_usb_status -0x0c7a mem_usb_fifo_empty -0x0c7b mem_usb_read_len -0x0c7d mem_usb_txbuf -0x0cbe mem_usb_txbuf1 -0x0cc8 mem_usb_txbuf2 -0x0cd2 mem_usb_rxbuf -0x0d0e mem_usb_rxbuf_end -0x0d0f mem_usb_state -0x0d10 mem_bufptr -0x0d12 mem_remain -0x0d13 mem_devicedesc -0x0d27 mem_hidreportdesc_kb -0x0d6d mem_hidreportdesc_m -0x0e35 mem_confdesc -0x0e7b mem_string0 -0x0e80 mem_string1 -0x0e9e mem_string2 -0x0ebc mem_string3 -0x0eda mem_usb_setup -0x0eda mem_usb_setup_bmRequestType -0x0edb mem_usb_setup_bRequest -0x0edc mem_usb_setup_bValue -0x0edd mem_usb_setup_bValueH -0x0ede mem_usb_setup_wIndex -0x0ee0 mem_usb_setup_bLength -0x0ee1 mem_usb_setup_bLengthH -0x0ee2 mem_usb0_setup_ptr -0x0ee4 mem_usb0_set_report_data_ptr -0x0ee6 mem_usb_setup_bValue_temp -0x0ee8 mem_usb0_get_set_report -0x0ee9 mem_usb0_data_ready_report -0x0eea mem_usb_tx_win_enable -0x0eeb mem_usb_tx_mac_enable -0x0eec mem_usb_zero_packet -0x0eee mem_usb_ones_packet -0x0ef0 mem_usb_two_packet -0x0ef2 mem_usb_idle_flag -0x0ef3 mem_usb_idle_rate -0x0ef4 mem_usb_get_protocol_flag -0x0ef5 mem_usb_set_protocol_status -0x0ef6 mem_usb_set_protocol_value -0x0ef7 mem_usb0_state -0x0ef8 mem_usb_remote_wakeup -0x0ef9 mem_usb_clear_remote_wakeup -0x0efa mem_usb_ep0_stall_status -0x0efb mem_usb_ep1_stall_status -0x0efc mem_usb_ep2_stall_status -0x0efd mem_usb_ep3_stall_status -0x0efe mem_dsc_info_data_pointer -0x0f00 mem_dsc_info_len -0x0f01 mem_usb_ep1_data -0x0f02 mem_usb_ep2_data -0x0f03 mem_usb_tx_enable -0x0f04 mem_usb_device_enumeration_endflag -0x0f05 mem_usb_wakestate_onetime_flag -0x0f06 mem_usb_mac_wakeup_trig -0x0f07 mem_usb_set_high_addr_flag -0x0f08 mem_usb_clear_halt -0x0f09 mem_hold_contr -0x0f0b mem_hold_contw -0x0f0d mem_fifo_temp -0x0f0e mem_max_bitsneed -0x0f12 mem_bits_need00 -0x0f12 mem_temp -0x0f16 mem_bits_need01 -0x0f16 mem_temp1 -0x0f1a mem_bits_need02 -0x0f1a mem_timeup -0x0f1e mem_bits_need03 -0x0f1e mem_rega -0x0f22 mem_bits_need04 -0x0f22 mem_regb -0x0f26 mem_bits_need05 -0x0f26 mem_regc -0x0f2a mem_bits_need06 -0x0f2a mem_contr -0x0f2c mem_contw -0x0f2e mem_bits_need07 -0x0f32 mem_bits_need10 -0x0f36 mem_bits_need11 -0x0f3a mem_bits_need12 -0x0f3e mem_bits_need13 -0x0f42 mem_bits_need14 -0x0f46 mem_bits_need15 -0x0f4a mem_bits_need16 -0x0f4e mem_bits_need17 -0x0f52 mem_wakup_from_power_flag -0x0f53 mem_saved_gpio_in -0x0f57 mem_flash_data_address_t -0x0f57 mem_le_data_len_temp//1byte -0x0f57 mem_tx_fifo_map_temp -0x0f57 mem_rpn_dlci//1byte -0x0f57 mem_event_cmd_response_content//2byte -0x0f57 mem_le_prand//16byte -0x0f57 mem_AES_CMAC_k//16 bytes -0x0f57 mem_regext_index//1 bytes -0x0f57 mem_temp_block0 -0x0f58 mem_le_data_temp//15bytes -0x0f58 mem_temp_block1 -0x0f67 mem_le_aes_128//16byte -0x0f67 mem_regext//64 bytes -0x0f67 mem_AES_CMAC_k1//16 bytes -0x0f67 mem_sum_temp -0x0f67 mem_temp_block2 -0x0f77 mem_AES_CMAC_k2//16 bytes -0x0f77 mem_temp_block3 -0x0f87 mem_AES_CMAC_temp// 16 bytes -0x0f87 mem_temp_block4 -0x0f97 mem_AES_CMAC_M_last// 16 bytes -0x0f97 mem_temp_block5 -0x0fa7 mem_le_mackey//16 bytes -0x0fa7 mem_temp_block6 -0x0fb7 mem_zcode_temp_param0 -0x0fb8 mem_zcode_temp_param1 -0x0fba mem_zcode_temp_param2 -0x0fbc mem_tws_sync_clk -0x0fc0 mem_tws_connecting_phase -0x0fc1 mem_temp_tx_power -0x0fc2 mem_msbc_miss -0x0fc4 mem_msbc_error -0x0fc6 mem_vp_length -0x0fc9 mem_ota_cmd -0x0fca mem_ota_return_result -0x0fcb mem_ota_update_flash_mode -0x0fcc mem_ota_write_index -0x0fce mem_ota_write_length -0x0fd0 mem_ota_write_data_addr -0x0fd3 mem_ota_write_flash_addr -0x0fd6 mem_ota_enable_xip_flag -0x0fd7 mem_xip_flash_offset_mram -0x0fda mem_storage_start_addr_mram -0x0fdd mem_ota_notify_handle_mram -0x0fde mem_ota_write_handle_mram -0x0fdf mem_ota_buck_size_mram -0x0fe1 mem_ota_packet_max_len_mram -0x0fe3 mem_ota_wdt_en_flag -0x0fe4 mem_ota_wdt_m0_en -0x4000 mem_patch00 -0x4001 mem_patch01 -0x4002 mem_patch02 -0x4003 mem_patch03 -0x4004 mem_patch04 -0x4005 mem_patch05 -0x4006 mem_patch06 -0x4007 mem_patch07 -0x4008 mem_patch08 -0x4009 mem_patch09 -0x400a mem_patch0a -0x400b mem_patch0b -0x400c mem_patch0c -0x400d mem_patch0d -0x400e mem_patch0e -0x400f mem_patch0f -0x4010 mem_patch10 -0x4011 mem_patch11 -0x4012 mem_patch12 -0x4013 mem_patch13 -0x4014 mem_patch14 -0x4015 mem_patch15 -0x4016 mem_patch16 -0x4017 mem_patch17 -0x4018 mem_patch18 -0x4019 mem_patch19 -0x401a mem_patch1a -0x401b mem_patch1b -0x401c mem_patch1c -0x401d mem_patch1d -0x401e mem_patch1e -0x401f mem_patch1f -0x4020 mem_patch20 -0x4021 mem_patch21 -0x4022 mem_patch22 -0x4023 mem_patch23 -0x4024 mem_patch24 -0x4025 mem_patch25 -0x4026 mem_patch26 -0x4027 mem_patch27 -0x4028 mem_patch28 -0x4029 mem_patch29 -0x402a mem_patch2a -0x402b mem_patch2b -0x402c mem_patch2c -0x402d mem_patch2d -0x402e mem_patch2e -0x402f mem_patch2f -0x4030 mem_patch30 -0x4031 mem_patch31 -0x4032 mem_patch32 -0x4033 mem_patch33 -0x4034 mem_patch34 -0x4035 mem_patch35 -0x4036 mem_patch36 -0x4037 mem_patch37 -0x4038 mem_patch38 -0x4039 mem_patch39 -0x403a mem_patch3a -0x403b mem_patch3b -0x403c mem_patch3c -0x403d mem_patch3d -0x403e mem_patch3e -0x403f mem_patch3f -0x4040 mem_context -0x4130 mem_current_amaddr -0x4131 mem_lpm_mode -0x4132 mem_device_option -0x4133 mem_scan_mode -0x4134 mem_last_clkn -0x4138 mem_features -0x4140 mem_lap -0x4143 mem_uap -0x4144 mem_nap -0x4146 mem_npage -0x4147 mem_glap -0x414a mem_class -0x414d mem_iscan_window -0x414f mem_iscan_interval -0x4151 mem_pscan_window -0x4153 mem_pscan_interval -0x4155 mem_page_interval -0x4157 mem_page_window -0x4159 mem_page_to -0x415b mem_inq_window -0x415d mem_fcomp_mul -0x415e mem_fcomp_div -0x415f mem_rx_window_init -0x4161 mem_rx_window_sniff -0x4163 mem_rf_init_ptr -0x4165 mem_rf_init -0x4166 mem_last_type -0x4167 mem_retransmission_cnt -0x4169 mem_next_btclk -0x416d mem_seqi -0x416e mem_rf_rccal -0x416f mem_handle_num -0x4170 mem_max_slot -0x4171 mem_eir_enable -0x4172 mem_afh_instant -0x4176 mem_afh_error_total -0x4178 mem_afh_cfg -0x4179 mem_afh_new_mod -0x417a mem_afh_map_lo -0x417f mem_afh_map_hi -0x4184 mem_afh_used -0x4185 mem_afh_index -0x4187 mem_afh_map_new -0x4192 mem_afh_map -0x41e2 mem_afh_timer -0x41e6 mem_afh_classify_channel_map -0x41f0 mem_chip_functions -0x41f2 mem_lpm_wake_lock -0x41f4 mem_lpm_interval -0x41f6 mem_lpm_overhead -0x41f7 mem_lpm_hibernate_switch -0x41f8 mem_sniff_unint_lost -0x41f9 mem_ptt -0x41fa mem_sleep_counter//should be 0x41fc in REVC -0x41fe mem_sleep_counter_all -0x4202 mem_sleep_clkn -0x4208 mem_sniff_rcv -0x420b mem_sniff_lost -0x420e mem_clks_per_lpo -0x4211 mem_lpm_loadcode_switch -0x4212 mem_lpm_memory_choose -0x4213 mem_lpm_mult -0x4214 mem_lpm_mult_timeout -0x4215 mem_lpm_mult_cnt -0x4216 mem_lpm_config -0x4219 mem_lpm_xtalcnt -0x421a mem_lpm_buckcnt -0x421b mem_lpm_ldocnt -0x421c mem_lpm_isogate -0x421d mem_lpm_isogate_final -0x421e mem_saved_gpio// should be 0x421e in REVC -0x4246 mem_saved_mark -0x424e mem_saved_spidctrl -0x424f mem_patch_ptr -0x4251 mem_patch_len -0x4253 mem_timers -0x4293 mem_link_key_exists -0x4294 mem_link_key_eeprom_head -0x4297 mem_link_key -0x42a7 mem_hci_cmd -0x42a8 mem_hci_conn_handle -0x42a9 mem_hci_plap -0x42ac mem_hci_puap -0x42ad mem_hci_pnap -0x42af mem_uartd_rxitems_got_data -0x42b0 mem_uartd_rxitems_threshold -0x42b1 mem_uartd_rx_timeout -0x42b3 mem_sco_attempt_cout -0x42b4 mem_tx_power -0x42b5 mem_sfreq_enable -0x42b6 mem_param_rf_setup -0x42b8 mem_param_pll_setup -0x42ba mem_avdtp_xmem_start -0x42ba mem_avdtpsignal_l2capch_ptr -0x42bc mem_avdtpmedia_l2capch_ptr -0x42be mem_audio_allow -0x42bf mem_audio_state -0x42c0 mem_audio_src_endpoint -0x42c1 mem_audio_src_endpoint_state -0x42c2 mem_a2dp_reconnct_delay_timer -0x42c3 mem_avdtp_xmem_end -0x42c3 mem_get_media_type -0x42c4 mem_get_codec_type -0x42c5 mem_get_samplefreq_channelmode -0x42c6 mem_get_blocklen_subb_allocation -0x42c7 mem_get_min_bitpool -0x42c8 mem_get_max_bitpool -0x42c9 mem_get_r_media_type -0x42ca mem_get_r_codec_type -0x42cb mem_get_r_samplefreq_channelmode -0x42cc mem_get_r_blocklen_subb_allocation -0x42cd mem_get_r_min_bitpool -0x42ce mem_get_r_max_bitpool -0x42cf mem_conf_media_type -0x42d0 mem_conf_codec_type -0x42d1 mem_conf_samplefreq_channelmode -0x42d2 mem_conf_blocklen_subb_allocation -0x42d3 mem_conf_min_bitpool -0x42d4 mem_conf_max_bitpool -0x42d5 mem_avc_local_transaction_label -0x42d6 mem_avdtp_signal -0x42d8 mem_avdtp_media -0x42da mem_a2dp_state -0x42db mem_a2dp_seq_num -0x42dd mem_audio_output_setting -0x42de mem_param_sco_use_cm0 -0x42df mem_media_in_fast_mode -0x42e0 mem_a2dp_buffer_judge_add -0x42e1 mem_param_a2dp_buffer_judge_add_limit -0x42e2 mem_a2dp_buffer_judge_drop -0x42e3 mem_param_a2dp_buffer_judge_drop_limit -0x42e4 mem_drop_or_add_process_state -0x42e5 mem_drop_or_add_min_receive_packet_size -0x42e7 mem_first_buffer_cache -0x42e8 mem_farrow_filter_delta_uk_sign_bit -0x42e9 mem_farrow_filter_delta_uk -0x42ed mem_a2dp_adjust_delta_uk_sign_bit -0x42ee mem_a2dp_adjust_delta_uk -0x42f2 mem_a2dp_adjust_total_work_sample -0x42f6 mem_a2dp_adjust_delta_bytes_sign_bit -0x42f7 mem_a2dp_adjust_delta_bytes -0x42f9 mem_slave_force_mute_a2dp_voice -0x42fa mem_slave_force_mute_a2dp_voice_cnt -0x42fb mem_tws_wait_sync_ok -0x42fc mem_last_a2dp_seq_num -0x42fe mem_param_a2dp_dac_sbc_same_buffer_flag -0x42ff mem_param_a2dp_dac_buffer_addr_mram_flag -0x4300 mem_param_a2dp_dac_buffer_start_addr -0x4302 mem_param_a2dp_dac_buffer_size -0x4304 mem_param_a2dp_sbc_buffer_addr_mram_flag -0x4305 mem_param_a2dp_sbc_buffer_start_addr -0x4307 mem_param_a2dp_sbc_buffer_size -0x4309 mem_app_state -0x430a mem_app_handshake_flag -0x430b mem_sniff_param_interval -0x430d mem_sniff_param_attempt -0x430f mem_sniff_param_timeout -0x4311 mem_cb_check_wakelock -0x4313 mem_cb_before_hibernate -0x4315 mem_cb_before_lpm -0x4317 mem_cb_le_process -0x4319 mem_cb_bt_process -0x431b mem_cb_idle_process -0x431d mem_cb_bb_event_process -0x431f mem_cb_event_timer -0x4321 mem_cb_keyscan -0x4323 mem_device_nums -0x4324 mem_uart_txpin -0x4325 mem_uart_rxpin -0x4326 mem_uart_rtspin -0x4327 mem_uart_ctspin -0x4328 mem_uartb_txpin -0x4329 mem_uartb_rxpin -0x432a mem_uartb_rtspin -0x432b mem_uartb_ctspin -0x432c mem_spid_sclkpin -0x432d mem_spid_sdiopin -0x432e mem_iic_sda_pin -0x432f mem_iic_scl_pin -0x4330 mem_ef_base -0x4333 mem_eeprom_block_size -0x4335 mem_mram_qspi_tx_addr -0x4337 mem_poweron_state -0x4338 mem_app_connection_options -0x4339 mem_app_disconn_reason -0x433b mem_app_disconn_reason_flag -0x433d mem_storage_start_addr -0x4340 mem_local_bdaddr -0x4346 mem_qspi_gpio_ncs -0x4347 mem_qspi_gpio_sck -0x4348 mem_qspi_gpio_io0 -0x4349 mem_qspi_gpio_io1 -0x434a mem_qspi_gpio_io2 -0x434b mem_qspi_gpio_io3 -0x434c mem_nv_data_ptr -0x434e mem_nv_data_number -0x434f mem_saradc_check_clk -0x4350 mem_saradc_flag -0x4351 mem_bat_read_timer -0x4352 mem_rf_debug_enable -0x4353 mem_rf_debug_rf_rx_debug_gpio -0x4354 mem_rf_debug_rf_tx_debug_gpio -0x4355 mem_rf_debug_rf_sync_detect_debug_gpio -0x4356 mem_rf_debug_rf_crc_error_debug_gpio -0x4357 mem_param_soft_dma_enable -0x4358 mem_param_soft_dma_table_start_addr -0x435b mem_param_m0_respin_sco_buffer_start_addr -0x435e mem_param_app_debug_info_timeout -0x435f mem_app_debug_info_timer -0x4360 mem_public_code_svn_version_code -0x4362 mem_public_code_time_info -0x4366 mem_public_code_size -0x4369 mem_fixed_param_area_start -0x4369 mem_fixed_param_area_reserve -0x436e mem_param_use_cm0_control_flag -0x436f mem_avctp_xmem_start -0x436f mem_avctp_tx_label -0x4370 mem_avr_state -0x4371 mem_avr_l2capch_ptr -0x4373 mem_hp_avctp_timer -0x4374 mem_avctp_play_state -0x4375 mem_vlm_notify_enable -0x4376 mem_vlm_notify_label -0x4377 mem_avctp_xmem_end -0x4377 mem_cvsd_in_addr_end -0x4379 mem_cvsd_in_addr_ptr -0x437b mem_cvsd_out_addr_start -0x437d mem_cvsd_out_addr_end -0x437f mem_cvsd_out_addr_ptr -0x4381 mem_pcm_in_addr_end -0x4383 mem_param_pcm_in_buffer_addr_mram_flag -0x4384 mem_param_pcm_in_buffer_addr -0x4386 mem_param_cvsd_out_buffer_addr_mram_flag -0x4387 mem_param_cvsd_out_buffer_addr -0x4389 mem_param_cvsd_in_buffer_addr_mram_flag -0x438a mem_param_cvsd_in_buffer_addr -0x438c mem_param_pcm_8k_out_buffer_addr_mram_flag -0x438d mem_param_pcm_8k_out_buffer_addr -0x438f mem_param_pcm_48k_out_buffer_addr_mram_flag -0x4390 mem_param_pcm_48k_out_buffer_addr -0x4392 mem_cvsd_start_send -0x4393 mem_baud -0x4395 mem_hci_lt_rx_state -0x4396 mem_hid_xmem_start -0x4396 mem_hid_l2capch_ptr -0x4398 mem_hidint_l2capch_ptr -0x439a mem_hid_xmem_end -0x439a mem_xmem_sco_start -0x439a mem_sco_asso_handle -0x439b mem_sco_handle -0x439d mem_sco_dsniff -0x439f mem_sco_tsniff -0x43a1 mem_sco_wsniff -0x43a2 mem_sco_tx_packet_type -0x43a3 mem_sco_rx_packet_type -0x43a4 mem_sco_rx_packet_len -0x43a6 mem_sco_tx_packet_len -0x43a8 mem_air_mode -0x43a9 mem_neogotiation_state -0x43aa mem_acl_amaddr -0x43ab mem_esco_amaddr -0x43ac mem_esco_arq -0x43ad mem_acl_arq -0x43ae mem_last_type_esco -0x43af mem_last_type_acl -0x43b0 mem_sco_poll -0x43b1 mem_esco_attempt -0x43b2 mem_esco_abnormal_attempt -0x43b3 mem_xmem_sco_end -0x43b3 mem_xmem_hf_state_start -0x43b3 mem_hf_state -0x43b4 mem_hf_call_state -0x43b5 mem_hf_command -0x43b6 mem_agoption -0x43b8 mem_AG_indicator_map -0x43bf mem_AG_indicator -0x43c6 mem_telephone_dialing_state -0x43c7 mem_telephone_dialing_timer -0x43c8 mem_xmem_hf_state_end -0x43c8 mem_hf_vlm_speaker -0x43c9 mem_music_vlm_speaker -0x43ca mem_hf_vlm_mic -0x43cb mem_at_payload_ptr -0x43cd mem_at_command_ptr -0x43cf mem_at_rfcomm_data_ptr -0x43d1 mem_UI_HF_brsf_feature -0x43d4 mem_codec_type -0x43d5 mem_codec_msbc_support -0x43d6 mem_cb_hfp_result_code -0x43d8 mem_hfp_battery_state -0x43d9 mem_esco_test -0x43da mem_sco_transaction_enable -0x43db mem_local_sco_in_process_flag -0x43dc mem_ipc_mcu_phase -0x43dd mem_ipc_mcu_state -0x43de mem_ipc_enable -0x43df mem_ipc_le_data_len -0x43e0 mem_ipc_le_data_att_handle -0x43e2 mem_ipc_tx_data_len -0x43e3 mem_ipc_tx_data_ptr -0x43e5 mem_ipc_loss_packet -0x43e7 mem_temp_for_addr -0x43ea mem_ipc_test_buff -0x43f4 mem_param_ipc_mem_block_start_addr -0x43f4 mem_param_ipc_to_bt_buf_start_addr -0x43f7 mem_param_ipc_to_bt_buf_end_addr -0x43fa mem_param_ipc_to_bt_wptr_addr -0x43fd mem_param_ipc_to_bt_rptr_addr -0x4400 mem_param_ipc_to_m0_wptr_addr -0x4403 mem_param_ipc_to_m0_rptr_addr -0x4406 mem_param_ipc_to_m0_buf_start_addr -0x4409 mem_param_ipc_mem_block_end_addr -0x4409 mem_param_ipc_to_m0_buf_end_addr -0x440c mem_param_debug_log_func_enable -0x440d mem_debug_log_temp_point -0x4411 mem_param_debug_log_mem_block_start_addr -0x4411 mem_param_debug_log_initial_flag_addr -0x4414 mem_param_debug_log_lock_flag_cm0_addr -0x4417 mem_param_debug_log_lock_flag_respin_addr -0x441a mem_param_debug_log_lock_victim_addr -0x441d mem_param_debug_log_read_index_addr -0x4420 mem_param_debug_log_write_index_addr -0x4423 mem_param_debug_log_buffer_start_addr -0x4426 mem_param_debug_log_mem_block_end_addr -0x4426 mem_param_debug_log_buffer_end_addr -0x4429 mem_wake_flag -0x442a mem_m0_lpm_flag -0x442c mem_l2cap_xmem_start -0x442c mem_l2cap_tx_multi_offset//0 means single packet -0x442e mem_l2cap_pending_info -0x442e mem_l2cap_pending_id0 -0x442f mem_l2cap_pending_delay_time0 -0x4433 mem_l2cap_pending_ptr0 -0x4435 mem_l2cap_pending_id1 -0x4436 mem_l2cap_pending_delay_time1 -0x443a mem_l2cap_pending_ptr1 -0x443c mem_l2cap_pending_id2 -0x443d mem_l2cap_pending_delay_time2 -0x4441 mem_l2cap_pending_ptr2 -0x4443 mem_l2cap_pending_count -0x4444 mem_l2cap_active_ch_count -0x4445 mem_l2cap_ch_info -0x4445 mem_l2cap_ch_psm0 -0x4446 mem_l2cap_ch_state0 -0x4447 mem_l2cap_local_cid0 -0x4449 mem_l2cap_remote_cid0 -0x444b mem_l2cap_ch_psm1 -0x444c mem_l2cap_ch_state1 -0x444d mem_l2cap_local_cid1 -0x444f mem_l2cap_remote_cid1 -0x4451 mem_l2cap_ch_psm2 -0x4452 mem_l2cap_ch_state2 -0x4453 mem_l2cap_local_cid2 -0x4455 mem_l2cap_remote_cid2 -0x4457 mem_l2cap_ch_psm3 -0x4458 mem_l2cap_ch_state3 -0x4459 mem_l2cap_local_cid3 -0x445b mem_l2cap_remote_cid3 -0x445d mem_l2cap_ch_psm4 -0x445e mem_l2cap_ch_state4 -0x445f mem_l2cap_local_cid4 -0x4461 mem_l2cap_remote_cid4 -0x4463 mem_l2cap_ch_psm5 -0x4464 mem_l2cap_ch_state5 -0x4465 mem_l2cap_local_cid5 -0x4467 mem_l2cap_remote_cid5 -0x4469 mem_l2cap_ch_psm6 -0x446a mem_l2cap_ch_state6 -0x446b mem_l2cap_local_cid6 -0x446d mem_l2cap_remote_cid6 -0x446f mem_l2cap_ch_psm7 -0x4470 mem_l2cap_ch_state7 -0x4471 mem_l2cap_local_cid7 -0x4473 mem_l2cap_remote_cid7 -0x4475 mem_l2cap_prepare_confreq_count -0x4476 mem_l2cap_channel_disconnect_timer -0x4477 mem_sdp_state -0x4478 mem_ML2CAP_comm_id -0x4479 mem_used_map -0x447a mem_tx_fifo0 -0x447a mem_tx_fifo0_map -0x447b mem_tx_fifo0_ptr -0x447d mem_tx_fifo1 -0x447d mem_tx_fifo1_map -0x447e mem_tx_fifo1_ptr -0x4480 mem_tx_fifo2 -0x4480 mem_tx_fifo2_map -0x4481 mem_tx_fifo2_ptr -0x4483 mem_tx_fifo3 -0x4483 mem_tx_fifo3_map -0x4484 mem_tx_fifo3_ptr -0x4486 mem_tx_fifo_end -0x4486 mem_alloc_block -0x4486 mem_alloc_header -0x4488 mem_alloc_rptr -0x448a mem_alloc_wptr -0x448c mem_alloc_end -0x448e mem_alloc_cur_len -0x448f mem_alloc_block_start -0x449e mem_media_release -0x449f mem_media_block -0x449f mem_media_header -0x44a1 mem_media_rptr -0x44a3 mem_media_wptr -0x44a5 mem_media_end -0x44a7 mem_media_cur_len -0x44a8 mem_media_block_start -0x44b7 mem_lcp_block -0x44b7 mem_lcp_header -0x44b9 mem_lcp_rptr -0x44bb mem_lcp_wptr -0x44bd mem_lcp_end -0x44bf mem_lcp_cur_len -0x44c0 mem_lcp_block_start -0x44cf mem_l2cap_flow_ctrl_flag -0x44d0 mem_l2cap_pending_item -0x44d1 mem_l2cap_rxbuff_len_error -0x44d2 mem_l2cap_xmem_end -0x44d2 mem_l2cap_rx_max_lenth -0x44d4 mem_l2cap_rx_malloc_num -0x44d5 mem_le_dsniff -0x44d7 mem_le_conn_interval -0x44d9 mem_le_scan_enable -0x44da mem_le_scan_interval -0x44dc mem_le_scan_window -0x44de mem_le_adv_enable -0x44df mem_le_adv_data_len -0x44e0 mem_le_adv_data -0x44ff mem_le_scan_data_len -0x4500 mem_le_scan_data -0x451f mem_le_interal_min -0x4521 mem_le_interal_max -0x4523 mem_le_latency -0x4525 mem_le_timeout -0x4527 mem_le_ch_mapped -0x4528 mem_le_new_map -0x452d mem_le_new_param -0x4536 mem_le_txheader -0x4537 mem_le_txlen -0x4538 mem_le_txpayload -0x453a mem_le_txcid -0x453c mem_le_l2cap -0x453d mem_le_l2cap_response -0x453e mem_le_txbdy -0x455d mem_le_pcnt_tx -0x4562 mem_le_pcnt_rx -0x4567 mem_le_last_mic -0x456b mem_le_ivm -0x456f mem_le_ivs -0x4573 mem_le_ltk -0x4583 mem_ltk_exists -0x4584 mem_le_rconfirm -0x4594 mem_le_srand -0x45a4 mem_le_iat -0x45a5 mem_le_rat -0x45a6 mem_le_preq -0x45a7 mem_le_preq_iocap -0x45a8 mem_le_preq_oob -0x45a9 mem_le_preq_auth -0x45aa mem_le_preq_max_keysize -0x45ab mem_le_preq_init_key_distribution -0x45ac mem_le_preq_resp_key_distribution -0x45ad mem_le_pres -0x45ae mem_le_pres_iocap -0x45af mem_le_pres_oob -0x45b0 mem_le_pres_auth -0x45b1 mem_le_pres_max_keysize -0x45b2 mem_le_pres_init_key_distribution -0x45b3 mem_le_pres_resp_key_distribution -0x45b4 mem_le_pairing_state -0x45b5 mem_le_enc_state -0x45b6 mem_le_pairing_mode -0x45b7 mem_le_tk -0x45bb mem_le_ediv -0x45bd mem_le_rand -0x45c5 mem_le_irk -0x45d5 mem_le_fixed_passkey_flag -0x45d6 mem_le_secure_connect_enable -0x45d7 mem_le_secure_connect_flag -0x45d8 mem_le_sc_calc -0x45d9 mem_le_secure_connect_state -0x45da mem_le_sc_confirm_gkey_flag -0x45db mem_le_sc_local_key_invalid -0x45dc mem_le_pairing_handle -0x45de mem_le_search_handle_start -0x45e0 mem_le_search_handle_end -0x45e2 mem_le_att_offset -0x45e2 mem_le_search_att_type_length -0x45e3 mem_le_search_att_type -0x45f3 mem_le_notify_handle -0x45f5 mem_le_search_uuid_length -0x45f6 mem_le_search_uuid -0x4606 mem_le_handle_data_len -0x4607 mem_le_handle_data -0x4617 mem_le_adv_param -0x4617 mem_le_adv_interval_min -0x4619 mem_le_adv_interval_max -0x461b mem_le_adv_type -0x461c mem_le_adv_own_addr_type -0x461d mem_le_adv_direct_addr_type -0x461e mem_le_adv_direct_addr -0x4624 mem_le_adv_channel_map -0x4625 mem_le_adv_filter_policy -0x4626 mem_le_conn_param -0x4626 mem_le_conn_peer_addr_type -0x4627 mem_le_conn_peer_addr -0x462d mem_le_conn_own_addr_type -0x462e mem_le_conn_interval_min -0x4630 mem_le_conn_interval_max -0x4632 mem_le_conn_latency -0x4634 mem_le_conn_superto -0x4636 mem_le_scan_params -0x4636 mem_le_scan_type -0x4637 mem_le_scan_own_addr_type -0x4638 mem_le_scan_filter_policy -0x4639 mem_le_lap -0x463c mem_le_uap -0x463d mem_le_nap -0x463f mem_le_xtype_fifo -0x4644 mem_le_transmit_window -0x4648 mem_le_connection_updata_param -0x4658 mem_le_l2cap_size -0x465a mem_le_packet_len_recved -0x465b mem_le_tx_buff_used -0x465c mem_le_tx_ptr0 -0x465e mem_le_tx_ptr1 -0x4660 mem_le_tx_ptr2 -0x4662 mem_le_tx_ptr3 -0x4664 mem_ui_le_uuid_table -0x4666 mem_le_cur_attlist_start_ptr -0x4668 mem_le_cur_handle_start -0x466a mem_le_cur_handle_end -0x466c mem_le_cur_uuid_lenth -0x466d mem_le_cur_uuid -0x467d mem_notify_handle_pool -0x4681 mem_le_curr_att_len -0x4682 mem_le_signaling_identifier -0x4683 mem_le_more_data -0x4684 mem_lmp_version -0x4687 mem_lmp_subversion -0x4689 mem_local_name_length -0x468a mem_local_name -0x468d mem_local_name2 -0x46cd mem_local_name_end -0x46ce mem_unsniff2sniff_timer -0x46cf mem_switch_flag -0x46d0 mem_role_switch_flag -0x46d1 mem_eeprom_ota_base_addr/*the start- writing addr in eeprom */ -0x46d3 mem_rfc_xmem_start -0x46d3 mem_pn_dlci -0x46d4 mem_pn_max_frame_size -0x46d6 memFCStemp1 -0x46d7 memFCStemp2 -0x46d8 memFCStemp3 -0x46d9 mem_rfcomm_initiator -0x46da mem_remote_spp_channel -0x46db mem_HIUfcs_SPP -0x46dc mem_HIUfcs_SPP_WCredits -0x46dd mem_remote_credits -0x46df mem_credit_given -0x46e0 mem_ms_channel -0x46e1 mem_current_packet_length -0x46e3 mem_profile_channel -0x46e4 mem_rfc_l2capch_ptr -0x46e6 mem_rfc_server_state -0x46e8 mem_rfc_xmem_end -0x46e8 mem_ui_uuid_table -0x46ea mem_all_uuid_16bits -0x4700 mem_all_uuid_128bits -0x4722 mem_sdp_l2capch_ptr -0x4724 mem_sp_local_key_invalid -0x4725 mem_le_private_key_256 -0x4745 mem_le_pubkey_local_x_256 -0x4765 mem_le_pubkey_local_y_256 -0x4785 mem_sp_private_key -0x479d mem_sp_pubkey_local -0x479d mem_sp_pubkey_local_x -0x47b5 mem_sp_pubkey_local_x_end -0x47b5 mem_sp_pubkey_local_y -0x47cd mem_ssp_enable -0x47ce mem_sp_iocap_local -0x47d1 mem_ssp_mode_flag -0x47d2 mem_spp_reject_justwork_flag -0x47d3 mem_sp_iocap_remote -0x47d6 mem_flag_mode_ssp_pin -0x47d7 mem_authentication_passkey_times -0x47d8 mem_passkey_1bit -0x47d9 mem_flag_pairing_state -0x47da mem_ipc_lock_bt -0x47db mem_ipc_lock_c51 -0x47dc mem_ipc_fifo_bt2c51 -0x47e1 mem_ipc_fifo_c512bt -0x47e6 mem_ui_timer_last_btclk -0x47ea mem_ui_state_map -0x47ec mem_discovery_timer_count -0x47ee mem_discovery_timeout -0x47f0 mem_ui_profile_supported -0x47f1 mem_pin_length -0x47f2 mem_pin -0x4802 mem_keyscan_switch -0x4803 mem_kscan_row_nums -0x4804 mem_kscan_col_nums -0x4805 mem_row_scanned -0x4806 mem_col_scanned -0x4807 mem_row_cnt -0x4808 mem_get_keypress_flag -0x4809 mem_kscan_row_gpio_pin -0x4829 mem_kscan_col_gpio_pin -0x4849 mem_button_gpio1 -0x484a mem_button_last_state1 -0x484b mem_button_timer1 -0x484c mem_button_press_count1 -0x484d mem_button_timeout1 -0x484e mem_button_press_timeout1 -0x484f mem_button_down_cb1 -0x4851 mem_button_up_cb1 -0x4853 mem_button_longpress_cb1 -0x4855 mem_button_long_release_cb1 -0x4857 mem_button_gpio2 -0x4858 mem_button_last_state2 -0x4859 mem_button_timer2 -0x485a mem_button_press_count2 -0x485b mem_button_timeout2 -0x485c mem_button_press_timeout2 -0x485d mem_button_down_cb2 -0x485f mem_button_up_cb2 -0x4861 mem_button_longpress_cb2 -0x4863 mem_button_long_release_cb2 -0x4865 mem_led_gpio1 -0x4866 mem_led_state1 -0x4867 mem_led_on_timer1 -0x4868 mem_led_off_timer1 -0x4869 mem_led_repeat1 -0x486a mem_led_timer1 -0x486b mem_led_gpio2 -0x486c mem_led_state2 -0x486d mem_led_on_timer2 -0x486e mem_led_off_timer2 -0x486f mem_led_repeat2 -0x4870 mem_led_timer2 -0x4871 mem_uppersm_xmem_start -0x4871 mem_major_uppersm -0x4872 mem_sub_uppersm -0x4873 mem_uppersm_list -0x4878 mem_uppersm_disl2capch_index -0x4879 mem_uppersm_xmem_end -0x4879 mem_m0_lock_qspi -0x487a mem_m0_pause_state -0x487b mem_xip_flash_offset -0x487e mem_xip_option -0x4880 mem_xip_flash_read_cmd -0x4881 mem_zcode_current_number -0x4882 mem_zcode_buff -0x4884 mem_ipc_to_bt_write_flag -0x4885 mem_ipc_to_bt_read_flag -0x4886 mem_ipc_to_m0_write_flag -0x4887 mem_ipc_to_m0_read_flag -0x4888 mem_ipc_to_bt_victim -0x4889 mem_ipc_to_m0_victim -0x488a mem_le_local_mtu -0x488c mem_mtu_size -0x488e mem_tws_bdaddr -0x488e mem_tws_lap -0x4891 mem_tws_uap -0x4892 mem_tws_nap -0x4894 mem_hsp_role -0x4895 mem_auto_hsp_role -0x4896 mem_tws_allow_pairing_rssi_limit -0x4897 mem_tws_role -0x4898 mem_tws_state -0x4899 mem_tws_last_rcv_phone_packet_crc_fail -0x489a mem_tws_rcv_ack -0x489b mem_tws_local_rcv_packet -0x489c mem_tws_last_send_ack -0x489d mem_tws_timeout_timer -0x489e mem_param_tws_timeout_master -0x489f mem_param_tws_timeout_slave -0x48a0 mem_tws_observe_wait_connect_timeout_timer -0x48a1 mem_param_tws_observe_wait_connect_timeout_no_connect -0x48a2 mem_param_tws_observe_wait_connect_timeout_error_disconnect -0x48a3 mem_tws_slave_loss_link_listen_master_timeout_timer -0x48a4 mem_param_tws_slave_loss_link_listen_master_timeout -0x48a5 mem_tws_poll_slave_timer -0x48a6 mem_param_tws_poll_slave -0x48a7 mem_tws_master_wait_slave_timeout_timer -0x48a8 mem_param_tws_master_wait_slave_timeout -0x48a9 mem_tws_m2s_ack_send_timeout_count -0x48aa mem_param_tws_m2s_ack_send_timeout -0x48ab mem_tws_poll_null_ack_interval -0x48ac mem_tws_poll_null_ack_interval_count -0x48ad mem_loss_match -0x48af mem_count_rcv_adv -0x48b0 mem_tws_adv_match -0x48b1 mem_tws_ack -0x48b2 mem_tws_count_poll -0x48b4 mem_tws_role_switch_in_process -0x48b5 mem_tws_slave_wait_master_first_polling_flag -0x48b6 mem_tws_profile_connected -0x48b7 mem_tws_profile_disconnected_after_connected -0x48b8 mem_tws_adv_count -0x48b9 mem_tws_adv_try_num -0x48ba mem_tws_snd_op -0x48bb mem_tws_snd_op_nextseq -0x48bc mem_tws_snd_cur_arq -0x48bd mem_tws_rcv_op -0x48be mem_tws_rcv_op_nextseq -0x48bf mem_tws_rcv_old_seq -0x48c0 mem_tws_cmd_fifo -0x48c5 mem_tws_no_connect_cmd_trans_limit -0x48c6 mem_tws_no_connect_cmd -0x48c7 mem_tws_is_slave_send -0x48c8 mem_tws_is_need_send_header -0x48c9 mem_tws_remote_version -0x48cb mem_param_tws_tx_power -0x48cc mem_le_tws_scan_interval_min -0x48ce mem_le_tws_scan_interval_max -0x48d0 mem_le_tws_scan_interval -0x48d2 mem_le_tws_scan_window -0x48d4 mem_le_tws_adv_interval -0x48d6 mem_param_le_tws_adv_interval_normal -0x48d8 mem_param_le_tws_adv_interval_master_listen -0x48da mem_tws_first_packet_dynamic_buffer -0x48da mem_tws_first_packet_dynamic_buffer_status -0x48dc mem_tws_first_packet_dynamic_buffer_local_bdaddr -0x48e2 mem_tws_first_packet_dynamic_buffer_paired_bdaddr -0x48e8 mem_tws_first_packet_dynamic_buffer_reserved -0x48f8 mem_tws_allow_pairing -0x48f9 mem_tws_last_paired_lap -0x48ff mem_tws_rf_start_anchor -0x4901 mem_tws_rf_rcv_window_size -0x4903 mem_tws_rf_packet_rx_window_size -0x4905 mem_tws_rf_slave_send_full_packet_sleep_time -0x4907 mem_tws_rf_master_check_raw_id_time -0x4909 mem_temp_rf_freq_index -0x490a mem_temp_rf_switch_flag -0x490b mem_tws_buffer_master_switch -0x490b mem_tws_buffer_master_switch_reason -0x490c mem_process_sync_buffer -0x490c mem_process_a2dp_seq_num -0x490e mem_process_clk -0x4912 mem_process_clkrt -0x4914 mem_process_used_buffer_size -0x4916 mem_process_audio_vol -0x4917 mem_process_sync_receive_buffer// Tws process sync packet -0x4917 mem_process_receive_a2dp_seq_num -0x4919 mem_process_receive_clk -0x491d mem_process_receive_clkrt -0x491f mem_process_receive_used_buffer_size -0x4921 mem_process_receive_audio_vol -0x4922 mem_enable_hfp_start_sync// Tws hfp start sync control -0x4923 mem_hfp_start_sync_buffer// Tws hfp start sync packet -0x4923 mem_hfp_start_sync_clk -0x4927 mem_param_tws_send_channel_array -0x492b mem_tws_last_send_channel_index -0x492c mem_conn_update_timer -0x492e mem_save_state -0x492f mem_hibernate_enable -0x4930 mem_timer_flag -0x4931 mem_timer_start -0x49f9 mem_timer_header -0x49fd mem_sequence_number_rx -0x49fe mem_sequence_number_tx -0x49ff mem_msbc_pcm_in_wptr -0x4a01 mem_msbc_pcm_in_rptr -0x4a03 mem_msbc_out_wptr -0x4a05 mem_msbc_out_rptr -0x4a07 mem_msbc_in_wptr -0x4a09 mem_msbc_in_rptr -0x4a0b mem_msbc_pcm_out_saddr -0x4a0d mem_msbc_pcm_out_wptr -0x4a0f mem_msbc_pcm_out_rptr -0x4a11 mem_msbc_packet_len -0x4a13 mem_msbc_pcm_packet_len -0x4a15 mem_msbc_enc_dec_bt_lock -0x4a16 mem_msbc_enc_dec_m0_lock -0x4a17 mem_msbc_adc_start_send -0x4a18 mem_vp_language -0x4a19 mem_vp_play_phonenumber -0x4a1a mem_vp_mram_flag -0x4a1b mem_vp_addr_temp -0x4a1e mem_vp_enable -0x4a1f mem_vp_dac_addr -0x4a21 mem_vp_dac_half -0x4a23 mem_vp_play_block_num -0x4a24 mem_vp_offset -0x4a26 mem_vp_start_addr -0x4a29 mem_vp_end_addr -0x4a2c mem_vp_play_by_cmd -0x4a2d mem_vp_play_addr_offset_temp -0x4a2e mem_param_tishi_start_addr -0x4a30 mem_vp_addr -0x4ac0 mem_vp_end -0x4ac0 mem_ota_notify_handle -0x4ac1 mem_ota_write_handle -0x4ac2 mem_ota_version -0x4ac4 mem_ota_buck_size -0x4ac6 mem_ota_packet_max_len -0x4ac8 mem_ota_work_mode -0x4ac9 mem_adc_start_addr -0x4acb mem_adc_buf_size -0x4acd mem_dac_start_addr -0x4acf mem_dac_buf_size -0x4ad1 mem_dac_clk -0x4ad2 mem_dac_mram_flag -0x4ad3 mem_adc_mram_flag -0x4ad4 mem_mono_flag -0x4ad5 mem_l_din_sel -0x4ad6 mem_r_din_sel -0x4ad7 mem_eq_flag -0x4ad8 mem_acl_credits -0x4ada mem_allow_switch -0x4adb mem_hci_acl_queue_start/*param_acl_pktcnt+2 byte*/ -0x4adf mem_hci_wake_clk -0x4ad8 mem_nv_data -0x4ad8 mem_nv_data0 -0x4af0 mem_nv_data1 -0x4b08 mem_nv_data2 -0x4b20 mem_nv_data3 -0x4b38 mem_nv_data4 -0x4b50 mem_battery_vol -0x4b51 mem_coef_base_addr -0x4b54 mem_ipc_tx_buf -0x4c1c mem_le_att_list -0x4c80 mem_a2dp_uuid -0x4e74 mem_tws_fac_adv_name -0x4e90 mem_play_button_state -0x4e91 mem_hibernate_flag -0x4e92 mem_leadv_action -0x4e93 mem_bat_level -0x4e94 mem_tws_master_skip_count -0x4e95 mem_change_ota_soft_flag -0x4e96 mem_tws_receive_spec_le_adv -0x4eb3 mem_lpm_write_temp_adc_low -0x4eb7 mem_lpm_write_temp_adc_high -0x4ebb mem_lpm_write_temp_charge_control -0x4ebf mem_lpm_write_temp_charge_wakeup_low_active -0x4ec1 mem_lpm_write_temp_charge_wakeup_high_active -0x4ec3 mem_ana_vol_value -0x4ec4 mem_a2dp_start_force_mute_voice_cnt -0x4ec5 mem_rssi_sum -0x4ec6 mem_rssi_update -0x4ec7 mem_efuse_dc_offset -0x4ec7 mem_efuse_dc_offset_l -0x4ec9 mem_efuse_dc_offset_r -0x4ecb mem_efuse_dc_offset_f6 -0x4ecb mem_efuse_dc_offset_l_f6 -0x4ecd mem_efuse_dc_offset_r_f6 -0x4ecf mem_efuse_adc_offset -0x4ecf mem_0_5_adc_io_data -0x4ed1 mem_3v_adc_hvin_data -0x4ed3 mem_1v_adc_io_data -0x4ed5 mem_5v_adc_hvin_data -0x4ed7 mem_adc_current_value -0x4ed9 mem_uart_tx_buffer -0x4edb mem_uart_tx_buffer_end -0x4edd mem_uart_rx_buffer -0x4edf mem_uart_rx_buffer_end -0x4ee1 mem_tws_master_connect_with_a2dp_start -0x4ee2 mem_xlmp_conn_state -0x4ee3 mem_xlmp_clock_offset_valid -0x4ee4 mem_slave_conflict_cnt -0x4ee5 mem_media_voice_not_good_detect_empty_detect_cnt -0x4ee6 mem_media_voice_not_good_detect_packet_total_cnt -0x4ee7 mem_media_voice_not_good_force_mute -0x4ee8 mem_headset_end -0x4ad8 mem_usb_mouse_data -0x4ae8 mem_usb_kb_data -0x4af8 mem_usb_kb_multikey -0x4b08 mem_usb0_get_report_data Index: tag/Soft/ModuleDemo/ADC/AD_Sound_Recording/CM0/Prj/Output/otp.dat =================================================================== --- /YC1121E/SoftCode/MCU/tag/Soft/ModuleDemo/ADC/AD_Sound_Recording/CM0/Prj/Output/otp.dat (revision 4280) +++ /YC1121E/SoftCode/MCU/tag/Soft/ModuleDemo/ADC/AD_Sound_Recording/CM0/Prj/Output/otp.dat (nonexistent) @@ -1,8 +0,0 @@ -00 -02 -aa -55 -00 -00 -b3 -23 Index: tag/Soft/ModuleDemo/ADC/AD_Sound_Recording/CM0/Prj/Output/out.rom =================================================================== --- /YC1121E/SoftCode/MCU/tag/Soft/ModuleDemo/ADC/AD_Sound_Recording/CM0/Prj/Output/out.rom (revision 4280) +++ /YC1121E/SoftCode/MCU/tag/Soft/ModuleDemo/ADC/AD_Sound_Recording/CM0/Prj/Output/out.rom (nonexistent) @@ -1,7716 +0,0 @@ -1001b640 -000000c1 -000000d9 -000000d9 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -000000d9 -00000000 -00000000 -000000d9 -00001213 -000000d9 -000000d9 -000000d9 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00 00 00 00 00 -#Client Characteristic Configuration -04 00 02 02 29 02 01 00 - -#Characteristic rx--write -05 00 02 03 28 01 04 -06 00 02 22 ff 14 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -#End of Attribute list -00 00 - - - - -#a2dp uuid -mem_a2dp_uuid: -#uuids -03 111e 0003 0100 - -#handle -00010000 - -#total length -360037 - -#attribute start, first 4 digit is attribute ID -09 00 00 0A 00 01 00 00 -09 00 01 35 06 19 11 1E 19 12 03 09 00 04 35 -0C 35 03 19 01 00 35 05 19 00 03 08 01 09 00 -09 35 08 35 06 19 11 1E 09 01 05 09 03 11 09 -00 1F -#attribute end - -#uuids -03 1108 0003 0100 - -#handle -00010001 - -#total length -36005e - -#attribute start, first 4 digit is attribute ID -09 00 00 0A 00 01 00 01 -09 00 01 35 09 19 11 08 19 12 03 19 11 31 -09 00 04 35 0C 35 03 19 01 00 35 05 19 00 03 08 02 -09 00 05 35 03 19 10 02 -09 00 06 35 09 09 65 6E 09 00 6A 09 01 00 -09 00 09 35 08 35 06 19 11 08 09 01 02 -09 01 00 25 0A 48 65 61 64 73 65 74 2D 48 53 -09 03 02 28 01 -#attribute end - -#uuids -03 1200 1002 0001 - -#handle -00010002 - -#total length -360033 - -#attribute start, first 4 digit is attribute ID -09 00 00 0A 00 01 00 02 -09 00 01 35 03 19 12 00 09 02 00 -09 01 03 09 02 01 09 00 94 09 02 02 09 12 34 09 02 -03 09 01 01 09 02 04 28 01 09 02 05 -09 00 01 - -#uuids -04 110d 110b 0003 0100 - -#handle -00010003 - -#total length -36002a - -#attribute start, first 4 digit is attribute ID -09 00 01 35 03 19 11 0B 09 00 04 35 -10 35 06 19 01 00 09 00 19 35 06 19 -00 19 09 01 03 09 00 09 35 08 35 06 -19 11 0D 09 01 03 - -#uuids -03 110e 0003 0100 - -#handle -00010004 - -#total length -36001e - -#attribute start, first 4 digit is attribute ID -09 00 01 35 06 19 11 0e 19 11 0f 09 00 09 35 08 35 06 19 11 0e 09 01 05 09 03 11 09 00 01 - -#uuids -03 110c 0003 0100 - -#handle -00010005 - -#total length -36001b - -#attribute start, first 4 digit is attribute ID -09 00 01 35 03 19 11 0c 09 00 09 35 08 35 06 19 11 0e 09 01 05 09 03 11 09 00 02 - -00 -00 - -mem_ui_uuid_table:mem_a2dp_uuid -mem_lpm_mode:01 -mem_lpm_overhead:08 -mem_lpm_interval:00 02 -mem_lpm_mult:04 -mem_lpm_mult_timeout:03 -mem_ptt:01 -mem_features: -ff -ff -8f -fa #fe--EDR F8--BR -8b #AFHclose 83 #AFHenable_slave cap and classification LMP_SLAVE_AFH_CLASSIFICATION enable 9b, disable 8b -b9 #9d -59 -82 - -mem_xip_option:5d 40 bb - -mem_ui_le_uuid_table:mem_le_att_list - -mem_seqi:7f - -mem_le_connection_updata_param: -06 00 -06 00 -2b 01 -b0 04 - -mem_codec_msbc_support:00 -mem_codec_type:01 - -mem_UI_HF_brsf_feature:313538 #30 33 30 -mem_le_more_data:01 -mem_ipc_enable:01 - -mem_tws_state:00 -mem_tws_bdaddr:96 55 12 11 33 62 -#mem_tws_bdaddr:96 45 12 00 19 62 - -mem_tws_allow_pairing:01 - - -mem_tws_rf_start_anchor:b0 04 # 0x1e0 40us, 0x78 10us, 0x4b0 100us, 0x618 130us -mem_tws_rf_rcv_window_size:78 00 - -mem_tws_rf_packet_rx_window_size:f0 0a # 2800 -mem_tws_rf_slave_send_full_packet_sleep_time:58 02 # 50us -# mem_tws_rf_rcv_window_size + 72us + hardware_delay(18us) -# send delay is mem_tws_rf_slave_send_full_packet_sleep_time, so we can think the judge below -# mem_tws_rf_packet_rx_window_size - (mem_tws_rf_rcv_window_size + 72us + hardware_delay(18us) + mem_tws_rf_slave_send_full_packet_sleep_time/2) -mem_tws_rf_master_check_raw_id_time:db 04 - -mem_rf_debug_enable: 00 -mem_rf_debug_rf_rx_debug_gpio: 18 -mem_rf_debug_rf_tx_debug_gpio: 19 -mem_rf_debug_rf_sync_detect_debug_gpio: 1c -mem_rf_debug_rf_crc_error_debug_gpio: 1f - -mem_le_tws_scan_interval:28 00 -mem_le_tws_scan_window:0c 00 -mem_param_le_tws_adv_interval_normal:00 01 -mem_param_le_tws_adv_interval_master_listen:58 00 - -# Tws Important timer param start -# master timeout must small than slave timeout -mem_param_tws_timeout_master:23 -mem_param_tws_timeout_slave:28 -# Need big to normal connection timeout, becouse our role switch may be error. -mem_param_tws_observe_wait_connect_timeout_no_connect:3c -# Need think may be master disconnect timeout not same -mem_param_tws_observe_wait_connect_timeout_error_disconnect:c8 -# Need big then mem_param_tws_timeout_master -mem_param_tws_slave_loss_link_listen_master_timeout:28 - -mem_param_tws_poll_slave:0d - -#For master wait slave connected timeout, unit is 100ms -mem_param_tws_master_wait_slave_timeout:20 - -#For master switch wait timeout, unit is count -mem_param_tws_m2s_ack_send_timeout:14 - -#For master receive poll null skip count -mem_tws_poll_null_ack_interval:02 -# Tws Important timer param end - -mem_param_a2dp_buffer_judge_add_limit:64 -mem_param_a2dp_buffer_judge_drop_limit:64 - -mem_param_sco_use_cm0:01 - -# below is default setting -mem_param_pcm_in_buffer_addr_mram_flag: 00 -mem_param_pcm_in_buffer_addr:00 20 -mem_param_cvsd_out_buffer_addr_mram_flag:00 -mem_param_cvsd_out_buffer_addr:00 28 -mem_param_cvsd_in_buffer_addr_mram_flag:00 -mem_param_cvsd_in_buffer_addr:00 30 -mem_param_pcm_8k_out_buffer_addr_mram_flag:00 -mem_param_pcm_8k_out_buffer_addr:00 38 -mem_param_pcm_48k_out_buffer_addr_mram_flag:01 -mem_param_pcm_48k_out_buffer_addr:40 b6 - - -# ipc define -#mem_param_ipc_mem_block_start_addr -mem_param_ipc_to_bt_buf_start_addr:00 d8 01 -mem_param_ipc_to_bt_buf_end_addr:00 db 01 -mem_param_ipc_to_bt_wptr_addr:00 db 01 -mem_param_ipc_to_bt_rptr_addr:04 db 01 -mem_param_ipc_to_m0_wptr_addr:08 db 01 -mem_param_ipc_to_m0_rptr_addr:0c db 01 -mem_param_ipc_to_m0_buf_start_addr:50 db 01 -mem_param_ipc_to_m0_buf_end_addr:00 dd 01 -#mem_param_ipc_mem_block_end_addr - - -# debug log define -#mem_param_debug_log_mem_block_start_addr -mem_param_debug_log_func_enable:01 - -mem_param_debug_log_initial_flag_addr:10 db 01 -mem_param_debug_log_lock_flag_cm0_addr:11 db 01 -mem_param_debug_log_lock_flag_respin_addr:12 db 01 -mem_param_debug_log_lock_victim_addr:13 db 01 -mem_param_debug_log_read_index_addr:14 db 01 -mem_param_debug_log_write_index_addr:16 db 01 -mem_param_debug_log_buffer_start_addr:18 db 01 -mem_param_debug_log_buffer_end_addr:50 db 01 -#mem_param_debug_log_mem_block_end_addr - -# soft dma define -# size is SOFT_DMA_TABLE_TOTAL_COUNT*4 + SOFT_DMA_TABLE_TOTAL_COUNT*SOFT_DMA_TABLE_UNIT_SIZE = 0x100 -mem_param_soft_dma_enable:01 -mem_param_soft_dma_table_start_addr:10 dd 01 - - -# sco m0 rx buffer define -# size is M0_SCO_RX_BUFFER_SIZE + M0_SCO_TX_BUFFER_SIZE -mem_param_m0_respin_sco_buffer_start_addr:10 de 01 - -# a2dp memory setting -mem_param_a2dp_dac_sbc_same_buffer_flag:01 - -mem_param_a2dp_dac_buffer_addr_mram_flag:00 -mem_param_a2dp_dac_buffer_start_addr:00 20 -mem_param_a2dp_dac_buffer_size:00 20 - -mem_param_a2dp_sbc_buffer_addr_mram_flag:00 -mem_param_a2dp_sbc_buffer_start_addr:00 20 -mem_param_a2dp_sbc_buffer_size:00 20 - - -mem_param_use_cm0_control_flag:01 -# tishi buffer size is 0x1000 -mem_param_tishi_start_addr:00 c8 - -#mem_app_debug_info_timer use to set first debug timeout -#mem_param_app_debug_info_timeout use to set period -mem_app_debug_info_timer:05 -mem_param_app_debug_info_timeout:32 - -mem_param_tws_tx_power:00 - -mem_param_tws_send_channel_array:08 24 08 24 -#mem_param_tws_send_channel_array:20 20 20 20 -#mem_param_tws_send_channel_array:08 09 10 11 - -mem_tx_power:02 - -mem_sfreq_enable:01 -#mem_param_rf_setup must big then mem_param_pll_setup, be-careful, mem_param_rf_setup real value = 0xEA6 - value -#we suggest must reserve 0x3A6, means mem_param_rf_setup = (0xEA6 - mem_param_pll_setup - 0x3A6) -mem_param_rf_setup:B8 07 -mem_param_pll_setup:48 03 -#mem_param_rf_setup:00 06 -#mem_param_pll_setup:00 05 - -mem_audio_output_setting: 01 - - -mem_coef_base_addr:00 e0 1f - -mem_mram_qspi_tx_addr:00 60 - -mem_vp_addr: -000000 000000 -000000 000000 -000000 000000 -000000 000000 -000000 000000 -000000 000000 -000000 000000 -000000 000000 -000000 000000 -000000 000000 - -000000 000000 -000000 000000 -000000 000000 -000000 000000 -000000 000000 -000000 000000 -000000 000000 -000000 000000 -000000 000000 -000000 000000 - -000000 000000 -000000 000000 -000000 000000 -000000 000000 - -mem_keyscan_switch:00 -mem_kscan_row_nums:06 -mem_kscan_col_nums:06 -mem_kscan_row_gpio_pin: 01 02 05 09 0a 0b -mem_kscan_col_gpio_pin:06 07 08 10 11 12 - - - -# User Change params, for software change, all the below must be unit, should not combine start -# For factory change name -mem_tws_fac_adv_name: -'012345678901234567890123456 - - -# For setting left right channel -mem_hsp_role:00 -# For setting allow rssi setting -mem_tws_allow_pairing_rssi_limit:30 -# For setting auto change role -mem_auto_hsp_role:01 - -# For setting eq enable or not -mem_eq_flag:00 - -# For setting bit pool -mem_get_media_type: -00 -00 -3f -ff -08 -35 # bitpool - - -mem_public_code_svn_version_code:00 00 00 00 00 00 00 00 00 -# User Change params, for software change, all the below must be unit, should not combine end - - -mem_lpm_write_temp_adc_low: bb 3a 48 00 -mem_lpm_write_temp_adc_high:18 00 00 00 -#re-charge battery set default to 4.1V, change in charge power off -#charge target battery set default to 4.3V, change in charge power off -#re-charge and charge must diff to 0.2V -#10% Charging termination current control -#Use Force on charger CC & CV loop when charger is in standby mode -mem_lpm_write_temp_charge_control:b0 2b 03 06 - -mem_a2dp_start_force_mute_voice_cnt:00 - -mem_lpm_config:8f 1f ca -mem_lpm_buckcnt:0a 0b ef 07 -mem_lpm_hibernate_switch:00 -mem_gpio_wakeup_low:00 00 00 00 00 00 00 00 00 00 -mem_fcomp_mul:02 -mem_fcomp_div:24 -mem_iscan_window:20 00 -mem_iscan_interval:00 04 -mem_pscan_window:16 00 -mem_pscan_interval:00 04 -mem_inq_window:20 00 -mem_page_window:30 00 -mem_page_to:00 30 -mem_rx_window_init:80 03 -mem_rx_window_sniff:00 06 - -mem_lpm_xtalcnt:00 20 18 bf 07 - -mem_ef_base:00 ff 87 -mem_eeprom_block_size:80 - -mem_rf_init: -ff - -mem_rf_init_ptr:mem_rf_init - Index: tag/Soft/ModuleDemo/ADC/AD_Sound_Recording/CM0/User/main.c =================================================================== --- /YC1121E/SoftCode/MCU/tag/Soft/ModuleDemo/ADC/AD_Sound_Recording/CM0/User/main.c (revision 4280) +++ /YC1121E/SoftCode/MCU/tag/Soft/ModuleDemo/ADC/AD_Sound_Recording/CM0/User/main.c (working copy) @@ -1,10 +1,13 @@ #include #include "yc11xx.h" #include "yc_timer.h" +#include "ipc.h" #include "yc11xx_audio.h" #include "yc11xx_uart.h" #include "yc_uart.h" +#define LPM_TEST +#ifndef LPM_TEST #define ADCBufferStartAddr 0xb800 #define ADCBufferLength 0x2000 @@ -52,7 +55,59 @@ UART_Tx_Adc_Buffer(); } } +#else +void Bt_ActionBeforeHibernate() +{ + uint8_t i; + + for(i=GPIO_0;i1 0 0 - 6 + 1 + 0 + 0 + 4 @@ -289,8 +292,20 @@ + 0 + 0 + 0 + + + + + + + + 1 + 0 0 1 10000000 @@ -309,7 +324,6 @@ 1 1 0 - 0 0 0 ..\..\User\main.c @@ -330,7 +344,6 @@ 2 2 0 - 0 0 0 .\Objects\startup\startup.s @@ -351,7 +364,6 @@ 3 1 0 - 0 0 0 ..\..\..\..\..\..\Librarier\drivers\gpio\yc11xx_gpio.c @@ -364,7 +376,6 @@ 4 1 0 - 0 0 0 ..\..\..\..\..\..\Librarier\drivers\hal_comm\yc_drv_common.c @@ -377,7 +388,6 @@ 5 1 0 - 0 0 0 ..\..\..\..\..\..\Librarier\drivers\saradc\saradc.c @@ -390,7 +400,6 @@ 6 1 0 - 0 0 0 ..\..\..\..\..\..\Librarier\drivers\systick\yc11xx_systick.c @@ -403,7 +412,6 @@ 7 1 0 - 0 0 0 ..\..\..\..\..\..\Librarier\drivers\timer\yc_timer.c @@ -416,7 +424,6 @@ 8 1 0 - 0 0 0 ..\..\..\..\..\..\Librarier\drivers\timer\yc11xx_timer.c @@ -429,7 +436,6 @@ 9 1 0 - 0 0 0 ..\..\..\..\..\..\Librarier\drivers\uart\yc_uart.c @@ -442,7 +448,6 @@ 10 1 0 - 0 0 0 ..\..\..\..\..\..\Librarier\drivers\uart\yc11xx_uart.c Index: trunk/Soft/ModuleDemo/SARDAC/SarAdc_Gpio/CM0/Prj/MDK/yc11xx.uvprojx =================================================================== --- /YC1121E/SoftCode/MCU/trunk/Soft/ModuleDemo/SARDAC/SarAdc_Gpio/CM0/Prj/MDK/yc11xx.uvprojx (revision 4280) +++ /YC1121E/SoftCode/MCU/trunk/Soft/ModuleDemo/SARDAC/SarAdc_Gpio/CM0/Prj/MDK/yc11xx.uvprojx (working copy) @@ -10,6 +10,8 @@ Target 1 0x4 ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 CMSDK_CM0 @@ -84,6 +86,8 @@ "Objects/tool/c.bat" 0 0 + 0 + 0 0 @@ -122,47 +126,6 @@ 0 16 - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - - 0 - 6 - - - - - - - - - - - - - - Segger\JL2CM3.dll - @@ -221,12 +184,14 @@ 0 0 0 + 0 0 0 8 1 0 0 + 0 3 3 0 @@ -360,7 +325,15 @@ 0 0 0 + 0 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 --c99 --gnu @@ -378,6 +351,7 @@ 0 0 0 + 0 Index: trunk/Soft/ModuleDemo/SARDAC/SarAdc_Gpio/CM0/Prj/MDK/yc11xx_asm.txt =================================================================== --- /YC1121E/SoftCode/MCU/trunk/Soft/ModuleDemo/SARDAC/SarAdc_Gpio/CM0/Prj/MDK/yc11xx_asm.txt (revision 4280) +++ /YC1121E/SoftCode/MCU/trunk/Soft/ModuleDemo/SARDAC/SarAdc_Gpio/CM0/Prj/MDK/yc11xx_asm.txt (working copy) @@ -14,13 +14,15 @@ Machine: EM_ARM (ARM) Image Entry point: 0x00001001 - Flags: EF_ARM_HASENTRY (0x05000002) + Flags: EF_ARM_HASENTRY + EF_ARM_ABI_FLOAT_SOFT (0x05000202) ARM ELF revision: 5 (ABI version 2) + Conforms to Soft float procedure-call standard + Built with - Component: ARM Compiler 5.05 update 1 (build 106) Tool: armasm [4d0efa] - Component: ARM Compiler 5.05 update 1 (build 106) Tool: armlink [4d0efa] + Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec] + Component: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed] Header size: 52 bytes (0x34) Program header entry size: 32 bytes (0x20) @@ -29,8 +31,8 @@ Program header entries: 2 Section header entries: 17 - Program header offset: 89336 (0x00015cf8) - Section header offset: 89400 (0x00015d38) + Program header offset: 89612 (0x00015e0c) + Section header offset: 89676 (0x00015e4c) Section header string table index: 16 @@ -44,7 +46,7 @@ ==================================== ** Program header #1 (PT_LOAD) [PF_X + PF_W + PF_R + PF_ARM_ENTRY] - Size : 16704 bytes (8452 bytes in file) + Size : 16684 bytes (8432 bytes in file) Virtual address: 0x00001000 (Alignment 4) @@ -72,7 +74,7 @@ 0x00000030: 00000000 .... DCD 0 0x00000034: 00000000 .... DCD 0 0x00000038: 000000d9 .... DCD 217 - 0x0000003c: 0000239b .#.. DCD 9115 + 0x0000003c: 000000d9 .... DCD 217 0x00000040: 000000d9 .... DCD 217 0x00000044: 000000d9 .... DCD 217 0x00000048: 000000d9 .... DCD 217 @@ -141,6 +143,7 @@ SD_IRQHandler SPI_IRQHandler SVC_Handler + SysTick_Handler TIMER0_IRQHandler TIMER1_IRQHandler TIMER2_IRQHandler @@ -162,7 +165,7 @@ 0x000000e4: 0000102d -... DCD 4141 ** Section #2 'ER_IROM2' (SHT_PROGBITS) [SHF_ALLOC + SHF_EXECINSTR] - Size : 8420 bytes (alignment 4) + Size : 8400 bytes (alignment 4) Address: 0x00001000 $t @@ -174,7 +177,7 @@ 0x00001002: 4685 .F MOV sp,r0 .ARM.Collect$$$$00000004 _main_scatterload - 0x00001004: f001ffd6 .... BL __scatterload ; 0x2fb4 + 0x00001004: f001ffcc .... BL __scatterload ; 0x2fa0 .ARM.Collect$$$$00000008 .ARM.Collect$$$$0000000A .ARM.Collect$$$$0000000B @@ -213,7 +216,7 @@ 0x0000102e: f001f876 ..v. BL SYS_TimerInit ; 0x211e 0x00001032: 4916 .I LDR r1,[pc,#88] ; [0x108c] = 0x8034 0x00001034: 2000 . MOVS r0,#0 - 0x00001036: f001fd23 ..#. BL UARTx_Configuration ; 0x2a80 + 0x00001036: f001fc95 .... BL UARTx_Configuration ; 0x2964 0x0000103a: e021 !. B 0x1080 ; main + 84 0x0000103c: 2101 .! MOVS r1,#1 0x0000103e: 208e . MOVS r0,#0x8e @@ -231,12 +234,12 @@ 0x0000105e: f000fe8f .... BL saradc_check_gpio ; 0x1d80 0x00001062: f000fea9 .... BL saradc_enable ; 0x1db8 0x00001066: f000fee8 .... BL read_adc ; 0x1e3a - 0x0000106a: 4909 .I LDR r1,[pc,#36] ; [0x1090] = 0x10011002 + 0x0000106a: 4909 .I LDR r1,[pc,#36] ; [0x1090] = 0x10011000 0x0000106c: 8008 .. STRH r0,[r1,#0] 0x0000106e: 4608 .F MOV r0,r1 0x00001070: 8801 .. LDRH r1,[r0,#0] 0x00001072: a008 .. ADR r0,{pc}+0x22 ; 0x1094 - 0x00001074: f001f9b4 .... BL MyPrintf ; 0x23e0 + 0x00001074: f001f9aa .... BL MyPrintf ; 0x23cc 0x00001078: 20ff . MOVS r0,#0xff 0x0000107a: 30f5 .0 ADDS r0,r0,#0xf5 0x0000107c: f001f984 .... BL SYS_delay_ms ; 0x2388 @@ -248,7 +251,7 @@ 0x00001086: 0000 .. DCW 0 0x00001088: 0000ffff .... DCD 65535 0x0000108c: 00008034 4... DCD 32820 - 0x00001090: 10011002 .... DCD 268505090 + 0x00001090: 10011000 .... DCD 268505088 0x00001094: 756c6176 valu DCD 1970037110 0x00001098: 203d2065 e = DCD 540876901 0x0000109c: 20207825 %x DCD 538998821 @@ -2164,26 +2167,26 @@ 0x00001f88: 70c4 .p STRB r4,[r0,#3] 0x00001f8a: 70c4 .p STRB r4,[r0,#3] 0x00001f8c: bf00 .. NOP - 0x00001f8e: f000fa08 .... BL hw_delay ; 0x23a2 - 0x00001f92: f000fa06 .... BL hw_delay ; 0x23a2 - 0x00001f96: f000fa04 .... BL hw_delay ; 0x23a2 - 0x00001f9a: f000fa02 .... BL hw_delay ; 0x23a2 - 0x00001f9e: f000fa00 .... BL hw_delay ; 0x23a2 - 0x00001fa2: f000f9fe .... BL hw_delay ; 0x23a2 - 0x00001fa6: f000f9fc .... BL hw_delay ; 0x23a2 - 0x00001faa: f000f9fa .... BL hw_delay ; 0x23a2 - 0x00001fae: f000f9f8 .... BL hw_delay ; 0x23a2 - 0x00001fb2: f000f9f6 .... BL hw_delay ; 0x23a2 - 0x00001fb6: f000f9f4 .... BL hw_delay ; 0x23a2 - 0x00001fba: f000f9f2 .... BL hw_delay ; 0x23a2 - 0x00001fbe: f000f9f0 .... BL hw_delay ; 0x23a2 - 0x00001fc2: f000f9ee .... BL hw_delay ; 0x23a2 - 0x00001fc6: f000f9ec .... BL hw_delay ; 0x23a2 - 0x00001fca: f000f9ea .... BL hw_delay ; 0x23a2 - 0x00001fce: f000f9e8 .... BL hw_delay ; 0x23a2 - 0x00001fd2: f000f9e6 .... BL hw_delay ; 0x23a2 - 0x00001fd6: f000f9e4 .... BL hw_delay ; 0x23a2 - 0x00001fda: f000f9e2 .... BL hw_delay ; 0x23a2 + 0x00001f8e: f000fa04 .... BL hw_delay ; 0x239a + 0x00001f92: f000fa02 .... BL hw_delay ; 0x239a + 0x00001f96: f000fa00 .... BL hw_delay ; 0x239a + 0x00001f9a: f000f9fe .... BL hw_delay ; 0x239a + 0x00001f9e: f000f9fc .... BL hw_delay ; 0x239a + 0x00001fa2: f000f9fa .... BL hw_delay ; 0x239a + 0x00001fa6: f000f9f8 .... BL hw_delay ; 0x239a + 0x00001faa: f000f9f6 .... BL hw_delay ; 0x239a + 0x00001fae: f000f9f4 .... BL hw_delay ; 0x239a + 0x00001fb2: f000f9f2 .... BL hw_delay ; 0x239a + 0x00001fb6: f000f9f0 .... BL hw_delay ; 0x239a + 0x00001fba: f000f9ee .... BL hw_delay ; 0x239a + 0x00001fbe: f000f9ec .... BL hw_delay ; 0x239a + 0x00001fc2: f000f9ea .... BL hw_delay ; 0x239a + 0x00001fc6: f000f9e8 .... BL hw_delay ; 0x239a + 0x00001fca: f000f9e6 .... BL hw_delay ; 0x239a + 0x00001fce: f000f9e4 .... BL hw_delay ; 0x239a + 0x00001fd2: f000f9e2 .... BL hw_delay ; 0x239a + 0x00001fd6: f000f9e0 .... BL hw_delay ; 0x239a + 0x00001fda: f000f9de .... BL hw_delay ; 0x239a 0x00001fde: bd70 p. POP {r4-r6,pc} SYS_ChangeToNormalDPLL 0x00001fe0: b570 p. PUSH {r4-r6,lr} @@ -2210,26 +2213,26 @@ 0x0000200a: 70c4 .p STRB r4,[r0,#3] 0x0000200c: 70c4 .p STRB r4,[r0,#3] 0x0000200e: bf00 .. NOP - 0x00002010: f000f9c7 .... BL hw_delay ; 0x23a2 - 0x00002014: f000f9c5 .... BL hw_delay ; 0x23a2 - 0x00002018: f000f9c3 .... BL hw_delay ; 0x23a2 - 0x0000201c: f000f9c1 .... BL hw_delay ; 0x23a2 - 0x00002020: f000f9bf .... BL hw_delay ; 0x23a2 - 0x00002024: f000f9bd .... BL hw_delay ; 0x23a2 - 0x00002028: f000f9bb .... BL hw_delay ; 0x23a2 - 0x0000202c: f000f9b9 .... BL hw_delay ; 0x23a2 - 0x00002030: f000f9b7 .... BL hw_delay ; 0x23a2 - 0x00002034: f000f9b5 .... BL hw_delay ; 0x23a2 - 0x00002038: f000f9b3 .... BL hw_delay ; 0x23a2 - 0x0000203c: f000f9b1 .... BL hw_delay ; 0x23a2 - 0x00002040: f000f9af .... BL hw_delay ; 0x23a2 - 0x00002044: f000f9ad .... BL hw_delay ; 0x23a2 - 0x00002048: f000f9ab .... BL hw_delay ; 0x23a2 - 0x0000204c: f000f9a9 .... BL hw_delay ; 0x23a2 - 0x00002050: f000f9a7 .... BL hw_delay ; 0x23a2 - 0x00002054: f000f9a5 .... BL hw_delay ; 0x23a2 - 0x00002058: f000f9a3 .... BL hw_delay ; 0x23a2 - 0x0000205c: f000f9a1 .... BL hw_delay ; 0x23a2 + 0x00002010: f000f9c3 .... BL hw_delay ; 0x239a + 0x00002014: f000f9c1 .... BL hw_delay ; 0x239a + 0x00002018: f000f9bf .... BL hw_delay ; 0x239a + 0x0000201c: f000f9bd .... BL hw_delay ; 0x239a + 0x00002020: f000f9bb .... BL hw_delay ; 0x239a + 0x00002024: f000f9b9 .... BL hw_delay ; 0x239a + 0x00002028: f000f9b7 .... BL hw_delay ; 0x239a + 0x0000202c: f000f9b5 .... BL hw_delay ; 0x239a + 0x00002030: f000f9b3 .... BL hw_delay ; 0x239a + 0x00002034: f000f9b1 .... BL hw_delay ; 0x239a + 0x00002038: f000f9af .... BL hw_delay ; 0x239a + 0x0000203c: f000f9ad .... BL hw_delay ; 0x239a + 0x00002040: f000f9ab .... BL hw_delay ; 0x239a + 0x00002044: f000f9a9 .... BL hw_delay ; 0x239a + 0x00002048: f000f9a7 .... BL hw_delay ; 0x239a + 0x0000204c: f000f9a5 .... BL hw_delay ; 0x239a + 0x00002050: f000f9a3 .... BL hw_delay ; 0x239a + 0x00002054: f000f9a1 .... BL hw_delay ; 0x239a + 0x00002058: f000f99f .... BL hw_delay ; 0x239a + 0x0000205c: f000f99d .... BL hw_delay ; 0x239a 0x00002060: bd70 p. POP {r4-r6,pc} SystemCheckInFastSpeed 0x00002062: 489d .H LDR r0,[pc,#628] ; [0x22d8] = 0x10011015 @@ -2557,12 +2560,12 @@ 0x000022f4: 10011014 .... DCD 268505108 $t SYS_ReleaseAllTimer - 0x000022f8: 492d -I LDR r1,[pc,#180] ; [0x23b0] = 0x10011008 + 0x000022f8: 492b +I LDR r1,[pc,#172] ; [0x23a8] = 0x10011008 0x000022fa: 6809 .h LDR r1,[r1,#0] 0x000022fc: 2900 .) CMP r1,#0 0x000022fe: d100 .. BNE 0x2302 ; SYS_ReleaseAllTimer + 10 0x00002300: 4770 pG BX lr - 0x00002302: 492b +I LDR r1,[pc,#172] ; [0x23b0] = 0x10011008 + 0x00002302: 4929 )I LDR r1,[pc,#164] ; [0x23a8] = 0x10011008 0x00002304: 6808 .h LDR r0,[r1,#0] 0x00002306: e002 .. B 0x230e ; SYS_ReleaseAllTimer + 22 0x00002308: 2100 .! MOVS r1,#0 @@ -2571,8 +2574,8 @@ 0x0000230e: 68c1 .h LDR r1,[r0,#0xc] 0x00002310: 2900 .) CMP r1,#0 0x00002312: d1f9 .. BNE 0x2308 ; SYS_ReleaseAllTimer + 16 - 0x00002314: 4927 'I LDR r1,[pc,#156] ; [0x23b4] = 0x10011020 - 0x00002316: 4a26 &J LDR r2,[pc,#152] ; [0x23b0] = 0x10011008 + 0x00002314: 4925 %I LDR r1,[pc,#148] ; [0x23ac] = 0x10011020 + 0x00002316: 4a24 $J LDR r2,[pc,#144] ; [0x23a8] = 0x10011008 0x00002318: 6011 .` STR r1,[r2,#0] 0x0000231a: bf00 .. NOP 0x0000231c: e7f0 .. B 0x2300 ; SYS_ReleaseAllTimer + 8 @@ -2580,7 +2583,7 @@ 0x0000231e: b500 .. PUSH {lr} 0x00002320: f7fffea2 .... BL SYS_ClkTicks ; 0x2068 0x00002324: 2001 . MOVS r0,#1 - 0x00002326: 4924 $I LDR r1,[pc,#144] ; [0x23b8] = 0x10011014 + 0x00002326: 4922 "I LDR r1,[pc,#136] ; [0x23b0] = 0x10011014 0x00002328: 7008 .p STRB r0,[r1,#0] 0x0000232a: bd00 .. POP {pc} Bt_100ms_timer @@ -2588,7 +2591,7 @@ 0x0000232e: 4604 .F MOV r4,r0 0x00002330: f7fffe9a .... BL SYS_ClkTicks ; 0x2068 0x00002334: 2001 . MOVS r0,#1 - 0x00002336: 4920 I LDR r1,[pc,#128] ; [0x23b8] = 0x10011014 + 0x00002336: 491e .I LDR r1,[pc,#120] ; [0x23b0] = 0x10011014 0x00002338: 7008 .p STRB r0,[r1,#0] 0x0000233a: bd10 .. POP {r4,pc} SYS_delay_us @@ -2602,13 +2605,13 @@ 0x0000234a: f7fffdc4 .... BL SYS_TimerGet1usTicks ; 0x1ed6 0x0000234e: 4378 xC MULS r0,r7,r0 0x00002350: 9001 .. STR r0,[sp,#4] - 0x00002352: 481a .H LDR r0,[pc,#104] ; [0x23bc] = 0xe000e000 + 0x00002352: 4818 .H LDR r0,[pc,#96] ; [0x23b4] = 0xe000e000 0x00002354: 6940 @i LDR r0,[r0,#0x14] 0x00002356: 9000 .. STR r0,[sp,#0] - 0x00002358: 4818 .H LDR r0,[pc,#96] ; [0x23bc] = 0xe000e000 + 0x00002358: 4816 .H LDR r0,[pc,#88] ; [0x23b4] = 0xe000e000 0x0000235a: 6985 .i LDR r5,[r0,#0x18] 0x0000235c: e011 .. B 0x2382 ; SYS_delay_us + 70 - 0x0000235e: 4817 .H LDR r0,[pc,#92] ; [0x23bc] = 0xe000e000 + 0x0000235e: 4815 .H LDR r0,[pc,#84] ; [0x23b4] = 0xe000e000 0x00002360: 6984 .i LDR r4,[r0,#0x18] 0x00002362: 42ac .B CMP r4,r5 0x00002364: d00d .. BEQ 0x2382 ; SYS_delay_us + 70 @@ -2638,1593 +2641,1584 @@ 0x00002392: 4608 .F MOV r0,r1 0x00002394: f7ffffd2 .... BL SYS_delay_us ; 0x233c 0x00002398: bd10 .. POP {r4,pc} - SysTick_Handler - 0x0000239a: b500 .. PUSH {lr} - 0x0000239c: f7ffffbf .... BL SYStick_handle ; 0x231e - 0x000023a0: bd00 .. POP {pc} hw_delay + 0x0000239a: bf00 .. NOP + 0x0000239c: bf00 .. NOP + 0x0000239e: bf00 .. NOP + 0x000023a0: bf00 .. NOP 0x000023a2: bf00 .. NOP - 0x000023a4: bf00 .. NOP - 0x000023a6: bf00 .. NOP - 0x000023a8: bf00 .. NOP - 0x000023aa: bf00 .. NOP - 0x000023ac: 4770 pG BX lr + 0x000023a4: 4770 pG BX lr $d - 0x000023ae: 0000 .. DCW 0 - 0x000023b0: 10011008 .... DCD 268505096 - 0x000023b4: 10011020 ... DCD 268505120 - 0x000023b8: 10011014 .... DCD 268505108 - 0x000023bc: e000e000 .... DCD 3758153728 + 0x000023a6: 0000 .. DCW 0 + 0x000023a8: 10011008 .... DCD 268505096 + 0x000023ac: 10011020 ... DCD 268505120 + 0x000023b0: 10011014 .... DCD 268505108 + 0x000023b4: e000e000 .... DCD 3758153728 $t .text - setprintportcb - 0x000023c0: 7841 Ax LDRB r1,[r0,#1] - 0x000023c2: 4ac0 .J LDR r2,[pc,#768] ; [0x26c4] = 0x10011016 - 0x000023c4: 7051 Qp STRB r1,[r2,#1] - 0x000023c6: 7801 .x LDRB r1,[r0,#0] - 0x000023c8: 7011 .p STRB r1,[r2,#0] - 0x000023ca: 4770 pG BX lr printfsend - 0x000023cc: b570 p. PUSH {r4-r6,lr} - 0x000023ce: 4605 .F MOV r5,r0 - 0x000023d0: 460e .F MOV r6,r1 - 0x000023d2: 4614 .F MOV r4,r2 - 0x000023d4: b2a2 .. UXTH r2,r4 - 0x000023d6: 4631 1F MOV r1,r6 - 0x000023d8: 4628 (F MOV r0,r5 - 0x000023da: f000fcec .... BL USART_SendDataFromBuff ; 0x2db6 - 0x000023de: bd70 p. POP {r4-r6,pc} + 0x000023b8: b570 p. PUSH {r4-r6,lr} + 0x000023ba: 4605 .F MOV r5,r0 + 0x000023bc: 460e .F MOV r6,r1 + 0x000023be: 4614 .F MOV r4,r2 + 0x000023c0: b2a2 .. UXTH r2,r4 + 0x000023c2: 4631 1F MOV r1,r6 + 0x000023c4: 4628 (F MOV r0,r5 + 0x000023c6: f000fcec .... BL USART_SendDataFromBuff ; 0x2da2 + 0x000023ca: bd70 p. POP {r4-r6,pc} MyPrintf - 0x000023e0: b40f .. PUSH {r0-r3} - 0x000023e2: b5f0 .. PUSH {r4-r7,lr} - 0x000023e4: b08b .. SUB sp,sp,#0x2c - 0x000023e6: a811 .. ADD r0,sp,#0x44 - 0x000023e8: 9001 .. STR r0,[sp,#4] - 0x000023ea: e148 H. B 0x267e ; MyPrintf + 670 - 0x000023ec: 2400 .$ MOVS r4,#0 - 0x000023ee: e000 .. B 0x23f2 ; MyPrintf + 18 - 0x000023f0: 1c64 d. ADDS r4,r4,#1 - 0x000023f2: 9810 .. LDR r0,[sp,#0x40] - 0x000023f4: 5d00 .] LDRB r0,[r0,r4] - 0x000023f6: 2825 %( CMP r0,#0x25 - 0x000023f8: d003 .. BEQ 0x2402 ; MyPrintf + 34 - 0x000023fa: 9810 .. LDR r0,[sp,#0x40] - 0x000023fc: 5d00 .] LDRB r0,[r0,r4] - 0x000023fe: 2800 .( CMP r0,#0 - 0x00002400: d1f6 .. BNE 0x23f0 ; MyPrintf + 16 - 0x00002402: 2c00 ., CMP r4,#0 - 0x00002404: d004 .. BEQ 0x2410 ; MyPrintf + 48 - 0x00002406: 4622 "F MOV r2,r4 - 0x00002408: 2000 . MOVS r0,#0 - 0x0000240a: 9910 .. LDR r1,[sp,#0x40] - 0x0000240c: f7ffffde .... BL printfsend ; 0x23cc - 0x00002410: 9810 .. LDR r0,[sp,#0x40] - 0x00002412: 1900 .. ADDS r0,r0,r4 - 0x00002414: 9010 .. STR r0,[sp,#0x40] - 0x00002416: 9810 .. LDR r0,[sp,#0x40] - 0x00002418: 7800 .x LDRB r0,[r0,#0] - 0x0000241a: 2825 %( CMP r0,#0x25 - 0x0000241c: d1e5 .. BNE 0x23ea ; MyPrintf + 10 - 0x0000241e: 9810 .. LDR r0,[sp,#0x40] - 0x00002420: 1c40 @. ADDS r0,r0,#1 - 0x00002422: 9010 .. STR r0,[sp,#0x40] - 0x00002424: 2500 .% MOVS r5,#0 - 0x00002426: 2020 MOVS r0,#0x20 - 0x00002428: 9003 .. STR r0,[sp,#0xc] - 0x0000242a: bf00 .. NOP - 0x0000242c: 9810 .. LDR r0,[sp,#0x40] - 0x0000242e: 7801 .x LDRB r1,[r0,#0] - 0x00002430: 1c40 @. ADDS r0,r0,#1 - 0x00002432: 9010 .. STR r0,[sp,#0x40] - 0x00002434: 2938 8) CMP r1,#0x38 - 0x00002436: d030 0. BEQ 0x249a ; MyPrintf + 186 - 0x00002438: dc14 .. BGT 0x2464 ; MyPrintf + 132 - 0x0000243a: 2933 3) CMP r1,#0x33 - 0x0000243c: d028 (. BEQ 0x2490 ; MyPrintf + 176 - 0x0000243e: dc08 .. BGT 0x2452 ; MyPrintf + 114 - 0x00002440: 2925 %) CMP r1,#0x25 - 0x00002442: d070 p. BEQ 0x2526 ; MyPrintf + 326 - 0x00002444: 2930 0) CMP r1,#0x30 - 0x00002446: d020 . BEQ 0x248a ; MyPrintf + 170 - 0x00002448: 2931 1) CMP r1,#0x31 - 0x0000244a: d01f .. BEQ 0x248c ; MyPrintf + 172 - 0x0000244c: 2932 2) CMP r1,#0x32 - 0x0000244e: d16b k. BNE 0x2528 ; MyPrintf + 328 - 0x00002450: e01d .. B 0x248e ; MyPrintf + 174 - 0x00002452: 2934 4) CMP r1,#0x34 - 0x00002454: d01d .. BEQ 0x2492 ; MyPrintf + 178 - 0x00002456: 2935 5) CMP r1,#0x35 - 0x00002458: d01c .. BEQ 0x2494 ; MyPrintf + 180 - 0x0000245a: 2936 6) CMP r1,#0x36 - 0x0000245c: d01b .. BEQ 0x2496 ; MyPrintf + 182 - 0x0000245e: 2937 7) CMP r1,#0x37 - 0x00002460: d1f5 .. BNE 0x244e ; MyPrintf + 110 - 0x00002462: e019 .. B 0x2498 ; MyPrintf + 184 - 0x00002464: 2970 p) CMP r1,#0x70 - 0x00002466: d075 u. BEQ 0x2554 ; MyPrintf + 372 - 0x00002468: dc08 .. BGT 0x247c ; MyPrintf + 156 - 0x0000246a: 2939 9) CMP r1,#0x39 - 0x0000246c: d016 .. BEQ 0x249c ; MyPrintf + 188 - 0x0000246e: 2958 X) CMP r1,#0x58 - 0x00002470: d072 r. BEQ 0x2558 ; MyPrintf + 376 - 0x00002472: 2963 c) CMP r1,#0x63 - 0x00002474: d022 ". BEQ 0x24bc ; MyPrintf + 220 - 0x00002476: 2964 d) CMP r1,#0x64 - 0x00002478: d1e9 .. BNE 0x244e ; MyPrintf + 110 - 0x0000247a: e02b +. B 0x24d4 ; MyPrintf + 244 - 0x0000247c: 2973 s) CMP r1,#0x73 - 0x0000247e: d03d =. BEQ 0x24fc ; MyPrintf + 284 - 0x00002480: 2975 u) CMP r1,#0x75 - 0x00002482: d05c \. BEQ 0x253e ; MyPrintf + 350 - 0x00002484: 2978 x) CMP r1,#0x78 - 0x00002486: d1e2 .. BNE 0x244e ; MyPrintf + 110 - 0x00002488: e073 s. B 0x2572 ; MyPrintf + 402 - 0x0000248a: bf00 .. NOP - 0x0000248c: bf00 .. NOP - 0x0000248e: bf00 .. NOP - 0x00002490: bf00 .. NOP - 0x00002492: bf00 .. NOP - 0x00002494: bf00 .. NOP - 0x00002496: bf00 .. NOP - 0x00002498: bf00 .. NOP - 0x0000249a: bf00 .. NOP + 0x000023cc: b40f .. PUSH {r0-r3} + 0x000023ce: b5f0 .. PUSH {r4-r7,lr} + 0x000023d0: b08b .. SUB sp,sp,#0x2c + 0x000023d2: a811 .. ADD r0,sp,#0x44 + 0x000023d4: 9001 .. STR r0,[sp,#4] + 0x000023d6: e148 H. B 0x266a ; MyPrintf + 670 + 0x000023d8: 2400 .$ MOVS r4,#0 + 0x000023da: e000 .. B 0x23de ; MyPrintf + 18 + 0x000023dc: 1c64 d. ADDS r4,r4,#1 + 0x000023de: 9810 .. LDR r0,[sp,#0x40] + 0x000023e0: 5d00 .] LDRB r0,[r0,r4] + 0x000023e2: 2825 %( CMP r0,#0x25 + 0x000023e4: d003 .. BEQ 0x23ee ; MyPrintf + 34 + 0x000023e6: 9810 .. LDR r0,[sp,#0x40] + 0x000023e8: 5d00 .] LDRB r0,[r0,r4] + 0x000023ea: 2800 .( CMP r0,#0 + 0x000023ec: d1f6 .. BNE 0x23dc ; MyPrintf + 16 + 0x000023ee: 2c00 ., CMP r4,#0 + 0x000023f0: d004 .. BEQ 0x23fc ; MyPrintf + 48 + 0x000023f2: 4622 "F MOV r2,r4 + 0x000023f4: 2000 . MOVS r0,#0 + 0x000023f6: 9910 .. LDR r1,[sp,#0x40] + 0x000023f8: f7ffffde .... BL printfsend ; 0x23b8 + 0x000023fc: 9810 .. LDR r0,[sp,#0x40] + 0x000023fe: 1900 .. ADDS r0,r0,r4 + 0x00002400: 9010 .. STR r0,[sp,#0x40] + 0x00002402: 9810 .. LDR r0,[sp,#0x40] + 0x00002404: 7800 .x LDRB r0,[r0,#0] + 0x00002406: 2825 %( CMP r0,#0x25 + 0x00002408: d1e5 .. BNE 0x23d6 ; MyPrintf + 10 + 0x0000240a: 9810 .. LDR r0,[sp,#0x40] + 0x0000240c: 1c40 @. ADDS r0,r0,#1 + 0x0000240e: 9010 .. STR r0,[sp,#0x40] + 0x00002410: 2500 .% MOVS r5,#0 + 0x00002412: 2020 MOVS r0,#0x20 + 0x00002414: 9003 .. STR r0,[sp,#0xc] + 0x00002416: bf00 .. NOP + 0x00002418: 9810 .. LDR r0,[sp,#0x40] + 0x0000241a: 7801 .x LDRB r1,[r0,#0] + 0x0000241c: 1c40 @. ADDS r0,r0,#1 + 0x0000241e: 9010 .. STR r0,[sp,#0x40] + 0x00002420: 2938 8) CMP r1,#0x38 + 0x00002422: d030 0. BEQ 0x2486 ; MyPrintf + 186 + 0x00002424: dc14 .. BGT 0x2450 ; MyPrintf + 132 + 0x00002426: 2933 3) CMP r1,#0x33 + 0x00002428: d028 (. BEQ 0x247c ; MyPrintf + 176 + 0x0000242a: dc08 .. BGT 0x243e ; MyPrintf + 114 + 0x0000242c: 2925 %) CMP r1,#0x25 + 0x0000242e: d070 p. BEQ 0x2512 ; MyPrintf + 326 + 0x00002430: 2930 0) CMP r1,#0x30 + 0x00002432: d020 . BEQ 0x2476 ; MyPrintf + 170 + 0x00002434: 2931 1) CMP r1,#0x31 + 0x00002436: d01f .. BEQ 0x2478 ; MyPrintf + 172 + 0x00002438: 2932 2) CMP r1,#0x32 + 0x0000243a: d16b k. BNE 0x2514 ; MyPrintf + 328 + 0x0000243c: e01d .. B 0x247a ; MyPrintf + 174 + 0x0000243e: 2934 4) CMP r1,#0x34 + 0x00002440: d01d .. BEQ 0x247e ; MyPrintf + 178 + 0x00002442: 2935 5) CMP r1,#0x35 + 0x00002444: d01c .. BEQ 0x2480 ; MyPrintf + 180 + 0x00002446: 2936 6) CMP r1,#0x36 + 0x00002448: d01b .. BEQ 0x2482 ; MyPrintf + 182 + 0x0000244a: 2937 7) CMP r1,#0x37 + 0x0000244c: d1f5 .. BNE 0x243a ; MyPrintf + 110 + 0x0000244e: e019 .. B 0x2484 ; MyPrintf + 184 + 0x00002450: 2970 p) CMP r1,#0x70 + 0x00002452: d075 u. BEQ 0x2540 ; MyPrintf + 372 + 0x00002454: dc08 .. BGT 0x2468 ; MyPrintf + 156 + 0x00002456: 2939 9) CMP r1,#0x39 + 0x00002458: d016 .. BEQ 0x2488 ; MyPrintf + 188 + 0x0000245a: 2958 X) CMP r1,#0x58 + 0x0000245c: d072 r. BEQ 0x2544 ; MyPrintf + 376 + 0x0000245e: 2963 c) CMP r1,#0x63 + 0x00002460: d022 ". BEQ 0x24a8 ; MyPrintf + 220 + 0x00002462: 2964 d) CMP r1,#0x64 + 0x00002464: d1e9 .. BNE 0x243a ; MyPrintf + 110 + 0x00002466: e02b +. B 0x24c0 ; MyPrintf + 244 + 0x00002468: 2973 s) CMP r1,#0x73 + 0x0000246a: d03d =. BEQ 0x24e8 ; MyPrintf + 284 + 0x0000246c: 2975 u) CMP r1,#0x75 + 0x0000246e: d05c \. BEQ 0x252a ; MyPrintf + 350 + 0x00002470: 2978 x) CMP r1,#0x78 + 0x00002472: d1e2 .. BNE 0x243a ; MyPrintf + 110 + 0x00002474: e073 s. B 0x255e ; MyPrintf + 402 + 0x00002476: bf00 .. NOP + 0x00002478: bf00 .. NOP + 0x0000247a: bf00 .. NOP + 0x0000247c: bf00 .. NOP + 0x0000247e: bf00 .. NOP + 0x00002480: bf00 .. NOP + 0x00002482: bf00 .. NOP + 0x00002484: bf00 .. NOP + 0x00002486: bf00 .. NOP + 0x00002488: 9810 .. LDR r0,[sp,#0x40] + 0x0000248a: 3820 8 SUBS r0,r0,#0x20 + 0x0000248c: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x0000248e: 2830 0( CMP r0,#0x30 + 0x00002490: d102 .. BNE 0x2498 ; MyPrintf + 204 + 0x00002492: 2d00 .- CMP r5,#0 + 0x00002494: d100 .. BNE 0x2498 ; MyPrintf + 204 + 0x00002496: 9003 .. STR r0,[sp,#0xc] + 0x00002498: 200a . MOVS r0,#0xa + 0x0000249a: 4345 EC MULS r5,r0,r5 0x0000249c: 9810 .. LDR r0,[sp,#0x40] 0x0000249e: 3820 8 SUBS r0,r0,#0x20 0x000024a0: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x000024a2: 2830 0( CMP r0,#0x30 - 0x000024a4: d102 .. BNE 0x24ac ; MyPrintf + 204 - 0x000024a6: 2d00 .- CMP r5,#0 - 0x000024a8: d100 .. BNE 0x24ac ; MyPrintf + 204 - 0x000024aa: 9003 .. STR r0,[sp,#0xc] - 0x000024ac: 200a . MOVS r0,#0xa - 0x000024ae: 4345 EC MULS r5,r0,r5 - 0x000024b0: 9810 .. LDR r0,[sp,#0x40] - 0x000024b2: 3820 8 SUBS r0,r0,#0x20 - 0x000024b4: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x000024b6: 3830 08 SUBS r0,r0,#0x30 - 0x000024b8: 1945 E. ADDS r5,r0,r5 - 0x000024ba: e7b7 .. B 0x242c ; MyPrintf + 76 - 0x000024bc: 9801 .. LDR r0,[sp,#4] - 0x000024be: 6800 .h LDR r0,[r0,#0] - 0x000024c0: 900a .. STR r0,[sp,#0x28] - 0x000024c2: 9801 .. LDR r0,[sp,#4] - 0x000024c4: 1d00 .. ADDS r0,r0,#4 - 0x000024c6: 9001 .. STR r0,[sp,#4] - 0x000024c8: 2201 ." MOVS r2,#1 - 0x000024ca: a90a .. ADD r1,sp,#0x28 - 0x000024cc: 2000 . MOVS r0,#0 - 0x000024ce: f7ffff7d ..}. BL printfsend ; 0x23cc - 0x000024d2: e0d3 .. B 0x267c ; MyPrintf + 668 - 0x000024d4: 9801 .. LDR r0,[sp,#4] - 0x000024d6: 6800 .h LDR r0,[r0,#0] + 0x000024a2: 3830 08 SUBS r0,r0,#0x30 + 0x000024a4: 1945 E. ADDS r5,r0,r5 + 0x000024a6: e7b7 .. B 0x2418 ; MyPrintf + 76 + 0x000024a8: 9801 .. LDR r0,[sp,#4] + 0x000024aa: 6800 .h LDR r0,[r0,#0] + 0x000024ac: 900a .. STR r0,[sp,#0x28] + 0x000024ae: 9801 .. LDR r0,[sp,#4] + 0x000024b0: 1d00 .. ADDS r0,r0,#4 + 0x000024b2: 9001 .. STR r0,[sp,#4] + 0x000024b4: 2201 ." MOVS r2,#1 + 0x000024b6: a90a .. ADD r1,sp,#0x28 + 0x000024b8: 2000 . MOVS r0,#0 + 0x000024ba: f7ffff7d ..}. BL printfsend ; 0x23b8 + 0x000024be: e0d3 .. B 0x2668 ; MyPrintf + 668 + 0x000024c0: 9801 .. LDR r0,[sp,#4] + 0x000024c2: 6800 .h LDR r0,[r0,#0] + 0x000024c4: 900a .. STR r0,[sp,#0x28] + 0x000024c6: 9801 .. LDR r0,[sp,#4] + 0x000024c8: 1d00 .. ADDS r0,r0,#4 + 0x000024ca: 9001 .. STR r0,[sp,#4] + 0x000024cc: 2600 .& MOVS r6,#0 + 0x000024ce: 980a .. LDR r0,[sp,#0x28] + 0x000024d0: 2800 .( CMP r0,#0 + 0x000024d2: da05 .. BGE 0x24e0 ; MyPrintf + 276 + 0x000024d4: 980a .. LDR r0,[sp,#0x28] + 0x000024d6: 4240 @B RSBS r0,r0,#0 0x000024d8: 900a .. STR r0,[sp,#0x28] - 0x000024da: 9801 .. LDR r0,[sp,#4] - 0x000024dc: 1d00 .. ADDS r0,r0,#4 - 0x000024de: 9001 .. STR r0,[sp,#4] - 0x000024e0: 2600 .& MOVS r6,#0 - 0x000024e2: 980a .. LDR r0,[sp,#0x28] - 0x000024e4: 2800 .( CMP r0,#0 - 0x000024e6: da05 .. BGE 0x24f4 ; MyPrintf + 276 - 0x000024e8: 980a .. LDR r0,[sp,#0x28] - 0x000024ea: 4240 @B RSBS r0,r0,#0 - 0x000024ec: 900a .. STR r0,[sp,#0x28] - 0x000024ee: 2001 . MOVS r0,#1 - 0x000024f0: 9009 .. STR r0,[sp,#0x24] - 0x000024f2: e001 .. B 0x24f8 ; MyPrintf + 280 - 0x000024f4: 2000 . MOVS r0,#0 - 0x000024f6: 9009 .. STR r0,[sp,#0x24] - 0x000024f8: 270a .' MOVS r7,#0xa - 0x000024fa: e048 H. B 0x258e ; MyPrintf + 430 - 0x000024fc: 9801 .. LDR r0,[sp,#4] - 0x000024fe: 6800 .h LDR r0,[r0,#0] - 0x00002500: 9008 .. STR r0,[sp,#0x20] - 0x00002502: 9801 .. LDR r0,[sp,#4] - 0x00002504: 1d00 .. ADDS r0,r0,#4 - 0x00002506: 9001 .. STR r0,[sp,#4] - 0x00002508: 2400 .$ MOVS r4,#0 - 0x0000250a: e000 .. B 0x250e ; MyPrintf + 302 - 0x0000250c: 1c64 d. ADDS r4,r4,#1 - 0x0000250e: 9808 .. LDR r0,[sp,#0x20] - 0x00002510: 5d00 .] LDRB r0,[r0,r4] - 0x00002512: 2800 .( CMP r0,#0 - 0x00002514: d1fa .. BNE 0x250c ; MyPrintf + 300 - 0x00002516: 4622 "F MOV r2,r4 - 0x00002518: 9908 .. LDR r1,[sp,#0x20] - 0x0000251a: f7ffff57 ..W. BL printfsend ; 0x23cc - 0x0000251e: 42a5 .B CMP r5,r4 - 0x00002520: d90c .. BLS 0x253c ; MyPrintf + 348 - 0x00002522: 1b2d -. SUBS r5,r5,r4 - 0x00002524: e006 .. B 0x2534 ; MyPrintf + 340 - 0x00002526: e09c .. B 0x2662 ; MyPrintf + 642 - 0x00002528: e0a2 .. B 0x2670 ; MyPrintf + 656 - 0x0000252a: 2201 ." MOVS r2,#1 - 0x0000252c: a166 f. ADR r1,{pc}+0x19c ; 0x26c8 - 0x0000252e: 2000 . MOVS r0,#0 - 0x00002530: f7ffff4c ..L. BL printfsend ; 0x23cc - 0x00002534: 4628 (F MOV r0,r5 - 0x00002536: 1e6d m. SUBS r5,r5,#1 - 0x00002538: 2800 .( CMP r0,#0 - 0x0000253a: d1f6 .. BNE 0x252a ; MyPrintf + 330 - 0x0000253c: e09e .. B 0x267c ; MyPrintf + 668 - 0x0000253e: 9801 .. LDR r0,[sp,#4] - 0x00002540: 6800 .h LDR r0,[r0,#0] - 0x00002542: 900a .. STR r0,[sp,#0x28] + 0x000024da: 2001 . MOVS r0,#1 + 0x000024dc: 9009 .. STR r0,[sp,#0x24] + 0x000024de: e001 .. B 0x24e4 ; MyPrintf + 280 + 0x000024e0: 2000 . MOVS r0,#0 + 0x000024e2: 9009 .. STR r0,[sp,#0x24] + 0x000024e4: 270a .' MOVS r7,#0xa + 0x000024e6: e048 H. B 0x257a ; MyPrintf + 430 + 0x000024e8: 9801 .. LDR r0,[sp,#4] + 0x000024ea: 6800 .h LDR r0,[r0,#0] + 0x000024ec: 9008 .. STR r0,[sp,#0x20] + 0x000024ee: 9801 .. LDR r0,[sp,#4] + 0x000024f0: 1d00 .. ADDS r0,r0,#4 + 0x000024f2: 9001 .. STR r0,[sp,#4] + 0x000024f4: 2400 .$ MOVS r4,#0 + 0x000024f6: e000 .. B 0x24fa ; MyPrintf + 302 + 0x000024f8: 1c64 d. ADDS r4,r4,#1 + 0x000024fa: 9808 .. LDR r0,[sp,#0x20] + 0x000024fc: 5d00 .] LDRB r0,[r0,r4] + 0x000024fe: 2800 .( CMP r0,#0 + 0x00002500: d1fa .. BNE 0x24f8 ; MyPrintf + 300 + 0x00002502: 4622 "F MOV r2,r4 + 0x00002504: 9908 .. LDR r1,[sp,#0x20] + 0x00002506: f7ffff57 ..W. BL printfsend ; 0x23b8 + 0x0000250a: 42a5 .B CMP r5,r4 + 0x0000250c: d90c .. BLS 0x2528 ; MyPrintf + 348 + 0x0000250e: 1b2d -. SUBS r5,r5,r4 + 0x00002510: e006 .. B 0x2520 ; MyPrintf + 340 + 0x00002512: e09c .. B 0x264e ; MyPrintf + 642 + 0x00002514: e0a2 .. B 0x265c ; MyPrintf + 656 + 0x00002516: 2201 ." MOVS r2,#1 + 0x00002518: a165 e. ADR r1,{pc}+0x198 ; 0x26b0 + 0x0000251a: 2000 . MOVS r0,#0 + 0x0000251c: f7ffff4c ..L. BL printfsend ; 0x23b8 + 0x00002520: 4628 (F MOV r0,r5 + 0x00002522: 1e6d m. SUBS r5,r5,#1 + 0x00002524: 2800 .( CMP r0,#0 + 0x00002526: d1f6 .. BNE 0x2516 ; MyPrintf + 330 + 0x00002528: e09e .. B 0x2668 ; MyPrintf + 668 + 0x0000252a: 9801 .. LDR r0,[sp,#4] + 0x0000252c: 6800 .h LDR r0,[r0,#0] + 0x0000252e: 900a .. STR r0,[sp,#0x28] + 0x00002530: 9801 .. LDR r0,[sp,#4] + 0x00002532: 1d00 .. ADDS r0,r0,#4 + 0x00002534: 9001 .. STR r0,[sp,#4] + 0x00002536: 2600 .& MOVS r6,#0 + 0x00002538: 270a .' MOVS r7,#0xa + 0x0000253a: 2000 . MOVS r0,#0 + 0x0000253c: 9009 .. STR r0,[sp,#0x24] + 0x0000253e: e01c .. B 0x257a ; MyPrintf + 430 + 0x00002540: e00e .. B 0x2560 ; MyPrintf + 404 + 0x00002542: e7ff .. B 0x2544 ; MyPrintf + 376 0x00002544: 9801 .. LDR r0,[sp,#4] - 0x00002546: 1d00 .. ADDS r0,r0,#4 - 0x00002548: 9001 .. STR r0,[sp,#4] - 0x0000254a: 2600 .& MOVS r6,#0 - 0x0000254c: 270a .' MOVS r7,#0xa - 0x0000254e: 2000 . MOVS r0,#0 - 0x00002550: 9009 .. STR r0,[sp,#0x24] - 0x00002552: e01c .. B 0x258e ; MyPrintf + 430 - 0x00002554: e00e .. B 0x2574 ; MyPrintf + 404 - 0x00002556: e7ff .. B 0x2558 ; MyPrintf + 376 - 0x00002558: 9801 .. LDR r0,[sp,#4] - 0x0000255a: 6800 .h LDR r0,[r0,#0] - 0x0000255c: 900a .. STR r0,[sp,#0x28] - 0x0000255e: 9801 .. LDR r0,[sp,#4] - 0x00002560: 1d00 .. ADDS r0,r0,#4 - 0x00002562: 9001 .. STR r0,[sp,#4] - 0x00002564: 2600 .& MOVS r6,#0 - 0x00002566: 2710 .' MOVS r7,#0x10 - 0x00002568: 2000 . MOVS r0,#0 - 0x0000256a: 9009 .. STR r0,[sp,#0x24] - 0x0000256c: 2058 X MOVS r0,#0x58 - 0x0000256e: 9002 .. STR r0,[sp,#8] - 0x00002570: e00d .. B 0x258e ; MyPrintf + 430 - 0x00002572: bf00 .. NOP - 0x00002574: 9801 .. LDR r0,[sp,#4] - 0x00002576: 6800 .h LDR r0,[r0,#0] - 0x00002578: 900a .. STR r0,[sp,#0x28] - 0x0000257a: 9801 .. LDR r0,[sp,#4] - 0x0000257c: 1d00 .. ADDS r0,r0,#4 - 0x0000257e: 9001 .. STR r0,[sp,#4] - 0x00002580: 2600 .& MOVS r6,#0 - 0x00002582: 2710 .' MOVS r7,#0x10 - 0x00002584: 2000 . MOVS r0,#0 - 0x00002586: 9009 .. STR r0,[sp,#0x24] - 0x00002588: 2078 x MOVS r0,#0x78 - 0x0000258a: 9002 .. STR r0,[sp,#8] - 0x0000258c: bf00 .. NOP - 0x0000258e: 2401 .$ MOVS r4,#1 - 0x00002590: e003 .. B 0x259a ; MyPrintf + 442 - 0x00002592: 4620 F MOV r0,r4 - 0x00002594: 4378 xC MULS r0,r7,r0 - 0x00002596: 4604 .F MOV r4,r0 - 0x00002598: 1e6d m. SUBS r5,r5,#1 - 0x0000259a: 4620 F MOV r0,r4 - 0x0000259c: 4378 xC MULS r0,r7,r0 - 0x0000259e: 990a .. LDR r1,[sp,#0x28] - 0x000025a0: 4288 .B CMP r0,r1 - 0x000025a2: d807 .. BHI 0x25b4 ; MyPrintf + 468 - 0x000025a4: 4621 !F MOV r1,r4 - 0x000025a6: 4379 yC MULS r1,r7,r1 - 0x000025a8: 4608 .F MOV r0,r1 - 0x000025aa: 4639 9F MOV r1,r7 - 0x000025ac: f000fcec .... BL __aeabi_uidiv ; 0x2f88 - 0x000025b0: 42a0 .B CMP r0,r4 - 0x000025b2: d0ee .. BEQ 0x2592 ; MyPrintf + 434 - 0x000025b4: 9809 .. LDR r0,[sp,#0x24] - 0x000025b6: 2800 .( CMP r0,#0 - 0x000025b8: d000 .. BEQ 0x25bc ; MyPrintf + 476 - 0x000025ba: 1e6d m. SUBS r5,r5,#1 - 0x000025bc: 9809 .. LDR r0,[sp,#0x24] - 0x000025be: 2800 .( CMP r0,#0 - 0x000025c0: d009 .. BEQ 0x25d6 ; MyPrintf + 502 - 0x000025c2: 9803 .. LDR r0,[sp,#0xc] - 0x000025c4: 2830 0( CMP r0,#0x30 - 0x000025c6: d106 .. BNE 0x25d6 ; MyPrintf + 502 - 0x000025c8: 222d -" MOVS r2,#0x2d - 0x000025ca: 4630 0F MOV r0,r6 - 0x000025cc: 1c76 v. ADDS r6,r6,#1 - 0x000025ce: a904 .. ADD r1,sp,#0x10 - 0x000025d0: 540a .T STRB r2,[r1,r0] - 0x000025d2: 2000 . MOVS r0,#0 - 0x000025d4: 9009 .. STR r0,[sp,#0x24] - 0x000025d6: 2d01 .- CMP r5,#1 - 0x000025d8: d90b .. BLS 0x25f2 ; MyPrintf + 530 - 0x000025da: 2d10 .- CMP r5,#0x10 - 0x000025dc: d209 .. BCS 0x25f2 ; MyPrintf + 530 - 0x000025de: 1e6d m. SUBS r5,r5,#1 - 0x000025e0: e005 .. B 0x25ee ; MyPrintf + 526 - 0x000025e2: 4631 1F MOV r1,r6 - 0x000025e4: 1c76 v. ADDS r6,r6,#1 - 0x000025e6: aa04 .. ADD r2,sp,#0x10 - 0x000025e8: 9803 .. LDR r0,[sp,#0xc] - 0x000025ea: 5450 PT STRB r0,[r2,r1] - 0x000025ec: 1e6d m. SUBS r5,r5,#1 - 0x000025ee: 2d00 .- CMP r5,#0 - 0x000025f0: d1f7 .. BNE 0x25e2 ; MyPrintf + 514 - 0x000025f2: 9809 .. LDR r0,[sp,#0x24] - 0x000025f4: 2800 .( CMP r0,#0 - 0x000025f6: d004 .. BEQ 0x2602 ; MyPrintf + 546 - 0x000025f8: 222d -" MOVS r2,#0x2d - 0x000025fa: 4630 0F MOV r0,r6 - 0x000025fc: 1c76 v. ADDS r6,r6,#1 - 0x000025fe: a904 .. ADD r1,sp,#0x10 - 0x00002600: 540a .T STRB r2,[r1,r0] - 0x00002602: e026 &. B 0x2652 ; MyPrintf + 626 - 0x00002604: 9802 .. LDR r0,[sp,#8] - 0x00002606: 2878 x( CMP r0,#0x78 - 0x00002608: d10f .. BNE 0x262a ; MyPrintf + 586 - 0x0000260a: 4621 !F MOV r1,r4 - 0x0000260c: 980a .. LDR r0,[sp,#0x28] - 0x0000260e: f000fcbb .... BL __aeabi_uidiv ; 0x2f88 - 0x00002612: 4639 9F MOV r1,r7 - 0x00002614: 9000 .. STR r0,[sp,#0] - 0x00002616: f000fcb7 .... BL __aeabi_uidiv ; 0x2f88 - 0x0000261a: 482c ,H LDR r0,[pc,#176] ; [0x26cc] = 0x2ff8 - 0x0000261c: 6800 .h LDR r0,[r0,#0] - 0x0000261e: 5c42 B\ LDRB r2,[r0,r1] - 0x00002620: 4630 0F MOV r0,r6 - 0x00002622: 1c76 v. ADDS r6,r6,#1 - 0x00002624: a904 .. ADD r1,sp,#0x10 - 0x00002626: 540a .T STRB r2,[r1,r0] - 0x00002628: e00e .. B 0x2648 ; MyPrintf + 616 - 0x0000262a: 4621 !F MOV r1,r4 - 0x0000262c: 980a .. LDR r0,[sp,#0x28] - 0x0000262e: f000fcab .... BL __aeabi_uidiv ; 0x2f88 - 0x00002632: 4639 9F MOV r1,r7 - 0x00002634: 9000 .. STR r0,[sp,#0] - 0x00002636: f000fca7 .... BL __aeabi_uidiv ; 0x2f88 - 0x0000263a: 4825 %H LDR r0,[pc,#148] ; [0x26d0] = 0x2ffc - 0x0000263c: 6800 .h LDR r0,[r0,#0] - 0x0000263e: 5c42 B\ LDRB r2,[r0,r1] - 0x00002640: 4630 0F MOV r0,r6 - 0x00002642: 1c76 v. ADDS r6,r6,#1 + 0x00002546: 6800 .h LDR r0,[r0,#0] + 0x00002548: 900a .. STR r0,[sp,#0x28] + 0x0000254a: 9801 .. LDR r0,[sp,#4] + 0x0000254c: 1d00 .. ADDS r0,r0,#4 + 0x0000254e: 9001 .. STR r0,[sp,#4] + 0x00002550: 2600 .& MOVS r6,#0 + 0x00002552: 2710 .' MOVS r7,#0x10 + 0x00002554: 2000 . MOVS r0,#0 + 0x00002556: 9009 .. STR r0,[sp,#0x24] + 0x00002558: 2058 X MOVS r0,#0x58 + 0x0000255a: 9002 .. STR r0,[sp,#8] + 0x0000255c: e00d .. B 0x257a ; MyPrintf + 430 + 0x0000255e: bf00 .. NOP + 0x00002560: 9801 .. LDR r0,[sp,#4] + 0x00002562: 6800 .h LDR r0,[r0,#0] + 0x00002564: 900a .. STR r0,[sp,#0x28] + 0x00002566: 9801 .. LDR r0,[sp,#4] + 0x00002568: 1d00 .. ADDS r0,r0,#4 + 0x0000256a: 9001 .. STR r0,[sp,#4] + 0x0000256c: 2600 .& MOVS r6,#0 + 0x0000256e: 2710 .' MOVS r7,#0x10 + 0x00002570: 2000 . MOVS r0,#0 + 0x00002572: 9009 .. STR r0,[sp,#0x24] + 0x00002574: 2078 x MOVS r0,#0x78 + 0x00002576: 9002 .. STR r0,[sp,#8] + 0x00002578: bf00 .. NOP + 0x0000257a: 2401 .$ MOVS r4,#1 + 0x0000257c: e003 .. B 0x2586 ; MyPrintf + 442 + 0x0000257e: 4620 F MOV r0,r4 + 0x00002580: 4378 xC MULS r0,r7,r0 + 0x00002582: 4604 .F MOV r4,r0 + 0x00002584: 1e6d m. SUBS r5,r5,#1 + 0x00002586: 4620 F MOV r0,r4 + 0x00002588: 4378 xC MULS r0,r7,r0 + 0x0000258a: 990a .. LDR r1,[sp,#0x28] + 0x0000258c: 4288 .B CMP r0,r1 + 0x0000258e: d807 .. BHI 0x25a0 ; MyPrintf + 468 + 0x00002590: 4621 !F MOV r1,r4 + 0x00002592: 4379 yC MULS r1,r7,r1 + 0x00002594: 4608 .F MOV r0,r1 + 0x00002596: 4639 9F MOV r1,r7 + 0x00002598: f000fcec .... BL __aeabi_uidiv ; 0x2f74 + 0x0000259c: 42a0 .B CMP r0,r4 + 0x0000259e: d0ee .. BEQ 0x257e ; MyPrintf + 434 + 0x000025a0: 9809 .. LDR r0,[sp,#0x24] + 0x000025a2: 2800 .( CMP r0,#0 + 0x000025a4: d000 .. BEQ 0x25a8 ; MyPrintf + 476 + 0x000025a6: 1e6d m. SUBS r5,r5,#1 + 0x000025a8: 9809 .. LDR r0,[sp,#0x24] + 0x000025aa: 2800 .( CMP r0,#0 + 0x000025ac: d009 .. BEQ 0x25c2 ; MyPrintf + 502 + 0x000025ae: 9803 .. LDR r0,[sp,#0xc] + 0x000025b0: 2830 0( CMP r0,#0x30 + 0x000025b2: d106 .. BNE 0x25c2 ; MyPrintf + 502 + 0x000025b4: 222d -" MOVS r2,#0x2d + 0x000025b6: 4630 0F MOV r0,r6 + 0x000025b8: 1c76 v. ADDS r6,r6,#1 + 0x000025ba: a904 .. ADD r1,sp,#0x10 + 0x000025bc: 540a .T STRB r2,[r1,r0] + 0x000025be: 2000 . MOVS r0,#0 + 0x000025c0: 9009 .. STR r0,[sp,#0x24] + 0x000025c2: 2d01 .- CMP r5,#1 + 0x000025c4: d90b .. BLS 0x25de ; MyPrintf + 530 + 0x000025c6: 2d10 .- CMP r5,#0x10 + 0x000025c8: d209 .. BCS 0x25de ; MyPrintf + 530 + 0x000025ca: 1e6d m. SUBS r5,r5,#1 + 0x000025cc: e005 .. B 0x25da ; MyPrintf + 526 + 0x000025ce: 4631 1F MOV r1,r6 + 0x000025d0: 1c76 v. ADDS r6,r6,#1 + 0x000025d2: aa04 .. ADD r2,sp,#0x10 + 0x000025d4: 9803 .. LDR r0,[sp,#0xc] + 0x000025d6: 5450 PT STRB r0,[r2,r1] + 0x000025d8: 1e6d m. SUBS r5,r5,#1 + 0x000025da: 2d00 .- CMP r5,#0 + 0x000025dc: d1f7 .. BNE 0x25ce ; MyPrintf + 514 + 0x000025de: 9809 .. LDR r0,[sp,#0x24] + 0x000025e0: 2800 .( CMP r0,#0 + 0x000025e2: d004 .. BEQ 0x25ee ; MyPrintf + 546 + 0x000025e4: 222d -" MOVS r2,#0x2d + 0x000025e6: 4630 0F MOV r0,r6 + 0x000025e8: 1c76 v. ADDS r6,r6,#1 + 0x000025ea: a904 .. ADD r1,sp,#0x10 + 0x000025ec: 540a .T STRB r2,[r1,r0] + 0x000025ee: e026 &. B 0x263e ; MyPrintf + 626 + 0x000025f0: 9802 .. LDR r0,[sp,#8] + 0x000025f2: 2878 x( CMP r0,#0x78 + 0x000025f4: d10f .. BNE 0x2616 ; MyPrintf + 586 + 0x000025f6: 4621 !F MOV r1,r4 + 0x000025f8: 980a .. LDR r0,[sp,#0x28] + 0x000025fa: f000fcbb .... BL __aeabi_uidiv ; 0x2f74 + 0x000025fe: 4639 9F MOV r1,r7 + 0x00002600: 9000 .. STR r0,[sp,#0] + 0x00002602: f000fcb7 .... BL __aeabi_uidiv ; 0x2f74 + 0x00002606: 482b +H LDR r0,[pc,#172] ; [0x26b4] = 0x2fe4 + 0x00002608: 6800 .h LDR r0,[r0,#0] + 0x0000260a: 5c42 B\ LDRB r2,[r0,r1] + 0x0000260c: 4630 0F MOV r0,r6 + 0x0000260e: 1c76 v. ADDS r6,r6,#1 + 0x00002610: a904 .. ADD r1,sp,#0x10 + 0x00002612: 540a .T STRB r2,[r1,r0] + 0x00002614: e00e .. B 0x2634 ; MyPrintf + 616 + 0x00002616: 4621 !F MOV r1,r4 + 0x00002618: 980a .. LDR r0,[sp,#0x28] + 0x0000261a: f000fcab .... BL __aeabi_uidiv ; 0x2f74 + 0x0000261e: 4639 9F MOV r1,r7 + 0x00002620: 9000 .. STR r0,[sp,#0] + 0x00002622: f000fca7 .... BL __aeabi_uidiv ; 0x2f74 + 0x00002626: 4824 $H LDR r0,[pc,#144] ; [0x26b8] = 0x2fe8 + 0x00002628: 6800 .h LDR r0,[r0,#0] + 0x0000262a: 5c42 B\ LDRB r2,[r0,r1] + 0x0000262c: 4630 0F MOV r0,r6 + 0x0000262e: 1c76 v. ADDS r6,r6,#1 + 0x00002630: a904 .. ADD r1,sp,#0x10 + 0x00002632: 540a .T STRB r2,[r1,r0] + 0x00002634: 4639 9F MOV r1,r7 + 0x00002636: 4620 F MOV r0,r4 + 0x00002638: f000fc9c .... BL __aeabi_uidiv ; 0x2f74 + 0x0000263c: 4604 .F MOV r4,r0 + 0x0000263e: 2c00 ., CMP r4,#0 + 0x00002640: d1d6 .. BNE 0x25f0 ; MyPrintf + 548 + 0x00002642: 4632 2F MOV r2,r6 0x00002644: a904 .. ADD r1,sp,#0x10 - 0x00002646: 540a .T STRB r2,[r1,r0] - 0x00002648: 4639 9F MOV r1,r7 - 0x0000264a: 4620 F MOV r0,r4 - 0x0000264c: f000fc9c .... BL __aeabi_uidiv ; 0x2f88 - 0x00002650: 4604 .F MOV r4,r0 - 0x00002652: 2c00 ., CMP r4,#0 - 0x00002654: d1d6 .. BNE 0x2604 ; MyPrintf + 548 - 0x00002656: 4632 2F MOV r2,r6 - 0x00002658: a904 .. ADD r1,sp,#0x10 - 0x0000265a: 2000 . MOVS r0,#0 - 0x0000265c: f7fffeb6 .... BL printfsend ; 0x23cc - 0x00002660: e00c .. B 0x267c ; MyPrintf + 668 - 0x00002662: 9810 .. LDR r0,[sp,#0x40] - 0x00002664: 1e41 A. SUBS r1,r0,#1 - 0x00002666: 2201 ." MOVS r2,#1 - 0x00002668: 2000 . MOVS r0,#0 - 0x0000266a: f7fffeaf .... BL printfsend ; 0x23cc - 0x0000266e: e005 .. B 0x267c ; MyPrintf + 668 - 0x00002670: 2205 ." MOVS r2,#5 - 0x00002672: a118 .. ADR r1,{pc}+0x62 ; 0x26d4 - 0x00002674: 2000 . MOVS r0,#0 - 0x00002676: f7fffea9 .... BL printfsend ; 0x23cc - 0x0000267a: bf00 .. NOP - 0x0000267c: bf00 .. NOP - 0x0000267e: 9810 .. LDR r0,[sp,#0x40] - 0x00002680: 7800 .x LDRB r0,[r0,#0] - 0x00002682: 2800 .( CMP r0,#0 - 0x00002684: d000 .. BEQ 0x2688 ; MyPrintf + 680 - 0x00002686: e6b1 .. B 0x23ec ; MyPrintf + 12 - 0x00002688: 9001 .. STR r0,[sp,#4] - 0x0000268a: b00b .. ADD sp,sp,#0x2c - 0x0000268c: bcf0 .. POP {r4-r7} - 0x0000268e: bc08 .. POP {r3} - 0x00002690: b004 .. ADD sp,sp,#0x10 - 0x00002692: 4718 .G BX r3 + 0x00002646: 2000 . MOVS r0,#0 + 0x00002648: f7fffeb6 .... BL printfsend ; 0x23b8 + 0x0000264c: e00c .. B 0x2668 ; MyPrintf + 668 + 0x0000264e: 9810 .. LDR r0,[sp,#0x40] + 0x00002650: 1e41 A. SUBS r1,r0,#1 + 0x00002652: 2201 ." MOVS r2,#1 + 0x00002654: 2000 . MOVS r0,#0 + 0x00002656: f7fffeaf .... BL printfsend ; 0x23b8 + 0x0000265a: e005 .. B 0x2668 ; MyPrintf + 668 + 0x0000265c: 2205 ." MOVS r2,#5 + 0x0000265e: a117 .. ADR r1,{pc}+0x5e ; 0x26bc + 0x00002660: 2000 . MOVS r0,#0 + 0x00002662: f7fffea9 .... BL printfsend ; 0x23b8 + 0x00002666: bf00 .. NOP + 0x00002668: bf00 .. NOP + 0x0000266a: 9810 .. LDR r0,[sp,#0x40] + 0x0000266c: 7800 .x LDRB r0,[r0,#0] + 0x0000266e: 2800 .( CMP r0,#0 + 0x00002670: d000 .. BEQ 0x2674 ; MyPrintf + 680 + 0x00002672: e6b1 .. B 0x23d8 ; MyPrintf + 12 + 0x00002674: 9001 .. STR r0,[sp,#4] + 0x00002676: b00b .. ADD sp,sp,#0x2c + 0x00002678: bcf0 .. POP {r4-r7} + 0x0000267a: bc08 .. POP {r3} + 0x0000267c: b004 .. ADD sp,sp,#0x10 + 0x0000267e: 4718 .G BX r3 open_log_print - 0x00002694: 4911 .I LDR r1,[pc,#68] ; [0x26dc] = 0x10011018 - 0x00002696: 7008 .p STRB r0,[r1,#0] - 0x00002698: 4770 pG BX lr + 0x00002680: 4910 .I LDR r1,[pc,#64] ; [0x26c4] = 0x10011016 + 0x00002682: 7008 .p STRB r0,[r1,#0] + 0x00002684: 4770 pG BX lr log_print + 0x00002686: b510 .. PUSH {r4,lr} + 0x00002688: 4604 .F MOV r4,r0 + 0x0000268a: 480e .H LDR r0,[pc,#56] ; [0x26c4] = 0x10011016 + 0x0000268c: 7800 .x LDRB r0,[r0,#0] + 0x0000268e: 2800 .( CMP r0,#0 + 0x00002690: d002 .. BEQ 0x2698 ; log_print + 18 + 0x00002692: 4620 F MOV r0,r4 + 0x00002694: f7fffe9a .... BL MyPrintf ; 0x23cc + 0x00002698: bd10 .. POP {r4,pc} + log2_print 0x0000269a: b510 .. PUSH {r4,lr} 0x0000269c: 4604 .F MOV r4,r0 - 0x0000269e: 480f .H LDR r0,[pc,#60] ; [0x26dc] = 0x10011018 + 0x0000269e: 4809 .H LDR r0,[pc,#36] ; [0x26c4] = 0x10011016 0x000026a0: 7800 .x LDRB r0,[r0,#0] - 0x000026a2: 2800 .( CMP r0,#0 - 0x000026a4: d002 .. BEQ 0x26ac ; log_print + 18 + 0x000026a2: 2801 .( CMP r0,#1 + 0x000026a4: dd02 .. BLE 0x26ac ; log2_print + 18 0x000026a6: 4620 F MOV r0,r4 - 0x000026a8: f7fffe9a .... BL MyPrintf ; 0x23e0 + 0x000026a8: f7fffe90 .... BL MyPrintf ; 0x23cc 0x000026ac: bd10 .. POP {r4,pc} - log2_print - 0x000026ae: b510 .. PUSH {r4,lr} - 0x000026b0: 4604 .F MOV r4,r0 - 0x000026b2: 480a .H LDR r0,[pc,#40] ; [0x26dc] = 0x10011018 - 0x000026b4: 7800 .x LDRB r0,[r0,#0] - 0x000026b6: 2801 .( CMP r0,#1 - 0x000026b8: dd02 .. BLE 0x26c0 ; log2_print + 18 - 0x000026ba: 4620 F MOV r0,r4 - 0x000026bc: f7fffe90 .... BL MyPrintf ; 0x23e0 - 0x000026c0: bd10 .. POP {r4,pc} $d - 0x000026c2: 0000 .. DCW 0 + 0x000026ae: 0000 .. DCW 0 + 0x000026b0: 00000020 ... DCD 32 + 0x000026b4: 00002fe4 ./.. DCD 12260 + 0x000026b8: 00002fe8 ./.. DCD 12264 + 0x000026bc: 4f525245 ERRO DCD 1330795077 + 0x000026c0: 00000052 R... DCD 82 0x000026c4: 10011016 .... DCD 268505110 - 0x000026c8: 00000020 ... DCD 32 - 0x000026cc: 00002ff8 ./.. DCD 12280 - 0x000026d0: 00002ffc ./.. DCD 12284 - 0x000026d4: 4f525245 ERRO DCD 1330795077 - 0x000026d8: 00000052 R... DCD 82 - 0x000026dc: 10011018 .... DCD 268505112 $t .text USART_Init - 0x000026e0: b5fe .. PUSH {r1-r7,lr} - 0x000026e2: 4605 .F MOV r5,r0 - 0x000026e4: 460c .F MOV r4,r1 - 0x000026e6: 2000 . MOVS r0,#0 - 0x000026e8: 9001 .. STR r0,[sp,#4] - 0x000026ea: 2600 .& MOVS r6,#0 - 0x000026ec: 2700 .' MOVS r7,#0 - 0x000026ee: 9000 .. STR r0,[sp,#0] - 0x000026f0: bf00 .. NOP - 0x000026f2: 2001 . MOVS r0,#1 - 0x000026f4: 49fa .I LDR r1,[pc,#1000] ; [0x2ae0] = 0x10008040 - 0x000026f6: 70c8 .p STRB r0,[r1,#3] - 0x000026f8: 70c8 .p STRB r0,[r1,#3] - 0x000026fa: bf00 .. NOP - 0x000026fc: bf00 .. NOP - 0x000026fe: 48f9 .H LDR r0,[pc,#996] ; [0x2ae4] = 0x10004fe0 + 0x000026c8: b5fe .. PUSH {r1-r7,lr} + 0x000026ca: 4605 .F MOV r5,r0 + 0x000026cc: 460c .F MOV r4,r1 + 0x000026ce: 2000 . MOVS r0,#0 + 0x000026d0: 9001 .. STR r0,[sp,#4] + 0x000026d2: 2600 .& MOVS r6,#0 + 0x000026d4: 2700 .' MOVS r7,#0 + 0x000026d6: 9000 .. STR r0,[sp,#0] + 0x000026d8: bf00 .. NOP + 0x000026da: 2001 . MOVS r0,#1 + 0x000026dc: 49fa .I LDR r1,[pc,#1000] ; [0x2ac8] = 0x10008040 + 0x000026de: 70c8 .p STRB r0,[r1,#3] + 0x000026e0: 70c8 .p STRB r0,[r1,#3] + 0x000026e2: bf00 .. NOP + 0x000026e4: bf00 .. NOP + 0x000026e6: 48f9 .H LDR r0,[pc,#996] ; [0x2acc] = 0x10004fe0 + 0x000026e8: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x000026ea: 2000 . MOVS r0,#0 + 0x000026ec: 7c49 I| LDRB r1,[r1,#0x11] + 0x000026ee: 4300 .C ORRS r0,r0,r0 + 0x000026f0: 49f5 .I LDR r1,[pc,#980] ; [0x2ac8] = 0x10008040 + 0x000026f2: 7c49 I| LDRB r1,[r1,#0x11] + 0x000026f4: 4308 .C ORRS r0,r0,r1 + 0x000026f6: 2180 .! MOVS r1,#0x80 + 0x000026f8: 4388 .C BICS r0,r0,r1 + 0x000026fa: 49f3 .I LDR r1,[pc,#972] ; [0x2ac8] = 0x10008040 + 0x000026fc: 7448 Ht STRB r0,[r1,#0x11] + 0x000026fe: 48f3 .H LDR r0,[pc,#972] ; [0x2acc] = 0x10004fe0 0x00002700: 7fc0 .. LDRB r0,[r0,#0x1f] 0x00002702: 2000 . MOVS r0,#0 0x00002704: 7c49 I| LDRB r1,[r1,#0x11] 0x00002706: 4300 .C ORRS r0,r0,r0 - 0x00002708: 49f5 .I LDR r1,[pc,#980] ; [0x2ae0] = 0x10008040 + 0x00002708: 49ef .I LDR r1,[pc,#956] ; [0x2ac8] = 0x10008040 0x0000270a: 7c49 I| LDRB r1,[r1,#0x11] 0x0000270c: 4308 .C ORRS r0,r0,r1 0x0000270e: 2180 .! MOVS r1,#0x80 0x00002710: 4388 .C BICS r0,r0,r1 - 0x00002712: 49f3 .I LDR r1,[pc,#972] ; [0x2ae0] = 0x10008040 + 0x00002712: 49ed .I LDR r1,[pc,#948] ; [0x2ac8] = 0x10008040 0x00002714: 7448 Ht STRB r0,[r1,#0x11] - 0x00002716: 48f3 .H LDR r0,[pc,#972] ; [0x2ae4] = 0x10004fe0 - 0x00002718: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x0000271a: 2000 . MOVS r0,#0 - 0x0000271c: 7c49 I| LDRB r1,[r1,#0x11] - 0x0000271e: 4300 .C ORRS r0,r0,r0 - 0x00002720: 49ef .I LDR r1,[pc,#956] ; [0x2ae0] = 0x10008040 - 0x00002722: 7c49 I| LDRB r1,[r1,#0x11] - 0x00002724: 4308 .C ORRS r0,r0,r1 - 0x00002726: 2180 .! MOVS r1,#0x80 - 0x00002728: 4388 .C BICS r0,r0,r1 - 0x0000272a: 49ed .I LDR r1,[pc,#948] ; [0x2ae0] = 0x10008040 - 0x0000272c: 7448 Ht STRB r0,[r1,#0x11] - 0x0000272e: bf00 .. NOP - 0x00002730: 2c00 ., CMP r4,#0 - 0x00002732: d104 .. BNE 0x273e ; USART_Init + 94 - 0x00002734: 4aec .J LDR r2,[pc,#944] ; [0x2ae8] = 0x3000 - 0x00002736: 212b +! MOVS r1,#0x2b - 0x00002738: a0ec .. ADR r0,{pc}+0x3b4 ; 0x2aec - 0x0000273a: f7fefca2 .... BL _assert_handler ; 0x1082 - 0x0000273e: 2d00 .- CMP r5,#0 - 0x00002740: d006 .. BEQ 0x2750 ; USART_Init + 112 - 0x00002742: 2d01 .- CMP r5,#1 - 0x00002744: d004 .. BEQ 0x2750 ; USART_Init + 112 - 0x00002746: 4ae8 .J LDR r2,[pc,#928] ; [0x2ae8] = 0x3000 - 0x00002748: 212c ,! MOVS r1,#0x2c - 0x0000274a: a0e8 .. ADR r0,{pc}+0x3a2 ; 0x2aec + 0x00002716: bf00 .. NOP + 0x00002718: 2c00 ., CMP r4,#0 + 0x0000271a: d104 .. BNE 0x2726 ; USART_Init + 94 + 0x0000271c: 4aec .J LDR r2,[pc,#944] ; [0x2ad0] = 0x2fec + 0x0000271e: 215b [! MOVS r1,#0x5b + 0x00002720: a0ec .. ADR r0,{pc}+0x3b4 ; 0x2ad4 + 0x00002722: f7fefcae .... BL _assert_handler ; 0x1082 + 0x00002726: 2d00 .- CMP r5,#0 + 0x00002728: d006 .. BEQ 0x2738 ; USART_Init + 112 + 0x0000272a: 2d01 .- CMP r5,#1 + 0x0000272c: d004 .. BEQ 0x2738 ; USART_Init + 112 + 0x0000272e: 4ae8 .J LDR r2,[pc,#928] ; [0x2ad0] = 0x2fec + 0x00002730: 215c \! MOVS r1,#0x5c + 0x00002732: a0e8 .. ADR r0,{pc}+0x3a2 ; 0x2ad4 + 0x00002734: f7fefca5 .... BL _assert_handler ; 0x1082 + 0x00002738: 6820 h LDR r0,[r4,#0] + 0x0000273a: 2800 .( CMP r0,#0 + 0x0000273c: d003 .. BEQ 0x2746 ; USART_Init + 126 + 0x0000273e: 49f3 .I LDR r1,[pc,#972] ; [0x2b0c] = 0xce20 + 0x00002740: 6820 h LDR r0,[r4,#0] + 0x00002742: 4288 .B CMP r0,r1 + 0x00002744: d304 .. BCC 0x2750 ; USART_Init + 136 + 0x00002746: 4ae2 .J LDR r2,[pc,#904] ; [0x2ad0] = 0x2fec + 0x00002748: 215e ^! MOVS r1,#0x5e + 0x0000274a: a0e2 .. ADR r0,{pc}+0x38a ; 0x2ad4 0x0000274c: f7fefc99 .... BL _assert_handler ; 0x1082 - 0x00002750: 6820 h LDR r0,[r4,#0] + 0x00002750: 88a0 .. LDRH r0,[r4,#4] 0x00002752: 2800 .( CMP r0,#0 - 0x00002754: d003 .. BEQ 0x275e ; USART_Init + 126 - 0x00002756: 49f3 .I LDR r1,[pc,#972] ; [0x2b24] = 0xce20 - 0x00002758: 6820 h LDR r0,[r4,#0] - 0x0000275a: 4288 .B CMP r0,r1 - 0x0000275c: d304 .. BCC 0x2768 ; USART_Init + 136 - 0x0000275e: 4ae2 .J LDR r2,[pc,#904] ; [0x2ae8] = 0x3000 - 0x00002760: 212e .! MOVS r1,#0x2e - 0x00002762: a0e2 .. ADR r0,{pc}+0x38a ; 0x2aec - 0x00002764: f7fefc8d .... BL _assert_handler ; 0x1082 - 0x00002768: 88a0 .. LDRH r0,[r4,#4] - 0x0000276a: 2800 .( CMP r0,#0 - 0x0000276c: d007 .. BEQ 0x277e ; USART_Init + 158 - 0x0000276e: 88a0 .. LDRH r0,[r4,#4] - 0x00002770: 2804 .( CMP r0,#4 - 0x00002772: d004 .. BEQ 0x277e ; USART_Init + 158 - 0x00002774: 4adc .J LDR r2,[pc,#880] ; [0x2ae8] = 0x3000 - 0x00002776: 212f /! MOVS r1,#0x2f - 0x00002778: a0dc .. ADR r0,{pc}+0x374 ; 0x2aec - 0x0000277a: f7fefc82 .... BL _assert_handler ; 0x1082 - 0x0000277e: 88e0 .. LDRH r0,[r4,#6] - 0x00002780: 2800 .( CMP r0,#0 - 0x00002782: d007 .. BEQ 0x2794 ; USART_Init + 180 - 0x00002784: 88e0 .. LDRH r0,[r4,#6] - 0x00002786: 2808 .( CMP r0,#8 - 0x00002788: d004 .. BEQ 0x2794 ; USART_Init + 180 - 0x0000278a: 4ad7 .J LDR r2,[pc,#860] ; [0x2ae8] = 0x3000 - 0x0000278c: 2130 0! MOVS r1,#0x30 - 0x0000278e: a0d7 .. ADR r0,{pc}+0x35e ; 0x2aec - 0x00002790: f7fefc77 ..w. BL _assert_handler ; 0x1082 - 0x00002794: 8920 . LDRH r0,[r4,#8] - 0x00002796: 2800 .( CMP r0,#0 - 0x00002798: d007 .. BEQ 0x27aa ; USART_Init + 202 - 0x0000279a: 8920 . LDRH r0,[r4,#8] - 0x0000279c: 2802 .( CMP r0,#2 - 0x0000279e: d004 .. BEQ 0x27aa ; USART_Init + 202 - 0x000027a0: 4ad1 .J LDR r2,[pc,#836] ; [0x2ae8] = 0x3000 - 0x000027a2: 2131 1! MOVS r1,#0x31 - 0x000027a4: a0d1 .. ADR r0,{pc}+0x348 ; 0x2aec - 0x000027a6: f7fefc6c ..l. BL _assert_handler ; 0x1082 - 0x000027aa: 8960 `. LDRH r0,[r4,#0xa] - 0x000027ac: 2840 @( CMP r0,#0x40 - 0x000027ae: d007 .. BEQ 0x27c0 ; USART_Init + 224 - 0x000027b0: 8960 `. LDRH r0,[r4,#0xa] - 0x000027b2: 2800 .( CMP r0,#0 - 0x000027b4: d004 .. BEQ 0x27c0 ; USART_Init + 224 - 0x000027b6: 4acc .J LDR r2,[pc,#816] ; [0x2ae8] = 0x3000 - 0x000027b8: 2132 2! MOVS r1,#0x32 - 0x000027ba: a0cc .. ADR r0,{pc}+0x332 ; 0x2aec - 0x000027bc: f7fefc61 ..a. BL _assert_handler ; 0x1082 - 0x000027c0: 89a0 .. LDRH r0,[r4,#0xc] - 0x000027c2: 2800 .( CMP r0,#0 - 0x000027c4: d007 .. BEQ 0x27d6 ; USART_Init + 246 - 0x000027c6: 89a0 .. LDRH r0,[r4,#0xc] - 0x000027c8: 2810 .( CMP r0,#0x10 - 0x000027ca: d004 .. BEQ 0x27d6 ; USART_Init + 246 - 0x000027cc: 4ac6 .J LDR r2,[pc,#792] ; [0x2ae8] = 0x3000 - 0x000027ce: 2133 3! MOVS r1,#0x33 - 0x000027d0: a0c6 .. ADR r0,{pc}+0x31c ; 0x2aec + 0x00002754: d007 .. BEQ 0x2766 ; USART_Init + 158 + 0x00002756: 88a0 .. LDRH r0,[r4,#4] + 0x00002758: 2804 .( CMP r0,#4 + 0x0000275a: d004 .. BEQ 0x2766 ; USART_Init + 158 + 0x0000275c: 4adc .J LDR r2,[pc,#880] ; [0x2ad0] = 0x2fec + 0x0000275e: 215f _! MOVS r1,#0x5f + 0x00002760: a0dc .. ADR r0,{pc}+0x374 ; 0x2ad4 + 0x00002762: f7fefc8e .... BL _assert_handler ; 0x1082 + 0x00002766: 88e0 .. LDRH r0,[r4,#6] + 0x00002768: 2800 .( CMP r0,#0 + 0x0000276a: d007 .. BEQ 0x277c ; USART_Init + 180 + 0x0000276c: 88e0 .. LDRH r0,[r4,#6] + 0x0000276e: 2808 .( CMP r0,#8 + 0x00002770: d004 .. BEQ 0x277c ; USART_Init + 180 + 0x00002772: 4ad7 .J LDR r2,[pc,#860] ; [0x2ad0] = 0x2fec + 0x00002774: 2160 `! MOVS r1,#0x60 + 0x00002776: a0d7 .. ADR r0,{pc}+0x35e ; 0x2ad4 + 0x00002778: f7fefc83 .... BL _assert_handler ; 0x1082 + 0x0000277c: 8920 . LDRH r0,[r4,#8] + 0x0000277e: 2800 .( CMP r0,#0 + 0x00002780: d007 .. BEQ 0x2792 ; USART_Init + 202 + 0x00002782: 8920 . LDRH r0,[r4,#8] + 0x00002784: 2802 .( CMP r0,#2 + 0x00002786: d004 .. BEQ 0x2792 ; USART_Init + 202 + 0x00002788: 4ad1 .J LDR r2,[pc,#836] ; [0x2ad0] = 0x2fec + 0x0000278a: 2161 a! MOVS r1,#0x61 + 0x0000278c: a0d1 .. ADR r0,{pc}+0x348 ; 0x2ad4 + 0x0000278e: f7fefc78 ..x. BL _assert_handler ; 0x1082 + 0x00002792: 8960 `. LDRH r0,[r4,#0xa] + 0x00002794: 2840 @( CMP r0,#0x40 + 0x00002796: d007 .. BEQ 0x27a8 ; USART_Init + 224 + 0x00002798: 8960 `. LDRH r0,[r4,#0xa] + 0x0000279a: 2800 .( CMP r0,#0 + 0x0000279c: d004 .. BEQ 0x27a8 ; USART_Init + 224 + 0x0000279e: 4acc .J LDR r2,[pc,#816] ; [0x2ad0] = 0x2fec + 0x000027a0: 2162 b! MOVS r1,#0x62 + 0x000027a2: a0cc .. ADR r0,{pc}+0x332 ; 0x2ad4 + 0x000027a4: f7fefc6d ..m. BL _assert_handler ; 0x1082 + 0x000027a8: 89a0 .. LDRH r0,[r4,#0xc] + 0x000027aa: 2800 .( CMP r0,#0 + 0x000027ac: d007 .. BEQ 0x27be ; USART_Init + 246 + 0x000027ae: 89a0 .. LDRH r0,[r4,#0xc] + 0x000027b0: 2810 .( CMP r0,#0x10 + 0x000027b2: d004 .. BEQ 0x27be ; USART_Init + 246 + 0x000027b4: 4ac6 .J LDR r2,[pc,#792] ; [0x2ad0] = 0x2fec + 0x000027b6: 2163 c! MOVS r1,#0x63 + 0x000027b8: a0c6 .. ADR r0,{pc}+0x31c ; 0x2ad4 + 0x000027ba: f7fefc62 ..b. BL _assert_handler ; 0x1082 + 0x000027be: 89e0 .. LDRH r0,[r4,#0xe] + 0x000027c0: 2800 .( CMP r0,#0 + 0x000027c2: dd03 .. BLE 0x27cc ; USART_Init + 260 + 0x000027c4: 89e0 .. LDRH r0,[r4,#0xe] + 0x000027c6: 49d2 .I LDR r1,[pc,#840] ; [0x2b10] = 0x1001 + 0x000027c8: 4288 .B CMP r0,r1 + 0x000027ca: dd04 .. BLE 0x27d6 ; USART_Init + 270 + 0x000027cc: 4ac0 .J LDR r2,[pc,#768] ; [0x2ad0] = 0x2fec + 0x000027ce: 2164 d! MOVS r1,#0x64 + 0x000027d0: a0c0 .. ADR r0,{pc}+0x304 ; 0x2ad4 0x000027d2: f7fefc56 ..V. BL _assert_handler ; 0x1082 - 0x000027d6: 89e0 .. LDRH r0,[r4,#0xe] + 0x000027d6: 8a20 . LDRH r0,[r4,#0x10] 0x000027d8: 2800 .( CMP r0,#0 - 0x000027da: dd03 .. BLE 0x27e4 ; USART_Init + 260 - 0x000027dc: 89e0 .. LDRH r0,[r4,#0xe] - 0x000027de: 49d2 .I LDR r1,[pc,#840] ; [0x2b28] = 0x1001 + 0x000027da: dd03 .. BLE 0x27e4 ; USART_Init + 284 + 0x000027dc: 8a20 . LDRH r0,[r4,#0x10] + 0x000027de: 49cc .I LDR r1,[pc,#816] ; [0x2b10] = 0x1001 0x000027e0: 4288 .B CMP r0,r1 - 0x000027e2: dd04 .. BLE 0x27ee ; USART_Init + 270 - 0x000027e4: 4ac0 .J LDR r2,[pc,#768] ; [0x2ae8] = 0x3000 - 0x000027e6: 2134 4! MOVS r1,#0x34 - 0x000027e8: a0c0 .. ADR r0,{pc}+0x304 ; 0x2aec + 0x000027e2: dd04 .. BLE 0x27ee ; USART_Init + 294 + 0x000027e4: 4aba .J LDR r2,[pc,#744] ; [0x2ad0] = 0x2fec + 0x000027e6: 2165 e! MOVS r1,#0x65 + 0x000027e8: a0ba .. ADR r0,{pc}+0x2ec ; 0x2ad4 0x000027ea: f7fefc4a ..J. BL _assert_handler ; 0x1082 - 0x000027ee: 8a20 . LDRH r0,[r4,#0x10] - 0x000027f0: 2800 .( CMP r0,#0 - 0x000027f2: dd03 .. BLE 0x27fc ; USART_Init + 284 - 0x000027f4: 8a20 . LDRH r0,[r4,#0x10] - 0x000027f6: 49cc .I LDR r1,[pc,#816] ; [0x2b28] = 0x1001 - 0x000027f8: 4288 .B CMP r0,r1 - 0x000027fa: dd04 .. BLE 0x2806 ; USART_Init + 294 - 0x000027fc: 4aba .J LDR r2,[pc,#744] ; [0x2ae8] = 0x3000 - 0x000027fe: 2135 5! MOVS r1,#0x35 - 0x00002800: a0ba .. ADR r0,{pc}+0x2ec ; 0x2aec - 0x00002802: f7fefc3e ..>. BL _assert_handler ; 0x1082 - 0x00002806: 8820 . LDRH r0,[r4,#0] - 0x00002808: 0129 ). LSLS r1,r5,#4 - 0x0000280a: 4ac8 .J LDR r2,[pc,#800] ; [0x2b2c] = 0x10011038 - 0x0000280c: 5250 PR STRH r0,[r2,r1] - 0x0000280e: 2d00 .- CMP r5,#0 - 0x00002810: d112 .. BNE 0x2838 ; USART_Init + 344 - 0x00002812: 4ec7 .N LDR r6,[pc,#796] ; [0x2b30] = 0x10011058 - 0x00002814: 0129 ). LSLS r1,r5,#4 - 0x00002816: 1889 .. ADDS r1,r1,r2 - 0x00002818: 810e .. STRH r6,[r1,#8] - 0x0000281a: 89e0 .. LDRH r0,[r4,#0xe] - 0x0000281c: 1980 .. ADDS r0,r0,r6 - 0x0000281e: 0129 ). LSLS r1,r5,#4 - 0x00002820: 1889 .. ADDS r1,r1,r2 - 0x00002822: 8148 H. STRH r0,[r1,#0xa] - 0x00002824: 4ec3 .N LDR r6,[pc,#780] ; [0x2b34] = 0x10012059 - 0x00002826: 0129 ). LSLS r1,r5,#4 - 0x00002828: 1889 .. ADDS r1,r1,r2 - 0x0000282a: 804e N. STRH r6,[r1,#2] - 0x0000282c: 8a20 . LDRH r0,[r4,#0x10] - 0x0000282e: 1980 .. ADDS r0,r0,r6 - 0x00002830: 0129 ). LSLS r1,r5,#4 - 0x00002832: 1889 .. ADDS r1,r1,r2 - 0x00002834: 8088 .. STRH r0,[r1,#4] - 0x00002836: e012 .. B 0x285e ; USART_Init + 382 - 0x00002838: 4ebf .N LDR r6,[pc,#764] ; [0x2b38] = 0x1001101b - 0x0000283a: 0129 ). LSLS r1,r5,#4 - 0x0000283c: 4abb .J LDR r2,[pc,#748] ; [0x2b2c] = 0x10011038 - 0x0000283e: 1889 .. ADDS r1,r1,r2 - 0x00002840: 810e .. STRH r6,[r1,#8] - 0x00002842: 89e0 .. LDRH r0,[r4,#0xe] - 0x00002844: 1980 .. ADDS r0,r0,r6 - 0x00002846: 0129 ). LSLS r1,r5,#4 - 0x00002848: 1889 .. ADDS r1,r1,r2 - 0x0000284a: 8148 H. STRH r0,[r1,#0xa] - 0x0000284c: 4ebb .N LDR r6,[pc,#748] ; [0x2b3c] = 0x1001101d - 0x0000284e: 0129 ). LSLS r1,r5,#4 - 0x00002850: 1889 .. ADDS r1,r1,r2 - 0x00002852: 804e N. STRH r6,[r1,#2] - 0x00002854: 8a20 . LDRH r0,[r4,#0x10] - 0x00002856: 1980 .. ADDS r0,r0,r6 - 0x00002858: 0129 ). LSLS r1,r5,#4 - 0x0000285a: 1889 .. ADDS r1,r1,r2 - 0x0000285c: 8088 .. STRH r0,[r1,#4] - 0x0000285e: 7aa0 .z LDRB r0,[r4,#0xa] - 0x00002860: 7b21 !{ LDRB r1,[r4,#0xc] - 0x00002862: 4308 .C ORRS r0,r0,r1 - 0x00002864: 7a21 !z LDRB r1,[r4,#8] - 0x00002866: 4308 .C ORRS r0,r0,r1 - 0x00002868: 79a1 .y LDRB r1,[r4,#6] - 0x0000286a: 4308 .C ORRS r0,r0,r1 - 0x0000286c: 7921 !y LDRB r1,[r4,#4] - 0x0000286e: 4308 .C ORRS r0,r0,r1 - 0x00002870: 2181 .! MOVS r1,#0x81 - 0x00002872: 4308 .C ORRS r0,r0,r1 - 0x00002874: b2c0 .. UXTB r0,r0 - 0x00002876: 9001 .. STR r0,[sp,#4] - 0x00002878: 0129 ). LSLS r1,r5,#4 - 0x0000287a: 4aac .J LDR r2,[pc,#688] ; [0x2b2c] = 0x10011038 - 0x0000287c: 1889 .. ADDS r1,r1,r2 - 0x0000287e: 9801 .. LDR r0,[sp,#4] - 0x00002880: 7388 .s STRB r0,[r1,#0xe] - 0x00002882: 2d00 .- CMP r5,#0 - 0x00002884: d104 .. BNE 0x2890 ; USART_Init + 432 - 0x00002886: 4fae .O LDR r7,[pc,#696] ; [0x2b40] = 0x8060 - 0x00002888: 4895 .H LDR r0,[pc,#596] ; [0x2ae0] = 0x10008040 - 0x0000288a: 3012 .0 ADDS r0,r0,#0x12 - 0x0000288c: 9000 .. STR r0,[sp,#0] - 0x0000288e: e004 .. B 0x289a ; USART_Init + 442 - 0x00002890: 4fab .O LDR r7,[pc,#684] ; [0x2b40] = 0x8060 - 0x00002892: 3711 .7 ADDS r7,r7,#0x11 - 0x00002894: 4892 .H LDR r0,[pc,#584] ; [0x2ae0] = 0x10008040 - 0x00002896: 3032 20 ADDS r0,r0,#0x32 - 0x00002898: 9000 .. STR r0,[sp,#0] - 0x0000289a: bf00 .. NOP - 0x0000289c: 4891 .H LDR r0,[pc,#580] ; [0x2ae4] = 0x10004fe0 - 0x0000289e: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x000028a0: 2000 . MOVS r0,#0 + 0x000027ee: 8820 . LDRH r0,[r4,#0] + 0x000027f0: 0129 ). LSLS r1,r5,#4 + 0x000027f2: 4ac8 .J LDR r2,[pc,#800] ; [0x2b14] = 0x10011038 + 0x000027f4: 5250 PR STRH r0,[r2,r1] + 0x000027f6: 2d00 .- CMP r5,#0 + 0x000027f8: d112 .. BNE 0x2820 ; USART_Init + 344 + 0x000027fa: 4ec7 .N LDR r6,[pc,#796] ; [0x2b18] = 0x10011058 + 0x000027fc: 0129 ). LSLS r1,r5,#4 + 0x000027fe: 1889 .. ADDS r1,r1,r2 + 0x00002800: 810e .. STRH r6,[r1,#8] + 0x00002802: 89e0 .. LDRH r0,[r4,#0xe] + 0x00002804: 1980 .. ADDS r0,r0,r6 + 0x00002806: 0129 ). LSLS r1,r5,#4 + 0x00002808: 1889 .. ADDS r1,r1,r2 + 0x0000280a: 8148 H. STRH r0,[r1,#0xa] + 0x0000280c: 4ec3 .N LDR r6,[pc,#780] ; [0x2b1c] = 0x10012059 + 0x0000280e: 0129 ). LSLS r1,r5,#4 + 0x00002810: 1889 .. ADDS r1,r1,r2 + 0x00002812: 804e N. STRH r6,[r1,#2] + 0x00002814: 8a20 . LDRH r0,[r4,#0x10] + 0x00002816: 1980 .. ADDS r0,r0,r6 + 0x00002818: 0129 ). LSLS r1,r5,#4 + 0x0000281a: 1889 .. ADDS r1,r1,r2 + 0x0000281c: 8088 .. STRH r0,[r1,#4] + 0x0000281e: e012 .. B 0x2846 ; USART_Init + 382 + 0x00002820: 4ebf .N LDR r6,[pc,#764] ; [0x2b20] = 0x1001101b + 0x00002822: 0129 ). LSLS r1,r5,#4 + 0x00002824: 4abb .J LDR r2,[pc,#748] ; [0x2b14] = 0x10011038 + 0x00002826: 1889 .. ADDS r1,r1,r2 + 0x00002828: 810e .. STRH r6,[r1,#8] + 0x0000282a: 89e0 .. LDRH r0,[r4,#0xe] + 0x0000282c: 1980 .. ADDS r0,r0,r6 + 0x0000282e: 0129 ). LSLS r1,r5,#4 + 0x00002830: 1889 .. ADDS r1,r1,r2 + 0x00002832: 8148 H. STRH r0,[r1,#0xa] + 0x00002834: 4ebb .N LDR r6,[pc,#748] ; [0x2b24] = 0x1001101d + 0x00002836: 0129 ). LSLS r1,r5,#4 + 0x00002838: 1889 .. ADDS r1,r1,r2 + 0x0000283a: 804e N. STRH r6,[r1,#2] + 0x0000283c: 8a20 . LDRH r0,[r4,#0x10] + 0x0000283e: 1980 .. ADDS r0,r0,r6 + 0x00002840: 0129 ). LSLS r1,r5,#4 + 0x00002842: 1889 .. ADDS r1,r1,r2 + 0x00002844: 8088 .. STRH r0,[r1,#4] + 0x00002846: 7aa0 .z LDRB r0,[r4,#0xa] + 0x00002848: 7b21 !{ LDRB r1,[r4,#0xc] + 0x0000284a: 4308 .C ORRS r0,r0,r1 + 0x0000284c: 7a21 !z LDRB r1,[r4,#8] + 0x0000284e: 4308 .C ORRS r0,r0,r1 + 0x00002850: 79a1 .y LDRB r1,[r4,#6] + 0x00002852: 4308 .C ORRS r0,r0,r1 + 0x00002854: 7921 !y LDRB r1,[r4,#4] + 0x00002856: 4308 .C ORRS r0,r0,r1 + 0x00002858: 2181 .! MOVS r1,#0x81 + 0x0000285a: 4308 .C ORRS r0,r0,r1 + 0x0000285c: b2c0 .. UXTB r0,r0 + 0x0000285e: 9001 .. STR r0,[sp,#4] + 0x00002860: 0129 ). LSLS r1,r5,#4 + 0x00002862: 4aac .J LDR r2,[pc,#688] ; [0x2b14] = 0x10011038 + 0x00002864: 1889 .. ADDS r1,r1,r2 + 0x00002866: 9801 .. LDR r0,[sp,#4] + 0x00002868: 7388 .s STRB r0,[r1,#0xe] + 0x0000286a: 2d00 .- CMP r5,#0 + 0x0000286c: d104 .. BNE 0x2878 ; USART_Init + 432 + 0x0000286e: 4fae .O LDR r7,[pc,#696] ; [0x2b28] = 0x8060 + 0x00002870: 4895 .H LDR r0,[pc,#596] ; [0x2ac8] = 0x10008040 + 0x00002872: 3012 .0 ADDS r0,r0,#0x12 + 0x00002874: 9000 .. STR r0,[sp,#0] + 0x00002876: e004 .. B 0x2882 ; USART_Init + 442 + 0x00002878: 4fab .O LDR r7,[pc,#684] ; [0x2b28] = 0x8060 + 0x0000287a: 3711 .7 ADDS r7,r7,#0x11 + 0x0000287c: 4892 .H LDR r0,[pc,#584] ; [0x2ac8] = 0x10008040 + 0x0000287e: 3032 20 ADDS r0,r0,#0x32 + 0x00002880: 9000 .. STR r0,[sp,#0] + 0x00002882: bf00 .. NOP + 0x00002884: 4891 .H LDR r0,[pc,#580] ; [0x2acc] = 0x10004fe0 + 0x00002886: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x00002888: 2000 . MOVS r0,#0 + 0x0000288a: 2101 .! MOVS r1,#1 + 0x0000288c: 0709 .. LSLS r1,r1,#28 + 0x0000288e: 1879 y. ADDS r1,r7,r1 + 0x00002890: 7809 .x LDRB r1,[r1,#0] + 0x00002892: 4300 .C ORRS r0,r0,r0 + 0x00002894: 2101 .! MOVS r1,#1 + 0x00002896: 0709 .. LSLS r1,r1,#28 + 0x00002898: 1879 y. ADDS r1,r7,r1 + 0x0000289a: 7809 .x LDRB r1,[r1,#0] + 0x0000289c: 4308 .C ORRS r0,r0,r1 + 0x0000289e: 0840 @. LSRS r0,r0,#1 + 0x000028a0: 0040 @. LSLS r0,r0,#1 0x000028a2: 2101 .! MOVS r1,#1 0x000028a4: 0709 .. LSLS r1,r1,#28 0x000028a6: 1879 y. ADDS r1,r7,r1 - 0x000028a8: 7809 .x LDRB r1,[r1,#0] - 0x000028aa: 4300 .C ORRS r0,r0,r0 - 0x000028ac: 2101 .! MOVS r1,#1 - 0x000028ae: 0709 .. LSLS r1,r1,#28 - 0x000028b0: 1879 y. ADDS r1,r7,r1 - 0x000028b2: 7809 .x LDRB r1,[r1,#0] - 0x000028b4: 4308 .C ORRS r0,r0,r1 - 0x000028b6: 0840 @. LSRS r0,r0,#1 - 0x000028b8: 0040 @. LSLS r0,r0,#1 + 0x000028a8: 7008 .p STRB r0,[r1,#0] + 0x000028aa: 4888 .H LDR r0,[pc,#544] ; [0x2acc] = 0x10004fe0 + 0x000028ac: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x000028ae: 2000 . MOVS r0,#0 + 0x000028b0: 2101 .! MOVS r1,#1 + 0x000028b2: 0709 .. LSLS r1,r1,#28 + 0x000028b4: 1879 y. ADDS r1,r7,r1 + 0x000028b6: 7809 .x LDRB r1,[r1,#0] + 0x000028b8: 4300 .C ORRS r0,r0,r0 0x000028ba: 2101 .! MOVS r1,#1 0x000028bc: 0709 .. LSLS r1,r1,#28 0x000028be: 1879 y. ADDS r1,r7,r1 - 0x000028c0: 7008 .p STRB r0,[r1,#0] - 0x000028c2: 4888 .H LDR r0,[pc,#544] ; [0x2ae4] = 0x10004fe0 - 0x000028c4: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x000028c6: 2000 . MOVS r0,#0 + 0x000028c0: 7809 .x LDRB r1,[r1,#0] + 0x000028c2: 4308 .C ORRS r0,r0,r1 + 0x000028c4: 0840 @. LSRS r0,r0,#1 + 0x000028c6: 0040 @. LSLS r0,r0,#1 0x000028c8: 2101 .! MOVS r1,#1 0x000028ca: 0709 .. LSLS r1,r1,#28 0x000028cc: 1879 y. ADDS r1,r7,r1 - 0x000028ce: 7809 .x LDRB r1,[r1,#0] - 0x000028d0: 4300 .C ORRS r0,r0,r0 - 0x000028d2: 2101 .! MOVS r1,#1 - 0x000028d4: 0709 .. LSLS r1,r1,#28 - 0x000028d6: 1879 y. ADDS r1,r7,r1 - 0x000028d8: 7809 .x LDRB r1,[r1,#0] - 0x000028da: 4308 .C ORRS r0,r0,r1 - 0x000028dc: 0840 @. LSRS r0,r0,#1 - 0x000028de: 0040 @. LSLS r0,r0,#1 - 0x000028e0: 2101 .! MOVS r1,#1 - 0x000028e2: 0709 .. LSLS r1,r1,#28 - 0x000028e4: 1879 y. ADDS r1,r7,r1 - 0x000028e6: 7008 .p STRB r0,[r1,#0] - 0x000028e8: bf00 .. NOP - 0x000028ea: 0128 (. LSLS r0,r5,#4 - 0x000028ec: 4a8f .J LDR r2,[pc,#572] ; [0x2b2c] = 0x10011038 - 0x000028ee: 5a11 .Z LDRH r1,[r2,r0] - 0x000028f0: 9800 .. LDR r0,[sp,#0] - 0x000028f2: f7fff944 ..D. BL HW_REG_16BIT ; 0x1b7e - 0x000028f6: 0128 (. LSLS r0,r5,#4 - 0x000028f8: 4a8c .J LDR r2,[pc,#560] ; [0x2b2c] = 0x10011038 - 0x000028fa: 1880 .. ADDS r0,r0,r2 - 0x000028fc: 8901 .. LDRH r1,[r0,#8] - 0x000028fe: 9800 .. LDR r0,[sp,#0] - 0x00002900: 3008 .0 ADDS r0,r0,#8 - 0x00002902: f7fff93c ..<. BL HW_REG_16BIT ; 0x1b7e - 0x00002906: 0128 (. LSLS r0,r5,#4 - 0x00002908: 4a88 .J LDR r2,[pc,#544] ; [0x2b2c] = 0x10011038 - 0x0000290a: 1880 .. ADDS r0,r0,r2 - 0x0000290c: 8941 A. LDRH r1,[r0,#0xa] - 0x0000290e: 9800 .. LDR r0,[sp,#0] - 0x00002910: 300a .0 ADDS r0,r0,#0xa - 0x00002912: f7fff934 ..4. BL HW_REG_16BIT ; 0x1b7e - 0x00002916: 0128 (. LSLS r0,r5,#4 - 0x00002918: 4a84 .J LDR r2,[pc,#528] ; [0x2b2c] = 0x10011038 - 0x0000291a: 1880 .. ADDS r0,r0,r2 - 0x0000291c: 8901 .. LDRH r1,[r0,#8] - 0x0000291e: 9800 .. LDR r0,[sp,#0] - 0x00002920: 300c .0 ADDS r0,r0,#0xc - 0x00002922: f7fff92c ..,. BL HW_REG_16BIT ; 0x1b7e - 0x00002926: 0128 (. LSLS r0,r5,#4 - 0x00002928: 4a80 .J LDR r2,[pc,#512] ; [0x2b2c] = 0x10011038 - 0x0000292a: 1880 .. ADDS r0,r0,r2 - 0x0000292c: 8841 A. LDRH r1,[r0,#2] - 0x0000292e: 9800 .. LDR r0,[sp,#0] - 0x00002930: 1c80 .. ADDS r0,r0,#2 - 0x00002932: f7fff924 ..$. BL HW_REG_16BIT ; 0x1b7e - 0x00002936: 0128 (. LSLS r0,r5,#4 - 0x00002938: 4a7c |J LDR r2,[pc,#496] ; [0x2b2c] = 0x10011038 - 0x0000293a: 1880 .. ADDS r0,r0,r2 - 0x0000293c: 8881 .. LDRH r1,[r0,#4] - 0x0000293e: 9800 .. LDR r0,[sp,#0] - 0x00002940: 1d00 .. ADDS r0,r0,#4 - 0x00002942: f7fff91c .... BL HW_REG_16BIT ; 0x1b7e - 0x00002946: 0128 (. LSLS r0,r5,#4 - 0x00002948: 4a78 xJ LDR r2,[pc,#480] ; [0x2b2c] = 0x10011038 - 0x0000294a: 1880 .. ADDS r0,r0,r2 - 0x0000294c: 8841 A. LDRH r1,[r0,#2] - 0x0000294e: 9800 .. LDR r0,[sp,#0] - 0x00002950: 1d80 .. ADDS r0,r0,#6 - 0x00002952: f7fff914 .... BL HW_REG_16BIT ; 0x1b7e - 0x00002956: bf00 .. NOP - 0x00002958: 0128 (. LSLS r0,r5,#4 - 0x0000295a: 4974 tI LDR r1,[pc,#464] ; [0x2b2c] = 0x10011038 - 0x0000295c: 1840 @. ADDS r0,r0,r1 - 0x0000295e: 7b80 .{ LDRB r0,[r0,#0xe] - 0x00002960: 2101 .! MOVS r1,#1 - 0x00002962: 0709 .. LSLS r1,r1,#28 - 0x00002964: 1879 y. ADDS r1,r7,r1 - 0x00002966: 7008 .p STRB r0,[r1,#0] - 0x00002968: 0128 (. LSLS r0,r5,#4 - 0x0000296a: 4970 pI LDR r1,[pc,#448] ; [0x2b2c] = 0x10011038 - 0x0000296c: 1840 @. ADDS r0,r0,r1 - 0x0000296e: 7b80 .{ LDRB r0,[r0,#0xe] - 0x00002970: 2101 .! MOVS r1,#1 - 0x00002972: 0709 .. LSLS r1,r1,#28 - 0x00002974: 1879 y. ADDS r1,r7,r1 - 0x00002976: 7008 .p STRB r0,[r1,#0] - 0x00002978: bf00 .. NOP - 0x0000297a: bdfe .. POP {r1-r7,pc} - USART_DeInit - 0x0000297c: b510 .. PUSH {r4,lr} - 0x0000297e: 4604 .F MOV r4,r0 - 0x00002980: 2c00 ., CMP r4,#0 - 0x00002982: d006 .. BEQ 0x2992 ; USART_DeInit + 22 - 0x00002984: 2c01 ., CMP r4,#1 - 0x00002986: d004 .. BEQ 0x2992 ; USART_DeInit + 22 - 0x00002988: 4a6e nJ LDR r2,[pc,#440] ; [0x2b44] = 0x300b - 0x0000298a: 216f o! MOVS r1,#0x6f - 0x0000298c: a057 W. ADR r0,{pc}+0x160 ; 0x2aec - 0x0000298e: f7fefb78 ..x. BL _assert_handler ; 0x1082 - 0x00002992: 2c00 ., CMP r4,#0 - 0x00002994: d139 9. BNE 0x2a0a ; USART_DeInit + 142 - 0x00002996: bf00 .. NOP - 0x00002998: 4852 RH LDR r0,[pc,#328] ; [0x2ae4] = 0x10004fe0 - 0x0000299a: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x0000299c: 2000 . MOVS r0,#0 - 0x0000299e: 4950 PI LDR r1,[pc,#320] ; [0x2ae0] = 0x10008040 - 0x000029a0: 3120 1 ADDS r1,r1,#0x20 - 0x000029a2: 7809 .x LDRB r1,[r1,#0] - 0x000029a4: 4300 .C ORRS r0,r0,r0 - 0x000029a6: 494e NI LDR r1,[pc,#312] ; [0x2ae0] = 0x10008040 - 0x000029a8: 3120 1 ADDS r1,r1,#0x20 - 0x000029aa: 7809 .x LDRB r1,[r1,#0] - 0x000029ac: 4308 .C ORRS r0,r0,r1 - 0x000029ae: 2101 .! MOVS r1,#1 - 0x000029b0: 4308 .C ORRS r0,r0,r1 - 0x000029b2: 494b KI LDR r1,[pc,#300] ; [0x2ae0] = 0x10008040 - 0x000029b4: 3120 1 ADDS r1,r1,#0x20 - 0x000029b6: 7008 .p STRB r0,[r1,#0] - 0x000029b8: 484a JH LDR r0,[pc,#296] ; [0x2ae4] = 0x10004fe0 - 0x000029ba: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x000029bc: 2000 . MOVS r0,#0 - 0x000029be: 7809 .x LDRB r1,[r1,#0] - 0x000029c0: 4300 .C ORRS r0,r0,r0 - 0x000029c2: 4947 GI LDR r1,[pc,#284] ; [0x2ae0] = 0x10008040 - 0x000029c4: 3120 1 ADDS r1,r1,#0x20 - 0x000029c6: 7809 .x LDRB r1,[r1,#0] - 0x000029c8: 4308 .C ORRS r0,r0,r1 - 0x000029ca: 2101 .! MOVS r1,#1 - 0x000029cc: 4308 .C ORRS r0,r0,r1 - 0x000029ce: 4944 DI LDR r1,[pc,#272] ; [0x2ae0] = 0x10008040 - 0x000029d0: 3120 1 ADDS r1,r1,#0x20 - 0x000029d2: 7008 .p STRB r0,[r1,#0] - 0x000029d4: bf00 .. NOP - 0x000029d6: bf00 .. NOP - 0x000029d8: 4842 BH LDR r0,[pc,#264] ; [0x2ae4] = 0x10004fe0 - 0x000029da: 7fc0 .. LDRB r0,[r0,#0x1f] - 0x000029dc: 2000 . MOVS r0,#0 - 0x000029de: 7809 .x LDRB r1,[r1,#0] - 0x000029e0: 4300 .C ORRS r0,r0,r0 - 0x000029e2: 493f ?I LDR r1,[pc,#252] ; [0x2ae0] = 0x10008040 - 0x000029e4: 3120 1 ADDS r1,r1,#0x20 - 0x000029e6: 7809 .x LDRB r1,[r1,#0] - 0x000029e8: 4308 .C ORRS r0,r0,r1 - 0x000029ea: 493d =I LDR r1,[pc,#244] ; [0x2ae0] = 0x10008040 - 0x000029ec: 3120 1 ADDS r1,r1,#0x20 - 0x000029ee: 7008 .p STRB r0,[r1,#0] - 0x000029f0: 483c 1 ADDS r1,r1,#0x3e + 0x00002dbe: 485a ZH LDR r0,[pc,#360] ; [0x2f28] = 0x2ad4 + 0x00002dc0: f7fef95f .._. BL _assert_handler ; 0x1082 + 0x00002dc4: 9803 .. LDR r0,[sp,#0xc] + 0x00002dc6: 2800 .( CMP r0,#0 + 0x00002dc8: d105 .. BNE 0x2dd6 ; USART_SendDataFromBuff + 52 + 0x00002dca: 4a5f _J LDR r2,[pc,#380] ; [0x2f48] = 0x304b + 0x00002dcc: 21ff .! MOVS r1,#0xff + 0x00002dce: 313f ?1 ADDS r1,r1,#0x3f + 0x00002dd0: 4855 UH LDR r0,[pc,#340] ; [0x2f28] = 0x2ad4 + 0x00002dd2: f7fef956 ..V. BL _assert_handler ; 0x1082 + 0x00002dd6: 9804 .. LDR r0,[sp,#0x10] + 0x00002dd8: 2800 .( CMP r0,#0 + 0x00002dda: dc05 .. BGT 0x2de8 ; USART_SendDataFromBuff + 70 + 0x00002ddc: 4a5a ZJ LDR r2,[pc,#360] ; [0x2f48] = 0x304b + 0x00002dde: 21ff .! MOVS r1,#0xff + 0x00002de0: 3140 @1 ADDS r1,r1,#0x40 + 0x00002de2: 4851 QH LDR r0,[pc,#324] ; [0x2f28] = 0x2ad4 + 0x00002de4: f7fef94d ..M. BL _assert_handler ; 0x1082 + 0x00002de8: 2c00 ., CMP r4,#0 + 0x00002dea: d101 .. BNE 0x2df0 ; USART_SendDataFromBuff + 78 + 0x00002dec: 4f4f OO LDR r7,[pc,#316] ; [0x2f2c] = 0x10008052 + 0x00002dee: e001 .. B 0x2df4 ; USART_SendDataFromBuff + 82 + 0x00002df0: 4f4e NO LDR r7,[pc,#312] ; [0x2f2c] = 0x10008052 + 0x00002df2: 3720 7 ADDS r7,r7,#0x20 + 0x00002df4: 4638 8F MOV r0,r7 + 0x00002df6: 300c .0 ADDS r0,r0,#0xc + 0x00002df8: f7fefeca .... BL HR_REG_16BIT ; 0x1b90 + 0x00002dfc: 4605 .F MOV r5,r0 + 0x00002dfe: 2600 .& MOVS r6,#0 + 0x00002e00: e018 .. B 0x2e34 ; USART_SendDataFromBuff + 146 + 0x00002e02: 9803 .. LDR r0,[sp,#0xc] + 0x00002e04: 5d80 .] LDRB r0,[r0,r6] + 0x00002e06: 494c LI LDR r1,[pc,#304] ; [0x2f38] = 0x10010000 + 0x00002e08: 1869 i. ADDS r1,r5,r1 + 0x00002e0a: 7008 .p STRB r0,[r1,#0] + 0x00002e0c: 4638 8F MOV r0,r7 + 0x00002e0e: 300a .0 ADDS r0,r0,#0xa + 0x00002e10: f7fefebe .... BL HR_REG_16BIT ; 0x1b90 + 0x00002e14: 42a8 .B CMP r0,r5 + 0x00002e16: d105 .. BNE 0x2e24 ; USART_SendDataFromBuff + 130 + 0x00002e18: 4638 8F MOV r0,r7 + 0x00002e1a: 3008 .0 ADDS r0,r0,#8 + 0x00002e1c: f7fefeb8 .... BL HR_REG_16BIT ; 0x1b90 + 0x00002e20: 4605 .F MOV r5,r0 + 0x00002e22: e001 .. B 0x2e28 ; USART_SendDataFromBuff + 134 + 0x00002e24: 1c68 h. ADDS r0,r5,#1 + 0x00002e26: b285 .. UXTH r5,r0 + 0x00002e28: 9801 .. LDR r0,[sp,#4] + 0x00002e2a: 1c40 @. ADDS r0,r0,#1 + 0x00002e2c: b280 .. UXTH r0,r0 + 0x00002e2e: 9001 .. STR r0,[sp,#4] + 0x00002e30: 1c70 p. ADDS r0,r6,#1 + 0x00002e32: b286 .. UXTH r6,r0 + 0x00002e34: 9804 .. LDR r0,[sp,#0x10] + 0x00002e36: 4286 .B CMP r6,r0 + 0x00002e38: dbe3 .. BLT 0x2e02 ; USART_SendDataFromBuff + 96 + 0x00002e3a: 4629 )F MOV r1,r5 + 0x00002e3c: 4638 8F MOV r0,r7 + 0x00002e3e: 300c .0 ADDS r0,r0,#0xc + 0x00002e40: f7fefe9d .... BL HW_REG_16BIT ; 0x1b7e + 0x00002e44: 2c00 ., CMP r4,#0 + 0x00002e46: d117 .. BNE 0x2e78 ; USART_SendDataFromBuff + 214 + 0x00002e48: bf00 .. NOP + 0x00002e4a: 4839 9H LDR r0,[pc,#228] ; [0x2f30] = 0x10004fe0 + 0x00002e4c: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x00002e4e: 2000 . MOVS r0,#0 + 0x00002e50: 4938 8I LDR r1,[pc,#224] ; [0x2f34] = 0x10008300 + 0x00002e52: 7b89 .{ LDRB r1,[r1,#0xe] + 0x00002e54: 4300 .C ORRS r0,r0,r0 + 0x00002e56: 4937 7I LDR r1,[pc,#220] ; [0x2f34] = 0x10008300 + 0x00002e58: 7b89 .{ LDRB r1,[r1,#0xe] + 0x00002e5a: 4308 .C ORRS r0,r0,r1 + 0x00002e5c: 4934 4I LDR r1,[pc,#208] ; [0x2f30] = 0x10004fe0 + 0x00002e5e: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x00002e60: 2100 .! MOVS r1,#0 + 0x00002e62: 4a34 4J LDR r2,[pc,#208] ; [0x2f34] = 0x10008300 + 0x00002e64: 7bd2 .{ LDRB r2,[r2,#0xf] + 0x00002e66: 4309 .C ORRS r1,r1,r1 + 0x00002e68: 4a32 2J LDR r2,[pc,#200] ; [0x2f34] = 0x10008300 + 0x00002e6a: 7bd2 .{ LDRB r2,[r2,#0xf] + 0x00002e6c: 4311 .C ORRS r1,r1,r2 + 0x00002e6e: 0209 .. LSLS r1,r1,#8 + 0x00002e70: 4308 .C ORRS r0,r0,r1 + 0x00002e72: 2800 .( CMP r0,#0 + 0x00002e74: d1e9 .. BNE 0x2e4a ; USART_SendDataFromBuff + 168 + 0x00002e76: e01a .. B 0x2eae ; USART_SendDataFromBuff + 268 + 0x00002e78: bf00 .. NOP + 0x00002e7a: 482d -H LDR r0,[pc,#180] ; [0x2f30] = 0x10004fe0 + 0x00002e7c: 7fc0 .. LDRB r0,[r0,#0x1f] + 0x00002e7e: 2000 . MOVS r0,#0 + 0x00002e80: 492c ,I LDR r1,[pc,#176] ; [0x2f34] = 0x10008300 + 0x00002e82: 3140 @1 ADDS r1,r1,#0x40 + 0x00002e84: 7d89 .} LDRB r1,[r1,#0x16] + 0x00002e86: 4300 .C ORRS r0,r0,r0 + 0x00002e88: 492a *I LDR r1,[pc,#168] ; [0x2f34] = 0x10008300 + 0x00002e8a: 3140 @1 ADDS r1,r1,#0x40 + 0x00002e8c: 7d89 .} LDRB r1,[r1,#0x16] + 0x00002e8e: 4308 .C ORRS r0,r0,r1 + 0x00002e90: 4927 'I LDR r1,[pc,#156] ; [0x2f30] = 0x10004fe0 + 0x00002e92: 7fc9 .. LDRB r1,[r1,#0x1f] + 0x00002e94: 2100 .! MOVS r1,#0 + 0x00002e96: 4a27 'J LDR r2,[pc,#156] ; [0x2f34] = 0x10008300 + 0x00002e98: 3240 @2 ADDS r2,r2,#0x40 + 0x00002e9a: 7dd2 .} LDRB r2,[r2,#0x17] + 0x00002e9c: 4309 .C ORRS r1,r1,r1 + 0x00002e9e: 4a25 %J LDR r2,[pc,#148] ; [0x2f34] = 0x10008300 + 0x00002ea0: 3240 @2 ADDS r2,r2,#0x40 + 0x00002ea2: 7dd2 .} LDRB r2,[r2,#0x17] + 0x00002ea4: 4311 .C ORRS r1,r1,r2 + 0x00002ea6: 0209 .. LSLS r1,r1,#8 + 0x00002ea8: 4308 .C ORRS r0,r0,r1 + 0x00002eaa: 2800 .( CMP r0,#0 + 0x00002eac: d1e5 .. BNE 0x2e7a ; USART_SendDataFromBuff + 216 + 0x00002eae: b005 .. ADD sp,sp,#0x14 + 0x00002eb0: bdf0 .. POP {r4-r7,pc} USART_SetRxITNum - 0x00002ec6: b570 p. PUSH {r4-r6,lr} - 0x00002ec8: 4605 .F MOV r5,r0 - 0x00002eca: 460c .F MOV r4,r1 + 0x00002eb2: b570 p. PUSH {r4-r6,lr} + 0x00002eb4: 4605 .F MOV r5,r0 + 0x00002eb6: 460c .F MOV r4,r1 + 0x00002eb8: 2d00 .- CMP r5,#0 + 0x00002eba: d007 .. BEQ 0x2ecc ; USART_SetRxITNum + 26 + 0x00002ebc: 2d01 .- CMP r5,#1 + 0x00002ebe: d005 .. BEQ 0x2ecc ; USART_SetRxITNum + 26 + 0x00002ec0: 4a22 "J LDR r2,[pc,#136] ; [0x2f4c] = 0x3062 + 0x00002ec2: 21ff .! MOVS r1,#0xff + 0x00002ec4: 3161 a1 ADDS r1,r1,#0x61 + 0x00002ec6: 4818 .H LDR r0,[pc,#96] ; [0x2f28] = 0x2ad4 + 0x00002ec8: f7fef8db .... BL _assert_handler ; 0x1082 0x00002ecc: 2d00 .- CMP r5,#0 - 0x00002ece: d007 .. BEQ 0x2ee0 ; USART_SetRxITNum + 26 - 0x00002ed0: 2d01 .- CMP r5,#1 - 0x00002ed2: d005 .. BEQ 0x2ee0 ; USART_SetRxITNum + 26 - 0x00002ed4: 4a2a *J LDR r2,[pc,#168] ; [0x2f80] = 0x3076 - 0x00002ed6: 21ff .! MOVS r1,#0xff - 0x00002ed8: 3120 1 ADDS r1,r1,#0x20 - 0x00002eda: 4820 H LDR r0,[pc,#128] ; [0x2f5c] = 0x2aec - 0x00002edc: f7fef8d1 .... BL _assert_handler ; 0x1082 - 0x00002ee0: 2d00 .- CMP r5,#0 - 0x00002ee2: d105 .. BNE 0x2ef0 ; USART_SetRxITNum + 42 - 0x00002ee4: bf00 .. NOP - 0x00002ee6: 481e .H LDR r0,[pc,#120] ; [0x2f60] = 0x10008052 - 0x00002ee8: 30ce .0 ADDS r0,r0,#0xce - 0x00002eea: 7484 .t STRB r4,[r0,#0x12] - 0x00002eec: 7484 .t STRB r4,[r0,#0x12] - 0x00002eee: e005 .. B 0x2efc ; USART_SetRxITNum + 54 - 0x00002ef0: bf00 .. NOP - 0x00002ef2: 481b .H LDR r0,[pc,#108] ; [0x2f60] = 0x10008052 - 0x00002ef4: 30ce .0 ADDS r0,r0,#0xce - 0x00002ef6: 7544 Du STRB r4,[r0,#0x15] - 0x00002ef8: 7544 Du STRB r4,[r0,#0x15] - 0x00002efa: bf00 .. NOP - 0x00002efc: bd70 p. POP {r4-r6,pc} + 0x00002ece: d105 .. BNE 0x2edc ; USART_SetRxITNum + 42 + 0x00002ed0: bf00 .. NOP + 0x00002ed2: 4816 .H LDR r0,[pc,#88] ; [0x2f2c] = 0x10008052 + 0x00002ed4: 30ce .0 ADDS r0,r0,#0xce + 0x00002ed6: 7484 .t STRB r4,[r0,#0x12] + 0x00002ed8: 7484 .t STRB r4,[r0,#0x12] + 0x00002eda: e005 .. B 0x2ee8 ; USART_SetRxITNum + 54 + 0x00002edc: bf00 .. NOP + 0x00002ede: 4813 .H LDR r0,[pc,#76] ; [0x2f2c] = 0x10008052 + 0x00002ee0: 30ce .0 ADDS r0,r0,#0xce + 0x00002ee2: 7544 Du STRB r4,[r0,#0x15] + 0x00002ee4: 7544 Du STRB r4,[r0,#0x15] + 0x00002ee6: bf00 .. NOP + 0x00002ee8: bd70 p. POP {r4-r6,pc} USART_SetRxTimeout - 0x00002efe: b570 p. PUSH {r4-r6,lr} - 0x00002f00: 4605 .F MOV r5,r0 - 0x00002f02: 460c .F MOV r4,r1 + 0x00002eea: b570 p. PUSH {r4-r6,lr} + 0x00002eec: 4605 .F MOV r5,r0 + 0x00002eee: 460c .F MOV r4,r1 + 0x00002ef0: 2d00 .- CMP r5,#0 + 0x00002ef2: d007 .. BEQ 0x2f04 ; USART_SetRxTimeout + 26 + 0x00002ef4: 2d01 .- CMP r5,#1 + 0x00002ef6: d005 .. BEQ 0x2f04 ; USART_SetRxTimeout + 26 + 0x00002ef8: 4a15 .J LDR r2,[pc,#84] ; [0x2f50] = 0x3073 + 0x00002efa: 21ff .! MOVS r1,#0xff + 0x00002efc: 3173 s1 ADDS r1,r1,#0x73 + 0x00002efe: 480a .H LDR r0,[pc,#40] ; [0x2f28] = 0x2ad4 + 0x00002f00: f7fef8bf .... BL _assert_handler ; 0x1082 0x00002f04: 2d00 .- CMP r5,#0 - 0x00002f06: d007 .. BEQ 0x2f18 ; USART_SetRxTimeout + 26 - 0x00002f08: 2d01 .- CMP r5,#1 - 0x00002f0a: d005 .. BEQ 0x2f18 ; USART_SetRxTimeout + 26 - 0x00002f0c: 4a1d .J LDR r2,[pc,#116] ; [0x2f84] = 0x3087 - 0x00002f0e: 21ff .! MOVS r1,#0xff - 0x00002f10: 312d -1 ADDS r1,r1,#0x2d - 0x00002f12: 4812 .H LDR r0,[pc,#72] ; [0x2f5c] = 0x2aec - 0x00002f14: f7fef8b5 .... BL _assert_handler ; 0x1082 - 0x00002f18: 2d00 .- CMP r5,#0 - 0x00002f1a: d10d .. BNE 0x2f38 ; USART_SetRxTimeout + 58 - 0x00002f1c: bf00 .. NOP - 0x00002f1e: bf00 .. NOP - 0x00002f20: 490f .I LDR r1,[pc,#60] ; [0x2f60] = 0x10008052 - 0x00002f22: 31ce .1 ADDS r1,r1,#0xce - 0x00002f24: 74cc .t STRB r4,[r1,#0x13] - 0x00002f26: 74cc .t STRB r4,[r1,#0x13] - 0x00002f28: bf00 .. NOP - 0x00002f2a: bf00 .. NOP - 0x00002f2c: 1220 . ASRS r0,r4,#8 - 0x00002f2e: 7508 .u STRB r0,[r1,#0x14] - 0x00002f30: 1220 . ASRS r0,r4,#8 - 0x00002f32: 7508 .u STRB r0,[r1,#0x14] - 0x00002f34: bf00 .. NOP - 0x00002f36: e00d .. B 0x2f54 ; USART_SetRxTimeout + 86 - 0x00002f38: bf00 .. NOP - 0x00002f3a: bf00 .. NOP - 0x00002f3c: 4908 .I LDR r1,[pc,#32] ; [0x2f60] = 0x10008052 - 0x00002f3e: 31ce .1 ADDS r1,r1,#0xce - 0x00002f40: 758c .u STRB r4,[r1,#0x16] - 0x00002f42: 758c .u STRB r4,[r1,#0x16] - 0x00002f44: bf00 .. NOP - 0x00002f46: bf00 .. NOP - 0x00002f48: 1220 . ASRS r0,r4,#8 - 0x00002f4a: 75c8 .u STRB r0,[r1,#0x17] - 0x00002f4c: 1220 . ASRS r0,r4,#8 - 0x00002f4e: 75c8 .u STRB r0,[r1,#0x17] - 0x00002f50: bf00 .. NOP - 0x00002f52: bf00 .. NOP - 0x00002f54: bd70 p. POP {r4-r6,pc} + 0x00002f06: d125 %. BNE 0x2f54 ; USART_SetRxTimeout + 106 + 0x00002f08: bf00 .. NOP + 0x00002f0a: bf00 .. NOP + 0x00002f0c: 4907 .I LDR r1,[pc,#28] ; [0x2f2c] = 0x10008052 + 0x00002f0e: 31ce .1 ADDS r1,r1,#0xce + 0x00002f10: 74cc .t STRB r4,[r1,#0x13] + 0x00002f12: 74cc .t STRB r4,[r1,#0x13] + 0x00002f14: bf00 .. NOP + 0x00002f16: bf00 .. NOP + 0x00002f18: 1220 . ASRS r0,r4,#8 + 0x00002f1a: 7508 .u STRB r0,[r1,#0x14] + 0x00002f1c: 1220 . ASRS r0,r4,#8 + 0x00002f1e: 7508 .u STRB r0,[r1,#0x14] + 0x00002f20: bf00 .. NOP + 0x00002f22: e024 $. B 0x2f6e ; USART_SetRxTimeout + 132 $d - 0x00002f56: 0000 .. DCW 0 - 0x00002f58: 00003018 .0.. DCD 12312 - 0x00002f5c: 00002aec .*.. DCD 10988 - 0x00002f60: 10008052 R... DCD 268468306 - 0x00002f64: 10004fe0 .O.. DCD 268455904 - 0x00002f68: 10008300 .... DCD 268468992 - 0x00002f6c: 10010000 .... DCD 268500992 - 0x00002f70: 00003027 '0.. DCD 12327 - 0x00002f74: 00003039 90.. DCD 12345 - 0x00002f78: 0000304a J0.. DCD 12362 - 0x00002f7c: 0000305f _0.. DCD 12383 - 0x00002f80: 00003076 v0.. DCD 12406 - 0x00002f84: 00003087 .0.. DCD 12423 + 0x00002f24: 00003004 .0.. DCD 12292 + 0x00002f28: 00002ad4 .*.. DCD 10964 + 0x00002f2c: 10008052 R... DCD 268468306 + 0x00002f30: 10004fe0 .O.. DCD 268455904 + 0x00002f34: 10008300 .... DCD 268468992 + 0x00002f38: 10010000 .... DCD 268500992 + 0x00002f3c: 00003013 .0.. DCD 12307 + 0x00002f40: 00003025 %0.. DCD 12325 + 0x00002f44: 00003036 60.. DCD 12342 + 0x00002f48: 0000304b K0.. DCD 12363 + 0x00002f4c: 00003062 b0.. DCD 12386 + 0x00002f50: 00003073 s0.. DCD 12403 + $t + 0x00002f54: bf00 .. NOP + 0x00002f56: bf00 .. NOP + 0x00002f58: 4905 .I LDR r1,[pc,#20] ; [0x2f70] = 0x10008120 + 0x00002f5a: 758c .u STRB r4,[r1,#0x16] + 0x00002f5c: 758c .u STRB r4,[r1,#0x16] + 0x00002f5e: bf00 .. NOP + 0x00002f60: bf00 .. NOP + 0x00002f62: 1220 . ASRS r0,r4,#8 + 0x00002f64: 75c8 .u STRB r0,[r1,#0x17] + 0x00002f66: 1220 . ASRS r0,r4,#8 + 0x00002f68: 75c8 .u STRB r0,[r1,#0x17] + 0x00002f6a: bf00 .. NOP + 0x00002f6c: bf00 .. NOP + 0x00002f6e: bd70 p. POP {r4-r6,pc} + $d + 0x00002f70: 10008120 ... DCD 268468512 $t .text __aeabi_uidiv __aeabi_uidivmod - 0x00002f88: b530 0. PUSH {r4,r5,lr} - 0x00002f8a: 460b .F MOV r3,r1 - 0x00002f8c: 4601 .F MOV r1,r0 - 0x00002f8e: 2000 . MOVS r0,#0 - 0x00002f90: 2220 " MOVS r2,#0x20 - 0x00002f92: 2401 .$ MOVS r4,#1 - 0x00002f94: e009 .. B 0x2faa ; __aeabi_uidiv + 34 - 0x00002f96: 460d .F MOV r5,r1 - 0x00002f98: 40d5 .@ LSRS r5,r5,r2 - 0x00002f9a: 429d .B CMP r5,r3 - 0x00002f9c: d305 .. BCC 0x2faa ; __aeabi_uidiv + 34 - 0x00002f9e: 461d .F MOV r5,r3 - 0x00002fa0: 4095 .@ LSLS r5,r5,r2 - 0x00002fa2: 1b49 I. SUBS r1,r1,r5 - 0x00002fa4: 4625 %F MOV r5,r4 - 0x00002fa6: 4095 .@ LSLS r5,r5,r2 - 0x00002fa8: 1940 @. ADDS r0,r0,r5 - 0x00002faa: 4615 .F MOV r5,r2 - 0x00002fac: 1e52 R. SUBS r2,r2,#1 - 0x00002fae: 2d00 .- CMP r5,#0 - 0x00002fb0: dcf1 .. BGT 0x2f96 ; __aeabi_uidiv + 14 - 0x00002fb2: bd30 0. POP {r4,r5,pc} + 0x00002f74: b530 0. PUSH {r4,r5,lr} + 0x00002f76: 460b .F MOV r3,r1 + 0x00002f78: 4601 .F MOV r1,r0 + 0x00002f7a: 2000 . MOVS r0,#0 + 0x00002f7c: 2220 " MOVS r2,#0x20 + 0x00002f7e: 2401 .$ MOVS r4,#1 + 0x00002f80: e009 .. B 0x2f96 ; __aeabi_uidiv + 34 + 0x00002f82: 460d .F MOV r5,r1 + 0x00002f84: 40d5 .@ LSRS r5,r5,r2 + 0x00002f86: 429d .B CMP r5,r3 + 0x00002f88: d305 .. BCC 0x2f96 ; __aeabi_uidiv + 34 + 0x00002f8a: 461d .F MOV r5,r3 + 0x00002f8c: 4095 .@ LSLS r5,r5,r2 + 0x00002f8e: 1b49 I. SUBS r1,r1,r5 + 0x00002f90: 4625 %F MOV r5,r4 + 0x00002f92: 4095 .@ LSLS r5,r5,r2 + 0x00002f94: 1940 @. ADDS r0,r0,r5 + 0x00002f96: 4615 .F MOV r5,r2 + 0x00002f98: 1e52 R. SUBS r2,r2,#1 + 0x00002f9a: 2d00 .- CMP r5,#0 + 0x00002f9c: dcf1 .. BGT 0x2f82 ; __aeabi_uidiv + 14 + 0x00002f9e: bd30 0. POP {r4,r5,pc} .text __scatterload __scatterload_rt2 - 0x00002fb4: 4c06 .L LDR r4,[pc,#24] ; [0x2fd0] = 0x30c4 - 0x00002fb6: 2501 .% MOVS r5,#1 - 0x00002fb8: 4e06 .N LDR r6,[pc,#24] ; [0x2fd4] = 0x30e4 - 0x00002fba: e005 .. B 0x2fc8 ; __scatterload + 20 - 0x00002fbc: 68e3 .h LDR r3,[r4,#0xc] - 0x00002fbe: cc07 .. LDM r4!,{r0-r2} - 0x00002fc0: 432b +C ORRS r3,r3,r5 - 0x00002fc2: 3c0c .< SUBS r4,r4,#0xc - 0x00002fc4: 4798 .G BLX r3 - 0x00002fc6: 3410 .4 ADDS r4,r4,#0x10 - 0x00002fc8: 42b4 .B CMP r4,r6 - 0x00002fca: d3f7 .. BCC 0x2fbc ; __scatterload + 8 - 0x00002fcc: f7fef81c .... BL __main_after_scatterload ; 0x1008 + 0x00002fa0: 4c06 .L LDR r4,[pc,#24] ; [0x2fbc] = 0x30b0 + 0x00002fa2: 2501 .% MOVS r5,#1 + 0x00002fa4: 4e06 .N LDR r6,[pc,#24] ; [0x2fc0] = 0x30d0 + 0x00002fa6: e005 .. B 0x2fb4 ; __scatterload + 20 + 0x00002fa8: 68e3 .h LDR r3,[r4,#0xc] + 0x00002faa: cc07 .. LDM r4!,{r0-r2} + 0x00002fac: 432b +C ORRS r3,r3,r5 + 0x00002fae: 3c0c .< SUBS r4,r4,#0xc + 0x00002fb0: 4798 .G BLX r3 + 0x00002fb2: 3410 .4 ADDS r4,r4,#0x10 + 0x00002fb4: 42b4 .B CMP r4,r6 + 0x00002fb6: d3f7 .. BCC 0x2fa8 ; __scatterload + 8 + 0x00002fb8: f7fef826 ..&. BL __main_after_scatterload ; 0x1008 $d - 0x00002fd0: 000030c4 .0.. DCD 12484 - 0x00002fd4: 000030e4 .0.. DCD 12516 + 0x00002fbc: 000030b0 .0.. DCD 12464 + 0x00002fc0: 000030d0 .0.. DCD 12496 $t i.__scatterload_copy __scatterload_copy - 0x00002fd8: e002 .. B 0x2fe0 ; __scatterload_copy + 8 - 0x00002fda: c808 .. LDM r0!,{r3} - 0x00002fdc: 1f12 .. SUBS r2,r2,#4 - 0x00002fde: c108 .. STM r1!,{r3} - 0x00002fe0: 2a00 .* CMP r2,#0 - 0x00002fe2: d1fa .. BNE 0x2fda ; __scatterload_copy + 2 - 0x00002fe4: 4770 pG BX lr + 0x00002fc4: e002 .. B 0x2fcc ; __scatterload_copy + 8 + 0x00002fc6: c808 .. LDM r0!,{r3} + 0x00002fc8: 1f12 .. SUBS r2,r2,#4 + 0x00002fca: c108 .. STM r1!,{r3} + 0x00002fcc: 2a00 .* CMP r2,#0 + 0x00002fce: d1fa .. BNE 0x2fc6 ; __scatterload_copy + 2 + 0x00002fd0: 4770 pG BX lr i.__scatterload_null __scatterload_null - 0x00002fe6: 4770 pG BX lr + 0x00002fd2: 4770 pG BX lr i.__scatterload_zeroinit __scatterload_zeroinit - 0x00002fe8: 2000 . MOVS r0,#0 - 0x00002fea: e001 .. B 0x2ff0 ; __scatterload_zeroinit + 8 - 0x00002fec: c101 .. STM r1!,{r0} - 0x00002fee: 1f12 .. SUBS r2,r2,#4 - 0x00002ff0: 2a00 .* CMP r2,#0 - 0x00002ff2: d1fb .. BNE 0x2fec ; __scatterload_zeroinit + 4 - 0x00002ff4: 4770 pG BX lr - 0x00002ff6: 0000 .. MOVS r0,r0 + 0x00002fd4: 2000 . MOVS r0,#0 + 0x00002fd6: e001 .. B 0x2fdc ; __scatterload_zeroinit + 8 + 0x00002fd8: c101 .. STM r1!,{r0} + 0x00002fda: 1f12 .. SUBS r2,r2,#4 + 0x00002fdc: 2a00 .* CMP r2,#0 + 0x00002fde: d1fb .. BNE 0x2fd8 ; __scatterload_zeroinit + 4 + 0x00002fe0: 4770 pG BX lr + 0x00002fe2: 0000 .. MOVS r0,r0 $d.realdata .constdata g_pcHex1 - 0x00002ff8: 000030b0 .0.. DCD 12464 + 0x00002fe4: 0000309c .0.. DCD 12444 g_pcHex2 - 0x00002ffc: 0000309c .0.. DCD 12444 + 0x00002fe8: 00003088 .0.. DCD 12424 .constdata __FUNCTION__ - 0x00003000: 52415355 USAR DCD 1380012885 - 0x00003004: 6e495f54 T_In DCD 1850302292 - 0x00003008: 7469 it DCW 29801 - 0x0000300a: 00 . DCB 0 + 0x00002fec: 52415355 USAR DCD 1380012885 + 0x00002ff0: 6e495f54 T_In DCD 1850302292 + 0x00002ff4: 7469 it DCW 29801 + 0x00002ff6: 00 . DCB 0 __FUNCTION__ - 0x0000300b: 55 U DCB 85 - 0x0000300c: 54524153 SART DCD 1414676819 - 0x00003010: 4965445f _DeI DCD 1231373407 - 0x00003014: 0074696e nit. DCD 7629166 + 0x00002ff7: 55 U DCB 85 + 0x00002ff8: 54524153 SART DCD 1414676819 + 0x00002ffc: 4965445f _DeI DCD 1231373407 + 0x00003000: 0074696e nit. DCD 7629166 __FUNCTION__ - 0x00003018: 52415355 USAR DCD 1380012885 - 0x0000301c: 65535f54 T_Se DCD 1699962708 - 0x00003020: 6144646e ndDa DCD 1631872110 - 0x00003024: 6174 ta DCW 24948 - 0x00003026: 00 . DCB 0 + 0x00003004: 52415355 USAR DCD 1380012885 + 0x00003008: 65535f54 T_Se DCD 1699962708 + 0x0000300c: 6144646e ndDa DCD 1631872110 + 0x00003010: 6174 ta DCW 24948 + 0x00003012: 00 . DCB 0 __FUNCTION__ - 0x00003027: 55 U DCB 85 - 0x00003028: 54524153 SART DCD 1414676819 - 0x0000302c: 6365525f _Rec DCD 1667584607 - 0x00003030: 65766965 eive DCD 1702259045 - 0x00003034: 61746144 Data DCD 1635017028 - 0x00003038: 00 . DCB 0 + 0x00003013: 55 U DCB 85 + 0x00003014: 54524153 SART DCD 1414676819 + 0x00003018: 6365525f _Rec DCD 1667584607 + 0x0000301c: 65766965 eive DCD 1702259045 + 0x00003020: 61746144 Data DCD 1635017028 + 0x00003024: 00 . DCB 0 __FUNCTION__ - 0x00003039: 555341 USA DCB 85,83,65 - 0x0000303c: 475f5452 RT_G DCD 1197429842 - 0x00003040: 78527465 etRx DCD 2018669669 - 0x00003044: 6e756f43 Coun DCD 1853189955 - 0x00003048: 0074 t. DCW 116 + 0x00003025: 555341 USA DCB 85,83,65 + 0x00003028: 475f5452 RT_G DCD 1197429842 + 0x0000302c: 78527465 etRx DCD 2018669669 + 0x00003030: 6e756f43 Coun DCD 1853189955 + 0x00003034: 0074 t. DCW 116 __FUNCTION__ - 0x0000304a: 5355 US DCW 21333 - 0x0000304c: 5f545241 ART_ DCD 1599361601 - 0x00003050: 64616552 Read DCD 1684104530 - 0x00003054: 61746144 Data DCD 1635017028 - 0x00003058: 75426f74 toBu DCD 1967288180 - 0x0000305c: 6666 ff DCW 26214 - 0x0000305e: 00 . DCB 0 + 0x00003036: 5355 US DCW 21333 + 0x00003038: 5f545241 ART_ DCD 1599361601 + 0x0000303c: 64616552 Read DCD 1684104530 + 0x00003040: 61746144 Data DCD 1635017028 + 0x00003044: 75426f74 toBu DCD 1967288180 + 0x00003048: 6666 ff DCW 26214 + 0x0000304a: 00 . DCB 0 __FUNCTION__ - 0x0000305f: 55 U DCB 85 - 0x00003060: 54524153 SART DCD 1414676819 - 0x00003064: 6e65535f _Sen DCD 1852134239 - 0x00003068: 74614464 dDat DCD 1952531556 - 0x0000306c: 6f724661 aFro DCD 1869760097 - 0x00003070: 6675426d mBuf DCD 1718960749 - 0x00003074: 0066 f. DCW 102 + 0x0000304b: 55 U DCB 85 + 0x0000304c: 54524153 SART DCD 1414676819 + 0x00003050: 6e65535f _Sen DCD 1852134239 + 0x00003054: 74614464 dDat DCD 1952531556 + 0x00003058: 6f724661 aFro DCD 1869760097 + 0x0000305c: 6675426d mBuf DCD 1718960749 + 0x00003060: 0066 f. DCW 102 __FUNCTION__ - 0x00003076: 5355 US DCW 21333 - 0x00003078: 5f545241 ART_ DCD 1599361601 - 0x0000307c: 52746553 SetR DCD 1383359827 - 0x00003080: 4e544978 xITN DCD 1314146680 - 0x00003084: 6d75 um DCW 28021 - 0x00003086: 00 . DCB 0 + 0x00003062: 5355 US DCW 21333 + 0x00003064: 5f545241 ART_ DCD 1599361601 + 0x00003068: 52746553 SetR DCD 1383359827 + 0x0000306c: 4e544978 xITN DCD 1314146680 + 0x00003070: 6d75 um DCW 28021 + 0x00003072: 00 . DCB 0 __FUNCTION__ - 0x00003087: 55 U DCB 85 - 0x00003088: 54524153 SART DCD 1414676819 - 0x0000308c: 7465535f _Set DCD 1952797535 - 0x00003090: 69547852 RxTi DCD 1767143506 - 0x00003094: 756f656d meou DCD 1970234733 - 0x00003098: 00000074 t... DCD 116 + 0x00003073: 55 U DCB 85 + 0x00003074: 54524153 SART DCD 1414676819 + 0x00003078: 7465535f _Set DCD 1952797535 + 0x0000307c: 69547852 RxTi DCD 1767143506 + 0x00003080: 756f656d meou DCD 1970234733 + 0x00003084: 00000074 t... DCD 116 .conststring + 0x00003088: 33323130 0123 DCD 858927408 + 0x0000308c: 37363534 4567 DCD 926299444 + 0x00003090: 42413938 89AB DCD 1111570744 + 0x00003094: 46454443 CDEF DCD 1178944579 + 0x00003098: 00000000 .... DCD 0 0x0000309c: 33323130 0123 DCD 858927408 0x000030a0: 37363534 4567 DCD 926299444 - 0x000030a4: 42413938 89AB DCD 1111570744 - 0x000030a8: 46454443 CDEF DCD 1178944579 + 0x000030a4: 62613938 89ab DCD 1650538808 + 0x000030a8: 66656463 cdef DCD 1717920867 0x000030ac: 00000000 .... DCD 0 - 0x000030b0: 33323130 0123 DCD 858927408 - 0x000030b4: 37363534 4567 DCD 926299444 - 0x000030b8: 62613938 89ab DCD 1650538808 - 0x000030bc: 66656463 cdef DCD 1717920867 - 0x000030c0: 00000000 .... DCD 0 Region$$Table$$Base - 0x000030c4: 000030e4 .0.. DCD 12516 - 0x000030c8: 10011000 .... DCD 268505088 - 0x000030cc: 00000020 ... DCD 32 - 0x000030d0: 00002fd8 ./.. DCD 12248 - 0x000030d4: 00003104 .1.. DCD 12548 - 0x000030d8: 10011020 ... DCD 268505120 - 0x000030dc: 0000203c < .. DCD 8252 - 0x000030e0: 00002fe8 ./.. DCD 12264 + 0x000030b0: 000030d0 .0.. DCD 12496 + 0x000030b4: 10011000 .... DCD 268505088 + 0x000030b8: 00000020 ... DCD 32 + 0x000030bc: 00002fc4 ./.. DCD 12228 + 0x000030c0: 000030f0 .0.. DCD 12528 + 0x000030c4: 10011020 ... DCD 268505120 + 0x000030c8: 0000203c < .. DCD 8252 + 0x000030cc: 00002fd4 ./.. DCD 12244 Region$$Table$$Limit ** Section #3 'RW_IRAM3' (SHT_PROGBITS) [SHF_ALLOC + SHF_WRITE] @@ -4242,37 +4236,37 @@ ** Section #6 '.debug_frame' (SHT_PROGBITS) - Size : 2584 bytes + Size : 2536 bytes ** Section #7 '.debug_info' (SHT_PROGBITS) - Size : 17544 bytes + Size : 17656 bytes ** Section #8 '.debug_line' (SHT_PROGBITS) - Size : 7800 bytes + Size : 7604 bytes ** Section #9 '.debug_loc' (SHT_PROGBITS) - Size : 5068 bytes + Size : 5736 bytes ** Section #10 '.debug_macinfo' (SHT_PROGBITS) - Size : 23524 bytes + Size : 23620 bytes ** Section #11 '.debug_pubnames' (SHT_PROGBITS) - Size : 2066 bytes + Size : 2027 bytes ** Section #12 '.symtab' (SHT_SYMTAB) - Size : 4240 bytes (alignment 4) + Size : 4224 bytes (alignment 4) String table #13 '.strtab' Last local symbol no. 118 ** Section #13 '.strtab' (SHT_STRTAB) - Size : 3476 bytes + Size : 3460 bytes ** Section #14 '.note' (SHT_NOTE) @@ -4280,7 +4274,7 @@ ** Section #15 '.comment' (SHT_PROGBITS) - Size : 12616 bytes + Size : 12352 bytes ** Section #16 '.shstrtab' (SHT_STRTAB) @@ -4288,9 +4282,11 @@ address size variable name type -0x10011019 0x2 printportcb printport_CB -0x10011019 0x1 printportcb.print_rxio uint8_t -0x1001101a 0x1 printportcb.print_txio uint8_t +0x10011017 0x4 printportcb printport_CB +0x10011017 0x1 printportcb.UARTA_rxio uint8_t +0x10011018 0x1 printportcb.UARTA_txio uint8_t +0x10011019 0x1 printportcb.UARTB_rxio uint8_t +0x1001101a 0x1 printportcb.UARTB_txio uint8_t address size variable name type 0x10011038 0x20 regBeck array[2] of UartxRegControlBackup @@ -4308,12 +4304,7 @@ 0x1001101b 0x2 uartB_TX_buf array[2] of uint8_t address size variable name type -0x10011018 0x1 is_open_log_print uint8_t - -address size variable name type -0x10011016 0x2 printportcb printport_CB -0x10011016 0x1 printportcb.print_rxio uint8_t -0x10011017 0x1 printportcb.print_txio uint8_t +0x10011016 0x1 is_open_log_print uint8_t address size variable name type 0x10011015 0x1 gSystemInFastDpll uint8_t @@ -4344,10 +4335,5 @@ 0x10011004 0x4 SystickCount tick address size variable name type -0x10011000 0x2 printportcb printport_CB -0x10011000 0x1 printportcb.print_rxio uint8_t -0x10011001 0x1 printportcb.print_txio uint8_t - -address size variable name type -0x10011002 0x2 value uint16_t +0x10011000 0x2 value uint16_t Index: trunk/Soft/ModuleDemo/SARDAC/SarAdc_Gpio/CM0/Prj/Output/out.rom =================================================================== --- /YC1121E/SoftCode/MCU/trunk/Soft/ModuleDemo/SARDAC/SarAdc_Gpio/CM0/Prj/Output/out.rom (revision 4280) +++ /YC1121E/SoftCode/MCU/trunk/Soft/ModuleDemo/SARDAC/SarAdc_Gpio/CM0/Prj/Output/out.rom (working copy) @@ -13,7 +13,7 @@ 00000000 00000000 000000d9 -0000239b +000000d9 000000d9 000000d9 000000d9 @@ -1023,7 +1023,7 @@ 00000000 00000000 46854803 -ffd6f001 +ffccf001 47004800 0000102d 1001b640 @@ -1036,7 +1036,7 @@ f0012000 4916f876 f0012000 -e021fd23 +e021fc95 208e2101 f830f000 30f520ff @@ -1051,14 +1051,14 @@ 4909fee8 46088008 a0088801 -f9b4f001 +f9aaf001 30f520ff f984f001 bf00e7dc 0000e7fe 0000ffff 00008034 -10011002 +10011000 756c6176 203d2065 20207825 @@ -2018,8 +2018,6 @@ 48d2bf00 70c470c4 f000bf00 -f000fa08 -f000fa06 f000fa04 f000fa02 f000fa00 @@ -2037,7 +2035,9 @@ f000f9e8 f000f9e6 f000f9e4 -bd70f9e2 +f000f9e2 +f000f9e0 +bd70f9de 2000b570 700849bc 7fc048b8 @@ -2050,8 +2050,6 @@ bf004304 70c448b1 bf0070c4 -f9c7f000 -f9c5f000 f9c3f000 f9c1f000 f9bff000 @@ -2070,6 +2068,8 @@ f9a5f000 f9a3f000 f9a1f000 +f99ff000 +f99df000 489dbd70 47707800 f7ffb510 @@ -2236,32 +2236,32 @@ 10011008 00001ed1 10011014 -6809492d +6809492b d1002900 -492b4770 +49294770 e0026808 75012100 68c168c0 d1f92900 -4a264927 +4a244925 bf006011 b500e7f0 fea2f7ff -49242001 +49222001 bd007008 4604b510 fe9af7ff -49202001 +491e2001 bd107008 4607b5fc 90012000 24002500 f7ff2600 4378fdc4 -481a9001 +48189001 90006940 -69854818 -4817e011 +69854816 +4815e011 42ac6984 42acd00d 1b28d202 @@ -2276,9 +2276,7 @@ 00c9217d 46084361 ffd2f7ff -b500bd10 -ffbff7ff -bf00bd00 +bf00bd10 bf00bf00 bf00bf00 00004770 @@ -2286,9 +2284,6 @@ 10011020 10011014 e000e000 -4ac07841 -78017051 -47707011 4605b570 4614460e 4631b2a2 @@ -2377,7 +2372,7 @@ 1b2dd90c e09ce006 2201e0a2 -2000a166 +2000a165 ff4cf7ff 1e6d4628 d1f62800 @@ -2436,7 +2431,7 @@ f000980a 4639fcbb f0009000 -482cfcb7 +482bfcb7 5c426800 1c764630 540aa904 @@ -2444,7 +2439,7 @@ f000980a 4639fcab f0009000 -4825fca7 +4824fca7 5c426800 1c764630 540aa904 @@ -2458,7 +2453,7 @@ 22011e41 f7ff2000 e005feaf -a1182205 +a1172205 f7ff2000 bf00fea9 9810bf00 @@ -2467,25 +2462,24 @@ b00b9001 bc08bcf0 4718b004 -70084911 +70084910 b5104770 -480f4604 +480e4604 28007800 4620d002 fe9af7ff b510bd10 -480a4604 +48094604 28017800 4620dd02 fe90f7ff 0000bd10 -10011016 00000020 -00002ff8 -00002ffc +00002fe4 +00002fe8 4f525245 00000052 -10011018 +10011016 4605b5fe 2000460c 26009001 @@ -2507,59 +2501,59 @@ 49ed4388 bf007448 d1042c00 -212b4aec +215b4aec f7fea0ec -2d00fca2 +2d00fcae 2d01d006 4ae8d004 -a0e8212c -fc99f7fe +a0e8215c +fca5f7fe 28006820 49f3d003 42886820 4ae2d304 -a0e2212e -fc8df7fe +a0e2215e +fc99f7fe 280088a0 88a0d007 d0042804 -212f4adc +215f4adc f7fea0dc -88e0fc82 +88e0fc8e d0072800 280888e0 4ad7d004 -a0d72130 -fc77f7fe +a0d72160 +fc83f7fe 28008920 8920d007 d0042802 -21314ad1 +21614ad1 f7fea0d1 -8960fc6c +8960fc78 d0072840 28008960 4accd004 -a0cc2132 -fc61f7fe +a0cc2162 +fc6df7fe 280089a0 89a0d007 d0042810 -21334ac6 +21634ac6 f7fea0c6 -89e0fc56 +89e0fc62 dd032800 49d289e0 dd044288 -21344ac0 +21644ac0 f7fea0c0 -8a20fc4a +8a20fc56 dd032800 49cc8a20 dd044288 -21354aba +21654aba f7fea0ba -8820fc3e +8820fc4a 4ac80129 2d005250 4ec7d112 @@ -2619,31 +2613,31 @@ 0128bf00 5a114a8f f7ff9800 -0128f944 +0128f950 18804a8c 98008901 f7ff3008 -0128f93c +0128f948 18804a88 98008941 f7ff300a -0128f934 +0128f940 18804a84 98008901 f7ff300c -0128f92c +0128f938 18804a80 98008841 f7ff1c80 -0128f924 +0128f930 18804a7c 98008881 f7ff1d00 -0128f91c +0128f928 18804a78 98008841 f7ff1d80 -bf00f914 +bf00f920 49740128 7b801840 07092101 @@ -2653,71 +2647,6 @@ 07092101 70081879 bdfebf00 -4604b510 -d0062c00 -d0042c01 -216f4a6e -f7fea057 -2c00fb78 -bf00d139 -7fc04852 -49502000 -78093120 -494e4300 -78093120 -21014308 -494b4308 -70083120 -7fc0484a -78092000 -49474300 -78093120 -21014308 -49444308 -70083120 -bf00bf00 -7fc04842 -78092000 -493f4300 -78093120 -493d4308 -70083120 -7fc0483c -78092000 -49394300 -78093120 -49374308 -70083120 -bf00e039 -7fc04835 -49332000 -7c493120 -49314300 -7c493120 -21014308 -492e4308 -74483120 -7fc0482d -7c492000 -492a4300 -7c493120 -21014308 -49274308 -74483120 -bf00bf00 -7fc04825 -7c492000 -49224300 -7c493120 -49204308 -74483120 -7fc0481f -7c492000 -491c4300 -7c493120 -491a4308 -74483120 -bd10bf00 b085b530 460d4604 21009500 @@ -2727,24 +2656,89 @@ 02892101 820181c1 d10a2c00 -78484928 +78484968 f7fe2108 -4926fce2 +4966fd70 21097808 -fcddf7fe +fd6bf7fe 2c01e00b -4922d109 -210c7848 -fcd5f7fe -7808491f +4962d109 +210c78c8 +fd63f7fe +7888495f f7fe210d -4669fcd0 +4669fd5e f7ff4620 -b005fe03 -0000bd30 +b005fe85 +b510bd30 +2c004604 +2c01d006 +4a58d004 +a04021a4 +fb55f7fe +d1392c00 +483bbf00 +20007fc0 +31204938 +43007809 +31204936 +43087809 +43082101 +31204933 +48337008 +20007fc0 +43007809 +3120492f +43087809 +43082101 +3120492c +bf007008 +482bbf00 +20007fc0 +43007809 +31204927 +43087809 +31204925 +48257008 +20007fc0 +43007809 +31204921 +43087809 +3120491f +e0397008 +481ebf00 +20007fc0 +3120491b +43007c49 +31204919 +43087c49 +43082101 +31204916 +48167448 +20007fc0 +43007c49 +31204912 +43087c49 +43082101 +3120490f +bf007448 +480ebf00 +20007fc0 +43007c49 +3120490a +43087c49 +31204908 +48087448 +20007fc0 +43007c49 +31204904 +43087c49 +31204902 +bf007448 +0000bd10 10008040 10004fe0 -00003000 +00002fec 2e5c2e2e 2e2e5c2e 5c2e2e5c @@ -2767,74 +2761,74 @@ 1001101b 1001101d 00008060 -0000300b -10011019 +10011017 +00002ff7 4604b5f8 2500460f 2c002600 2c01d006 -4afed004 -48fe2195 -fa8df7fe +4af7d004 +48f721bb +fa99f7fe d1012c00 -e0014dfc -35204dfb +e0014df5 +35204df4 30084628 d1042800 -219c4af6 -f7fe48f6 -4628fa7e +21c24aef +f7fe48ef +4628fa8a f7ff300c -4606f801 +4606f80d d10c2c00 -48f3bf00 +48ecbf00 20007fc0 -7b8949f2 -49f14300 +7b8949eb +49ea4300 43087b89 dcf42800 bf00e00d -7fc048ec -49ec2000 +7fc048e5 +49e52000 7d893140 -49ea4300 +49e34300 7d893140 28004308 -48e8dcf2 +48e1dcf2 70071830 300a4628 -ffdcf7fe +ffe8f7fe d10542b0 30084628 -ffd6f7fe +ffe2f7fe e0014606 b2861c70 46284631 f7fe300c -2c00ffc4 +2c00ffd0 bf00d117 -7fc048d9 -49d92000 +7fc048d2 +49d22000 43007b89 -7b8949d7 -49d54308 +7b8949d0 +49ce4308 21007fc9 -7bd24ad4 -4ad34309 +7bd24acd +4acc4309 43117bd2 43080209 d1e92800 bf00e01a -7fc048cd -49cd2000 +7fc048c6 +49c62000 7d893140 -49cb4300 +49c44300 7d893140 -49c84308 +49c14308 21007fc9 -32404ac7 +32404ac0 43097dd2 -32404ac5 +32404abe 43117dd2 43080209 d1e52800 @@ -2843,61 +2837,62 @@ 27002600 d0062c00 d0042c01 -21bb4abe -f7fe48b8 -2c00fa02 -4db7d101 -4db6e001 +21e74ab7 +f7fe48b1 +2c00fa0e +4db0d101 +4dafe001 1da83520 -ff80f7fe -48b64606 +ff8cf7fe +48af4606 f7fe1830 -b2c7ff7b +b2c7ff87 f7fe1d28 -42b0ff77 +42b0ff83 1ca8d104 -ff72f7fe +ff7ef7fe e0014606 b2861c70 1da84631 -ff61f7fe +ff6df7fe bdf84638 4604b510 d0062c00 d0042c01 -21cc4aa9 -f7fe48a2 -2c00f9d6 -48a3d104 +21fd4aa2 +f7fe489b +2c00f9e2 +489cd104 f7fe3012 -bd10ff57 -305a48a0 -ff52f7fe +bd10ff63 +305a4899 +ff5ef7fe b5f7e7f9 4604b084 20004615 26009003 90022700 2c009001 -2c01d006 -4a9bd004 -489321dc -f9b7f7fe -28009805 -4a97d104 -488f21dd -f9aff7fe +2c01d007 +4a94d005 +311421ff +f7fe488b +9805f9c2 +d1052800 +21ff4a8f +48873115 +f9b9f7fe d1052c00 -9001488d -3012488e +90014885 +30124886 e0059002 -3020488a -488b9001 +30204882 +48839001 9002305a 07122201 43119902 f7fe4608 -9003ff21 +9003ff2b d0062d00 42a89803 2000da02 @@ -2906,55 +2901,55 @@ d1002800 9801e7f8 f7fe1d80 -4606ff0f +4606ff19 e0142700 -1830487c +18304874 98057801 980155c1 f7fe1d00 -42b0ff03 +42b0ff0d 9801d105 f7fe1c80 -4606fefd +4606ff07 1c70e001 1c78b286 9803b287 dbe74287 98014631 f7fe1d80 -4638fee6 +4638fef0 b5f7e7d2 4604b082 20002500 27009001 d0072c00 d0052c01 -21ff4a6b -48623101 -f955f7fe +21ff4a63 +485a313e +f95ff7fe 28009803 -4a67d105 -310221ff -f7fe485d -9804f94c +4a5fd105 +313f21ff +f7fe4855 +9804f956 dc052800 -21ff4a62 -48593103 -f943f7fe +21ff4a5a +48513140 +f94df7fe d1012c00 -e0014f57 -37204f56 +e0014f4f +37204f4e 300c4638 -fec0f7fe +fecaf7fe 26004605 9803e018 -49545d80 +494c5d80 70081869 300a4638 -feb4f7fe +febef7fe d10542a8 30084638 -feaef7fe +feb8f7fe e0014605 b2851c68 1c409801 @@ -2963,30 +2958,30 @@ 42869804 4629dbe3 300c4638 -fe93f7fe +fe9df7fe d1172c00 -4841bf00 +4839bf00 20007fc0 -7b894940 -493f4300 +7b894938 +49374300 43087b89 -7fc9493c -4a3c2100 +7fc94934 +4a342100 43097bd2 -7bd24a3a +7bd24a32 02094311 28004308 e01ad1e9 -4835bf00 +482dbf00 20007fc0 -31404934 +3140492c 43007d89 -31404932 +3140492a 43087d89 -7fc9492f -4a2f2100 +7fc94927 +4a272100 7dd23240 -4a2d4309 +4a254309 7dd23240 02094311 28004308 @@ -2995,51 +2990,51 @@ 460c4605 d0072d00 d0052d01 -21ff4a2a -48203120 -f8d1f7fe +21ff4a22 +48183161 +f8dbf7fe d1052d00 -481ebf00 +4816bf00 748430ce e0057484 -481bbf00 +4813bf00 754430ce bf007544 b570bd70 460c4605 d0072d00 d0052d01 -21ff4a1d -4812312d -f8b5f7fe -d10d2d00 +21ff4a15 +480a3173 +f8bff7fe +d1252d00 bf00bf00 -31ce490f +31ce4907 74cc74cc bf00bf00 75081220 75081220 -e00dbf00 -bf00bf00 -31ce4908 -758c758c -bf00bf00 -75c81220 -75c81220 -bf00bf00 -0000bd70 -00003018 -00002aec +e024bf00 +00003004 +00002ad4 10008052 10004fe0 10008300 10010000 -00003027 -00003039 -0000304a -0000305f -00003076 -00003087 +00003013 +00003025 +00003036 +0000304b +00003062 +00003073 +bf00bf00 +758c4905 +bf00758c +1220bf00 +122075c8 +bf0075c8 +bd70bf00 +10008120 460bb530 20004601 24012220 @@ -3057,9 +3052,9 @@ 3c0c432b 34104798 d3f742b4 -f81cf7fe -000030c4 -000030e4 +f826f7fe +000030b0 +000030d0 c808e002 c1081f12 d1fa2a00 @@ -3068,8 +3063,8 @@ 1f12c101 d1fb2a00 00004770 -000030b0 0000309c +00003088 52415355 6e495f54 55007469 @@ -3119,19 +3114,19 @@ 62613938 66656463 00000000 -000030e4 +000030d0 10011000 00000020 -00002fd8 -00003104 +00002fc4 +000030f0 10011020 0000203c -00002fe8 -00001c19 +00002fd4 +00000000 00000000 00000000 00000000 00000000 -1c190000 -001c1900 +19000000 +00170c1c 00000000